4-Channel, 1.5 MSPS, 10-Bit and 12-Bit Parallel ADCs with a Sequencer AD7933/AD7934 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD AGND AD7933/AD7934 VREFIN/ VREFOUT 2.5V VREF VIN0 I/P MUX CLKIN 12-/10-BIT SAR ADC AND CONTROL T/H CONVST BUSY VIN3 SEQUENCER VDRIVE PARALLEL INTERFACE/CONTROL REGISTER DB0 DB11 CS RD WR W/B DGND 03713-001 Throughput rate: 1.5 MSPS Specified for VDD of 2.7 V to 5.25 V Low power 6 mW maximum at 1.5 MSPS with 3 V supplies 13.5 mW maximum at 1.5 MSPS with 5 V supplies 4 analog input channels with a sequencer Software configurable analog inputs 4-channel single-ended inputs 2-channel fully differential inputs 2-channel pseudo differential inputs Accurate on-chip 2.5 V reference ±0.2% maximum @ 25°C, 25 ppm/°C maximum (AD7934) 70 dB SINAD at 50 kHz input frequency No pipeline delays High speed parallel interface—word/byte modes Full shutdown mode: 2 μA maximum 28-lead TSSOP package Figure 1. GENERAL DESCRIPTION The AD7933/AD7934 are 10-bit and 12-bit, high speed, low power, successive approximation (SAR) analog-to-digital converters (ADCs). The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS. The parts contain a low noise, wide bandwidth, differential trackand-hold amplifier that handles input frequencies up to 50 MHz. These parts use advanced design techniques to achieve very low power dissipation at high throughput rates. They also feature flexible power management options. An on-chip control register allows the user to set up different operating conditions, including analog input range and configuration, output coding, power management, and channel sequencing. The AD7933/AD7934 feature four analog input channels with a channel sequencer that allows a preprogrammed selection of channels to be sequentially converted. These parts can accept either single-ended, fully differential, or pseudo differential analog inputs. PRODUCT HIGHLIGHTS The conversion process and data acquisition are controlled using standard control inputs that allow for easy interfacing to microprocessors and DSPs. The input signal is sampled on the falling edge of CONVST, and the conversion is also initiated at this point. The AD7933/AD7934 has an accurate on-chip 2.5 V reference that is used as the reference source for the analog-to-digital conversion. Alternatively, this pin can be overdriven to provide an external reference. 1. 2. 3. 4. 5. 6. 7. High throughput with low power consumption. Four analog inputs with a channel sequencer. Accurate on-chip 2.5 V reference. Single-ended, pseudo differential or fully differential analog inputs that are software selectable. Single-supply operation with VDRIVE function. The VDRIVE function allows the parallel interface to connect directly to 3 V or 5 V processor systems independent of VDD. No pipeline delay. Accurate control of the sampling instant via a CONVST input and once-off conversion control. Table 1. Related Devices Device AD7938/AD7939 AD7938-6 AD7934-6 No. of Bits 12/10 12 12 No. of Channels 8 8 4 Speed 1.5 MSPS 625 kSPS 625 kSPS Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved. AD7933/AD7934 TABLE OF CONTENTS Features .............................................................................................. 1 Converter Operation.................................................................. 17 Functional Block Diagram .............................................................. 1 ADC Transfer Function............................................................. 17 General Description ......................................................................... 1 Typical Connection Diagram ................................................... 18 Product Highlights ........................................................................... 1 Analog Input Structure.............................................................. 18 Revision History ............................................................................... 2 Analog Inputs ............................................................................. 19 Specifications..................................................................................... 3 Analog Input Selection .............................................................. 21 AD7933 Specifications................................................................. 3 Reference ..................................................................................... 22 AD7934 Specifications................................................................. 5 Parallel Interface......................................................................... 23 Timing Specifications .................................................................. 7 Power Modes of Operation ....................................................... 26 Absolute Maximum Ratings............................................................ 8 Power vs. Throughput Rate....................................................... 27 ESD Caution.................................................................................. 8 Microprocessor Interfacing....................................................... 27 Pin Configuration and Function Descriptions............................. 9 Application Hints ........................................................................... 29 Typical Performance Characteristics ........................................... 11 Grounding and Layout .............................................................. 29 Terminology .................................................................................... 13 Evaluating the AD7933/AD7934 Performance...................... 29 Control Register.............................................................................. 15 Outline Dimensions ....................................................................... 30 Sequencer Operation ................................................................. 16 Ordering Guide .......................................................................... 30 Circuit Information ........................................................................ 17 REVISION HISTORY 2/07—Rev. A to Rev B Changes to Timing Specifications .................................................. 7 Changes to Figure 13...................................................................... 12 12/05—Rev. 0 to Rev. A Replaced Figures .................................................................Universal Changes to General Description .................................................... 1 Changes to Product Highlights....................................................... 1 Added Table 1.................................................................................... 1 Changes to Specifications Section.................................................. 3 Changes to Table 5............................................................................ 9 Changes to Terminology Section.................................................. 13 Changes to Control Register Section ........................................... 15 Changes to Circuit Information Section ..................................... 17 Changes to Application Hints Section......................................... 29 1/05—Revision 0: Initial Version Rev. B | Page 2 of 32 AD7933/AD7934 SPECIFICATIONS AD7933 SPECIFICATIONS VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to TMAX1, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation Aperture Delay2 Aperture Jitter2 Full Power Bandwidth2 DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Single-Ended and Pseudo Differential Input Offset Error2 Offset Error Match2 Gain Error2 Gain Error Match2 Fully Differential Input Positive Gain Error2 Positive Gain Error Match2 Zero-Code Error2 Zero-Code Error Match2 Negative Gain Error2 Negative Gain Error Match2 ANALOG INPUT Single-Ended Input Range Pseudo Differential Input Range VIN+ VIN− Fully Differential Input Range3 VIN+ and VIN− VIN+ and VIN− DC Leakage Current4 Input Capacitance Value1 Unit 61 60 −70 −72 dB min dB min dB max dB max −86 −90 −75 5 72 50 10 dB typ dB typ dB typ ns typ ps typ MHz typ MHz typ 10 ±0.5 ±0.5 Bits LSB max LSB max ±2 ±0.5 ±1.5 ±0.5 LSB max LSB max LSB max LSB max ±1.5 ±0.5 ±2 ±0.5 ±1.5 ±0.5 LSB max LSB max LSB max LSB max LSB max LSB max 0 to VREF 0 to 2 × VREF V V RANGE bit = 0 RANGE bit = 1 0 to VREF 0 to 2 × VREF −0.3 to +0.7 −0.3 to +1.8 V V V typ V typ RANGE bit = 0 RANGE bit = 1 VDD = 3 V VDD = 5 V VCM ± VREF/2 VCM ± VREF ±1 45 10 V V μA max pF typ pF typ VCM = VREF/2, RANGE bit = 0 VCM = VREF, RANGE bit = 1 Test Conditions/Comments fIN = 50 kHz sine wave Differential mode Single-ended mode fa = 30 kHz, fb = 50 kHz fIN= 50 kHz, fNOISE = 300 kHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 10 bits Straight binary output coding Twos complement output coding Rev. B | Page 3 of 32 When in track When in hold AD7933/AD7934 Parameter REFERENCE INPUT/OUTPUT VREF Input Voltage 5 DC Leakage Current4 VREFOUT Output Voltage VREFOUT Temperature Coefficient VREF Noise VREF Output Impedance VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD 6 Normal Mode (Static) Normal Mode (Operational) Autostandby Mode Full/Autoshutdown Mode (Static) Power Dissipation Normal Mode (Operational) Autostandby Mode (Static) Full/Autoshutdown Mode Value 1 Unit Test Conditions/Comments 2.5 ±1 2.5 25 5 10 130 10 15 25 V μA max V ppm/°C max ppm/°C typ μV typ μV typ Ω typ pF typ pF typ ±1% specified performance 2.4 0.8 ±5 10 V min V max μA max pF max 2.4 0.4 ±3 10 Straight (natural) binary Twos complement V min V max μA max pF max t2 + 13 tCLK 125 80 1.5 ns ns max ns typ MSPS max 2.7/5.25 2.7/5.25 V min/max V min/max 0.8 2.7 2.0 0.3 160 2 mA typ mA max mA max mA typ μA typ μA max Digital inputs = 0 V or VDRIVE VDD = 2.7 V to 5.25 V, SCLK on or off VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V FSAMPLE = 100 kSPS, VDD = 5 V Static SCLK on or off 13.5 6 800 480 10 6 mW max mW max μW typ μW typ μW max μW max VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V ±0.2% max @ 25°C 0.1 Hz to 10 Hz bandwidth 0.1 Hz to 1 MHz bandwidth When in track When in hold Typically 10 nA, VIN = 0 V or VDRIVE ISOURCE = 200 μA ISINK = 200 μA CODING bit = 0 CODING bit = 1 1 Full-scale step input Sine wave input Temperature range is −40°C to +85°C. See Terminology section. 3 VCM is the common-mode voltage. For full common-mode range, see Figure 25 and Figure 26. VIN+ and VIN− must always remain within GND/VDD. 4 Sample tested during initial release to ensure compliance. 5 This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more information. 6 Measured with a midscale dc analog input. 2 Rev. B | Page 4 of 32 AD7933/AD7934 AD7934 SPECIFICATIONS VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation Aperture Delay2 Aperture Jitter2 Full Power Bandwidth2 DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity 2 Differential Mode Single-Ended Mode Single-Ended and Pseudo Differential Input Offset Error2 Offset Error Match2 Gain Error2 Gain Error Match2 Fully Differential Input Positive Gain Error2 Positive Gain Error Match2 Zero-Code Error2 Zero-Code Error Match2 Negative Gain Error2 Negative Gain Error Match2 ANALOG INPUT Single-Ended Input Range Pseudo Differential Input Range VIN+ VIN− Fully Differential Input Range 3 VIN+ and VIN− VIN+ and VIN− DC Leakage Current 4 Input Capacitance Value 1 Unit 70 68 71 69 −73 −70 −73 dB min dB min dB min dB min dB max dB max dB max −86 −90 −85 5 72 50 10 dB typ dB typ dB typ ns typ ps typ MHz typ MHz typ @ 3 dB @ 0.1 dB 12 ±1 ±1.5 Bits LSB max LSB max Differential mode Single-ended mode ±0.95 −0.95/+1.5 LSB max LSB max ±6 ±1 ±3 ±1 LSB max LSB max LSB max LSB max ±3 ±1 ±6 ±1 ±3 ±1 LSB max LSB max LSB max LSB max LSB max LSB max 0 to VREF 0 to 2 × VREF V V RANGE bit = 0 RANGE bit = 1 0 to VREF 0 to 2 × VREF −0.3 to +0.7 −0.3 to +1.8 V V V typ V typ RANGE bit = 0 RANGE bit = 1 VDD = 3 V VDD = 5 V VCM ± VREF/2 VCM ± VREF ±1 45 10 V V μA max pF typ pF typ VCM = VREF/2, RANGE bit = 0 VCM = VREF, RANGE bit = 1 Rev. B | Page 5 of 32 Test Conditions/Comments fIN = 50 kHz sine wave Differential mode Single-ended mode Differential mode Single-ended mode −85 dB typ, differential mode −80 dB typ, single-ended mode −82 dB typ fa = 30 kHz, fb = 50 kHz fIN = 50 kHz, fNOISE = 300 kHz Guaranteed no missed codes to 12 bits Guaranteed no missed codes to 12 bits Straight binary output coding Twos complement output coding When in track When in hold AD7933/AD7934 Parameter REFERENCE INPUT/OUTPUT VREF Input Voltage 5 DC Leakage Current VREFOUT Output Voltage VREFOUT Temperature Coefficient VREF Noise VREF Output Impedance VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD 6 Normal Mode (Static) Normal Mode (Operational) Autostandby Mode Full/Autoshutdown Mode (Static) Power Dissipation Normal Mode (Operational) Autostandby Mode (Static) Full/Autoshutdown Mode Value 1 Unit Test Conditions/Comments 2.5 ±1 2.5 25 5 10 130 10 15 25 V μA max V ppm/°C max ppm/°C typ μV typ μV typ Ω typ pF typ pF typ ±1% specified performance 2.4 0.8 ±5 10 V min V max μA max pF max 2.4 0.4 ±3 10 Straight (natural) binary Twos complement V min V max μA max pF max t2 + 13 tCLK 125 80 1.5 ns ns max ns typ MSPS max 2.7/5.25 2.7/5.25 V min/max V min/max 0.8 2.7 2.0 0.3 160 2 mA typ mA max mA max mA typ μA typ μA max Digital inputs = 0 V or VDRIVE VDD = 2.7 V to 5.25 V, SCLK on or off VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V fSAMPLE = 100 kSPS, VDD = 5 V Static SCLK on or off 13.5 6 800 480 10 6 mW max mW max μW typ μW typ μW max μW max VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V 1 ±0.2% max @ 25°C 0.1 Hz to 10 Hz bandwidth 0.1 Hz to 1 MHz bandwidth When in track-and-hold When in track-and-hold Typically 10 nA, VIN = 0 V or VDRIVE ISOURCE = 200 μA ISINK = 200 μA CODING bit = 0 CODING bit = 1 Full-scale step input Sine wave input Temperature range is −40°C to +85°C. See the Terminology section. VCM is the common-mode voltage. For full common-mode range, see Figure 25 and Figure 26. VIN+ and VIN− must always remain within GND/VDD. 4 Sample tested during initial release to ensure compliance. 5 This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more information. 6 Measured with a midscale dc analog input. 2 3 Rev. B | Page 6 of 32 AD7933/AD7934 TIMING SPECIFICATIONS VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1 fCLKIN 2 tQUIET t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 3 t14 4 t15 t16 t17 t18 t19 t20 t21 t22 Limit at TMIN, TMAX AD7933 AD7934 700 700 25.5 25.5 30 30 Unit kHz min MHz max ns min 10 15 50 0 0 10 10 10 10 0 0 30 30 3 50 0 0 10 0 10 40 15.7 7.8 ns min ns min ns max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns max ns min ns min ns min ns min ns min ns max ns min ns min 10 15 50 0 0 10 10 10 10 0 0 30 30 3 50 0 0 10 0 10 40 15.7 7.8 Description CLKIN frequency Minimum time between end of read and start of next conversion, that is, the time from when the data bus goes into three-state until the next falling edge of CONVST CONVST pulse width CONVST falling edge to CLKIN falling edge setup time CLKIN falling edge to BUSY rising edge CS to WR setup time CS to WR hold time WR pulse width Data setup time before WR Data hold after WR New data valid before falling edge of BUSY CS to RD setup time CS to RD hold time RD pulse width Data access time after RD Bus relinquish time after RD Bus relinquish time after RD HBEN to RD setup time HBEN to RD hold time Minimum time between reads/writes HBEN to WR setup time HBEN to WR hold time CLKIN falling edge to BUSY falling edge CLKIN low pulse width CLKIN high pulse width 1 Sample tested during initial release to ensure compliance. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications are with a 25 pF load capacitance (see Figure 34, Figure 35, Figure 36, and Figure 37). Minimum CLKIN for specified performance; with slower SCLK frequencies, performance specifications apply typically. 3 The time required for the output to cross 0.4 V or 2.4 V. 4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 2 Rev. B | Page 7 of 32 AD7933/AD7934 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to AGND/DGND VDRIVE to AGND/DGND Analog Input Voltage to AGND Digital Input Voltage to DGND VDRIVE to VDD Digital Output Voltage to AGND VREFIN to AGND AGND to DGND Input Current to Any Pin Except Supplies 1 Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature θJA Thermal Impedance (TSSOP) θJC Thermal Impedance (TSSOP) Lead Temperature, Soldering Reflow Temperature (10 sec to 30 sec) ESD 1 Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to +0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 97.9°C/W 14°C/W 255°C 1.5 kV Transient currents of up to 100 mA do not cause SCR latch-up. Rev. B | Page 8 of 32 AD7933/AD7934 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 28 VIN3 27 VIN2 DB0 3 26 VIN1 DB1 4 25 VIN0 DB2 5 24 VREFIN/VREFOUT DB3 6 23 AGND DB4 7 DB5 8 DB6 AD7933/ AD7934 TOP VIEW (Not to Scale) 22 CS 21 RD 9 20 WR DB7 10 19 CONVST VDRIVE 11 18 CLKIN DGND 12 17 BUSY DB8/HBEN 13 16 DB11 DB9 14 15 DB10 03713-006 VDD 1 W/B 2 Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic VDD 2 W/B 3 to 10 DB0 to DB7 11 VDRIVE 12 DGND 13 DB8/HBEN 14 to 16 DB9 to DB11 17 BUSY 18 CLKIN 19 CONVST Description Power Supply Input. The VDD range for the AD7933/AD7934 is from 2.7 V to 5.25 V. Decouple the supply to AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor. Word/Byte Input. When this input is logic high, word transfer mode is enabled, and data is transferred to and from the AD7933/AD7934 in 10-bit words on Pin DB2 to Pin DB11, or in 12-bit words on Pin DB0 to Pin DB11. When W/B is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. When operating in byte transfer mode, tie off unused data lines to DGND. Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow programming of the control register. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. When reading from the AD7933, the two LSBs (DB0 and DB1) are always 0, and the LSB of the conversion result is available on DB2. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7933/AD7934 operates. Decouple this pin to DGND. The voltage at this pin may be different to that at VDD but should never exceed VDD by more than 0.3 V. Digital Ground. This is the ground reference point for all digital circuitry on the AD7933/AD7934. Connect this pin to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data written to or read from the AD7933/AD7934 is on DB0 to DB7. When HBEN is high, the top four bits of the data being written to, or read from, the AD7933/AD7934 are on DB0 to DB3. When reading from the device, DB4 and DB5 contain the ID of the channel to which the conversion result corresponds (see the channel address bits in Table 10). DB6 and DB7 are always 0. When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when reading from the AD7933, the two LSBs in the low byte are 0s, and the remaining six bits are conversion data. Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. Busy Output. This is the logic output indicating the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the falling edge of BUSY, on the 13th rising edge of CLKIN (see Figure 34). Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7933/AD7934 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the conversion time and achievable throughput rate. The CLKIN signal can be a continuous or burst clock. Conversion Start Input. A falling edge on CONVST initiates a conversion. The track-and-hold goes from track to hold mode on the falling edge of CONVST, and the conversion process is initiated at this point. Following powerdown, when operating in the autoshutdown or autostandby mode, a rising edge on CONVST is used to power up the device. Rev. B | Page 9 of 32 AD7933/AD7934 Pin No. 20 21 Mnemonic WR RD 22 CS 23 AGND 24 VREFIN/VREFOUT 25 to 28 VIN0 to VIN3 Description Write Input. Active low logic input used in conjunction with CS to write data to the control register. Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low. Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or write data to the control register. Analog Ground. This is the ground reference point for all analog circuitry on the AD7933/AD7934. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC. The nominal internal reference voltage is 2.5 V, and this appears at this pin. It is recommended to decouple the VREFIN/VREFOUT pin to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input voltage range for the external reference is 0.1 V to VDD; however, ensure that the analog input range does not exceed VDD + 0.3 V. See the Reference section. Analog Input 0 to Analog Input 3. Four analog input channels that are multiplexed into the on-chip track-andhold. The analog inputs can be programmed as four single-ended inputs, two fully differential pairs, or two pseudo differential pairs by appropriately setting the MODE bits in the control register (see Table 10). Select the analog input channel to be converted either by writing to Address Bit ADD1 and Address Bit ADD0 in the control register prior to the conversion, or by using the on-chip sequencer. The input range for all input channels can either be 0 V to VREF or 0 V to 2 × VREF, and the coding can be binary or twos complement, depending on the states of the RANGE and CODING bits in the control register. To avoid noise pickup, connect any unused input channels to AGND. Rev. B | Page 10 of 32 AD7933/AD7934 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. –60 0 100mV p-p SINE WAVE ON VDD AND/OR VDRIVE NO DECOUPLING DIFFERENTIAL/SINGLE-ENDED MODE –70 –20 AMPLITUDE (dB) INT REF –80 PSRR (dB) 4096 POINT FFT VDD = 5V FSAMPLE = 1.5MSPS FIN = 49.62kHz SINAD = 70.94dB THD = –90.09dB DIFFERENTIAL MODE –10 –90 EXT REF –100 –30 –40 –50 –60 –70 –80 03713-007 700 600 VDD = 5V DIFFERENTIAL MODE 0.8 0.6 DNL ERROR (LSB) –75 –80 –85 –90 0.4 0.2 0 –0.2 –0.4 03713-021 –0.6 0 100 200 300 400 500 600 NOISE FREQUENCY (kHz) 700 03713-010 NOISE ISOLATION (dB) 500 1.0 INTERNAL/EXTERNAL REFERENCE VDD = 5V –0.8 –1.0 800 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 Figure 7. AD7934 Typical DNL @ VDD = 5 V Figure 4. Channel-to-Channel Isolation 1.0 80 VDD = 5V VDD = 5V DIFFERENTIAL MODE 0.8 70 0.6 VDD = 3V INL ERROR (LSB) 60 50 40 0.4 0.2 0 –0.2 –0.4 –0.6 30 0 100 200 300 400 500 600 700 FREQUENCY (kHz) 03713-008 FSAMPLE = 1.5MSPS RANGE = 0 TO VREF DIFFERENTIAL MODE 800 900 1000 Figure 5. AD7934 SINAD vs. Analog Input Frequency for Various Supply Voltages Rev. B | Page 11 of 32 03713-011 SINAD (dB) 400 Figure 6. AD7934 FFT @ VDD = 5 V –70 20 300 FREQUENCY (kHz) Figure 3. PSRR vs. Supply Ripple Frequency Without Supply Decoupling –95 200 –110 1010 100 210 410 610 810 SUPPLY RIPPLE FREQUENCY (kHz) –100 0 –120 10 03713-009 –90 –110 –0.8 –1.0 0 500 1000 1500 2000 2500 CODE 3000 Figure 8. AD7934 Typical INL @ VDD = 5 V 3500 4000 AD7933/AD7934 10000 4 SINGLE-ENDED MODE DIFFERENTIAL MODE 9000 9997 CODES INTERNAL REF 8000 3 6000 2 ??? DNL (LSB) 7000 1 5000 4000 POSITIVE DNL 3000 03713-012 NEGATIVE DNL –1 0.25 0.50 0.75 1.00 1.25 1.50 1.75 VREF (V) 2.00 2.25 2.50 03713-015 2000 0 1000 0 2046 2.75 3 CODES 2047 2048 2049 2050 CODE Figure 9. AD7934 DNL vs. VREF for VDD = 3 V Figure 12. AD7934 Histogram of Codes for 10,000 Samples @ VDD = 5 V with Internal Reference 12 120 11 110 VDD = 5V DIFFERENTIAL MODE 10 100 VDD = 5V SINGLE-ENDED MODE 9 CMRR (dB) VDD = 3V SINGLE-ENDED MODE 8 80 VDD = 3V DIFFERENTIAL MODE 70 03713-013 7 6 0 0.5 1.0 1.5 2.0 2.5 VREF (V) 3.0 3.5 4.0 0 VDD = 5V –0.5 –1.0 VDD = 3V –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 SINGLE-ENDED MODE 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 03713-014 OFFSET (LSB) –1.5 60 0 200 400 600 800 RIPPLE FREQUENCY (kHz) 1000 1200 Figure 13. CMRR vs. Common-Mode Ripple with VDD = 5 V and 3 V Figure 10. AD7934 ENOB vs. VREF –5.0 90 03713-017 EFFECTIVE NUMBER OF BITS DIFFERENTIAL MODE 3.5 Figure 11. AD7934 Offset vs. VREF Rev. B | Page 12 of 32 AD7933/AD7934 TERMINOLOGY Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, 1 LSB below the first code transition, and full scale, 1 LSB above the last code transition. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Negative Gain Error This applies when using the twos complement output coding option, in particular to the 2 × VREF input range with −VREF to +VREF biased about the VREF point. It is the deviation of the first code transition (100…000) to (100…001) from the ideal (that is, −VREFIN + 1 LSB) after the zero-code error has been adjusted out. Negative Gain Error Match The difference in negative gain error between any two channels. Offset Error The deviation of the first code transition (00…000) to (00…001) from the ideal (that is, AGND + 1 LSB). Offset Error Match The difference in offset error between any two channels. Gain Error The deviation of the last code transition (111…110) to (111…111) from the ideal (that is, VREF – 1 LSB) after the offset error has been adjusted out. Gain Error Match The difference in gain error between any two channels. Zero-Code Error This applies when using the twos complement output coding option, in particular to the 2 × VREF input range with −VREF to +VREF biased about the VREFIN point. It is the deviation of the midscale transition (all 0s to all 1s) from the ideal VIN voltage (that is, VREF). Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale sine wave signal to the three nonselected input channels and applying a 50 kHz signal to the selected channel. The channel-to-channel isolation is defined as the ratio of the power of the 50 kHz signal on the selected channel to the power of the noise signal on the unselected channels that appears in the FFT of this channel. The noise frequency on the unselected channels varies from 40 kHz to 740 kHz. The noise amplitude is at 2 × VREF, while the signal amplitude is at 1 × VREF. See Figure 4. Power Supply Rejection Ratio (PSRR) PSRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC VDD supply of frequency, fS. The frequency of the input varies from 1 kHz to 1 MHz. PSRR (dB) = 10 log(Pf/PfS) where: Zero-Code Error Match The difference in zero-code error between any two channels. Pf is the power at frequency f in the ADC output. PfS is the power at frequency fS in the ADC output. Positive Gain Error This applies when using the twos complement output coding option, in particular to the 2 × VREF input range with −VREF to +VREF biased about the VREFIN point. It is the deviation of the last code transition (011…110) to (011…111) from the ideal (that is, +VREF – 1 LSB) after the zero-code error has been adjusted out. Common-Mode Rejection Ratio (CMRR) Positive Gain Error Match The difference in positive gain error between any two channels. CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− of frequency, fS. CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency f in the ADC output. PfS is the power at frequency fS in the ADC output. Rev. B | Page 13 of 32 AD7933/AD7934 Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±½ LSB, after the end of conversion. Signal-to-(Noise + Distortion) Ratio (SINAD) This is the measured ratio of signal-to-noise and distortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fSAMPLE/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-noise and distortion ratio for an ideal N-bit converter with a sine wave input is given by SINAD = (6.02 N + 1.76) dB Thus, for a 12-bit converter, SINAD is 74 dB, and for a 10-bit converter, SINAD is 62 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7933/AD7934, it is defined as ⎛ V 2 2 + V 3 2 + V 4 2 + V 5 2 + V6 2 THD (dB ) = −20 log⎜ ⎜ V1 ⎝ ⎞ ⎟ ⎟ ⎠ Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fSAMPLE/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7933/AD7934 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The intermodulation distortion is calculated per the THD specification, as the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in dB. where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Rev. B | Page 14 of 32 AD7933/AD7934 CONTROL REGISTER The control register on the AD7933/AD7934 is a 12-bit, writeonly register. Data is written to this register using the CS and WR pins. The functions of the control register bits are described in Table 8. At power-up, the default bit settings in the control register are all 0s. When writing to the control register between conversions, ensure that CONVST returns high before performing the write. Table 7. Control Register Bits MSB DB11 PM1 DB10 PM0 DB9 CODING DB8 REF DB7 ZERO DB6 ADD1 DB5 ADD0 DB4 MODE1 DB3 MODE0 DB2 SEQ1 DB1 SEQ0 LSB DB0 RANGE Table 8. Control Register Bit Function Description Bit No. 11, 10 Mnemonic PM1, PM0 9 CODING 8 REF 7 6, 5 ZERO ADD1, ADD0 4, 3 2 MODE1, MODE0 SEQ1 1 SEQ0 0 RANGE Description Power Management Bits. Use these two bits to select the power mode of operation. The user can choose between normal mode or various power-down modes of operation as shown in Table 9. This bit selects the output coding of the conversion result. If the CODING bit is set to 0, the output coding is straight (natural) binary. If the CODING bit is set to 1, the output coding is twos complement. This bit selects whether the internal or external reference is used to perform the conversion. If the REF bit is Logic 0, an external reference should be applied to the VREF pin, and if it is Logic 1, the internal reference is selected. See the Reference section. This bit is not used; therefore, it should always be set to Logic 0. Use these two address bits to select which analog input channel is to be converted in the next conversion, if the sequencer is not being used, or to select the final channel in a consecutive sequence when the sequencer is being used (see Table 11 for more information). The selected input channel is decoded as shown in Table 10. The two mode pins select the type of analog input on the four VIN pins. The AD7933/AD7934 have either four single-ended inputs, two fully differential inputs, or two pseudo differential inputs (see Table 10). The SEQ1 bit in the control register is used in conjunction with the SEQ0 bit to control the sequencer function (see Table 11). The SEQ0 bit in the control register is used in conjunction with the SEQ1 bit to control the sequencer function (see Table 11). This bit selects the analog input range of the AD7933/AD7934. If RANGE is set to 0, the analog input range extends from 0 V to VREF. If RANGE is set to 1, the analog input range extends from 0 V to 2 × VREF. When this range is selected, VDD must be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that the analog input remains within the supply rails. See the Analog Inputs section for more information. Table 9. Power Mode Selection Using the Power Management Bits in the Control Register PM1 0 0 PM0 0 1 Mode Normal Mode Autoshutdown 1 0 Autostandby 1 1 Full Shutdown Description When operating in normal mode, all circuitry is fully powered up at all times. When operating in autoshutdown mode, the AD7933/AD7934 enters full shutdown mode at the end of each conversion. In this mode, all circuitry is powered down. When the AD7933/AD7934 enters this mode, the reference remains fully powered, the reference buffer is partially powered down, and all other circuitry is fully powered down. This mode is similar to autoshutdown mode, but it allows the part to power up in 7 μs (or 600 ns if an external reference is used). See the Power Modes of Operation section for more information. When the AD7933/AD7934 enters this mode, all circuitry is powered down. The information in the control register is retained. Rev. B | Page 15 of 32 AD7933/AD7934 SEQUENCER OPERATION The configuration of the SEQ0 and SEQ1 bits in the control register allows use of the sequencer function. Table 11 outlines the two sequencer modes of operation. Writing to the Control Register to Program the Sequencer The AD7933 and AD7934 need 13 full CLKIN periods to perform a conversion. If the ADC does not receive the full 13 CLKIN periods, the conversion aborts. If a conversion is aborted after applying 12.5 CLKIN periods to the ADC, ensure that a rising edge of CONVST or a falling edge of CLKIN is applied to the part before writing to the control register to program the sequencer. If these conditions are not met, the sequencer will not be in the correct state to handle being reprogrammed for another sequence of conversions and the performance of the converter is not guaranteed. Table 10. Analog Input Type Selection Channel Address ADD1 ADD0 0 0 0 1 1 0 1 1 MODE0 = 0, MODE1 = 0 Four Single-Ended Input Channels VIN+ VIN− VIN0 AGND VIN1 AGND VIN2 AGND VIN3 AGND MODE0 = 0, MODE1 = 1 Two Fully Differential Input Channels VIN+ VIN− VIN0 VIN1 VIN1 VIN0 VIN2 VIN3 VIN3 VIN2 MODE0 = 1, MODE1 = 0 Two Pseudo Differential Input Channels VIN+ VIN− VIN0 VIN1 VIN1 VIN0 VIN2 VIN3 VIN3 VIN2 MODE0 = 1, MODE1 = 1 Not Used Table 11. Sequence Selection Modes SEQ0 0 SEQ1 0 0 1 1 1 0 1 Sequence Type Select this configuration when the sequence function is not used. The analog input channel selected on each individual conversion is determined by the contents of ADD1 and ADD0, the channel address bits, in each prior write operation. This mode of operation reflects the normal operation of a multichannel ADC, without using the sequencer function, where each write to the AD7933/AD7934 selects the next channel for conversion. Not used. Not used. Use this configuration in conjunction with ADD1 and ADD0, the channel address bits, to program continuous conversions on a consecutive sequence of channels. The sequence of channels extends from Channel 0 through to a selected final channel as determined by the channel address bits in the control register. When in differential or pseudo differential mode, inverse channels (for example, VIN1, VIN0) are not converted. Rev. B | Page 16 of 32 AD7933/AD7934 CIRCUIT INFORMATION The AD7933/AD7934 provide the user with an on-chip track-and-hold, an internal accurate reference, an analog-todigital converter, and a parallel interface housed in a 28-lead TSSOP package. The AD7933/AD7934 have four analog input channels that can be configured to be four single-ended inputs, two fully differential pairs, or two pseudo differential pairs. There is an on-chip channel sequencer that allows the user to select a consecutive sequence of channels through which the ADC can cycle with each falling edge of CONVST. When the ADC starts a conversion (see Figure 15), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the output code of the ADC. The output impedances of the sources driving the VIN+ and the VIN− pins must match; otherwise, the two inputs have different settling times, resulting in errors. CAPACITIVE DAC COMPARATOR VIN+ The analog input range for the AD7933/AD7934 is 0 V to VREF or 0 V to 2 × VREF, depending on the status of the RANGE bit in the control register. The output coding of the ADC can be either binary or twos complement, depending on the status of the CODING bit in the control register. CS B A SW1 A B SW2 CONTROL LOGIC SW3 VIN– VREF CS 03713-024 The AD7933/AD7934 are fast, 4-channel, 10-bit and 12-bit, single-supply, successive approximation analog-to-digital converters. The parts operate from a 2.7 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS. CAPACITIVE DAC Figure 15. ADC Conversion Phase CONVERTER OPERATION The AD7933/AD7934 are successive approximation ADCs based around two capacitive digital-to-analog converters (DACs). Figure 14 and Figure 15 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC comprises control logic, a SAR, and two capacitive DACs. Both figures show the operation of the ADC in differential/pseudo differential modes. Single-ended mode operation is similar but VIN− is internally tied to AGND. In acquisition phase, SW3 is closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. ADC TRANSFER FUNCTION The output coding for the AD7933/AD7934 is either straight binary or twos complement, depending on the status of the CODING bit in the control register. The designed code transitions occur at successive LSB values (1 LSB, 2 LSBs, and so on), and the LSB size is VREF/1024 for the AD7933 and VREF/4096 for the AD7934. The ideal transfer characteristics of the AD7933/AD7934 for both straight binary and twos complement output coding are shown in Figure 16 and Figure 17, respectively. 111...111 111...110 ADC CODE The AD7933/AD7934 provide flexible power management options to allow users to achieve the best power performance for a given throughput rate. These options are selected by programming PM1 and PM0, the power management bits, in the control register. CAPACITIVE DAC CS 000...001 000...000 SW1 SW3 VIN– A B SW2 VREF 1 LSB = VREF /4096 (AD7934) 1 LSB = VREF /1024 (AD7933) CONTROL LOGIC 0V +VREF – 1 LSB ANALOG INPUT CS CAPACITIVE DAC 1 LSB Figure 14. ADC Acquisition Phase Rev. B | Page 17 of 32 NOTES 1. VREF IS EITHER VREF OR 2 × VREF . Figure 16. AD7933/AD7934 Ideal Transfer Characteristic with Straight Binary Output Coding 03713-025 A 03713-023 VIN+ 011...111 000...010 COMPARATOR B 111...000 AD7933/AD7934 1 LSB = 2 × VREF /4096 (AD7934) 1 LSB = 2 × VREF /1024 (AD7933) ANALOG INPUT STRUCTURE 011...111 Figure 19 shows the equivalent circuit of the analog input structure of the AD7933/AD7934 in differential/pseudo differential modes. In single-ended mode, VIN− is internally tied to AGND. The four diodes provide ESD protection for the analog inputs. Ensure that the analog input signals never exceed the supply rails by more than 300 mV; doing so causes these diodes to become forward-biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. 000...001 000...000 111...111 100...010 100...000 –VREF + 1 LSB VREF +VREF – 1 LSB 03713-026 100...001 Figure 17. AD7933/AD7934 Ideal Transfer Characteristic with Twos Complement Output Coding and 2 × VREF Range TYPICAL CONNECTION DIAGRAM Figure 18 shows a typical connection diagram for the AD7933/AD7934. The AGND and DGND pins are connected together at the device for good noise suppression. If the internal reference is used, the VREFIN/VREFOUT pin is decoupled to AGND with a 0.47 μF capacitor to avoid noise pickup. Alternatively, VREFIN/VREFOUT can be connected to an external reference source. In this case, decouple the reference pin with a 0.1 μF capacitor. In both cases, the analog input range can either be 0 V to VREF (RANGE bit = 0) or 0 V to 2 × VREF (RANGE bit = 1). The analog input configuration can be either four single-ended inputs, two differential pairs, or two pseudo differential pairs (see Table 10). The VDD pin is connected to either a 3 V or 5 V supply. The voltage applied to the VDRIVE input controls the voltage of the digital interface. As shown in Figure 18, it is connected to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the Digital Inputs section). 0.1µF + 10µF + The C1 capacitors in Figure 19 are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. The C2 capacitors are the sampling capacitors of the ADC and typically have a capacitance of 45 pF. For ac applications, removing high frequency components from the analog input signal is recommended by using an RC lowpass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, drive the analog input from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. VDD D VIN+ C1 3V/5V SUPPLY VIN– AD7933/AD7934 VIN0 C1 MICROCONTROLLER/ MICROPROCESSOR CLKIN CS RD VIN3 WR BUSY CONVST AGND DB0 DGND DB11/DB9 VREFIN/VREFOUT C2 0.1µF + + 10µF 3V SUPPLY + 0.1µF EXTERNAL VREF 0.47µF INTERNAL VREF D Figure 19. Equivalent Analog Input Circuit, Conversion Phase: Switches Open, Track Phase: Switches Closed 03713-027 2.5V VREF VDRIVE R1 VDD W/B 0 TO VREF / 0 TO 2 × VREF C2 D D VDD R1 03713-028 ADC CODE 011...110 When no amplifier is used to drive the analog input, limit the source impedance to low values. The maximum source impedance depends on the amount of THD that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 20 and Figure 21 show a graph of the THD vs. source impedance with a 50 kHz input tone for both VDD = 5 V and 3 V in single-ended mode and fully differential mode, respectively. Figure 18. Typical Connection Diagram Rev. B | Page 18 of 32 AD7933/AD7934 –40 ANALOG INPUTS FIN = 50kHz –45 The AD7933/AD7934 have software selectable analog input configurations. Users can choose from among the following configurations: four single-ended inputs, two fully differential pairs, or two pseudo differential pairs. The analog input configuration is chosen by setting the MODE0/MODE1 bits in the internal control register (see Table 10). –50 VDD = 3V THD (dB) –55 –60 –65 –70 –75 Single-Ended Mode VDD = 5V 03713-018 –80 –85 –90 10 100 RSOURCE (Ω) 1k Figure 20. THD vs. Source Impedance in Single-Ended Mode –60 FIN = 50kHz –65 If the analog input signal to be sampled is bipolar, the internal reference of the ADC can be used to externally bias up this signal to make it the correct format for the ADC. –70 –75 THD (dB) The AD7933/AD7934 can have four single-ended analog input channels by setting the MODE0 and MODE1 bits in the control register to 0. In applications where the signal source has a high impedance, it is recommended to buffer the analog input before applying it to the ADC. An amplifier suitable for this function is the AD8021. The analog input range of the AD7933/AD7934 can be programmed to be either 0 V to VREF, or 0 V to 2 × VREF. –80 –85 VDD = 3V –90 VDD = 5V 03713-019 –95 –100 10 100 RSOURCE (Ω) 1k Figure 23 shows a typical connection diagram when operating the ADC in single-ended mode. This diagram shows a bipolar signal of amplitude ±1.25 V being preconditioned before it is applied to the AD7933/AD7934. In cases where the analog input amplitude is ±2.5 V, the 3R resistor can be replaced with a resistor of value R. The resultant voltage on the analog input of the AD7933/AD7934 is a signal ranging from 0 V to 5 V. In this case, the 2 × VREF mode can be used. Figure 21. THD vs. Source Impedance in Fully Differential Mode R Figure 22 shows a graph of the THD vs. the analog input frequency for various supplies, while sampling at 1.5 MHz with an SCLK of 25.5 MHz. In this case, the source impedance is 10 Ω. +1.25V 0V –1.25V VIN +2.5V 0V R 3R VIN0 AD7933/ AD7934* VIN3 VREFOUT R –50 VDD = 3V SINGLE-ENDED MODE THD (dB) 0.47µF VDD = 5V SINGLE-ENDED MODE –70 –80 *ADDITIONAL PINS OMITTED FOR CLARITY. VDD = 5V/3V DIFFERENTIAL MODE –90 Figure 23. Single-Ended Mode Connection Diagram Differential Mode –110 –120 03713-020 –100 FSAMPLE = 1.5MSPS RANGE = 0 TO VREF 0 100 200 300 400 500 INPUT FREQUENCY (kHz) 600 The AD7933/AD7934 can have two differential analog input pairs by setting the MODE0 and MODE1 bits in the control register to 0 and 1, respectively. 700 Figure 22. THD vs. Analog Input Frequency for Various Supply Voltages Differential signals have some benefits over single-ended signals, including noise immunity based on the device’s common-mode rejection and improvements in distortion performance. Figure 24 defines the fully differential analog input of the AD7933/AD7934. Rev. B | Page 19 of 32 03713-031 –60 AD7933/AD7934 4.5 VIN– AD7933/ AD7934* *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 24. Differential Input Definition The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN− pins in each differential pair (that is, VIN+ − VIN−). VIN+ and VIN− should be simultaneously driven by two signals, each of amplitude VREF (or 2 × VREF depending on the range chosen) that are 180° out of phase. The amplitude of the differential signal is, therefore, −VREF to +VREF peak-to-peak (that is, 2 × VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals (that is (VIN+ + VIN−)/2) and is, therefore, the voltage on which the two inputs are centered. This results in the span of each input being CM ± VREF/2. This voltage has to be set up externally and its range varies with the reference value, VREF. As the value of VREF increases, the common-mode range decreases. When driving the inputs with an amplifier, the actual common-mode range is determined by the output voltage swing of the amplifier. Figure 25 and Figure 26 show how the common-mode range typically varies with VREF for a 5 V power supply using the 0 V to VREF range or 2 × VREF range, respectively. The common mode must be in this range to guarantee the functionality of the AD7933/AD7934. When a conversion takes place, the common mode is rejected, resulting in a virtually noise-free signal of amplitude −VREF to +VREF corresponding to the digital codes of 0 to 1024 for the AD7933, and 0 to 4096 for the AD7934. If the 2 × VREF range is used, the input signal amplitude extends from −2 VREF to +2 VREF. 3.5 TA = 25°C 2.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.1 0.6 1.1 1.6 2.1 2.6 VREF (V) Figure 26. Input Common-Mode Range vs. VREF (2 × VREF Range, VDD = 5 V) Driving Differential Inputs Differential operation requires that VIN+ and VIN− be simultaneously driven with two equal signals that are 180° out of phase. The common mode must be set up externally and has a range that is determined by VREF, the power supply, and the particular amplifier used to drive the analog inputs. Differential modes of operation with either an ac or dc input provide the best THD performance over a wide frequency range. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform single-ended-to-differential conversion. Using an Op Amp Pair An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7933/AD7934. The circuit configurations shown in Figure 27 and Figure 28 show how a dual op amp converts a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. The AD8022 is a suitable dual op amp that can be used in this configuration to provide differential drive to the AD7933/AD7934. Take care when choosing the op amp; the selection depends on the required power supply and system performance objectives. The driver circuits in Figure 27 and Figure 28 are optimized for dc coupling applications requiring best distortion performance. 2.0 1.5 1.0 0.5 0 03713-033 COMMON-MODE RANGE (V) 3.0 3.5 03713-034 VREF p-p 4.0 COMMON-MODE RANGE (V) VIN+ 03713-032 COMMON-MODE VOLTAGE TA = 25°C VREF p-p 0 0.5 1.0 1.5 VREF (V) 2.0 2.5 Figure 25. Input Common-Mode Range vs. VREF (0 V to VREF Range, VDD = 5 V) 3.0 The circuit configuration shown in Figure 27 is configured to convert and level shift a single-ended, ground-referenced (bipolar) signal to a differential signal centered at the VREF level of the ADC. The circuit in Figure 28 converts a unipolar, single-ended signal into a differential signal. Rev. B | Page 20 of 32 AD7933/AD7934 220Ω VREF p-p 2 × VREF p-p 27Ω V– VREF AD7933/ AD7934 220Ω V+ 20kΩ VIN– VIN+ 220Ω 27Ω A AD7933/ AD7934* V– + 3.75V 2.5V 1.25V VIN– DC INPUT VOLTAGE VREF Figure 29. Pseudo Differential Mode Connection Diagram 0.47µF 10kΩ 220Ω VREF p-p V+ 27Ω GND V– 3.75V 2.5V 1.25V VIN+ 220Ω AD7933/ AD7934 220Ω V+ A 27Ω V– 10kΩ 3.75V 2.5V 1.25V ANALOG INPUT SELECTION As shown in Table 10, users can set up their analog input configuration by setting the values in the MODE0 and MODE1 bits in the control register. Assuming the configuration has been chosen, there are two different ways of selecting the analog input to be converted depending on the state of the SEQ0 and SEQ1 bits in the control register. Traditional Multichannel Operation (SEQ0 = SEQ1 = 0) VIN– VREF 0.47µF 03713-036 440Ω 0.47µF *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 27. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a Unipolar Differential Signal VREF + Figure 28. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal Any one of four analog input channels or two pairs of channels can be selected for conversion in any order by setting the SEQ0 and SEQ1 bits in the control register to 0. The channel to be converted is selected by writing to the address bits, ADD1 and ADD0, in the control register to program the multiplexer prior to the conversion. This mode of operation is that of a traditional multichannel ADC where each data write selects the next channel for conversion. Figure 30 shows a flowchart of this mode of operation. The channel configurations are shown in Table 10. POWER ON Another method of driving the AD7933/AD7934 is to use the AD8138 differential amplifier. The AD8138 can be used as a single-ended-to-differential amplifier, or differential-to-differential amplifier. The device is as easy to use as an op amp and greatly simplifies differential signal amplification and driving. WRITE TO THE CONTROL REGISTER TO SET UP OPERATING MODE, ANALOG INPUT AND OUTPUT CONFIGURATION SET SEQ0 = SEQ1 = 0. SELECT THE DESIRED CHANNEL TO CONVERT ON (ADD1 TO ADD0). ISSUE CONVST PULSE TO INITIATE A CONVERSION ON THE SELECTED CHANNEL. INITIATE A READ CYCLE TO READ THE DATA FROM THE SELECTED CHANNEL. Pseudo Differential Mode The AD7933/AD7934 can have two pseudo differential pairs by setting the MODE0 and MODE1 bits in the control register to 1 and 0, respectively. VIN+ is connected to the signal source and must have an amplitude of VREF (or 2 × VREF depending on the range chosen) to make use of the full dynamic range of the part. A dc input is applied to the VIN− pin. The voltage applied to this input provides an offset from ground or a pseudo ground for the VIN+ input. The benefit of pseudo differential inputs is that they separate the analog input signal ground from the ADC ground, allowing the cancellation of dc common-mode voltages. Typically, this range can extend to −0.3 V to +0.7 V when VDD = 3 V, or −0.3 V to +1.8 V when VDD = 5 V. Figure 29 shows a connection diagram for pseudo differential mode. INITIATE A WRITE CYCLE TO SELECT THE NEXT CHANNEL TO BE CONVERTED ON BY CHANGING THE VALUES OF BITS ADD2 TO ADD0 IN THE CONTROL REGISTER. SEQ0 = SEQ1 = 0. 03713-038 220Ω VIN+ 3.75V 2.5V 1.25V 03713-035 440Ω GND 03713-037 V+ Figure 30. Traditional Multichannel Operation Flow Chart Using the Sequencer: Consecutive Sequence (SEQ0 = 1, SEQ1 = 1) A sequence of consecutive channels can be converted beginning with Channel 0 and ending with a final channel selected by writing to the ADD1 and ADD0 bits in the control register. This is done by setting the SEQ0 and SEQ1 bits in the control register both to 1. Once the control register is written to, the next conversion is on Channel 0, then Channel 1, and so on until the channel selected by the Address Bit ADD1 and Address Bit ADD0 is reached. The ADC then returns to Channel 0 and Rev. B | Page 21 of 32 AD7933/AD7934 starts the sequence again. The WR input must be kept high to ensure that the control register is not accidentally overwritten and the sequence interrupted. This pattern continues until the AD7933/AD7934 is written to. Figure 31 shows the flowchart of the consecutive sequence mode. The performance of the part with different reference values is shown in Figure 9 to Figure 11. The value of the reference sets the analog input span and the common-mode voltage range. Errors in the reference source result in gain errors in the AD7933/AD7934 transfer function and add to the specified full-scale errors on the part. POWER ON Table 12 lists suitable voltage references available from Analog Devices that can be used. Figure 33 shows a typical connection diagram for an external reference. WRITE TO THE CONTROL REGISTER TO SET UP OPERATING MODE, ANALOG INPUT AND OUTPUT CONFIGURATION SELECT FINAL CHANNEL (ADD1 AND ADD0) IN CONSECUTIVE SEQUENCE. SET SEQ0 = 1 SEQ1 = 1. Table 12. Examples of Suitable Voltage References Reference AD780 ADR421 ADR420 03713-039 CONTINUOUSLY CONVERT ON A CONSECUTIVE SEQUENCE OF CHANNELS FROM CHANNEL 0 UP TO AND INCLUDING THE PREVIOUSLY SELECTED FINAL CHANNEL ON ADD1 AND ADD0 WITH EACH CONVST PULSE. Figure 31. Consecutive Sequence Mode Flow Chart Output Voltage (V) 2.5/3 2.5 2.048 Initial Accuracy (% maximum) 0.04 0.04 0.05 Operating Current (μA) 1000 500 500 REFERENCE BUFFER ADC AD7933/ AD7934 03713-040 REFERENCE VREFIN/ VREFOUT Figure 32. Internal Reference Circuit Block Diagram Alternatively, an external reference can be applied to the VREFIN/VREFOUT pin of the AD7933/AD7934. An external reference input is selected by setting the REF bit in the internal control register to 0. The external reference input range is 0.1 V to VDD. It is important to ensure that, when choosing the reference value, the maximum analog input range (VIN MAX) is never greater than VDD + 0.3 V to comply with the maximum ratings of the device. For example, if operating in differential mode and the reference is sourced from VDD, the 0 V to 2 × VREF range cannot be used. This is because the analog input signal range now extends to 2 × VDD, which exceeds the maximum rating conditions. In the pseudo differential modes, the user must ensure that VREF + VIN− ≤ VDD when using the 0 V to VREF range, or when using the 2 × VREF range that 2 × VREF + VIN− ≤ VDD. AD7933/ AD7934* AD780 NC VDD 0.1µF 10nF 0.1µF 1 O/P SELECT 8 2 +VIN 3 TEMP VOUT 6 4 GND TRIM 5 7 NC VREF NC 2.5V NC 0.1µF NC = NO CONNECT *ADDITIONAL PINS OMITTED FOR CLARITY. 03713-041 The AD7933/AD7934 can operate with either the on-chip reference or an external reference. The internal reference is selected by setting the REF bit in the internal control register to 1. A block diagram of the internal reference circuitry is shown in Figure 32. The internal reference circuitry includes an on-chip 2.5 V band gap reference and a reference buffer. When using the internal reference, decouple the VREFIN/VREFOUT pin to AGND with a 0.47 μF capacitor. This internal reference not only provides the reference for the analog-to-digital conversion, but it can also be used externally in the system. It is recommended that the reference output is buffered using an external precision op amp before applying it anywhere in the system. Figure 33. Typical VREF Connection Diagram Digital Inputs The digital inputs applied to the AD7933/AD7934 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the VDD + 0.3 V limit that is on the analog inputs. Another advantage of the digital inputs not being restricted by the VDD + 0.3 V limit is the fact that power supply sequencing issues are avoided. If any of these inputs are applied before VDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to VDD. VDRIVE Input The AD7933/AD7934 have a VDRIVE feature. VDRIVE controls the voltage at which the parallel interface operates. VDRIVE allows the ADC to easily interface to 3 V and 5 V processors. For example, if the AD7933/AD7934 are operated with a VDD of 5 V, and the VDRIVE pin is powered from a 3 V supply, the AD7933/AD7934 have better dynamic performance with a VDD of 5 V while still being able to interface to 3 V processors. Ensure that VDRIVE does not exceed VDD by more than 0.3 V (see the Absolute Maximum Ratings section). In all cases, the specified reference is 2.5 V. Rev. B | Page 22 of 32 AD7933/AD7934 PARALLEL INTERFACE At the end of the conversion, BUSY goes low and can be used to activate an interrupt service routine. The CS and RD lines are then activated in parallel to read the 10 bits or 12 bits of conversion data. When power supplies are first applied to the device, a rising edge on CONVST is necessary to put the trackand-hold into track. The acquisition time of 125 ns minimum must be allowed before CONVST is brought low to initiate a conversion. The ADC then goes into hold on the falling edge of CONVST and back into track on the 13th rising edge of CLKIN after this (see Figure 34). When operating the device in autoshutdown or autostandby mode, where the ADC powers down at the end of each conversion, a rising edge on the CONVST signal is used to power up the device. The AD7933/AD7934 have a flexible, high speed, parallel interface. This interface is 10 bits (AD7933) or 12 bits (AD7934) wide and is capable of operating in either word (W/B tied high) or byte (W/B tied low) mode. The CONVST signal is used to initiate conversions and, when operating in autoshutdown or autostandby mode, it is used to initiate power-up. A falling edge on the CONVST signal is used to initiate conversions, and it also puts the ADC track-and-hold into track. Once the CONVST signal goes low, the BUSY signal goes high for the duration of the conversion. In between conversions, CONVST must be brought high for a minimum time of t1. This must happen after the 14th falling edge of CLKIN; otherwise, the conversion is aborted and the track-and-hold goes back into track. B t1 A CONVST 1 CLKIN 2 3 4 tCONVERT 5 12 13 14 t2 t20 BUSY t3 t9 INTERNAL TRACK/HOLD tACQUISITION CS t10 RD t12 t13 DB0 TO DB11 THREE-STATE t11 t14 DATA THREE-STATE tQUIET DB0 TO DB11 OLD DATA DATA Figure 34. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/B = 1) Rev. B | Page 23 of 32 03713-004 WITH CS AND RD TIED LOW AD7933/AD7934 Reading Data from the AD7933/AD7934 The CS and RD signals are gated internally and the level is triggered active low. In either word mode or byte mode, CS and RD can be tied together as the timing specifications for t10 and t11 are 0 ns minimum. This means the bus is constantly driven by the AD7933/AD7934. With the W/B pin tied logic high, the AD7933/AD7934 interface operates in word mode. In this case, a single read operation from the device accesses the conversion data-word on Pin DB0 to Pin DB11 (12-bit word) and Pin DB2 to DB11 (10-bit word). The DB8/HBEN pin assumes its DB8 function. With the W/B pin tied to logic low, the AD7933/AD7934 interface operates in byte mode. In this case, the DB8/HBEN pin assumes its HBEN function. The data is placed onto the data bus a time t13 after both CS and RD go low. The RD rising edge can be used to latch data out of the device. After a time, t14, the data lines become three-stated. Alternatively, CS and RD can be tied permanently low, and the conversion data is valid and placed onto the data bus a time, t9, before the falling edge of BUSY. Conversion data from the AD7933/AD7934 must be accessed in two read operations with eight bits of data provided on DB0 to DB7 for each of the read operations. The HBEN pin determines whether the read operation accesses the high byte or the low byte of the 12- or 10-bit word. For a low byte read, DB0 to DB7 provide the eight LSBs of the 12-bit word. For 10-bit operation, the two LSBs of the low byte are 0s and are followed by six bits of conversion data. For a high byte read, DB0 to DB3 provide the four MSBs of the 12-/10-bit word. DB4 and DB5 of the high byte provide the Channel ID. DB6 and DB7 are always 0. Note that if RD is pulsed during the conversion time, this causes a degradation in linearity performance of approximately 0.25 LSB. Reading during conversion, by way of tying CS and RD low, does not cause any degradation. Figure 34 shows the read cycle timing diagram for a 12- or 10-bit transfer. When operating in word mode, the HBEN input does not exist and only the first read operation is required to access data from the device. When operating in byte mode, the two read cycles shown in Figure 35 are required to access the full data-word from the device. HBEN/DB8 t15 t16 t15 t16 CS t11 RD t13 DB0 TO DB7 t17 t12 t14 LOW BYTE HIGH BYTE 03713-005 t10 Figure 35. AD7933/AD7934 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/B = 0) Rev. B | Page 24 of 32 AD7933/AD7934 Writing Data to the AD7933/AD7934 Figure 36 shows the write cycle timing diagram of the AD7933/AD7934 in word mode. When operating in word mode, the HBEN input does not exist and only one write operation is required to write the word of data to the device. Provide data on DB0 to DB11. When operating in byte mode, the two write cycles shown in Figure 37 are required to write the full data-word to the AD7933/AD7934. In Figure 37, the first write transfers the lower eight bits of the data-word from DB0 to DB7, and the second write transfers the upper four bits of the data-word. With W/B tied logic high, a single write operation transfers the full data-word on DB0 to DB11 to the control register on the AD7933/AD7934. The DB8/HBEN pin assumes its DB8 function. Data written to the AD7933/AD7934 should be provided on the DB0 to DB11 inputs, with DB0 being the LSB of the data-word. With W/B tied logic low, the AD7933/AD7934 requires two write operations to transfer a full 12-bit word. DB8/HBEN assumes its HBEN function. Data written to the AD7933/AD7934 should be provided on the DB0 to DB7 inputs. HBEN determines whether the byte written is high byte or low byte data. The low byte of the data-word has DB0 being the LSB of the full data-word. For the high byte write, HBEN should be high and the data on the DB0 input should be Data Bit 8 of the 12-bit word. When writing to the AD7933/AD7934, the top four bits in the high byte must be 0s. The data is latched into the device on the rising edge of WR. The data needs to be set up a time, t7, before the WR rising edge and held for a time, t8, after the WR rising edge. The CS and WR signals are gated internally. CS and WR can be tied together as the timing specifications for t4 and t5 are 0 ns minimum (assuming CS and RD have not already been tied together). CS t5 t6 t8 t7 DB0 TO DB11 03713-002 t4 WR DATA Figure 36. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/B = 1) HBEN/DB8 t18 t19 t18 t19 CS WR t5 t7 DB0 TO DB7 t17 t6 t8 LOW BYTE HIGH BYTE 03713-003 t4 Figure 37. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/B = 0) Rev. B | Page 25 of 32 AD7933/AD7934 POWER MODES OF OPERATION Autostandby (PM1 = 1; PM0 = 0) The AD7933/AD7934 have four different power modes of operation. These modes are designed to provide flexible power management options. Different options can be chosen to optimize the power dissipation/throughput rate ratio for differing applications. The mode of operation is selected by PM1 and PM0, the power management bits, in the control register (see Table 9 for details). When power is first applied to the AD7933/AD7934, an on-chip, power-on reset circuit ensures the default power-up condition is normal mode. In this mode of operation, the AD7933/AD7934 automatically enter standby mode at the end of each conversion, shown as Point A in Figure 34. When this mode is entered, all circuitry on the AD7933/AD7934 is powered down except for the reference and reference buffer. The track-and-hold goes into hold at this point and remains in hold as long as the device is in standby. The part remains in standby until the next rising edge of CONVST powers up the device. The power-up time required depends on whether the internal or external reference is used. With an external reference, the power-up time required is a minimum of 600 ns, while using the internal reference, the power-up time required is a minimum of 7 μs. The user should ensure this power-up time has elapsed before initiating another conversion as shown in Figure 38. This rising edge of CONVST also places the track-and-hold back into track mode. Note that, after power-on, track-and-hold is in hold mode, and the first rising edge of CONVST places the track-and-hold into track mode. Normal Mode (PM1 = PM0 = 0) This mode is intended for the fastest throughput rate performance wherein the user does not have to worry about any power-up times because the AD7933/AD7934 remain fully powered up at all times. At power-on reset, this mode is the default setting in the control register. Autoshutdown (PM1 = 0; PM0 = 1) In this mode of operation, the AD7933/AD7934 automatically enter full shutdown at the end of each conversion, shown at Point A in Figure 34 and Figure 38. In shutdown mode, all internal circuitry on the device is powered down. The part retains information in the control register during shutdown. The track-and-hold also goes into hold at this point and remains in hold as long as the device is in shutdown. The AD7933/AD7934 remains in shutdown mode until the next rising edge of CONVST (see Point B in Figure 34 and Figure 38). In order to keep the device in shutdown for as long as possible, CONVST should idle low between conversions, as shown in Figure 38. On this rising edge, the part begins to power up and the track-and-hold returns to track mode. The power-up time required is 10 ms minimum regardless of whether the user is operating with the internal or external reference. The user should ensure that the power-up time has elapsed before initiating a conversion. Full Shutdown Mode (PM1 = 1; PM0 = 1) When this mode is entered, all circuitry on the AD7933/AD7934 is powered down upon completion of the write operation, that is, on the rising edge of WR. The track-and-hold enters hold mode at this point. The part retains the information in the control register while in shutdown. The AD7933/AD7934 remain in full shutdown mode, with the track-and-hold in hold mode, until the power management bits (PM1 and PM0) in the control register are changed. If a write to the control register occurs while the part is in full shutdown mode, and the power management bits are changed to PM0 = PM1 = 0 (normal mode), the part begins to power up on the WR rising edge, and the track-and-hold returns to track. To ensure the part is fully powered up before a conversion is initiated, the power-up time of 10 ms minimum should be allowed before the CONVST falling edge; otherwise, invalid data is read. Note that all power-up times quoted apply with a 470 nF capacitor on the VREFIN pin. tPOWER-UP B A CONVST 1 14 1 14 03713-048 CLKIN BUSY Figure 38. Autoshutdown/Autostandby Mode Rev. B | Page 26 of 32 AD7933/AD7934 POWER vs. THROUGHPUT RATE Figure 40 shows a plot of the power vs. the throughput rate when operating in normal mode for both VDD = 5 V and 3 V. In both plots, the figures apply when using the internal reference. If an external reference is used, the power-up time reduces to 600 ns; therefore, the AD7933/AD7934 remains in standby for a greater time in every cycle. Additionally, the current consumption, when converting, should be lower than the specified maximum of 2.7 mA with VDD = 5 V, or 2.0 mA with VDD = 3 V, respectively. 1.8 TA = 25°C 1.6 1.4 10 TA = 25°C 9 8 VDD = 5V 7 POWER (mW) 6 5 4 VDD = 3V 3 2 03713-043 A considerable advantage of powering the ADC down after a conversion is that the power consumption of the part is significantly reduced at lower throughput rates. When using the different power modes, the AD7933/AD7934 are only powered up for the duration of the conversion. Therefore, the average power consumption per cycle is significantly reduced. Figure 39 shows a plot of power vs. throughput rate when operating in autostandby mode for both VDD = 5 V and 3 V. For example, if the device runs at a throughput rate of 10 kSPS, the overall cycle time is 100 μs. If the maximum CLKIN frequency of 25.5 MHz is used, the conversion time accounts for only 0.525 μs of the overall cycle time while the AD7933/AD7934 remains in standby mode for the remainder of the cycle. 1 0 0 200 400 600 800 1000 THROUGHPUT (kSPS) 1200 1400 1600 Figure 40. Power vs. Throughput in Normal Mode Using Internal Reference MICROPROCESSOR INTERFACING AD7933/AD7934 to ADSP-21xx Interface Figure 41 shows the AD7933/AD7934 interfaced to the ADSP-21xx series of DSPs as a memory-mapped device. A single wait state may be necessary to interface the AD7933/ AD7934 to the ADSP-21xx, depending on the clock speed of the DSP. The wait state can be programmed via the data memory wait state control register of the ADSP-21xx (see the ADSP-21xx family User’s Manual for details). The following instruction reads from the AD7933/AD7934: VDD = 5V MR = DM (ADC) where ADC is the address of the AD7933/AD7934. 1.0 DSP/USER SYSTEM 0.8 VDD = 3V A0 TO A15 AD7933/ AD7934* ADSP-21xx* 0.4 0.2 0 CONVST ADDRESS BUS 0 20 40 60 80 100 THROUGHPUT (kSPS) 120 ADDRESS DECODER DMS IRQ2 140 Figure 39. Power vs. Throughput in Autostandby Mode Using Internal Reference CS BUSY WR WR RD RD DB0 TO DB11 D0 TO D23 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 41. Interfacing to the ADSP-21xx Rev. B | Page 27 of 32 03713-044 0.6 03713-042 POWER (mW) 1.2 AD7933/AD7934 DSP/USER SYSTEM AD7933/AD7934 to ADSP-21065L Interface Figure 42 shows a typical interface between the AD7933/AD7934 and the ADSP-21065L SHARC® processor. This interface is an example of one of three DMA handshake modes. The MSX control line is actually three memory select lines. Internal ADDR25 to 24 are decoded into MS3 to 0, these lines are then asserted as chip selects. The DMAR1 (DMA Request 1) is used in this setup as the interrupt to signal the end of the conversion. The rest of the interface is standard handshaking operation. A0 TO A15 TMS32020/ TMS320C25/ TMS320C50* IS CONVST ADDRESS BUS AD7933/ AD7934* ADDRESS EN DECODER CS READY TMS320C25 ONLY MSC STRB WR R/W DSP/USER SYSTEM INTX BUSY DMD0 TO DMD15 MSX AD7933/ AD7934* ADDRESS LATCH *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 43. Interfacing to TMS32020/TMS320C25/TMS320C5x ADDRESS BUS ADSP-21065L* ADDRESS DECODER DMAR1 CS AD7933/AD7934 to 80C186 Interface BUSY Figure 44 shows the AD7933/AD7934 interfaced to the 80C186 microprocessor. The 80C186 DMA controller provides two independent, high speed DMA channels where data transfers can occur between memory and I/O spaces. Each data transfer consumes two bus cycles, one cycle to fetch data and the other to store data. After the AD7933/AD7934 finish a conversion, the BUSY line generates a DMA request to Channel 1 (DRQ1). Because of the interrupt, the processor performs a DMA read operation, which also resets the interrupt latch. Sufficient priority must be assigned to the DMA channel to ensure that the DMA request is serviced before the completion of the next conversion. RD RD WR WR DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY. 03713-045 DB0 TO DB11 D0 TO D31 DB11 TO DB0 DATA BUS 03713-046 CONVST ADDRESS BUS Figure 42. Interfacing to the ADSP-21065L AD7933/AD7934 to TMS32020, TMS320C25, and TMS320C5x Interface Parallel interfaces between the AD7933/AD7934 and the TMS32020, TMS320C25 and TMS320C5x family of DSPs are shown in Figure 43. Select the memory-mapped address for the AD7933/AD7934 to fall in the I/O memory space of the DSPs. The parallel interface on the AD7933/AD7934 is fast enough to interface to the TMS32020 with no extra wait states. If high speed glue logic, such as 74AS devices, is used to drive the RD and the WR lines when interfacing to the TMS320C25, no wait states are necessary. However, if slower logic is used, data accesses may be slowed sufficiently when reading from, and writing to, the part to require the insertion of one wait state. Extra wait states are necessary when using the TMS320C5x at their fastest clock speeds (see the TMS320C5x User’s Guide for details). MICROPROCESSOR/ USER SYSTEM AD0 TO AD15 A16 TO A19 ALE ADDRESS/DATA BUS CONVST ADDRESS LATCH AD7933/ AD7934* ADDRESS BUS 80C186* ADDRESS DECODER DRQ1 Q CS R S BUSY RD RD WR WR DATA BUS DB0 TO DB11 Data is read from the ADC using the following instruction: *ADDITIONAL PINS OMITTED FOR CLARITY. IN D, ADC Figure 44. Interfacing to the 80C186 where: D is the data memory address. ADC is the AD7933/AD7934 address. Rev. B | Page 28 of 32 03713-047 ADDR 0 TO ADDR23 RD AD7933/AD7934 APPLICATION HINTS GROUNDING AND LAYOUT Design the printed circuit board that houses the AD7933/AD7934 so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Generally, a minimum etch technique is best for ground planes because it offers optimum shielding. Join digital and analog ground planes in only one place, establishing a star ground point connection as close as possible to the ground pins on the AD7933/AD7934. Avoid running digital lines under the device because this couples noise onto the die. However, the analog ground plane should be allowed to run under the AD7933/AD7934 to avoid noise coupling. To provide low impedance paths and reduce the effects of glitches on the power supply line, use as large a trace as possible on the power supply lines to the AD7933/AD7934. Shield fast switching signals, such as clocks, with digital ground to avoid radiating noise to other sections of the board, and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough through the board, run traces on opposite sides of the board at right angles to each other. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is also important. Decouple all analog supplies with 10 μF tantalum capacitors in parallel with 0.1 μF capacitors to GND. To achieve the best performance from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 μF capacitors should have a low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types or surface-mount types. These types of capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. EVALUATING THE AD7933/AD7934 PERFORMANCE The recommended layout for the AD7933/AD7934 is outlined in the evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7933/AD7934 evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate and evaluate the ac and dc performance of the AD7933/AD7934. The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7933/AD7934. The software and documentation are on the CD that ships with the evaluation board. Rev. B | Page 29 of 32 AD7933/AD7934 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 1 6.40 BSC 14 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 COPLANARITY 0.10 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 45. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters ORDERING GUIDE Model AD7933BRU AD7933BRU-REEL AD7933BRU-REEL7 AD7933BRUZ 2 AD7933BRUZ-REEL72 AD7934BRU AD7934BRU-REEL AD7934BRU-REEL7 AD7934BRUZ2 AD7934BRUZ-REEL72 EVAL-AD7933CB 3 EVAL-AD7934CB3 EVAL-CONTROL-BRD2 4 Temperature Range −40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C −40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Linearity Error (LSB) 1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 1 Package Description 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP Evaluation Board Evaluation Board Controller Board Package Option RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 Linearity error here refers to integral linearity error. Z = Pb-free part. 3 This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes. 4 The evaluation board controller is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the letters CB. The following needs to be ordered to obtain a complete evaluation kit: the ADC evaluation board (for example, EVAL-AD7934CB), the EVAL-CONTROL-BRD2, and a 12 V ac transformer. See the relevant evaluation board data sheet for more details. 2 Rev. B | Page 30 of 32 AD7933/AD7934 NOTES Rev. B | Page 31 of 32 AD7933/AD7934 NOTES ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03713-0-2/07(B) Rev. B | Page 32 of 32