a FEATURES Four 8-Bit DACs with Output Amplifiers Separate Reference Input for Each DAC mP Compatible with Double-Buffered Inputs Simultaneous Update of All Four Outputs Operates with Single or Dual Supplies Extended Temperature Range Operation No User Trims Required Skinny 24-Pin DIP, SOIC and 28-Terminal Surface Mount Packages LC2MOS Quad 8-Bit DAC with Separate Reference Inputs AD7225 FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The AD7225 contains four 8-bit voltage output digital-toanalog converters, with output buffer amplifiers and interface logic on a single monolithic chip. Each D/A converter has a separate reference input terminal. No external trims are required to achieve full specified performance for the part. The double-buffered interface logic consists of two 8-bit registers per channel–an input register and a DAC register. Control inputs A0 and A1 determine which input register is loaded when WR goes low. Only the data held in the DAC registers determines the analog outputs of the converters. The doublebuffering allows simultaneous update of all four outputs under control of LDAC. All logic inputs are TTL and CMOS (5 V) level compatible and the control logic is speed compatible with most 8-bit microprocessors. PRODUCT HIGHLIGHTS 1. DACs and Amplifiers on CMOS Chip The single-chip design of four 8-bit DACs and amplifiers allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. Its pinout is aimed at optimizing board layout with all analog inputs and outputs at one end of the package and all digital inputs at the other. 2. Single or Dual Supply Operation The voltage-mode configuration of the AD7225 allows single supply operation. The part can also be operated with dual supplies giving enhanced performance for some parameters. Specified performance is guaranteed for input reference voltages from +2 V to +12.5 V when using dual supplies. The part is also specified for single supply operation using a reference of +10 V. Each output buffer amplifier is capable of developing +10 V across a 2 kΩ load. 3. Versatile Interface Logic The AD7225 has a common 8-bit data bus with individual DAC latches, providing a versatile control architecture for simple interface to microprocessors. The double-buffered interface allows simultaneous update of the four outputs. The AD7225 is fabricated on an all ion-implanted high-speed Linear Compatible CMOS (LC2MOS) process which has been specifically developed to integrate high speed digital logic circuits and precision analog circuitry on the same chip. 4. Separate Reference Input for Each DAC The AD7225 offers great flexibility in dealing with input signals with a separate reference input provided for each DAC and each reference having variable input voltage capability. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD7225–SPECIFICATIONS DUAL SUPPLY (VDD = 11.4 V to 16.5 V, VSS = –5 V 6 10%; AGND = DGND = O V; VREF = +2 V to (VDD – 4 V)1 unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.) Parameter K, B Versions2 L, C Versions2 T Version U Version Units STATIC PERFORMANCE Resolution Total Unadjusted Error Relative Accuracy Differential Nonlinearity Full-Scale Error Full-Scale Temp. Coeff. Zero Code Error @ 25°C TMIN to TMAX Zero Code Error Temp Coeff. 8 ±2 ±1 ±1 ±1 ±5 ± 25 ± 30 ± 30 8 ±1 ± 1/2 ±1 ± 1/2 ±5 ± 15 ± 20 ± 30 8 ±2 ±1 ±1 ±1 ±5 ± 25 ± 30 ± 30 8 ±1 ± 1/2 ±1 ± 1/2 ±5 ± 15 ± 20 ± 30 Bits LSB max LSB max LSB max LSB max ppm/°C typ mV max mV max µV/°C typ REFERENCE INPUT Voltage Range Input Resistance Input Capacitance 3 Channel-to-Channel Isolation 3 AC Feedthrough 3 2 to (VDD – 4) 11 100 60 –70 2 to (VDD – 4) 11 100 60 –70 2 to (VDD – 4) 11 100 60 –70 2 to (VDD – 4) 11 100 60 –70 V min to V max kΩ min pF max Occurs when each DAC is loaded with all 1s. dB min VREF = 10 V p-p Sine Wave @ 10 kHz dB max VREF = 10 V p-p Sine Wave @ 10 kHz DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Leakage Current Input Capacitance 3 Input Coding 2.4 0.8 ±1 8 Binary 2.4 0.8 ±1 8 Binary 2.4 0.8 ±1 8 Binary 2.4 0.8 ±1 8 Binary V min V max µA max pF max Conditions/Comments VDD = +15 V ± 5%, VREF = +10 V Guaranteed Monotonic VDD = 14 V to 16.5 V, V REF = +10 V VIN = 0 V or VDD DYNAMIC PERFORMANCE Voltage Output Slew Rate 3 Voltage Output Settling Time 3 Positive Full-Scale Change Negative Full-Scale Change Digital Feedthrough 3 Digital Crosstalk 3 Minimum Load Resistance 2.5 2.5 2.5 2.5 V/µs min 5 5 50 50 2 5 5 50 50 2 5 5 50 50 2 5 5 50 50 2 µs max µs max nV secs typ nV secs typ kΩ min POWER SUPPLIES VDD Range IDD ISS 11.4/16.5 10 9 11.4/16.5 10 9 11.4/16.5 12 10 11.4/16.5 12 10 V min to V max For Specified Performance mA max Outputs Unloaded; V IN = VINL or VINH mA max Outputs Unloaded; V IN = VINL or VINH 95 120 95 150 95 150 ns min ns min Write Pulse Width 0 0 0 0 0 0 ns min ns min Address to Write Setup Time 0 0 0 0 0 0 ns min ns min Address to Write Hold Time 70 90 70 90 70 90 ns min ns min Data Valid to Write Setup Time 10 10 10 10 10 10 ns min ns min Data Valid to Write Hold Time 95 120 95 150 95 150 ns min ns min Load DAC Pulse Width SWITCHING CHARACTERISTICS 3, 4 t1 @ 25°C 95 TMIN to TMAX 120 t2 @ 25°C 0 TMIN to TMAX 0 t3 @ 25°C 0 TMIN to TMAX 0 t4 @ 25°C 70 TMIN to TMAX 90 t5 @ 25°C 10 TMIN to TMAX 10 t6 @ 25°C 95 TMIN to TMAX 120 VREF = +10 V; Settling Time to ± 1/2 LSB VREF = +10 V; Settling Time to ± 1/2 LSB Code transition all 0s to all 1s. Code transition all 0s to all 1s. VOUT = +10 V NOTES 1 Maximum possible reference voltage. 2 Temperature ranges are as follows: K, L Versions: –40°C to +85°C B, C Versions: –40°C to +85°C T, U Versions: –55°C to +125°C 3 Sample Tested at 25°C to ensure compliance. 4 Switching characteristics apply for single and dual supply operation. Specifications subject to change without notice. –2– REV. B AD7225 SINGLE SUPPLY (VDD = +15 V 6 5%; VSS = AGND = DGND = O V; VREF = +10 V1 unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.) Parameter K, B Versions2 L, C Versions2 T Version U Version Units Conditions/Comments STATIC PERFORMANCE Resolution Total Unadjusted Error 3 Differential Nonlinearity 3 8 ±2 ±1 8 ±1 ±1 8 ±2 ±1 8 ±1 ±1 Bits LSB max LSB max Guaranteed Monotonic REFERENCE INPUT Input Resistance Input Capacitance 4 Channel-to-Channel Isolation 3, 4 AC Feedthrough3, 4, 5 11 100 60 –70 11 100 60 –70 11 100 60 –70 11 100 60 –70 kΩ min pF max dB min dB max Occurs when each DAC is loaded with all 1s. VREF = 10 V p-p Sine Wave @ 10 kHz VREF = 10 V p-p Sine Wave @ 10 kHz DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Leakage Current Input Capacitance 4 Input Coding 2.4 0.8 ±1 8 Binary 2.4 0.8 ±1 8 Binary 2.4 0.8 ±1 8 Binary 2.4 0.8 ±1 8 Binary V min V max µA max pF max 2 2 2 2 V/µs min 5 7 50 50 2 5 7 50 50 2 5 7 50 50 2 5 7 50 50 2 µs max µs max nV secs typ nV secs typ kΩ min 14.25/15.75 10 14.25/15.75 10 14.25/15.75 12 14.25/15.75 12 V min to V max For Specified Performance mA max Outputs Unloaded; V IN = VINL or VINH 95 120 95 150 95 150 ns min ns min Write Pulse Width 0 0 0 0 0 0 ns min ns min Address to Write Setup Time 0 0 0 0 0 0 ns min ns min Address to Write Hold Time 70 90 70 90 70 90 ns min ns min Data Valid to Write Setup Time 10 10 10 10 10 10 ns min ns min Data Valid to Write Hold Time 95 120 95 150 95 150 ns min ns min Load DAC Pulse Width DYNAMIC PERFORMANCE Voltage Output Slew Rate 4 Voltage Output Settling Time 4 Positive Full-Scale Change Negative Full-Scale Change Digital Feedthrough 3, 4 Digital Crosstalk 3, 4 Minimum Load Resistance POWER SUPPLIES VDD Range IDD SWITCHING CHARACTERISTICS 4 t1 @ 25°C 95 TMIN to TMAX 120 t2 @ 25°C 0 TMIN to TMAX 0 t3 @ 25°C 0 TMIN to TMAX 0 t4 @ 25°C 70 TMIN to TMAX 90 t5 @ 25°C 10 TMIN to TMAX 10 t6 @ 25°C 95 TMIN to TMAX 120 NOTES 1 Maximum possible reference voltage. 2 Temperature ranges are as follows: K, L Versions: –40°C to +85°C B, C Versions: –40°C to +85°C T, U Versions: –55°C to +125°C VIN = 0 V or VDD Settling Time to ± 1/2 LSB Settling Time to ± 1/2 LSB Code transition all 0s to all 1s. Code transition all 0s to all 1s. VOUT = +10 V 3 Sample Tested at 25°C to ensure compliance. Switching characteristics apply for single and dual supply operation. Specifications subject to change without notice. 4 ORDERING GUIDE Model1 Temperature Range Total Unadjusted Error Package Option2 AD7225KN AD7225LN AD7225KP AD7225LP AD7225KR AD7225LR AD7225BQ AD7225CQ –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C ± 2 LSB ± 1 LSB ± 2 LSB ± 1 LSB ± 2 LSB ± 1 LSB ± 2 LSB ± 1 LSB N-24 N-24 P-28A P-28A R-24 R-24 Q-24 Q-24 REV. B Model1 Temperature Range Total Unadjusted Error Package Option2 AD7225TQ AD7225UQ AD7225TE AD7225UE –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C ± 2 LSB ± 1 LSB ± 2 LSB ± 1 LSB Q-24 Q-24 E-28A E-28A NOTES 1 To order MIL-STD-883 processed parts, add /883B to part number. Contact your local sales office for military data sheet. 2 E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. –3– AD7225 ABSOLUTE MAXIMUM RATINGS 1 Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C Extended (T, U Versions) . . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD Power Dissipation (Any Package) to +75°C . . . . . . . . 500 mW Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 2.0 mW/°C Operating Temperature Commercial (K, L Versions) . . . . . . . . . . . –40°C to +85°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Outputs may be shorted to any voltage in the range V SS to VDD provided that the power dissipation of the package is not exceeded. Typical short circuit current for a short to AGND or V SS is 50 mA. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7225 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. DIP and SOIC PIN CONFIGURATIONS LCCC WARNING! ESD SENSITIVE DEVICE PLCC DIGITAL FEEDTHROUGH TERMINOLOGY TOTAL UNADJUSTED ERROR Digital Feedthrough is the glitch impulse transferred to the output of the DAC due to a change in its digital input code. It is specified in nV secs and is measured at VREF = 0 V. Total Unadjusted Error is a comprehensive specification which includes full-scale error, relative accuracy, and zero code error. Maximum output voltage is VREF – 1 LSB (ideal), where 1 LSB (ideal) is VREF/256. The LSB size will vary over the VREF range. Hence the zero code error will, relative to the LSB size, increase as VREF decreases. Accordingly, the total unadjusted error, which includes the zero code error, will also vary in terms of LSBs over the VREF range. As a result, total unadjusted error is specified for a fixed reference voltage of +10 V. DIGITAL CROSSTALK Digital Crosstalk is the glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter. It is specified in nV secs and is measured at VREF = 0 V. AC FEEDTHROUGH AC Feedthrough is the proportion of reference input signal which appears at the output of a converter when that DAC is loaded with all 0s. RELATIVE ACCURACY Relative Accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after allowing for zero code error and full-scale error and is normally expressed in LSBs or as a percentage of full-scale reading. CHANNEL-TO-CHANNEL ISOLATION Channel-to-channel isolation is the proportion of input signal from the reference of one DAC (loaded with all 1s) which appears at the output of one of the other three DACs (loaded with all 0s) The figure given is the worst case for the three other outputs and is expressed as a ratio in dBs. DIFFERENTIAL NONLINEARITY Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB max over the operating temperature range ensures monotonicity. FULL-SCALE ERROR Full-Scale Error is defined as: Measured Value – Zero Code Error – Ideal Value –4– REV. B Typical Performance Characteristics–AD7225 TA = 258C, VDD = +15 V, VSS = –5 V unless otherwise noted. REV. B Figure 1. Channel-to-Channel Matching Figure 2. Relative Accuracy vs. VREF Figure 3. Differential Nonlinearity vs. VREF Figure 4. Power Supply Current vs. Temperature Figure 5. Zero Code Error vs. Temperature Figure 6. Broadband Noise –5– AD7225 CIRCUIT INFORMATION D/A SECTION The AD7225 contains four, identical, 8-bit voltage mode digital-to-analog converters. Each D/A converter has a separate reference input. The output voltages from the converters have the same polarity as the reference voltages, allowing single supply operation. A novel DAC switch pair arrangement on the AD7225 allows a reference voltage range from +2 V to +12.5 V on each reference input. Each DAC consists of a highly stable, thin-film, R-2R ladder and eight high speed NMOS, single-pole, double-throw switches. The simplified circuit diagram for channel A is shown in Figure 7. Note that AGND (Pin 6) is common to all four DACs. Figure 8. Variation of ISINK with VOUT Additionally, the negative VSS gives more headroom to the output amplifiers which results in better zero code performance and improved slew rate at the output, than can be obtained in the single supply mode. Figure 7. D/A Simplified Circuit Diagram The input impedance at any of the reference inputs is code dependent and can vary from 11 kΩ minimum to infinity. The lowest input impedance at any reference input occurs when that DAC is loaded with the digital code 01010101. Therefore, it is important that the reference presents a low output impedance under changing load conditions. The nodal capacitance at the reference terminals is also code dependent and typically varies from 15 pF to 35 pF. DIGITAL SECTION The AD7225 digital inputs are compatible with either TTL or 5 V CMOS levels. All logic inputs are static protected MOS gates with typical input currents of less than 1 nA. Internal input protection is achieved by an on-chip distributed diode between DGND and each MOS gate. To minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (VDD and DGND) as practically possible. Each VOUT pin can be considered as a digitally programmable voltage source with an output voltage of: VOUTX = DX • VREFX where DX is fractional representation of the digital input code and can vary from 0 to 255/256. INTERFACE LOGIC INFORMATION The output impedance is that of the output buffer amplifier. The AD7225 contains two registers per DAC, an input register and a DAC register. Address lines A0 and A1 select which input register will accept data from the input port. When the WR signal is LOW, the input latches of the selected DAC are transparent. The data is latched into the addressed input register on the rising edge of WR. Table I shows the addressing for the input registers on the AD7225. OP-AMP SECTION Each voltage mode D/A converter output is buffered by a unity gain noninverting CMOS amplifier. This buffer amplifier is capable of developing +10 V across a 2 kΩ load and can drive capacitive loads of 3300 pF. The AD7225 can be operated single or dual supply; operating with dual supplies results in enhanced performance in some parameters which cannot be achieved with single supply operation. In single supply operation (VSS = 0 V = AGND) the sink capability of the amplifier, which is normally 400 µA, is reduced as the output voltage nears AGND. The full sink capability of 400 µA is maintained over the full output voltage range by tying VSS to –5 V. This is indicated in Figure 8. Table I. AD7225 Addressing A1 A0 Selected Input Register L L H H L H L H DAC A Input Register DAC B Input Register DAC C Input Register DAC D Input Register Settling-time for negative-going output signals approaching AGND is similarly affected by VSS. Negative-going settling-time for single supply operation is longer than for dual supply operation. Positive-going settling-time is not affected by VSS. –6– REV. B AD7225 Only the data held in the DAC register determines the analog output of the converter. The LDAC signal is common to all four DACs and controls the transfer of information from the input registers to the DAC registers. Data is latched into all four DAC registers simultaneously on the rising edge of LDAC. The LDAC signal is level triggered and therefore the DAC registers may be made transparent by tying LDAC LOW (in this case the outputs of the converters will respond to the data held in their respective input latches). LDAC is an asynchronous signal and is independent of WR. This is useful in many applications. However, in systems where the asynchronous LDAC can occur during a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched through to the output. In other words, if LDAC is activated prior to the rising edge of WR (or WR occurs during LDAC), then LDAC must stay LOW for t6 or longer after WR goes HIGH to ensure correct data is latched through to the output. Table II shows the truth table for AD7225 operation. Figure 9 shows the input control logic for the part and the write cycle timing diagram is given in Figure 10. Figure 9. Input Control Logic Table II. AD7225 Truth Table WR LDAC Function H L No Operation. Device not selected Input Register of Selected DAC Transparent Input Register of Selected DAC Latched All Four DAC Registers Transparent (i.e. Outputs respond to data held in respective input registers) Input Registers are Latched All Four DAC Registers Latched DAC Registers and Selected Input Register Transparent Output follows Input Data for Selected Channel. H H H H L H L L g g Figure 10. Write Cycle Timing Diagram GROUND MANAGEMENT AND LAYOUT Since the AD7225 contains four reference inputs which can be driven from ac sources (see AC REFERENCE SIGNAL section) careful layout and grounding is important to minimize analog crosstalk between the four channels. The dynamic performance of the four DACs depends upon the optimum choice of board layout. Figure 11 shows the relationship between input Figure 12. Suggested PCB Layout for AD7225. Layout Shows Component Side (Top View) Figure 11. Channel-to-Channel Isolation REV. B frequency and channel-to-channel isolation. Figure 12 shows a printed circuit board layout which is aimed at minimizing crosstalk and feedthrough. The four input signals are screened by AGND. VREF was limited to between 2 V and 3.24 V to avoid slew rate limiting effects from the output amplifier during measurements. –7– AD7225 SPECIFICATION RANGES Table III. Unipolar Code Table For the AD7225 to operate to rated specifications, its input reference voltage must be at least 4 V below the VDD power supply voltage. This voltage differential is the overhead voltage required by the output amplifiers. DAC Latch Contents MSB LSB The AD7225 is specified to operate over a VDD range from +12 V ± 5% to +15 V ± 10% (i.e., from +11.4 V to +16.5 V) with a VSS of –5 V ± 10%. Operation is also specified for a single +15 V ± 5% VDD supply. Applying a VSS of –5 V results in improved zero code error, improved output sink capability with outputs near AGND and improved negative going settling time. Performance is specified over a wide range of reference voltages from 2 V to (VDD – 4 V) with dual supplies. This allows a range of standard reference generators to be used such as the AD580, a +2.5 V bandgap reference and the AD584, a precision +10 V reference. Note that an output voltage range of 0 V to +10 V requires a nominal +15 V ± 5% power supply voltage. UNIPOLAR OUTPUT OPERATION This is the basic mode of operation for each channel of the AD7225, with the output voltage having the same positive polarity as VREF. The AD7225 can be operated single supply (VSS = AGND) or with positive/negative supplies (see op-amp section which outlines the advantages of having negative VSS). Connections for the unipolar output operation are shown in Figure 13. The voltage at any of the reference inputs must never be negative with respect to DGND. Failure to observe this precaution may cause parasitic transistor action and possible device destruction. The code table for unipolar output operation is shown in Table III. Analog Output 1111 1111 255 +V REF 256 1000 0001 129 +V REF 256 1000 0000 128 V REF +V REF =+ 2 256 0111 1111 127 +V REF 256 0000 0001 1 +V REF 256 0000 0000 0V ( ) 1 Note: 1 LSB = (V REF ) 2−8 = V REF 256 BIPOLAR OUTPUT OPERATION Each of the DACs of the AD7225 can be individually configured to provide bipolar output operation. This is possible using one external amplifier and two resistors per channel. Figure 14 shows a circuit used to implement offset binary coding (bipolar operation) with DAC A of the AD7225. In this case R2 R2 V OUT = 1 + ⋅ ( DAV REF ) – ⋅ (V REF ) R1 R1 With R1 = R2 VOUT = (2 DA – 1) • VREF where DA is a fractional representation of the digital word in latch A. (0 ≤ DA ≤ 255/256) Mismatch between R1 and R2 causes gain and offset errors and, therefore, these resistors must match and track over temperature. Once again the AD7225 can be operated in single supply or from positive/negative supplies. Table IV shows the digital code versus output voltage relationship for the circuit of Figure 14 with R1 = R2. Figure 13. Unipolar Output Circuit –8– REV. B AD7225 For a given VIN, increasing AGND above system GND will reduce the effective VDD–VREF which must be at least 4 V to ensure specified operation. Note that because the AGND pin is common to all four DACs, this method biases up the output voltages of all the DACs in the AD7225. Note that VDD and VSS of the AD7225 should be referenced to DGND. AC REFERENCE SIGNAL Figure 14. AD7225 Bipolar Output Circuit Table IV. Bipolar (Offset Binary) Code Table DAC Latch Contents MSB LSB Analog Output 1111 1111 127 +V REF 128 1000 0001 1 +V REF 128 1000 0000 0V 0111 1111 1 –V REF 128 0000 0001 127 –V REF 128 0000 0000 128 –V REF = –V REF 128 In some applications it may be desirable to have ac reference signals. The AD7225 has multiplying capability within the upper (VDD – 4 V) and lower (2 V) limits of reference voltage when operated with dual supplies. Therefore ac signals need to be ac coupled and biased up before being applied to the reference inputs. Figure 16 shows a sine wave signal applied to VREF A. For input signal frequencies up to 50 kHz the output distortion typically remains less than 0.1%. The typical 3 dB bandwidth figure for small signal inputs is 800 kHz. Figure 16. Applying an AC Signal to the AD7225 APPLICATIONS PROGRAMMABLE TRANSVERSAL FILTER AGND BIAS The AD7225 AGND pin can be biased above system GND (AD7225 DGND) to provide an offset “zero” analog output voltage level. Figure 15 shows a circuit configuration to achieve this for channel A of the AD7225. The output voltage, VOUT A, can be expressed as: VOUT A = VBIAS + DA (VIN) where DA is a fractional representation of the digital word in DAC latch A. (0 ≤ DA ≤ 255/256). A discrete-time filter may be described by either multiplication in the frequency domain or convolution in the time domain i.e. N Y ( ω ) = H ( ω ) X ( ω ) or yn = ∑ hkXn –k+1 k=1 The convolution sum may be implemented using the special structure known as the transversal filter (Figure 17). Basically, it consists of an N-stage delay line with N taps weighted by N coefficients, the resulting products being accumulated to form the output. The tap weights or coefficients hk are actually the nonzero elements of the impulse response and therefore determine the filter transfer function. A particular filter frequency response is realized by setting the coefficients to the appropriate values. This property leads to the implementation of transversal filters whose frequency response is programmable. Figure 15. AGND Bias Circuit Figure 17. Transversal Filter REV. B –9– AD7225 FILTER I/P ACCUMULATOR O/P VOUT A DELAYED I/P I/P VOUT B AD7820 Am29520 AD7225 ADC TLD QUAD DAC VOUT C FILTER O/P AD585 + SHA VOUT D SAMPLES SAMPLES VREF A h1 h2 VOUT A AD584 Am7224 +10V REF VREF A h3 VREF A VOUT A VOUT A Xn–1 Xn h4 FILTER I/P T VOUT A 1 Xn–2 Xn–3 T 2 h1 AD7226 VOUT DAC VREF VREF A h2 T 3 4 h3 h4 QUAD DAC VREF + FILTER O/P GAIN SET Yn TAP WEIGHTS Figure 18. Programmable Transversal Filter A 4-tap programmable transversal filter may be implemented using the AD7225 (Figure 18). The input signal is first sampled and converted to allow the tapped delay line function to be provided by the Am29520. The multiplication of delayed input samples by fixed, programmable up weights is accomplished by the AD7225, the four coefficients or reference inputs being set by the digital codes stored in the AD7226. The resultant products are accumulated to yield the convolution sum output sample which is held by the AD585. 0 –10 –20 filter with the coefficients indicated. Although the theoretical prediction does not take into account the quantization of the input samples and the truncation of the coefficients, nevertheless, there exists a good correlation with the actual performance of the transversal filter (Figure 20). DIGITAL WORD MULTIPLICATION Since each DAC of the AD7225 has a separate reference input, the output of one DAC can be used as the reference input for another. This means that multiplication of digital words can be performed (with the result given in analog form). For example, if the output from DACA is applied to VREF B then the output from DACB, VOUT B, can be expressed as: VOUT B = DA • DB • VREF A GAIN – dB –30 –40 h1 h2 h3 h4 –50 –60 = 0.117 = 0.417 = 0.417 = 0.417 where DA and DB are the fractional representations of the digital words in DAC latches A and B respectively. If DA = DB = D then the result is D2 • VREF A –70 In this manner, the four DACs can be used on their own or in conjunction with an external summing amplifier to generate complex waveforms. Figure 21 shows one such application. In this case the output waveform, Y, is represented by: –80 –90 –100 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 NORMALIZED FREQUENCY – f/fs Y = –(x4 + 2x3 + 3x2 + 2x + 4) • VIN Figure 19. Predicted (Theoretical) Response where x is the digital code which is applied to all four DAC latches. +15V 25kΩ VDD VIN VREF A 100kΩ 50kΩ VOUT A AD7225* 33kΩ VREF B VOUT B VREF C VOUT C VREF D VOUT D Y 50kΩ 100kΩ Figure 20. Actual Response Low pass, bandpass and high pass filters may be synthesized using this arrangement. The particular up weights needed for any desired transfer function may be obtained using the standard Remez Exchange Algorithm. Figure 19 shows the theoretical low pass frequency response produced by a 4-tap transversal –10– AGND DGND VSS *DIGITAL INPUTS OMITTED FOR CLARITY Figure 21. Complex Waveform Generation REV. B AD7225 MICROPROCESSOR INTERFACE A23 A15 ADDRESS BUS A8 8085A/ 8088 ADDRESS DECODE WR ALE ADDRESS BUS A1 A0 A1 LDAC AD7225* AS WR LATCH EN A0 A1 ADDRESS DECODE 68008 AD7225* EN WR LDAC R/W DB7 DTACK DB0 AD0 DB7 DB0 AD7 ADDRESS DATA BUS D7 *LINEAR CIRCUITRY OMITTED FOR CLARITY D0 Figure 22. AD7225 to 8085A/8088 Interface, Double-Buffered Mode ADDRESS BUS A0 R/W A0 A1 ADDRESS DECODE LDAC AD7225* EN WR E OR φ2 DB7 DB0 D7 D0 DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 23. AD7225 to 6809/6502 Interface, Single-Buffered Mode A15 Operating the AD7225 from dual supplies results in enhanced performance over single supply operation on a number of parameters as previously outlined. Some applications may require this enhanced performance, but may only have a single power supply rail available. The circuit of Figure 26 shows a method of generating a negative voltage using one CD4049, operated from a VDD of +15 V. Two inverters of the hex inverter chip are used as an oscillator. The other four inverters are in parallel and used as buffers for higher output current. The square-wave output is level translated to a negative-going signal, then rectified and filtered. The circuit configuration shown will provide an output voltage of –5.1 V for current loadings in the range 0.5 mA to 9 mA. This will satisfy the AD7225 ISS requirement over the commercial operating temperature range. ADDRESS BUS A8 1/6 CD4049AE A0 A1 Z-80 ADDRESS DECODE MREQ Figure 25. AD7225 to 68008 Interface, Single-Buffered Mode VSS GENERATION A15 6809/ 6502 1/6 CD4049AE LDAC 1/6 CD4049AE AD7225* EN 510k DB7 5.1k DB0 D0 1/6 CD4049AE 1/6 CD4049AE WR WR D7 DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY 0.02µF DATA BUS 1/6 CD4049AE + 510Ω 47µF –VOUT *LINEAR CIRCUITRY OMITTED FOR CLARITY 1N4001 1N4001 Figure 24. AD7225 to Z-80 Interface, Double-Buffered Mode + 47µF Figure 26. VSS Generation Circuit REV. B –11– 5V1 AD7225 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead SOIC (R-24) 24-Pin Cerdip (Q-24) 28-Terminal Leadless Ceramic Chip Carrier (E-28A) C927a–5–5/86 24-Pin Plastic (N-24) PRINTED IN U.S.A. 28-Lead PLCC (P-28A) –12– REV. B