AKM AKD4145 Digital btsc stereo encoder Datasheet

[AK4145]
AK4145
Digital BTSC Stereo Encoder
GENERAL DESCRIPTION
The AK4145 is a BTSC Encoder with D/A Converter, which is optimized for Digital AV application. The
AK4145 achieves high audio performance using a digital BTSC encoding architecture which requires no
alignment of external parts. The AK4145 supports major audio data formats (MSB justified, I2S, TDM) to
interface with usual DSP. Therefore, the AK4145 is suitable for the systems such as Digital STB/TV,
digital recorder.
FEATURES
† Alignment Free Digital BTSC Stereo Encoding
† Base band Composite Audio Output (Mono/Stereo)
† Digital Volume for Composite Audio Output
† Digital De-emphasis filter (32k/44.1k/48kHz)
† Stereo Digital Volume Control for Audio Input Data
† Soft Mute
† Stereo Matrix Control
† Sampling Rate (fs): 32k/44.1k/48kHz
† Master Clock: 256fs/384fs/512fs/768fs
† I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S
† Control: Standalone/I2C-bus Selectable
† Video Input for Pilot Synchronization
† S/(N+D): 0.01%
† S/N: 82dB
† Channel Separation: 47dB
† Power Supply: 1.7V ~ 1.9V, 2.7 ~ 3.6V
† Ta: -20 ~ 85°C
P/S
PDN
MCLK
FILT
TVDD
DVDD
FS1/SDA
VSS
PLL
µP
Interface
VCOM
DIF/SCL
AVDD
LRCK
BICK
SDTI
Audio
Data
Interface
De-emphasis,
DVOL,
Stereo Matrix
Digital
BTSC
Encoder
DATT
DAC
Sync
separator
MS0982-E-01
CA
CV/27M
2010/09
-1-
[AK4145]
■ Ordering Guide
-20 ∼ +85°C
Evaluation Board
AK4145ET
AKD4145
16pinTSSOP
■ Pin Layout
FILT
1
16
CA
PSN
2
15
AVDD
CV27M
3
14
VCOM
PDN
4
13
VSS
MCLK
5
12
DVDD
LRCK
6
11
TVDD
BICK
7
10
DIF/SCL
SDTI
8
9
FS/SDA
Top
View
MS0982-E-01
2010/09
-2-
[AK4145]
PIN/FUNCTION
No.
1
2
Pin Name
FILT
PSN
I/O
Function
Filter Pin, 4.7nF must be connected between FILT pin and VSS pin.
Parallel/Serial Select Pin
“L”: Serial control mode, “H”: Parallel control mode
3
CV27M
I
Composite Video or 27MHz Signal Input Pin.
4
PDN
I
Power-Down Mode Pin
When at “L”, the AK4145 is in the power-down mode and is held in reset.
The AK4145 must be reset once upon power-up.
5
MCLK
I
Master Clock Input Pin
6
LRCK
I
Channel Clock Input Pin
7
BICK
I
Audio Serial Data Clock Input Pin
8
SDTI
I
Audio Serial Data Input Pin
9
FS
I
Sampling Rate Control Pin in parallel control mode
SDA
I/O
Control Data Pin in serial control mode
10 DIF
I
Audio Data Interface Format Pin in parallel control mode
SCL
I
Control Data Clock Pin in serial control mode
11 TVDD
Digital I/O Power Supply Pin, DVDD(min:1.7V) ∼ 3.6V
12 DVDD
Digital Power Supply Pin, 1.7 ∼ 1.9V
13 VSS
Ground Pin
14 VCOM
O
Common Voltage Pin, AVDD/2
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a 10μF
electrolytic cap.
15 AVDD
Analog Power Supply Pin, 2.7 ∼ 3.6V
16 CA
O
Baseband Composite Audio Output Pin
Note: All input pins should not be left floating.
I
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
CV
FS(Parallel mode), DIF(Parallel mode)
Setting
Connect to VSS.
Connect to VDD or VSS.
■ Output Status at PDN pin = “L”
Below is the output status of each output pin when the PDN pin = “L”.
Pin#
1
9
14
16
Pin Name
FILT
SDA
VCOM
CA
Status
VSS
Hi-Z
VSS
VCOM(=VSS)
MS0982-E-01
2010/09
-3-
[AK4145]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Power Supply
Symbol
AVDD
DVDD
TVDD
IIN
VINA
VIND
Ta
Tstg
Input Current, Any Pin Except Supply
Analog Input Voltage (CV27M pin)
Digital Input Voltage (Note 2)
Ambient Temperature (powered applied)
Storage Temperature
Note 1. All voltages with respect to ground.
Note 2. PSN, PDN, MCLK, LRCK, BICK, SDTI, FS/SDA, DIF/SCL pin
min
-0.3
-0.3
-0.3
-0.3
-0.3
-20
-65
max
4.3
2.4
4.3
±10
AVDD+0.3
TVDD+0.3
85
150
Units
V
V
V
mA
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Power Supply
Symbol
AVDD
DVDD
TVDD
min
2.7
1.7
DVDD
typ
3.3
1.8
3.3
max
3.6
1.9
3.6
Units
V
V
V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0982-E-01
2010/09
-4-
[AK4145]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=TVDD=3.3V; DVDD=1.8V; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 16bit Data;
Measurement frequency=50Hz ∼ 13kHz; unless otherwise specified)
Parameter
min
typ
max
Units
Resolution
16
Bits
Composite Audio Output Characteristics
Output Voltage
2.2
Vp-p
Load Resistance
(Note 3)
5
kΩ
Load Capacitance
25
pF
BTSC Encoder Characteristics (Note 4)
S/(N+D)
Mono (1kHz, 100%EIM)
0.01
0.3
%
Stereo (1kHz, 100%EIM. L or R)
0.01
0.3
%
S/N
Mono (input off)
75
82
dB
(A-weighted)
Stereo (input off)
75
82
dB
Stereo Separation
1kHz
47
dB
20Hz~500Hz
30
dB
500Hz~5kHz
27
dB
5kHz~13kHz
23
dB
Frequency response Mono (20~13kHz)
-1
1
dB
Stereo (20~13kHz)
-1
1
dB
Video Sync Input Characteristics
Video Input Sync Level
100
mVp-p
Video Input Current
2
uA
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”):
mA
AVDD
14
mA
DVDD
9
mA
TVDD
1
mA
AVDD+DVDD+TVDD
30
Power down mode (PDN pin = “L”): (Note 5)
μA
AVDD
10
100
DVDD
10
100
μA
TVDD
10
100
μA
Note 3. AC-load.
Note 4. Received by the Belar TVM230 (BTSC Decoder) and measured by the Audio Precision (System Two). Refer to
the evaluation board manual.
Note 5. All digital input pins are held to VSS.
MS0982-E-01
2010/09
-5-
[AK4145]
DC CHARACTERISTICS
(Ta=-20∼ 85°C; AVDD=TVDD=1.7~3.6V, DVDD=1.7~1.9V)
Parameter
Symbol
min
High-Level Input Voltage
TVDD < 2.7V
VIH
80%TVDD
VIH
80%TVDD
TVDD ≥ 2.7V(PSN pin)
VIH
70%TVDD
TVDD ≥ 2.7V(except PSN pin)
Low-Level Input Voltage
VIL
TVDD < 2.7V
VIL
TVDD ≥ 2.7V(PSN pin)
VIL
TVDD ≥ 2.7V(except PSN pin)
Low-Level Output Voltage (SDA pin: Iout= 3mA)
VOL
Input Leakage Current
Iin
-
typ
Max
Units
-
-
V
V
V
V
-
20%TVDD
20%TVDD
30%TVDD
0.3
± 10
-
SWITCHING CHARACTERISTICS
(Ta=-20∼ 85°C; AVDD=2.7 ~ 3.6V, TVDD=1.7~3.6V, DVDD=1. 7~1.9V)
Parameter
Symbol
min
fCLK
8.192
Master Clock Frequency
dCLK
40
Duty Cycle
LRCK Frequency
fs
32
Duty Cycle
Duty
45
Audio Interface Timing
tBCK
1/128fs
BICK Period
tBCKL
30
BICK Pulse Width Low
tBCKH
30
Pulse Width High
tBLR
20
BICK rising to LRCK Edge
(Note 6)
tLRB
20
LRCK Edge to BICK rising
(Note 6)
tSDH
20
SDTI Hold Time
tSDS
20
SDTI Setup Time
Control Interface Timing (I2C Bus)
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
(Note 7)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
Capacitive load on bus
Cb
0
Reset Timing
tPD
150
PDN Pulse Width
(Note 8)
Note 6. BICK rising edge must not occur at the same time as LRCK edge.
Note 7. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 8. The AK4145 can be reset by bringing the PDN pin = “L”.
Note 9. I2C-bus is a trademark of NXP B.V.
MS0982-E-01
typ
max
36.8640
60
48
55
V
V
V
μA
Units
MHz
%
kHz
%
ns
ns
ns
ns
ns
ns
ns
400
-
kHz
μs
μs
0.3
0.3
50
400
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
ns
2010/09
-6-
[AK4145]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 1. Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Figure 2. Serial Interface Timing
MS0982-E-01
2010/09
-7-
[AK4145]
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
Figure 3. I2C Bus mode Timing
tPD
PDN
VIL
Figure 4. Power-down Timing
MS0982-E-01
2010/09
-8-
[AK4145]
OPERATION OVERVIEW
■ Parallel/Serial Control Mode
Pins (Parallel Control Mode) or registers (Serial Control Mode) control each function of the AK4145 (Table 1). In
Parallel Control Mode (PSN pin = “H”), register settings are ignored, and pin settings are ignored in Serial Control Mode
(PSN pin = “L”). In Serial Control Mode, the default state is in software reset and soft-muted. Write “1” to RSTN bit and
“0” to SMUTE bit for normal operation. The PSN pin must be fixed during power-up.
Function
Sampling Rate
Parallel mode
32k, 48k
I2S,
MSB justified
Serial mode
32k, 44.1k, 48k
I2S,
Audio Data Format
MSB justified,
LSB justified
Stereo Volume Control
X
De-emphasis Filter
X
Soft Mute
X
MONO Mode
X
Audio Composite Volume Control
X
Video Signal
Video Signal,
Sync Source for Pilot Generation
27MHz Clock
Stereo Matrix Control
X
Table 1. Function List (X: Available, -: Not available)
■ System Reset and Power-down Mode
The AK4145 should be reset once by bringing the PDN pin = “L” upon power-up.
PDN pin: Power down pin
“H”: Normal operation
“L”: Device power down. All registers are initialized.
■ Audio Sampling Rate
The AK4145 supports 3 sampling rates (32kHz, 44.1kHz and 48kHz). The FS1-0 bits select the sampling rate in serial
control mode. The FS1 pin is only available in parallel control mode (Table 2, Table 3). These bits and pin can be changed
without a reset by the PDN pin.
FS1bit
FS0 bit
Sampling rate
0
0
32kHz
0
1
44.1kHz
1
0
48kHz
(default)
1
1
(Reserved)
Table 2. Sampling rate select in serial control mode
FS1pin
Sampling rate
0
32kHz
1
48kHz
Table 3. Sampling rate select in parallel control mode
MS0982-E-01
2010/09
-9-
[AK4145]
■ Power-on Sequence
After setting the PDN pin “L” to “H”, the AK4145 remains in power-down mode until a LRCK rising edge after MCLK.
When the MCLK and LRCK are provided, the AK4145 exits reset state, power-on the voltage reference circuit, and the
PLL will be locked. The output signal is masked until when the PLL locks to the MCLK (also RSTN bit = “1” is required
in serial mode).
Power off
Power on
AVDD
TVDD
AVDD
PDN (I)
···
MC LK (I)
LRCK (I)
(1)
(PLL: Internal)
(2)
(PLL Lock : Internal)
CA=VC OM≅AVDD/2
CA (O)
CA=VCOM=VSS
Normal Operat ion
(3)
Pow er-down state
(1) Waiting the MCLK &L RCK . PLL=free run
(2) PLL Locking Time
(3) Data output is Muted
Figure 5. Power-on Sequence
Note:
When changing the sampling rate, the PLL lock signal and BTSC encoder are initialized. The output is muted until the
PLL re-locks.
■ System Clock
The external clocks required to operate the AK4145 are MCLK, LRCK and BICK. The AK4145 supports 256fs, 384fs,
512fs and 768fs as master clock (MCLK). The AK4145 should be reset by the PDN pin = “L” after these clocks are
provided. After exiting reset by the PDN pin = “H”, the AK4145 remains in power-down mode until a LRCK rising edge
after MCLK.
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
512fs
768fs
12.2880MHz 16.3840MHz
24.576MHz
16.9344MHz 22.5792MHz
33.8688MHz
18.4320MHz 24.5760MHz
36.8640MHz
Table 4. System clock example
MS0982-E-01
BICK
64fs
128fs
2.0480MHz 4.0960MHz
2.8224MHz 5.6448MHz
3.0720MHz 6.1440MHz
2010/09
- 10 -
[AK4145]
■ Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. In serial control mode (P/S pin = “L”), the DIF0-2 bits
select five serial data modes as shown in Table 5. In parallel control mode (P/S pin = “H”), the DIF pin select two serial
data modes as shown in Table 6. In all modes the serial data is MSB-first, 2’s compliment format and it is latched on the
rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
Bit
0
0
0
0
1
DIF1
Bit
0
0
1
1
0
DIF0
SDTI Format
BICK
bit
0
16bit LSB Justified
≥32fs
1
20bit LSB Justified
≥40fs
0
24bit MSB Justified
≥48fs
1
16/24bit I2S Compatible
32fs or ≥48fs
0
24bit LSB Justified
≥48fs
Table 5. Audio Data Formats (Serial control mode)
Mode
2
3
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
DIF
SDTI Format
BICK
pin
0
24bit MSB Justified
≥48fs
1
16/24bit I2S Compatible
32fs or ≥48fs
Table 6. Audio Data Formats (Parallel control mode)
(default)
Figure
Figure 3
Figure 4
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15
0
14
1
6
5
14
4
15
3
2
16
17
1
0
31
15
0
14
1
6
5
14
4
15
3
16
2
17
1
0
31
15
0
14
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15
14
0
15
Don’t care
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
MS0982-E-01
2010/09
- 11 -
[AK4145]
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
0
1
0
1
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
22
21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1/4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
0
1
Don’t care
23
22
0
1
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
MS0982-E-01
2010/09
- 12 -
[AK4145]
■ Input Level to BTSC Encoder
The AK4145 is designed to be 100% modulation of L+R signal when L=R= 50% (approx. -6dBFS) signal data is input. In
addition to this -6dBFS, the BTSC standard contains the pre-emphasis filter. To prevent the clipping in a BTSC encoder
of the AK4145, following maximum input levels are recommended. The input data can be attenuated by controlling the
Stereo Volume Control registers (L7-0, R7-0 bits).
Maximum Input Level
to BTSC Encoder[dBFS]
20~1000
-7
2500
-10
5000
-14
8000
-15
13000
-22
Table 7. Maximum Input Level to BTSC Encoder
Frequency[Hz]
■ Stereo Volume Control (DVOL)
The AK4145 has a stereo digital volume control (DVOL. 256 levels, 0.5dB step, Mute). The L7-0, R7-0 bits control the
gain. The gain ranges from +31.0dB to –96.0dB, or MUTE. When the VOLC bit = “1” (default), the L7-0 bits control gain
for both Lch and Rch. When the VOLC bit = “0”, the L7-0 bits control gain for Lch and R7-0 bits control gain for Rch.
This volume has a soft transition function. When changing levels, transitions are executed in soft changes; thus no
switching noise occurs during these transitions. The transition time of 1 level and all levels are shown in Table 8. In
parallel control mode, volume control is fixed to 0dB.
DVOL Transition Time
1 Level
0dB to -96dB
+31.0dB to -96dB
4LRCK
768LRCK
1016LRCK
Table 8. DVOL Transition Time
L7-0
00H
01H
:
3DH
3EH
3FH
FDH
FEH
FFH
R7-0
00H
01H
:
3DH
3EH
3FH
FDH
FEH
FFH
Gain
+31.0dB
+30.5dB
:
+0.5dB
0dB
-0.5dB
:
-95.5dB
-96.0dB
MUTE (-∞)
Table 9. Lch Digital Volume
Gain
+31.0dB
+30.5dB
:
+0.5dB
0dB
-0.5dB
:
-95.5dB
-96.0dB
MUTE (-∞)
Table 10. Rch Digital Volume
MS0982-E-01
(default)
(default)
2010/09
- 13 -
[AK4145]
■ De-emphasis Filter
A digital de-emphasis filter is built-in (tc = 50/15µs) for pre-emphasized audio data input. Setting the DEM bit “1”
enables the digital de-emphasis filter. In parallel control mode, the de-emphasis filter is always “OFF”
DEM bit
De-emphasis Filter
1
ON
0
OFF
(default)
Table 11. De-emphasis Filter Control
■ Soft Mute Operation
When the SMUTE bit is set to “1”, if the volume level was 0dB, the output signal is attenuated to -∞dB in 772 LRCK
cycles. When the SMUTE bit returns to “0”, the mute is cancelled and the attenuation gradually changes to the volume
level. If the soft mute is cancelled before attenuating to the mute state, the attenuation is discontinued and returned to
volume level by the same cycles. The soft mute is effective for changing the signal source without stopping the signal
transmission. In parallel control mode, the soft mute function is not available.
SMUTE bit
Volume level
Gain (at the input of
encoder block)
-∞dB
(2)
(1)
(1)
Notes:
(1) Transition time. 772 LRCK cycles (772/fs) when the volume level is 0dB.
(2) If the soft mute is cancelled before attenuating to -∞, the attenuation is discontinued
and returned to the volume level by the same number of clock cycles.
Figure 6. Soft Mute
MS0982-E-01
2010/09
- 14 -
[AK4145]
■ BTSC Stereo/MONO Output Control
The STR bit controls Stereo/MONO output mode. Setting of the STR bit “1” (default) selects BTSC stereo output mode.
Setting of the STR bit “0” selects MONO mode. In parallel control mode, the AK4145 is fixed to stereo mode. The
external pre-emphasis circuit must not be used.
STR bit
1
0
Composite audio output
Stereo mode. outputs BTSC stereo composite
MONO mode, outputs only pre-emphasized (L+R) component.
Table 12. Stereo/MONO Control
(default)
■ Audio Composite Output Volume (DATT)
The AK4145 includes a digital output volume control (DATT) for base band with 256 levels at linear step including
MUTE. This volume control is in front of the DAC and can attenuate the input data from 0dB to –42dB and mute. When
changing levels, transitions are executed in soft changes; thus no switching noise occurs during these transitions. The
transition time of 1 level and all 256 levels is shown in Table 10. In parallel control mode, this volume is fixed to 0dB.
DATT Transition Time
1 Level
255 to 0
4LRCK
1020LRCK
Table 10. DATT Transition Time
■ Video Sync Input
When VCLK bit = “0”(default), the sync separator generates the sync signal using external composite video signal via the
CV27M pin. When VCLK bit = “1”, the 27MHz clock is required through this pin to generate the video sync signal. The
sync signal is used to generate the 15.734kHz pilot tone for BTSC stereo encoding. In parallel control mode, this pin is
fixed to video sync input.
■ Stereo Matrix Control
The AK4145 has the stereo matrix control. The PL3-0 bits control the matrix.
PL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
PL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Lch Output
Rch Output
MUTE
MUTE
MUTE
R
MUTE
L
MUTE
(L+R)/2
R
MUTE
R
R
R
L
R
(L+R)/2
L
MUTE
L
R
L
L
L
(L+R)/2
(L+R)/2
MUTE
(L+R)/2
R
(L+R)/2
L
(L+R)/2
(L+R)/2
Table 13. Stereo Matrix Control
MS0982-E-01
Note
MUTE
REVERSE
STEREO
(default)
MONO
2010/09
- 15 -
[AK4145]
■ Serial Control Interface
The AK4145 supports the fast-mode I2C-bus system (max: 400kHz).
1. Data transfer
All commands are preceded by START condition. After the START condition, a slave address is sent. When the AK4145
recognizes START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA
line. If the transmitted slave address matches an address for one of the devices, the designated slave device (receiver) pulls
the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by STOP condition generated by the
master device.
1-1. Data validity
The data on the SDA line must be stable during the HIGH period of the clock. HIGH or LOW state of the data line can
only be changed when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 7. Data transfer
1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition. All sequences start from the
START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition. All
sequences end by the STOP condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 8. START and STOP conditions
MS0982-E-01
2010/09
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[AK4145]
1-3. ACKNOWLEDGE
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The device will release the SDA
line (HIGH) after transmitting the eight bits. The receiver must pull down the SDA line during the acknowledge clock
pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4145 will generate an acknowledge
after each byte is received.
In read mode, the slave device, the AK4145 will transmit the eight bits of data, release the SDA line and monitor the line
for an acknowledge. If an acknowledge is detected, the slave device will continue transmitting the data. If an
acknowledge is not detected, the slave device will terminate further data transmissions and await STOP condition.
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 9. Acknowledge on the I2C-bus
1-4. FIRST BYTE
The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If the
transmitted slave address matches an address for one of the device, the receiver which is addressed pulls down the SDA
line.
The most significant seven bits of the slave address are fixed as “0010011”. The eighth bit (LSB) of the first byte (R/W
bit) defines whether the master requested a write or read condition. A “1” indicates that the read operation is to be
executed. A “0” indicates that the write operation is to be executed.
0
0
1
0
0
1
1
R/W
Figure 10. The First Byte
MS0982-E-01
2010/09
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[AK4145]
2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4145.
After receipt the start condition and the first byte, the AK4145 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of the AK4145. The format is MSB first,
and those most significant 3-bits are “Don’t care”.
*
*
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 11. The Second Byte
After receipt the second byte, the AK4145 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 12. Byte structure after the second byte
The AK4145 is capable of more than one byte write operation in one sequence.
After receipt of the third byte, the AK4145 generates an acknowledge, and awaits the next data again. The master can
transmit more than one words instead of terminating write cycle after the first data word is transferred. After the receipt of
each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address
automatically. If the address exceeds 05H prior to generating stop condition, the address counter will “roll over” to 00H
and the previous data will be overwritten.
S
T
A
R
T
SDA
Slave
Address
Register
Address(n)
Data(n)
S
T
Data(n+x) O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 13. WRITE Operation
MS0982-E-01
2010/09
- 18 -
[AK4145]
3. READ Operations
The AK4145 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
3-1. CURRENT ADDRESS READ
The AK4145 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would
access data from the address “n+1”.
After receipt of the slave address when R/W bit set to “1”, the AK4145 generates an acknowledge, transmits 1byte data
which address is set by the internal address counter and increments the internal address counter by 1. The master can read
next address’s data by generating an acknowledge instead of terminating the read cycle after the receipt of the data. If the
address exceeds 05H prior to generating stop condition, the address counter will “roll over” to 00H and the previous data
will be re-read. If the master does not generate an acknowledge but generates stop condition, the AK4145 discontinues
transmission.
S
T
A
R
T
SDA
Slave
Address
Data(n)
Data(n+1)
S
Data(n+x) T
O
P
Data(n+2)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 14. CURRENT ADDRESS READ
3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues start condition, slave address(R/W=“0”) and then the register address to read. After the register
address’s acknowledge, the master immediately reissues start condition and the slave address with the R/W bit set to “1”.
Then the AK4145 generates an acknowledge, 1byte data and increments the internal address counter by 1. The master can
read next address’s data by generating the acknowledge instead of terminating read cycle after the receipt of the data. If
the address exceeds 05H prior to generating the stop condition, the address counter will “roll over” to 00H and the
previous data will be re-read. If the master does not generate an acknowledge but generates stop condition, the AK4145
discontinues transmission.
S
T
A
R
T
SDA
Slave
Address
S
T
A
R
T
Word
Address(n)
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 15. RANDOM READ
MS0982-E-01
2010/09
- 19 -
[AK4145]
■ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
01H
02H
03H
04H
05H
Control 1
Control 2
Lch Volume
Rch Volume
Composite Volume
Stereo Matrix
VCLK
VOLC
L7
R7
ATT7
0
DIF2
0
L6
R6
ATT6
0
DIF1
FS1
L5
R5
ATT5
0
DIF0
FS0
L4
R4
ATT4
0
0
0
L3
R3
ATT3
PL3
0
DEM
L2
R2
ATT2
PL2
SMUTE
0
L1
R1
ATT1
PL1
RSTN
STR
L0
R0
ATT0
PL0
Note: For addresses from 06H to 1FH, data must not be written.
When the PDN pin is set to “L”, the registers are initialized to their default values.
When the RSTN bit is set to “0”, the internal timing is reset, but registers are not initialized to their default values.
Do not write “1” data to the register named “0”.
MS0982-E-01
2010/09
- 20 -
[AK4145]
■ Register Definitions
Control 1
Addr
00H
Register Name
Control 1
R/W
Default
D7
VCLK
R/W
0
D6
DIF2
R/W
0
D5
DIF1
R/W
1
D4
DIF0
R/W
1
D3
0
RD
0
D2
0
RD
0
D1
SMUTE
R/W
1
D0
RSTN
R/W
0
D3
0
RD
0
D2
DEM
R/W
0
D1
0
RD
0
D0
STR
R/W
1
RSTN: Internal timing reset control
0: Reset. Initialize the device except register settings (default).
1: Normal Operation
SMUTE: Soft Mute Control
0: Soft Mute disabled (Normal Operation).
1: Soft Mute enabled (default).
DIF2-0: Audio data interface formats (Table 5)
Default: “011”, I2S
VCLK: Sync Source Control
0: Composite video (default).
1: 27MHz clock
Control 2
Addr
01H
Register Name
Control 2
R/W
Default
D7
VOLC
R/W
1
D6
0
RD
0
D5
FS1
R/W
1
D4
FS0
R/W
0
STR: BTSC Stereo/MONO Output Control
0: MONO
1: BTSC Stereo Composite (default)
DEM: De-emphasis Response
0: Disable (default)
1: Enable
FS1-0: Sampling speed control
00: 32kHz
01: 44.1kHz
10: 48kHz (default)
11: Reserved
VOLC: Lch/Rch Volume Common Control Enable
0: Independent Control. L7-0 and R7-0 bits control Lch and Rch independently.
1: Common Control (default). L7-0 bits control both Lch and Rch. R7-0 bits are ignored.
MS0982-E-01
2010/09
- 21 -
[AK4145]
Lch Volume control
Addr
02H
Register Name
Lch Volume
R/W
Default
D7
L7
R/W
0
D6
L6
R/W
0
D5
L5
R/W
1
D4
L4
R/W
1
D3
L3
R/W
1
D2
L2
R/W
1
D1
L1
R/W
1
D0
L0
R/W
0
D4
R4
R/W
1
D3
R3
R/W
1
D2
R2
R/W
1
D1
R1
R/W
1
D0
R0
R/W
0
D5
ATT5
R/W
1
D4
ATT4
R/W
1
D3
ATT3
R/W
1
D2
ATT2
R/W
1
D1
ATT1
R/W
1
D0
ATT0
R/W
1
D5
0
RD
0
D4
0
RD
0
D3
PL3
R/W
1
D2
PL2
R/W
0
D1
PL1
R/W
0
D0
PL0
R/W
1
L7-0: Lch Volume Control when VOLC bit = “0” (Table 9).
These bits control both Lch and Rch volume when VOLC bit = “1”.
Rch Volume control
Addr
03H
Register Name
Rch Volume
R/W
Default
D7
R7
R/W
0
D6
R6
R/W
0
D5
R5
R/W
1
R7-0: Rch Volume Control when VOLC bit = “0” (Table 10).
Don’t care when VOLC bit = “1”.
BTSC Composite Volume control
Addr
04H
Register Name
Composite Volume
R/W
Default
D7
ATT7
R/W
1
D6
ATT6
R/W
1
ATT = 20 log10 ((ATT_DATA + 1) / 256) [dB]
FFH: 0dB (default)
….
00H: Mute
Stereo Matrix control
Addr
05H
Register Name
Stereo Matrix
R/W
Default
D7
0
RD
0
D6
0
RD
0
PL3-0: Stereo Matrix control
Refer to Table 13.
MS0982-E-01
2010/09
- 22 -
[AK4145]
SYSTEM DESIGN
The Figure 16 shows the system connection diagram. The evaluation board (AKD4145) is available for fast evaluation as
well as suggestions for peripheral circuitry.
Analog Video (CVBS)
Amp
10u
1
FILT
CA
16
2
PSN
A VDD
15
4.7n
+
0.1 u
0.1u
3
CV27M
Reset & Power down
4
PDN
Master Clock
5
fs
6
V COM
14
VS S
13
MCLK
DVDD
12
LRCK
TVDD
11
0.1u
AK4145
+
0.1 u
10k
7
BICK
SCL
10
Audio Data
8
SDTI
SDA
9
Analog
Supply 3.3V
10u
Digital
Supply 1.8V
0.1 u
64fs
10u
RF
Modulator
Digital
Supply 3.3V
Micro
Controller
Digital Ground
Analog Ground
Figure 16. Typical Connection Diagram
MS0982-E-01
2010/09
- 23 -
[AK4145]
1. Grounding and Power Supply Decoupling
The AK4145 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and TVDD are
usually supplied from analog supply in system. If AVDD1, AVDD2, DVDD1, DVDD2 and TVDD are supplied
separately, the power up sequence is not critical. VSS of the AK4145 must be connected to analog ground plane.
System analog ground and digital ground should be connected together near to where the supplies are brought onto the
printed circuit board. Decoupling capacitors should be as near to the AK4145 as possible, with the small value ceramic
capacitor being the nearest.
2. Voltage Reference Inputs
The voltage of AVDD sets the DAC analog output range. VCOM is signal ground of analog output signal. The FILT pin
is Loop filter pin for internal PLL. An electrolytic capacitor 10μF parallel with a 0.1μF ceramic capacitor attached
between the VCOM pin and VSS pin eliminate the effects of high frequency noise. An 4.7nF capacitor should be attached
between the FILTM pin and VSS pin. No load current may be drawn from these VCOM and FILT pins. All signals,
especially clocks, should be kept away from the AVDD, VCOM and FILT pins in order to avoid unwanted coupling into
the AK4145.
3. Analog Video Input
In case of composite video input mode (VCLK bit = “0”), the AK4145 receives the analog video input through the
CV27M pin using a 0.1μF ceramic capacitor in series. This video signal is used for the synchronization between the video
sync and the pilot frequency on composite audio output. The video input mode is NOT available only when the TVDD is
lower than 2.7V. In case of 27MHz clock input mode (VCLK bit = “1”), input the 27MHz clock directly without using a
0.1uF capacitor.
4. Analog Composite Audio Output
The analog output is single-ended and centered on around the VCOM voltage. The output signal range scales with the
supply voltage and nominally 2.2 x AVDD/3.3 Vpp (@100kHz deviation) at the CA pin. DC offsets on analog outputs are
eliminated by AC coupling. The modulation level of sound intermediate frequency (SIF) at RF modulator can be adjusted
by the internal composite volume control of the AK4145 (04H D7-0: ATT7-0 bits). The stereo separation can be
maximized by tuning the modulation level. If the output level of the AK4145 (typ: 2.2Vpp @100kHz deviation) is not
sufficient for the RF modulator device, the external gain stage is used for the extra gain.
AK4145
Vop
10u
22k
C (note)
CA
RF Modulator
Vop
47k
47k
should be C value should be determine
0.1u 10u
Note:
The C value must be determined taking account of the input impedance Z at RF modulator. The recommended fc
(cut-off frequency) of this high-pass filter is 1Hz or less for low frequency stereo separation. fc = 1/(2 x 3.14 x C x Z).
Example: C= 10uF @Z=15kohm, C= 3.3uF @Z=50kohm.
Figure 17. External Gain Stage Example.
MS0982-E-01
2010/09
- 24 -
[AK4145]
PACKAGE
16pin TSSOP (Unit: mm)
1.1 (max)
*5.0±0.1
16
9
8
1
0.13
M
6.4±0.2
*4.4±0.1
A
0.65
0.22±0.1
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Material & Lead finish
Package molding compound: Epoxy
Lead frame material:
Cu
Lead frame surface treatment: Solder plate (Pb Free)
MS0982-E-01
2010/09
- 25 -
[AK4145]
MARKING
AKM
4145ET
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4145ET
Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD)
08/08/25
10/09/17
Revision
00
01
Reason
First Edition
Specification
Change
Page
Contents
25
PACKAGE
The package dimension was changed.
MS0982-E-01
2010/09
- 26 -
[AK4145]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
MS0982-E-01
2010/09
- 27 -
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