Fairchild FXMHD103UMX Fxmhd103 hdmi voltage translator Datasheet

FXMHD103 — HDMI Voltage Translator
Description
Features

CEC, DDC, and HPD Level Shifting without a
Direction Pin



Host Port Voltage Supply (VCCA): 1.6V – 3.6V


Supports DDC (I2C) Clock Stretching


Back Drive Protection


Operating Temperature Range: -40°C to 85°C
HDMI Port Voltage Supply (VCCC): 4.8V – 5.3V
Long HDMI Cable Support with Integrated DDC
(I2C) Edge Rate Accelerators
Pin Out Tailored for PCB Trace Routing to HDMI
Type D Connectors
Non-Preferential Power-Up/Down Sequencing
between VCCA and VCCC
ESD Protection:
- 8kV HBM (per JESD22-A114)
- 2kV CDM (per JESD22-C101)
There are three non-inverting bi-directional voltage
translation circuits for the DDC serial data (SDA)/clock
(SCL) lines and CEC lines. Each line has a common
power rail (VCCA) on the host side from 1.6V to 3.6V. On
the HDMI connector side, the SCL_C and SDA_C pins
each have an internal 1.75KΩ pull-up connected to the
HDMI 5V rail, VCCC. The SCL and SDA pins exceed the
HDMI specification for driving up to 800pF loads. The
CEC_C pin has an internal 27KΩ pull-up to an internal
3.3V supply (VREG).
The HPD_C path is uni-directional. The direction is from
the HDMI connector port to the host port. HPD_H
references VCCA, and HPD_C references VCCC. HPD_C
offers hysteresis to avoid false detection due to
bouncing while inserting the HDMI plug.
The FXMHD103 device can be powered down if the OE
pin is LOW. If OE is HIGH, the HPD path is enabled. If
an HDMI sink asserts the HPD_C pin HIGH, the DDC
and CEC paths are enabled. OE references VCCA.
Applications








The FXMHD103 is a reduced-pin-count, low-power,
High-Definition Multimedia Interface (HDMI), voltage
translator for the Data Display Channel (DDC),
Consumer Electronic Control (CEC), and Hot Plug
Detect (HPD) control lines.
Smart Phones
Back drive protection is provided on pins facing the
HDMI connector.
Multimedia Phones
Digital Camcorders
Digital Still Cameras
Portable Game Consoles
Notebooks
MP3 Players
PC and Consumer Electronics
Ordering Information
Part Number
Top Mark
Operating
Temperature Range
FXMHD103UMX
BZ
-40°C to 85°C
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
Package
12-Terminal, Quad µMLP,
1.8mm x 1.8mm Package
Packing
Method
5000 Units on
Tape and Reel
www.fairchildsemi.com
FXMHD103 — HDMI Voltage Translator
July 2012
Host Port:
HDMI Port:
VBAT
Regulated 5.0V
(55mA)
PMIC
VCCA (1.6V – 3.6V)
FXMHD103
HDMI Translator
Regulated
5.0V
(55mA)
TVS
Qty:
1
Host VCC
Ref erence
1.6V – 3.6V
HDMI
Connect
or
Type C/D
3.3V
VREG
HDMI
Host
Controller
DDC (I2C) Translation
DDC/CEC/HPD
HPD Translation
CEC Translation
DDC/CEC/HPD
TVS
Qty:
4
Enable Translation
VREF
Control
TMDS
TVS
Qty:
8
Figure 1. System Block Diagram
Figure 2. Application Drawing
Note:
1. The external TVS devices depicted in the Application Drawing (Figure 2) provide system-level IEC61000-4-2,
Level 4 ESD protection to the mobile device system at the HDMI connector. The FXMHD103 provides devicelevel ESD protection defined in the ESD section of the Absolute Maximum Ratings table.
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
www.fairchildsemi.com
2
FXMHD103 — HDMI Voltage Translator
Block Diagrams
FXMHD103 — HDMI Voltage Translator
Block Diagrams (Continued)
Figure 3. Circuit Block Diagram
Table 1.
Truth Table (VCCA & VCCC Valid)
OE
HPD_C
OE Internal
VREG
HPD_H
SCL_C
SDA_C
CEC_C
LOW
Don’t Care
LOW
Disabled
3-State
3-State
3-State
3-State
HIGH
LOW
LOW
Disabled
Enabled
3-State
3-State
3-State(2)
HIGH
HIGH
HIGH
Enabled
Enabled
Enabled
Enabled
Enabled
(2)
(2)
Note:
2. SCL_C and SDA_C internally pulled up to VCCC. CEC_C is 0V because VREG is disabled. This is required for
HDMI compliance testing. The VOUTDIS parameter captures this requirement.
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
www.fairchildsemi.com
3
FXMHD103 — HDMI Voltage Translator
CEC_H
VCCA
HPD_H
HPD_C
Pin Configuration
12
11
10
9
1
SCL_H
4
5
VCCC
CEC_C
7
SCL_C
6
SDA_C
3
GND
2
OE
SDA_H
8
Figure 4. Pin Assignments (Top View)
Pin Definitions
Pin #
Signal Name
1
SCL_H
Host-side (DDC) SCL bi-directional I2C pin; referenced to VCCA.
2
SDA_H
Host-side (DDC) SDA bi-directional I2C pin; referenced to VCCA.
3
OE
4
GND
5
VCCC
HDMI port supply: 5V VCC reference for HPD_C, SCL_C, SDA_C, and VREG input.
6
SDA_C
Connector-side (DDC) SDA bi-directional I2C pin; referenced to VCCC.
7
SCL_C
Connector-side (DDC) SCL bi-directional I C pin; referenced to VCCC.
8
CEC_C
Connector-side (CEC) bi-directional pin; referenced to internal 3.3V voltage regulator
(VREG). RPU decoupled from “3.3V Internal” if OE=LOW.
9
HPD_C
Connector-side HPD, input for the “hot plug” detect.
10
HPD_H
Host-side HPD; output for the hot plug detect. This pin references VCCA and
indicates to the HDMI controller (HDMI source) when there is an HDMI sink connected
to the FXMHD103.
11
VCCA
12
CEC_H
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
Description
Output enable: LOW=DDC, CEC, & HPD paths disabled; HIGH=DDC, CEC, & HPD
paths enabled.
Device GND
2
Host-side power supply, 1.6V – 3.6V.
Host-side CEC, bi-directional pin; referenced to VCCA. RPU decoupled from VCCA if
OE=LOW.
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
Supply Voltage Range
VIN(3)
Input Voltage Range
VO(3)
Output Voltage
Condition
Min.
Max.
Unit
VCCA, VCCC
-0.5
6.5
V
SCL_H, SDA_H, CEC_H, OE
-0.5
6.5
SCL_C, SDA_C, CEC_C, HPD_C
-0.5
6.5
SCL_H, SDA_H, CEC_H, HPD_H
-0.5
6.5
SCL_C, SDA_C, CEC_C
-0.5
6.5
V
V
IIK
Input Clamp Current
VIN < 0V
IOK
Output Clamp Current
VO < 0V
TJ
Junction Temperature
-40
Storage Temperature Range
-65
+150
°C
TSTG
ESD
Electrostatic Discharge Capability
-50
mA
-50
mA
+150
°C
Human Body Model,
JESD22-A114-B
All Pins
8
Charged Device Model,
JESD22-C101
All Pins
2
Air Gap
16
Contact
9
IEC 61000-4-2
kV
Note:
3. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings. Unless otherwise noted, values are across
the recommended operating free-air temperature range.
Symbol
Parameter
Condition
VCCA
Supply Voltage
VCCA
VCCC
Supply Voltage
VCCC
Host Port
VIN
Input Voltages
Min.
Max.
Unit
1.6
3.6
V
V
4.8
5.3
SCL_H, SDA_H, CEC_H
0
VCCA
OE
0
VCCA
SCL_C, SDA_C
V
0
VCCC
Connector Port CEC_C
0
3.3V (Internal)
HPD_C
0
VCCC
TA
Ambient Temperature
-40
+85
°C
TJ
Junction Temperature
-40
+125
°C
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
www.fairchildsemi.com
5
FXMHD103 — HDMI Voltage Translator
Absolute Maximum Ratings
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with fourlayer 2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction
temperature TJ (maximum) at a given ambient temperature.
Symbol Parameter
ΘJA
Junction-to-Ambient Thermal Resistance
Typ.
Unit
320
°C/W
Max.
Unit
DC Electrical Characteristics (ICC)
Unless otherwise specified, TA=-40 to 85°C.
Symbol
Parameter
Condition
Min.
Typ.
ICCPD1
Power Down 1
VCCA=0V, or VCCC=0V, All Other Pins=Don’t Care
1
μA
ICCPD2
Power Down 2
OE=LOW, VCCA and VCCC Valid, All Other
Pins=Don’t Care
1
µA
ICCHPD
Active HPD Only
OE=HIGH, VCCA and VCCC Valid, SCL_H,
SDA_H and CEC_H=HIGH, HPD_C=0V
1.5
µA
VCCA and VCCC Valid, SCL_H, SDA_H and
CEC_H=HIGH, HPD_C=VCCC, OE=HIGH
5
µA
VCCA and VCCC Valid, SCL_H, SDA_H and
CEC_H=HIGH, HPD_C=VCCC, OE=HIGH
5
µA
ICCA
Active HDMI Link
ICCC
Back Drive Current
Unless otherwise specified, TA=-40 to 85°C.
Symbol
Parameter
Condition
VCCA
VCCC
Typ.
Max.
Unit
IbackCEC
Current Through CEC_C
CEC_C=0V - 5V
0V
0V
0.1
1.8
µA
IbackDDC
Current Through SDA_C
and SCL_C
SDA_C and SCL_C=0V – 5V
0V
0V
0.1
5.0
µA
IbackVCCC
Current Through VCCC
VCCC=0V – 5V
0V
NA
0.1
5.0
µA
IbackHPD
Current Through HPD_C
HPD_C=0V – 5V
0V
0V
0.1
5.0
µA
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
www.fairchildsemi.com
6
FXMHD103 — HDMI Voltage Translator
Thermal Properties
Unless otherwise specified, TA=-40 to 85°C.
Symbol
Parameter
Condition
Host Side
VIH
Min.
1.6V to 3.6V
VCCA 0.4
1.6V to 3.6V
VCCC 0.4
High Level input Voltage
Connector Side
VIL
VCCA
Low Level Input Voltage
Typ.
Max.
V
Host Side
<2V
0.2 x
VCCA
Host Side
>2V
0.4
Connector Side
Unit
1.6V to 3.6V
V
0.4
Host Side: IOH=-10µA
1.6V to 3.6V
VCCA x
0.8
Connector Side: IOH=-10µA
1.6V to 3.6V
VCCC 0.3
VOL1
IOL=3mA, VIL=0V; Both
Directions
1.6V to 3.6V
0.05
V
VOL2
IOL=3mA, VIL=0.25V; Both
Directions
1.6V to 3.6V
0.30
V
IOL=3mA, VIL=0.3V; Both
Directions
1.6V to 3.6V
0.35
V
VOL4
IOL=3mA, VIL=0.4V; Both
Directions
1.6V to 3.6V
0.45
V
VOL5
IOL=3mA, VIL=0.6V C H
Direction Only
1.6V to 3.6V
0.65
V
VOH
VOL3
RPU
High Level Output Voltage
Low Level Output Voltage
Internal Pull-up
Transient Boosted Pull-up
IPULLUPAC Current (Edge Rate
Accelerator)
SCL_H, Internal Pull-up
Connected to SDA_H,
VCCA Rail
10.00
SCL_C, Internal Pull-up
Connected to SDA_C,
VCCC
1.75
SCL_C, Internal Pull-up
Connected to SDA_C,
VCCC
15
kΩ
mA
Host Port
VCCA=0V, VI or VO=0 to
3.6V
0V
±5
Connector Port
VCCC=0V, VI or VO=0 to
5.3V
0V to 3.6V
±5
Connector Port
VO=VCCO or GND
1.6V to 3.6V
±5
Host Port
VI=VCCI or GND
1.6V to 3.6V
±5
IOFF
IOZ
V
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
µA
µA
www.fairchildsemi.com
7
FXMHD103 — HDMI Voltage Translator
Voltage Level Shifter: SCL, SDA Lines (Host/Connector Ports)
Unless otherwise specified, TA=-40 to 85°C.
Symbol
VIH
VIL
Parameter
Condition
High Level input Voltage
Low Level Input Voltage
VCCA
Min.
Host Side
1.6V to 3.6V
VCCA 0.4
Host Side
<2V
0.2 x
VCCA
Host Side
>2V
0.4
1.6V to 3.6V
0.6
Connector Side
VOH
High Level Output Voltage Host Side, IOH=-10µA
1.6V – 3.6V
VCCA x
0.8
VOH
High Level Output Voltage Connector Side, IOH=-10µA
1.6V – 3.6V
2.75
IOL=3mA, VIL=0V
VOL1
VOL2
VOL3
VOL4
Low Level Output Voltage
Host & Connector Sides
VOL5
VOUTDIS
RPU
Output Voltage when
Disabled
Internal Pull-up
Max.
Unit
VCCA
V
V
V
3.10
V
1.6V to 3.6V
0.05
V
IOL=3mA, VIL=0.25V
1.6V to 3.6V
0.30
V
IOL=3mA, VIL=0.3V
1.6V to 3.6V
0.35
V
IOL=3mA, VIL=0.4V
1.6V to 3.6V
0.45
V
IOL=3mA, VIL=0.6V
1.6V to 3.6V
0.65
V
CEC_C: HPD_C=LOW,
OE=HIGH, VCCC=4.8V –
5.3V
1.6V to 3.6V
0.3
V
CEC_H, Internal Pull-up
Connected to VCCA Rail
10
CEC_C, Internal Pull-up
Connected to Internal 3.3V
Rail
27
kΩ
H Port
VCCA=0V, VI or VO=0 to
3.6V
0V
±5.0
C Port
VCCC=0V, VI or VO=0 to
5.3V
0V to 3.6V
±1.8
C Port
VO=VCCO or GND
1.6V to 3.6V
±5.0
H Port
VI=VCCI or GND
1.6V to 3.6V
±5.0
IOFF
IOZ
Typ.
µA
µA
Voltage Level Shifter: HPD Lines (Host/Connector Ports)
TA=-40 to 85°C unless otherwise specified.
Symbol
Parameter
Condition
VCCA
Min.
2
VIH
High Level Input
Voltage
1.6V to 3.6V
VIL
Low Level Input
Voltage
1.6V to 3.6V
VOH
High Level Output
Voltage
IOH=-3mA
1.6V to 3.6V
VOL
Low Level Output
Voltage
IOL=3mA
1.6V to 3.6V
VHYS
HPD_C (VT+ - VT-)
RPD
Internal Pull-Down
HPD_C, Internal Pull-down
Connected to Ground, VCCA
and VCCC Powered up
IOFF
Host Port
VO=VCCO or GND
IOZ
Host Port
VI=VCCI or GND
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
1.6V to 3.6V
Typ.
Max.
Unit
V
0.8
0.7 x VCCA
V
V
0.3
V
200
mV
100
KΩ
0V
±5
µA
3.6V
±5
µA
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8
FXMHD103 — HDMI Voltage Translator
Voltage Level Shifter: CEC Lines (Host/Connector Ports)
Unless otherwise specified, TA=-40 to 85°C. Typical values TA= 25°C.
Voltage Level Shifter: SCL, SDA Lines (Host and Connector Ports); VCCA=1.8V
Symbol
Parameter
Propagation Delay
tPLH
tr
fMAX
Condition
Min.
H to C
tPHL
tf
Pins
C to H
H to C
H Port
C Port Fall time
C Port
H Port Rise Time
H Port
C Port Rise Time
C Port
Maximum Switching
Frequency
Max.
Unit
100
5
DDC Channels Enabled
ns
25
C to H
H Port Fall Time
Typ.
5
2
DDC Channels Enabled 70% -30%
2
DDC Channels Enabled 30% -70%
DDC Channels Enabled
ns
80
ns
50
400
kHZ
Voltage Level Shifter: CEC Line (Host and Connector Ports); VCCA=1.8V
Symbol
Parameter
tPHL
Propagation Delay
tPLH
tf
tr
Pins
Condition
Min.
Typ.
H to C
100
C to H
5
H to C
CEC Channels Enabled
H Port
C Port Fall time
C Port
H Port Rise Time
H Port
C Port Rise Time
C Port
ns
5
CEC Channels Enabled 90% - 10%
CEC Channels Enabled 10% - 90%
Unit
ns
25
C to H
H Port Fall Time
Max.
10
50000
200
50000
5
400
ns
0.2
250
µs
Typ.
Max.
ns
Voltage Level Shifter: HPD Line (Host and Connector Ports); VCCA=1.8V
Symbol
tPHL
tPLH
Parameter
Propagation Delay
Pins
C to H
C to H
Condition
Min.
10
HPD Channel Enabled
Unit
ns
5
tf
H Port Fall Time
H Port
HPD Channel Enabled 90% - 10%
1
ns
tr
H Port Rise Time
H Port
HPD Channel Enabled 10% - 90%
3
ns
I/O Capacitance
TA= 25°C unless otherwise specified.
Symbol
CI
CIO
Parameter
Condition
VCCA & VCCC
Min.
Typ.
Max.
Unit
Control Inputs
0V
2
pF
DDC & CEC on Host Port
0V
5
pF
DDC on Connector Port
LCR: Vbias=2.5V; AC
Input=3.5Vpp; f=100kHZ
0V
10
16.5
pF
CEC on Connector Port
LCR: Vbias=1.65V; AC
Input=2.5Vpp; f=100kHZ
0V
10
16.5
pF
Note:
4. AC Characteristics are guaranteed by Design and Characterization, not production tested.
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
www.fairchildsemi.com
9
FXMHD103 — HDMI Voltage Translator
AC Electrical Characteristics(4)
VCCI
VCCO
DUT
IN
OUT
Input
CL
1MΩ
Figure 5. Device Under Test Setup
Table 2.
Symbol
CL
AC Load
Parameter
Condition
VCCA
Min.
Typ.
Max.
Bus Load Capacitance (Connector-Side)
CEC
1.6V to 3.6V
1300
Bus Load Capacitance (Connector-Side)
DDC & HPD
1.6V to 3.6V
800
Bus Load Capacitance (Host-Side)
All Pins
1.6V to 3.6V
15
Unit
pF
Notes:
5. RT termination resistance should be equal to ZOUT of the pulse generator.
6. CL includes probe and jig capacitance.
7. All input pulses supplied by generators have the following characteristics: PRR < 10MHz, ZO=50Ω, slew rate >
1V/ns.
8. The outputs are measured one at a time, with one transition per measurement.
9. tPLH and tPHL are the same as tPD.
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
www.fairchildsemi.com
10
FXMHD103 — HDMI Voltage Translator
AC Parameter Measurement Information(5,6,7,8,9)
DATA
IN
VCCI
Vmi
tpxx
GND
Vmo
DATA
OUT
VCCO
VCCA
Vmi
DATA
OUT
Figure 8.
VOL
3-STATE Output Low Enable Time
Symbol
VCC
Vmi
VCCI / 2
Vx
VOL
VY
Figure 7.
GND
tPLZ
GND
tPZL
Waveform for Inverting and Non-Inverting
Functions
OUTPUT
CONTROL
VCCA
Vmi
tpxx
DATA
OUT
Figure 6.
OUTPUT
CONTROL
Vmo
VCCO / 2
VX
0.5 x VCCO
VY
0.1 x VCCO
3-STATE Output High Enable Time
Figure 9.
Active Output Rise Time
Figure 10. Active Output Fall Time
VCCO
DATA
OUTPUT
Vmo
Vmo
GND
tperiod
DATA
IN
VCCI / 2
VCCI / 2
tskew
VCCI
VCCO
DATA
OUTPUT
GND
F-toggle rate, f = 1 / tperiod
tskew
Vmo
Vmo
GND
tskew = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin)
Figure 11.
F-Toggle Rate
Figure 12.
Output Skew Time
Notes:
10. Input tR=tF=2.0ns, 10% to 90% at VIN=1.65V to 1.95V;
Input tR=tF=2.0ns, 10% to 90% at VIN=2.3 to 2.7V;
Input tR=tF=2.5ns, 10% to 90%, at VIN=3.0V to 3.6V only;
Input tR=tF=2.5ns, 10% to 90%, at VIN=4.5V to 5.5 only.
11. VCCI=VCCA for control pin OE or Vmi=(VCCA / 2).
12. DDC Rise Times 30% - 70%, CEC & HPD Rise Times 10% - 90%
13. DDC Fall Times 30% - 70%, CEC & HPD Fall Times 10% - 90%
14. VCCI is the VCC associated with the input side. VCCO is the VCC associated with the output side.
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
www.fairchildsemi.com
11
FXMHD103 — HDMI Voltage Translator
Timing Diagrams(10,11,12,13,14)
Power Down
Backdrive Protection
The FXMHD103 can be powered down if either
VCCA or VCCC equals 0V, or if OE is LOW.
Backdrive-current protection is available on all
FXMHD103 signals interfacing with the HDMI
connector, including VCCC, SCL_C, SDA_C,
CEC_C, and HPD_C. If the FXMHD103 is
powered down, VCCA=0V or VCCC=0V and the
HDMI sink forces 0V – 5V onto any of the HDMI
connector-facing pins (VCCC, SCL_C, SDA_C,
CEC_C & HPD_C). The maximum current flow
from the FXMHD103 is only 5µA, with the
exception of 1.8µA (maximum) on CEC_C.
“Hot Plug” Detect Operation
After VCCA and VCCC have powered up to valid
levels, and OE enabled (HIGH) the HPD path is
enabled. The internal 3.3V voltage regulator and
the CEC & DDC blocks are disabled due to the
internal weak pull-down resistor (100kΩ to GND)
on HPD_C. When the HDMI sink recognizes a
valid 5V signal on the HDMI connector, to inform
the HDMI source there is a valid HDMI sink
connected to the HDMI connector; the sink
typically ties the HPD_C signal to the HDMI 5V
supply through a 1KΩ resistor. A HIGH on
HPD_C, in turn, enables the internal voltage
regulator, as well as the DDC & CEC paths. The
HDMI link is active between the HDMI source and
the HDMI sink.
DDC Channel Description
The HDMI specification implements the Video
Electronics Standards Association (VESA) Display
Data Channel (DDC) for communication between
a single HDMI source and a single HDMI sink. The
DDC is used by the HDMI source to read the
HDMI sink’s Enhanced Extended Display
Identification Data (E-EDID) to discover the sink’s
configuration or capabilities. DDC must meet the
I2C specification, version 2.1, for Standard Mode
devices. Because the HDMI application is meant
for high-definition Transition-Minimized Differential
Signaling (TMDS) video transport across a cable,
the HDMI specification requires the DDC signals
(SCL & SDA) be able to drive a minimum
capacitance of 800pF (source 50pF + cable
assembly 700pF + sink 50pF). The I2C specification
requires a minimum of 400pF capacitance.
When HPD_C is LOW, the respective resistor pullups (RPUs) on the host and connector sides of the
DDC paths remain coupled to their respective
voltage references. Likewise, when HPD_C is
LOW, the RPUs on the host and connector sides
of the CEC path remain coupled to their respective
voltage references. Since HPD_C disables VREG
and VREG is the CEC_C voltage reference, CEC_C
is held to 0V by a weak (50nA) current source
when HPD_C is LOW. This is captured by the
VOUTDIS parameter.
Figure 13.
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
DDC Channel Block Diagram, 1 of 2 Channels (SDA & SCL)
www.fairchildsemi.com
12
FXMHD103 — HDMI Voltage Translator
Application Information
The FXMHD103 DDC channel is designed for highperformance I2C level shifting. Figure 13 shows that
each bi-directional channel contains an Npassgate and
two dynamic drivers. This hybrid architecture is highly
2
beneficial in an I C application with large capacitive
loads and where auto-direction is necessary.
For example, during the following I2C protocol events
the bus direction needs to change from “Source-to-Sink”
to “Sink-to-Source” without the occurrence of an edge:

Clock Stretching

Slave’s ACK Bit (9th bit=0) following a Master’s
Write Bit (8th bit=0)

Clock Synchronization and Multi Master Arbitration
2
If there is an I C translator between the source and sink
2
in these examples, the I C translator must change
direction when both A and C ports are LOW. The
Npassgate can accomplish this efficiently because,
when both A and C ports are LOW, the Npassgate acts
as a low resistive short between the (A and C) ports.
Driving a Capacitive Load
The FXMHD103 dynamic drivers have enough current
sourcing capability to drive an 800pF capacitive bus.
The Figure 14 scope shot is of an FXMHD103 driving a
lumped load of 600pF. Notice the (30% - 70%) rise time
is only 112ns (RPU=5KΩ). This is well below the
maximum rise time of 1000ns in Standard Mode
(100KHz) or 300ns in Fast Mode (400KHz).
VOL vs. VIL & IOL
The I2C specification mandates a maximum VIL (IOL of
2
3mA) of VCC x 0.3 for an I C receiver and a maximum
2
VOL of 0.4V for an I C transmitter. If there is an HDMI
2
source on the A port of an I C translator with a VCC of
2
1.8V and an HDMI sink on the I C translator C port with
a VCC of 5.0V, the maximum VIL of the source is (1.6V x
0.3) 480mV. Meanwhile, the sink could transmit a valid
logic LOW of 0.4V to the source. 80mV is not very much
margin between the maximum transmitted VOL of
400mV (HDMI sink) to the maximum received VIL of
480mV (HDMI source). This appears to be an oversight
in the I2C specification, but there is an explanation. The
2
I C specification assumes transmitters and receivers
share the same VCC. The I2C specification does call out
separate VOL requirements vs. VCC conditions where
VOL1=0.4V when VCC is > 2.0V and VOL3=0.2 x VCC,
when VCC is < 2.0V. When there is VCC alignment
between I2C transmitters and receivers, the I2C
specification provides adequate VIL vs. VOL margins.
However, when you have a transmitter operating at 5V
and a receiver operating at 1.6V through a translator or
level shifter, the VOL vs. VIL margin gets very tight, as in
the above example. Therefore, the voltage drop across
2
the I C translator must be as low as possible.
Due to the I2C open-drain topology, I2C drivers are not
push/pull devices. Logic LOWs are “pulled down” (Isink),
while logic HIGHs are “let go” (3-state). For example,
when the source lets go of SCL (SCL always comes
from the source), the rise time of SCL is largely
determined by the RC time constant, where R=RPU and
C=the bus capacitance. If the FXMHD103 is attached to
the source [on the A port] and there is a source on the C
port, the Npassgate acts as a low-resistive short
between both ports until either of the port’s VCC/2
thresholds is reached. After the RC time constant has
reached the VCC/2 threshold of either port, the port’s
edge detector triggers both dynamic drivers to drive
their respective ports in the LOW-to-HIGH (LH)
direction, accelerating the rising edge. The resulting rise
time resembles the scope shot in Figure 14. Effectively,
two distinct slew rates appear in rise time. The first slew
rate (slower) is the RC time constant of the bus. The
second slew rate (much faster) is the dynamic driver
accelerating the edge.
In general, if the I2C translator’s channel resistance is
too high, the voltage drop across the translator could
present a VIL to a receiver greater than the receiver’s
maximum VIL. To complicate matters, the I2C
specification states that 6mA of IOL is recommended for
bus capacitances approaching 400pF in Fast Mode.
2
More IOL increases the voltage drop across the I C
translator. The I2C application benefits when I2C
translators exhibit low VOL performance. Table 3 depicts
the FXMHD103 targeted VOL performance vs. VIL/IOL
when the direction is from C side to A side, VCCC=5.0V
and VCCA=1.6V.
Figure 14. Rise Time Driving 600pF Load
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
www.fairchildsemi.com
13
FXMHD103 — HDMI Voltage Translator
If both the A and C ports of the translator are HIGH, a
high-impedance path exists between the A and C ports
because both the Npassgates are turned off. If a source
or sink device decides to pull SCL or SDA LOW, that
device’s driver pulls down (Isink) SCL or SDA until the
edge reaches the A or C port VCC/2 threshold. When
either the A or C port threshold is reached, the port’s
edge detector triggers both dynamic drivers to drive
their respective ports in the HIGH-to-LOW (HL)
direction, accelerating the falling edge.
Edge Rate Accelerators
DDC Voltage Drop (VOL vs. VIL/IOL): Port C  Port A Direction, VCCA=1.6V
VIL (mV)
IOL (mA)
VOL Max. (mV)
Voltage Drop Max. (mV)
Calculated Max. RON (Ω)
0
6
50
50
8.33
250
6
300
50
8.33
300
6
350
50
8.33
400
6
450
50
8.33
600
6
650
50
8.33
PCB Layout Recommendation
Figure 15. PCB Routing Example (Molex HDMI Type-D Connector)
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
www.fairchildsemi.com
14
FXMHD103 — HDMI Voltage Translator
Table 3.
FXMHD103 — HDMI Voltage Translator
Physical Dimensions
1.80
0.10 C
A
(11X)
2.10
B
0.563
0.588
2X
1
1.80
0.40
2.10
PIN#1 IDENT
TOP VIEW
0.55 MAX.
0.10 C
0.10 C
(12X) 0.20
2X
RECOMMENDED
LAND PATTERN
0.152
0.45
0.35
0.08 C
0.05
0.00
0.10
SEATING C
PLANE
SIDE VIEW
0.10
0.10
DETAIL A
SCALE : 2X
NOTES:
0.35
(11X)
0.45
3
6
0.40
DETAIL A
A. PACKAGE DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
1
PIN#1 IDENT
12
9
BOTTOM VIEW
0.25
0.15 (12X)
0.10 C A B
0.05 C
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-UMLP12Arev4.
PACKAGE
EDGE
LEAD
OPTION 1
SCALE : 2X
LEAD
OPTION 2
SCALE : 2X
Figure 16.
12-Lead, UMLP, Quad JEDEC MO-252, 1.8mm x 1.8mm, 0.4mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
www.fairchildsemi.com
15
FXMHD103 — HDMI Voltage Translator
© 2012 Fairchild Semiconductor Corporation
FXMHD103 • Rev. 1.0.2
www.fairchildsemi.com
16