Lattice ISPGDX120A-7T176 In-system programmable generic digital crosspoint Datasheet

®
ispGDX Family
In-System Programmable
Generic Digital Crosspoint
Features
Functional Block Diagram
ISP
Control
I/O Pins A
I/O Pins D
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 5V Power Supply
— 5.0ns Input-to-Output/5.0ns Clock-to-Output Delay
— Low-Power: 40mA Quiescent Icc
— Balanced 24mA Output Buffers with Programmable
Slew Rate Control
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
I/O
Cells
Boundary
Scan
Control
Global Routing
Pool
(GRP)
I/O
Cells
I/O Pins C
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— Three Device Options: 80 to 160 Programmable I/O
Pins
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving TQFP, PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
— PCI Compliant Output Drive
I/O Pins B
Description
• ispGDX OFFERS THE FOLLOWING ADVANTAGES
The ispGDX architecture provides a family of fast, flexible
programmable devices to address a variety of systemlevel digital signal routing and interface requirements
including:
— In-System Programmable
— Lattice ISP or JTAG Programming Interface
— Only 5V Power Supply Required
— Change Interconnects in Seconds
— Reprogram Soldered Devices
• Multi-Port Multiprocessor Interfaces
• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock Input Pins (two or four) or
Programmable Clocks from I/O Pins (from 20 up to
40)
— Up to 4:1 Dynamic Path Selection
— Programmable Output Pull-up Resistors
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
• Wide Data and Address Bus Multiplexing
(e.g. 4:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The ispGDX Family consists of three members with 80,
120 and 160 Programmable I/Os. These devices are
available in packages ranging from the 100-pin TQFP to
the 208-pin PQFP. The devices feature fast operation,
with input-to-output signal delays (Tpd) of 5ns and clockto-output delays of 5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
Copyright © 2002 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
ispgdx_11
1
November 2003
Specifications ispGDX Family
Description (Continued)
ing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock
(CLK) and two multiplexer control (MUX0 and MUX1)
inputs. Polarity for these signals is programmable for
each I/O cell. The MUX0 and MUX1 inputs control a fast
4:1 MUX, allowing dynamic selection of up to four signal
sources for a given output. OE, CLK and MUX0 and
MUX1 inputs can be driven directly from selected sets of
I/O pins. Optional dedicated clock input pins give minimum clock-to-output delays.
In addition, there are no pin-to-pin routing constraints for
1:1 or 1:n signal routing. That is, any I/O pin configured
as an input can drive one or more I/O pins configured as
outputs.
The device pins also have the ability to set outputs to
fixed HIGH or LOW logic levels (Jumper or DIP Switch
mode). Device outputs are specified for 24mA sink and
source current and can be tied together in parallel for
greater drive. Programmable output slew rate can be
defined independently for each I/O pin to reduce overall
ground bounce and switching noise.
All I/O pins are equipped with IEEE1149.1-compliant
Boundary Scan Test circuitry for enhanced testability. In
addition, in-system programming is supported through
the Test Access Port via a special set of private commands or through Lattice’s industry-standard ISP protocol.
The BSCAN/ispEN pin is used to make this selection.
Through in-system programming, connections between
I/O pins and architectural features (latched or registered
inputs or outputs, output enable control, etc.) can be
defined. In keeping with its data path application focus,
the ispGDX devices contain no programmable logic
arrays. All input pins include Schmitt trigger buffers for
noise immunity. These connections are programmed
into the device using non-volatile E2CMOS technology.
Non-volatile technology means the device configuration
is saved even when the power is removed from the
device.
The ispGDX I/Os are designed to withstand “live insertion” system environments. The I/O buffers are disabled
during power-up and power-down cycles. When designing for “live insertion,” absolute maximum rating conditions
for the Vcc and I/O pins must still be met. For additional
information, an application note about using Lattice devices in hot swap environments can be downloaded from
the Lattice web site at www.latticesemi.com.
Table 1. ispGDX Family Members
ispGDX DEVICE
ispGDX80A
ispGDX120A
ispGDX160A
I/O Pins
80
120
160
I/O-OE Inputs*
20
30
40
I/O-Clk Inputs*
20
30
40
I/O-MUXsel1 Inputs*
20
30
40
I/O-MUXsel2 Inputs*
20
30
40
Dedicated Clock Pins
2
4
4
BSCAN / ispEN
1
1
1
1**
1
1
BSCAN / ISP Interface
4
4
4
RESET
1
1
1
Power/GND
12
25
33
100-Pin TQFP
176-Pin TQFP/
160-Pin PQFP
208-Pin PQFP
272-Ball BGA
TOE
Pin Count/Package
* The CLK, OE, MUX0 and MUX1 terminals on each I/O cell can each access 25% of the I/Os.
** MUXed with Y1.
2
Specifications ispGDX Family
Architecture
The ispGDX architecture is different from traditional PLD
architectures, in keeping with its unique application focus. The block diagram is shown below. The
programmable interconnect consists of a single Global
Routing Pool (GRP). Unlike ispLSI® devices, there are
no programmable logic arrays on the device. Control
signals for OEs, Clocks and MUX Controls must come
from designated sets of I/O pins. The polarity of these
signals can be independently programmed in each I/O
cell.
Figure 1. The four data inputs to the MUX (called MUXA,
MUXB, MUXC and MUXD) come from I/O signals found
in the GRP. Each MUX data input can access one quarter
of the total I/Os. For example, in a 160 I/O ispGDX, each
data input can connect to one of 40 I/O pins. MUX0 and
MUX1 can be driven by designated I/O pins called
MUXsel1 and MUXsel2. Each MUXsel input covers 25%
of the total I/O pins (e.g. 40 out of 160). MUX0 and MUX1
can be driven from either MUXsel1 or MUXsel2. The I/O
cell also includes a programmable flow-through latch or
register that can be placed in the input or output path and
bypassed for combinatorial outputs. As shown in Figure
1, when both register/latch control MUXes select the “A”
path, the register/latch gets its inputs from the 4:1 MUX
and drives the I/O output. When selecting the “B” path,
the register/latch is directly driven by the I/O input while
its output feeds the GRP. The programmable polarity
Clock to the latch or register can be connected to any
I/O in the I/O-Clock set (one-quarter of total I/Os) or to
one of the dedicated clock input pins (Yx). Use of the
dedicated clock inputs gives minimum clock-to-output
delays and minimizes delay variation with fanout. Combinatorial output mode may be implemented by a
dedicated architecture bit and bypass MUX. I/O cell
output polarity can be programmed as active high or
active low.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
The in-system programming process uses either a Boundary Scan based or Lattice ISP protocol. The programming
protocol is selected by the BSCAN/ispEN pin as described later.
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines called MUX0 and MUX1 as shown in
Figure 1. ispGDX I/O Cell and GRP Detail (160 I/O Device)
Logic "1"
160 I/O Inputs
I/O MUX Operation
I/O 0
I/O 1
MUX1 MUX0 DATA INPUT SELECTED
I/O 80
I/O 81
E2CMOS
••
•
Programmable
Interconnect
I/O Cell N
Prog.
Pull-up
Bypass Option
4-to-1 MUX
MUXA
MUXB
MUXC
MUXD
•
•
•
•
•
•
A
B
MUX0 MUX1
Register
or Latch
D
Q
CLK
Reset
C
I/O Pin
R
Programmable
Slew Rate
Boundary
Scan Cell
I/O 78
I/O 79
••••••
80 I/O Cells
160 Input GRP
Inputs Vertical
Y0-Y3
Outputs Horizontal Global
Clocks
I/O 158
I/O 159
80 I/O Cells
Global
Reset
3
0
0
MUXA
0
1
MUXB
1
1
MUXC
1
0
MUXD
Specifications ispGDX Family
Applications
The ispGDX family architecture has been developed to
deliver an in-system programmable signal routing solution with high speed and high flexibility. The devices are
targeted for three similar but distinct classes of endsystem applications:
Programmable Switch Replacement (PSR)
Includes solid-state replacement and integration of mechanical DIP Switch and jumper functions. Through
in-system programming, pins of the ispGDX devices can
be driven to HIGH or LOW logic levels to emulate the
traditional device outputs. PSR functions do not require
any input pin connections.
Programmable, Random Signal Interconnect (PRSI)
This class includes PCB-level programmable signal routing and may be used to provide arbitrary signal swapping
between chips. It opens up the possibilities of programmable system hardware. It is characterized by the need
to provide a large number of 1:1 pin connections which
are statically configured, i.e., the pin-to-pin paths do not
need to change dynamically in response to control inputs.
These applications actually require somewhat different
silicon features. PRSI functions require that the device
support arbitrary signal routing on-chip between any two
pins with no routing restrictions. The routing connections
are static (determined at programming time) and each
input-to-output path operates independently. As a result,
there is little need for dynamic signal controls (OE,
clocks, etc.). Because the ispGDX device will interface
with control logic outputs from other components (such
as ispLSI) on the board (which frequently change late in
the design process as control logic is finalized), there
must be no restrictions on pin-to-pin signal routing for this
type of application.
Programmable Data Path (PDP)
This application area includes system data path transceiver, MUX and latch functions. With today’s 32- and
64-bit microprocessor buses, but standard data path glue
components still relegated primarily to eight bits, PCBs
are frequently crammed with a dozen or more data path
glue chips that use valuable real estate. Many of these
applications consist of “on-board” bus and memory interfaces that do not require the very high drive of standard
glue functions but can benefit from higher integration.
Therefore, there is a need for a flexible means to integrate these on-board data path functions in an analogous
way to programmable logic’s solution to control logic
integration. Lattice’s ispLSI High-Density PLDs make an
ideal control logic complement to the ispGDX in-system
programmable data path devices as shown below.
PDP functions, on the other hand, require the ability to
dynamically switch signal routing (MUXing) as well as
latch and tri-state output signals. As a result, the programmable interconnect is used to define possible signal
routes that are then selected dynamically by control
signals from an external MPU or control logic. These
functions are usually formulated early in the conceptual
design of a product. The data path requirements are
driven by the microprocessor, bus and memory architecture defined for the system. This part of the design is the
earliest portion of the system design frozen, and will not
usually change late in the design because the result
would be total system and PCB redesign. As a result, the
ability to accommodate arbitrary any pin-to-any pin rerouting is not a strong requirement as long as the designer
has the ability to define his functions with a reasonable
degree of freedom initially.
Figure 2. ispGDX Complements Lattice ispLSI
Address
Inputs
(from µP)
Control
Inputs
(from µP)
Data Path
Bus #1
ISP/JTAG
Interface
As a result, the ispGDX architecture has been defined to
support PSR and PRSI applications (including bidirectional paths) with no restrictions, while PDP applications
(using dynamic MUXing) are supported with a minimal
number of restrictions as described below. In this way,
speed and cost can be optimized and the devices can still
support the system designer’s needs.
Buffers / Registers
State Machines
Control
Outputs
ispLSI Device
ispGDX Device
Decoders
Buffers / Registers
System
Clock(s)
Configuration
(Switch)
Outputs
The following diagrams illustrate several ispGDX applications.
Data Path
Bus #2
4
Specifications ispGDX Family
Applications (Cont.)
Figure 3. Address Demultiplex/Data Buffering
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
XCVR
Muxed Address Data Bus
Control Bus
Designing with the ispGDX
I/OA
Buffered
Data
I/OB
OEA OEB
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
To Memory/
Peripherals
Address
Latch
D
Q
Address
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O0-19 (80 I/O device), it is not
possible to use I/O0 and I/O9 in the same MUX function.
As previously discussed, data path functions will be
assigned early in the design process and these restrictions are reasonable in order to optimize speed and cost.
CLK
Figure 4. Data Bus Byte Swapper
XCVR
I/OA
D0-7
I/OB
Data Bus A
Control Bus
I/OA
I/OB
OEA OEB
XCVR
D8-15
I/OA
User Electronic Signature
XCVR
OEA OEB
The ispGDX Family includes dedicated User Electronic
Signature (UES) E2CMOS storage to allow users to code
design-specific information into the devices to identify
particular manufacturing dates, code revisions, or the
like. The UES information is accessible through the
boundary scan or Lattice ISP programming port via a
specific command. This information can be read even
when the security cell is programmed.
Data Bus B
D0-7
D8-15
I/OB
XCVR
OEA OEB
I/OA
I/OB
OEA OEB
Security Bit
The ispGDX Family includes a security bit feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
Figure 5. Four-Port Memory Interface
Bus 1
Bus 2
Bus 3
Bus 4
4-to-1
16-Bit MUX
Bidirectional
Port #1
OE1
Memory
Port
Port #2
OE2
OEM
Port #3
OE3
SEL0
Port #4
OE4
SEL1
To
Memory
Note: All OE and SEL lines driven by external arbiter logic (not shown).
5
Specifications ispGDX Family
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
VCC
VIL1
VIH1
PARAMETER
MIN.
MAX.
UNITS
4.75
5.25
V
Input Low Voltage
0
0.8
V
Input High Voltage
2.0
Vcc + 1
V
Supply Voltage
Commercial
TA = 0°C to +70°C
1. Typical 100mV of input hysteresis.
Capacitance (TA=25oC, f=1.0 MHz)
TYPICAL
UNITS
I/O Capacitance
8
pf
VCC = 5.0V, VI/O = 2.0V
Dedicated Clock Capacitance
10
pf
VCC = 5.0V, VY = 2.0V
SYMBOL
C1
C2
PARAMETER
TEST CONDITIONS
Table 2 - 0006
Erase/Reprogram Specifications
PARAMETER
ispGDX Erase/Reprogram Cycles
6
MINIMUM
MAXIMUM
UNITS
10,000
–
Cycles
Specifications ispGDX Family
Switching Test Conditions
Input Pulse Levels
+ 5V
GND to 3.0V
Input Rise and Fall Time
≤ 1.5ns 10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
R1
Device
Output
See figure at right
Test
Point
CL*
R2
3-state levels are measured 0.5V from steady-state
active level.
Output Load Conditions
*CL includes Test Fixture and Probe Capacitance.
TEST CONDITION
R1
R2
CL
160Ω
90Ω
35pF
Active High
∞
90Ω
35pF
Active Low
160Ω
90Ω
35pF
Active High to Z
at VOH -0.5V
∞
90Ω
5pF
Active Low to Z
at VOL +0.5V
160Ω
90Ω
5pF
A
B
C
Table 2 - 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
ICCQ
ICC
MIN.
TYP.2
MAX.
UNITS
IOL =24 mA
–
–
0.55
V
Output High Voltage
IOH =-24 mA
2.4
–
–
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (MAX.)
–
–
-10
µA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
–
–
10
µA
ispEN Input Low Leakage Current
0V ≤ VIN ≤ VIL (MAX.)
–
–
-150
µA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V, TA = 25˚C
-100
–
-250
mA
Quiescent Power Supply Current
VIL = 0.5V, VIH = VCC
–
25
40
mA
Dynamic Power Supply Current
per Input Switching
One input toggling @ 50% duty cycle,
outputs open.
–
See
Note 3
–
mA/MHz
PARAMETER
Output Low Voltage
CONDITION
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Typical values are at VCC = 5V and TA = 25oC.
3. I CC / MHz = (0.0114 x I/O cell fanout) + 0.06
e.g. An input driving four I/O cells at 40 MHz results in a dynamic I CC of approximately ((0.0114 x 4) + 0.06) x 40 = 4.2 mA.
7
Specifications ispGDX Family
External Timing Parameters
Over Recommended Operating Conditions
1
PARAMETER TEST #
tpd
tsel
fmax(ext)
tsu1
tsu2
th
tgco1
tgco2
tco1
tco2
ten
tdis
ttoeen
ttoedis
twh
twl
trst
trw
tsl
tsk
-5
DESCRIPTION
COND.
-7
UNITS
MIN. MAX. MIN. MAX.
A
1
Data Propagation Delay from any I/O pin to any I/O pin
–
5.0
–
7.0
ns
A
2
Data Propagation Delay from MUXsel Inputs to any Output
–
6.5
–
9.0
ns
–
3
Clock Frequency with External Feedback (
111
–
80.0
–
MHz
–
4
Input Latch or Register Setup Time before any Clk
4.0
–
5.5
–
ns
–
5
Output Latch or Register MUX Data Setup Time before any Clk
4.0
–
5.5
–
ns
0.0
–
0.0
–
ns
1
tsu2+tgco1
)
–
6
Latch or Register Hold Time after any Clk
A
7
Output Latch or Register Clk (from Yx) to Output Delay
–
5
–
7.0
ns
A
8
Input Latch or Register Clk (from Yx) to Output Delay
–
8.5
–
11.0
ns
A
9
Output Latch or Register Clk (from I/O pin) to Output Delay
9.0
ns
A
10 Input Latch or Register Clock (from I/O pin) to Output Delay
–
9.5
–
13.0
ns
B
11 Input to Output Enable
–
6.0
–
8.5
ns
C
12 Input to Output Disable
–
6.0
–
8.5
ns
B
13 Test OE Output Enable
–
9.0
–
12.0
ns
C
14 Test OE Output Disable
–
9.0
–
12.0
ns
–
15 Clock Pulse Duration, High
3.5
–
5.0
–
ns
–
16 Clock Pulse Duration, Low
3.5
–
5.0
–
ns
–
17 Register Reset Delay from RESET Low
–
14.0
–
18.0
ns
6.0
–
18 Reset pulse width
10.0
–
14.0
–
ns
A
19 Output Delay Adder for Output Timings Using Slow Slew Rate
–
5.0
–
7.0
ns
A
20 Output Skew (tgco1 across chip)
–
0.5
–
0.5
ns
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
Maximum ∆ GRP Delay vs. I/O Cell Fanout
ispGDX timings are specified with a GRP load (fanout) of
four I/O cells. The figure at right shows the Maximum ∆
GRP Delay with increased GRP loads. These deltas
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK, MUXsel0-1). Global Clock signals, which do
not use the GRP, have no fanout delay adder.
∆ GRP Delay (ns)
10
8
6
4
2
0 4 10
20
30
40
50
I/O Cell Fanout
8
60
70
Specifications ispGDX Family
Internal Timing Parameters1
Over Recommended Operating Conditions
-5
PARAMETER #2
DESCRIPTION1
-7
MIN. MAX. MIN. MAX. UNITS
Inputs
tio
21 Input Buffer Delay
—
0.7
—
1.3
ns
22 GRP Delay
—
2.0
—
2.5
ns
tmuxd
23 I/O Cell MUX A/B/C/D Data Delay
—
1.0
—
1.4
ns
tmuxs
24 I/O Cell MUX A/B/C/D Data Select
—
2.5
—
3.4
ns
tiolat
25 I/O Latch Delay
—
1.6
—
2.2
ns
tiosu
26 I/O Register Setup Time Before Clock
—
1.6
—
1.8
ns
tioh
27 I/O Register Hold Time After Clock
—
2.4
—
3.6
ns
tioco
28 I/O Register Clock to Output Delay
—
1.6
—
2.2
ns
tior
29 I/O Reset to Output Delay
—
0.7
—
1.0
ns
trfdbk
30 I/O Register Feedback Delay
—
0.2
—
0.3
ns
tiobp
31 I/O Register Bypass Delay
—
0.4
—
0.6
ns
tioob
32 I/O Register Output Buffer Delay
—
0.1
—
0.7
ns
tmuxc (Yx Clk) 33 I/O Register Data Input MUX Delay
—
1.1
—
1.2
ns
tmuxc (I/O Clk) 34 I/O Register Data Input MUX Delay
—
2.1
—
3.2
ns
GRP
tgrp
MUX
Register
Data Path
tiod (Yx Clk)
35 I/O Register I/O Input MUX Delay
—
4.1
—
5.1
ns
tiod (I/O Clk) 36 I/O Register I/O Input MUX Delay
—
5.1
—
7.1
ns
Outputs
tob
37 Output Buffer Delay
—
0.9
—
1.3
ns
tobs
38 Output Buffer Delay, Slow Slew
—
5.9
—
8.3
ns
toen
39 I/O Cell OE to Output Enabled
—
0.8
—
1.1
ns
toedis
40 I/O Cell OE to Output Disabled
—
0.8
—
1.1
ns
tgoe
41 Global Output Enable Delay
—
2.5
—
3.6
ns
ttoe
42 Test OE Enable Delay
—
8.2
—
10.9
ns
tcio
43 I/O Clock Delay
—
0.7
—
1.0
ns
tgy0/1/2/3
44 Clock Delay, Y0/1/2/3
—
2.4
—
2.8
ns
45 Global Reset to I/O Register/Latch
—
12.3
—
15.0
ns
Clocks
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
9
Specifications ispGDX Family
Switching Waveforms
DATA
(I/O INPUT)
VALID INPUT
MUXSEL (I/O INPUT)
VALID INPUT
tsel
DATA (I/O INPUT)
VALID INPUT
th
tgco1
tgco2
tco1
tco2
tsu1
tsu2
CLK
tpd
COMBINATORIAL
I/O OUTPUT
REGISTERED
I/O OUTPUT
Combinatorial Output
1/fmax
(external fdbk)
Registered Output
OE (I/O INPUT)
tdis
ten
COMBINATORIAL
I/O OUTPUT
RESET
trw
I/O Output Enable/Disable
twh
trst
REGISTERED
I/O OUTPUT
twl
CLK
(I/O INPUT)
Reset
Clock Width
ispGDX Timing Model
OE
tmuxd #23
tmuxs #24
tgoe #41
TOE
A
ttoe #42
tiobp #31
B
tmuxc #33, #34
C
D
tioob #32
MUX0
D
Q
I/O Pin
MUX1
tob #37
tobs #38
toen #39
toedis #40
GRP
tgrp #22
tiod #35, #36
tiolat #25
tiosu #26
tioh #27
tioco #28
tior #29
tgr #45
Reset
trfdbk #30
tio #21
Clock
Y0,1,2,3
tcio #43
0902/gdx
tgy0/1/2/3 #44
10
Specifications ispGDX Family
while the pin is held low. After pulling the pin high the
JTAG controller becomes active. The intent of this feature is to allow the JTAG interface to be directly controlled
by the data bus of an embedded controller (hence the
name Embedded Port Enable). The EPEN signal is used
as a “device select” to prevent spurious programming
and/or testing from occurring due to random bit patterns
on the data bus. Figure 9 illustrates the block diagram for
the ispJTAG™ interface.
ispLEVER Development System
The ispLEVER Development System supports ispGDX
design using a VHDL or Verilog language syntax. From
creation to in-system programming, the ispLEVER system is an easy-to-use, self-contained design tool.
Features
• VHDL and Verilog Synthesis Support Available
• ispGDX Design Compiler
- Design Rule Checker
- I/O Connectivity Checker
- Automatic Compiler Function
Figure 5. ISP Device Programming Interface
SDO
SDI
MODE
SCLK
ispEN
• Industry Standard JEDEC File for Programming
• Min/Max Timing Report
5-wire
Programming
Interface
• Interfaces To Popular Timing Simulators
• User Electronic Signature (UES) Support
• Detailed Log and Report Files For Easy Design
Debug
• On-line Help
• Windows® XP, Windows 2000, Windows 98 and
Windows NT® Compatible
BSCAN/ispEN
BSCAN/ispEN
BSCAN/ispEN
ispGDX
80A
ispGDX
120A
ispGDX
160A
• Solaris® and HP-UX Versions Available
In-System Programmability
Figure 6. ispJTAG Device Programming Interface
All necessary programming of the ispGDXV/VA is done
via four TTL level logic interface signals. These four
signals are fed into the on-chip programming circuitry
where a state machine controls the programming.
TDO
TDI
TMS
TCK
ispJTAG
Programming
Interface
On-chip programming can be accomplished using an
IEEE 1149.1 boundary scan protocol. The IEEE 1149.1compliant interface signals are Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS) control. The EPEN pin is also used to enable or
disable the JTAG port.
VCC
The embedded controller port enable pin (EPEN) is used
to enable the JTAG tap controller and in that regard has
similar functionality to a TRST pin. When the pin is driven
high, the JTAG TAP controller is enabled. This is also true
when the pin is left unconnected, in which case the pin is
pulled high by the permanent internal pullup. This allows
ISP programming and BSCAN testing to take place as
specified by the Instruction Table.
When the pin is driven low, the JTAG TAP controller is
driven to a reset state asynchronously. It stays there
11
BSCAN/ispEN
BSCAN/ispEN
BSCAN/ispEN
ispGDX
80A
ispGDX
120A
ispGDX
160A
Specifications ispGDX Family
Table 3. I/O Shift Register Order
DEVICE
I/O SHIFT REGISTER ORDER
ispGDX80A
SDI/TDI, I/O B10 .. B19, I/O C0 .. C19, I/O D0 .. D9, RESET, Y1/TOE, Y0, I/O B9 .. B0, I/O A19.. A0,
I/O D19 .. D10, SDO/TDO
ispGDX120A
SDI/TDI, I/O B15 .. B29, I/O C0 .. C29, I/O D0 .. D14, TOE, Y2, Y3, RESET, Y1, Y0, I/O B14 .. B0,
I/O A29.. A0, I/O D29 .. D15, SDO/TDO
ispGDX160/A
SDI/TDI, I/O B20 .. B39, I/O C0 .. C39, I/O D0 .. D19, TOE, Y2, Y3, RESET, Y1, Y0, I/O B19 .. B0,
I/O A39.. A0, I/O D39 .. D20, SDO/TDO
I/O Shift Reg Order/ispGDX
Table 4. ispGDX Device ID Codes
8-BIT ISP ID
32-BIT BOUNDARY SCAN IDCODE
ispGDX80A
DEVICE
0111 0111
0000 0000 0010 0101 0001 0000 0100 0011
ispGDX120A
0111 1000
0000 0000 0010 0101 0010 0000 0100 0011
ispGDX160/A
0111 1001
0000 0000 0010 0101 0011 0000 0100 0011
GDX ID Codes
Boundary Scan
The ispGDXV/VA devices provide IEEE1149.1a test
capability and ISP programming through a standard
Boundary Scan Test Access Port (TAP) interface.
The boundary scan circuitry on the ispGDXV/VA Family
operates independently of the programmed pattern. This
allows customers using boundary scan test to have full
test capability with only a single BSDL file.
The ispGDXV/VA devices are identified by the 32-bit
JTAG IDCODE register. The device ID assignments are
listed in Table 4.
The ispJTAG programming is accomplished by executing Lattice private instructions under the Boundary Scan
State Machine.
Contact Lattice Technical Support to obtain more detailed programming information.
12
Specifications ispGDX Family
Figure 7. Boundary Scan I/O Register Cell
SCANIN
(from
previous
cell)
Normal
Function
OE
M
U
X
Q
D
D
M
U
X
Q
TOE
EXTEST
Normal
Function
OE
M
U
X
Q
D
D
M
U
X
Q
I/O Pin
Update DR
M
U
X
Shift DR
Q
D
SCANOUT (to next cell)
Clock DR
Figure 8. Boundary Scan State Machine
1
0
Test-Logic-Reset
0
1
Run-Test/Idle
Select-DR-Scan
0
1
Capture-DR
0
Shift-DR
0
1
Exit1-DR
1
0
Pause-DR
1
1
Select-IR-Scan
0
1
Capture-IR
0
Shift-IR
0
1
Exit1-IR
1
0
Pause-IR
1
0
1
0
0
Exit2-DR
1
Update-DR
1
0
0
Exit2-IR
1
Update-IR
1
0
TCK
t su
th
TMS or
TDI
t co
TDO
tsu = 0.1µs (min.)
th = 0.1µs (min.)
13
tco = 0.1µs (min.)
Specifications ispGDX Family
Signal Descriptions
Signal Name
Description
I/O
Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs, each
may be independently latched, registered or tristated. They can also each assume one other control
function (OE, CLK and MUXsel as described in the text).
TOE
Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven.
RESET
Active LOW Input Pin – Resets all I/O register outputs when LOW.
Y0, Y1, Y2, Y3
Input Pins – Dedicated clock input pins. Each pin can drive any or all I/O cell registers.
BSCAN/ispEN
Input Pin – When HIGH, this pin enables the Boundary Scan Test and Programming Interface. When
LOW, this pin enables the Lattice ISP protocol for programming and tristates all I/O pins, except those
used for the programming interface.
TDI/SDI
Input/Input Pin – Serial data input during ISP programming or Boundary Scan mode.
TCK/SCLK
Input/Input Pin – Serial data clock during ISP programming or Boundary Scan mode.
TMS/MODE
Input/Input Pin – Control input during ISP programming or Boundary Scan mode.
TDO/SDO
Output/Output Pin – Serial data output during ISP programming or Boundary Scan mode.
GND
Ground (GND)
VCC
Vcc – Supply voltage (5V).
NC1
No Connect.
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Locations: ispGDX160A
Signal
208-Pin PQFP
272-Ball BGA
TOE
178
A12
RESET
185
D10
Y0, Y1, Y2, Y3, 75, 76, 180, 181
V10, Y10, C11, A11
BSCAN/ispEN
183
B10
TDI/SDI
81
Y12
TCK/SCLK
80
U11
TMS/MODE
79
V11
TDO/SDO
78
W11
GND
6, 15, 25, 35, 44, 54, 63, 77, 91, 100, 110, 119, 129, A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12,
139, 148, 159, 168, 182, 195, 204
K9, K10, K11, K12, L9, L10, L11, L12, M9, M10,
M11, M12, N4, N17, U4, U8, U13, U17
VCC
1, 17, 33, 49, 65, 89, 105, 121, 137, 153, 170, 184
193
D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10,
U15
NC1
73, 74, 156, 179
A2, A6, A7, A10, A15, A19, A20, B1, B2, B4, B11,
B14, B18, B19, B20, C2, C3, C10, C18, D2, D3, D16,
E2, E17, E19, H1, H3, H18, H20, K20, L1, N1, N3,
N18, N20, T2, T4, T19, U5, U18, U19, V3, V14, V18,
V19, W1, W2, W3, W7, W10, W14, W19, W20, Y1,
Y2, Y6, Y9, Y11, Y18, Y20
1. NC pins are not to be connected to any active signals, VCC or GND.
14
Specifications ispGDX Family
I/O Locations: ispGDX160A
Signal
I/O A0
I/O A1
I/O A2
I/O A3
I/O A4
I/O A5
I/O A6
I/O A7
I/O A8
I/O A9
I/O A10
I/O A11
I/O A12
I/O A13
I/O A14
I/O A15
I/O A16
I/O A17
I/O A18
I/O A19
I/O A20
I/O A21
I/O A22
I/O A23
I/O A24
I/O A25
I/O A26
I/O A27
I/O A28
I/O A29
I/O A30
I/O A31
208 272
PQFP BGA
2
3
4
5
7
8
9
10
11
12
13
14
16
18
19
20
21
22
23
24
26
27
28
29
30
31
32
34
36
37
38
39
E4
C1
D1
E3
E1
F3
G4
F2
F1
G3
G2
G1
H2
J4
J3
J2
J1
K2
K3
K1
L2
L3
L4
M1
M2
M3
M4
N2
P1
P2
R1
P3
Signal
I/O A32
I/O A33
I/O A34
I/O A35
I/O A36
I/O A37
I/O A38
I/O A39
I/O B0
I/O B1
I/O B2
I/O B3
I/O B4
I/O B5
I/O B6
I/O B7
I/O B8
I/O B9
I/O B10
I/O B11
I/O B12
I/O B13
I/O B14
I/O B15
I/O B16
I/O B17
I/O B18
I/O B19
I/O B20
I/O B21
I/O B22
I/O B23
208
272
PQFP BGA
40
41
42
43
45
46
47
48
50
51
52
53
55
56
57
58
59
60
61
62
64
66
67
68
69
70
71
72
82
83
84
85
R2
T1
P4
R3
U1
T3
U2
V1
U3
V2
W4
V4
Y3
Y4
V5
W5
Y5
V6
U7
W6
V7
Y7
V8
W8
Y8
U9
V9
W9
W12
V12
U12
Y13
Signal
208
PQFP
272
BGA
Signal
I/O B24
I/O B25
I/O B26
I/O B27
I/O B28
I/O B29
I/O B30
I/O B31
I/O B32
I/O B33
I/O B34
I/O B35
I/O B36
I/O B37
I/O B38
I/O B39
I/O C0
I/O C1
I/O C2
I/O C3
I/O C4
I/O C5
I/O C6
I/O C7
I/O C8
I/O C9
I/O C10
I/O C11
I/O C12
I/O C13
I/O C14
I/O C15
86
87
88
90
92
93
94
95
96
97
98
99
101
102
103
104
106
107
108
109
111
112
113
114
115
116
117
118
120
122
123
124
W13
V13
Y14
Y15
W15
Y16
U14
V15
W16
Y17
V16
W17
U16
V17
W18
Y19
T17
V20
U20
T18
T20
R18
P17
R19
R20
P18
P19
P20
N19
M17
M18
M19
I/O C16
I/O C17
I/O C18
I/O C19
I/O C20
I/O C21
I/O C22
I/O C23
I/O C24
I/O C25
I/O C26
I/O C27
I/O C28
I/O C29
I/O C30
I/O C31
I/O C32
I/O C33
I/O C34
I/O C35
I/O C36
I/O C37
I/O C38
I/O C39
I/O D0
I/O D1
I/O D2
I/O D3
I/O D4
I/O D5
I/O D6
I/O D7
15
208
PQFP
272
BGA
Signal
125
126
127
128
130
131
132
133
134
135
136
138
140
141
142
143
144
145
146
147
149
150
151
152
154
155
157
158
160
161
162
163
M20
L19
L18
L20
K19
K18
K17
J20
J19
J18
J17
H19
G20
G19
F20
G18
F19
E20
G17
F18
D20
E18
D19
C20
D18
C19
B17
C17
A18
A17
C16
B16
I/O D8
I/O D9
I/O D10
I/O D11
I/O D12
I/O D13
I/O D14
I/O D15
I/O D16
I/O D17
I/O D18
I/O D19
I/O D20
I/O D21
I/O D22
I/O D23
I/O D24
I/O D25
I/O D26
I/O D27
I/O D28
I/O D29
I/O D30
I/O D31
I/O D32
I/O D33
I/O D34
I/O D35
I/O D36
I/O D37
I/O D38
I/O D39
208
PQFP
272
BGA
164
165
166
167
169
171
172
173
174
175
176
177
186
187
188
189
190
191
192
194
196
197
198
199
200
201
202
203
205
206
207
208
A16
C15
D14
B15
C14
A14
C13
B13
A13
D12
C12
B12
A9
B9
C9
D9
A8
B8
C8
B7
C7
B6
A5
D7
C6
B5
A4
C5
A3
D5
C4
B3
Specifications ispGDX Family
Signal Configuration: ispGDX160A
ispGDX160A 272-Ball BGA Signal Diagram
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
A
NC1
NC1
I/O
D4
I/O
D5
I/O
D8
NC1
I/O
D13
I/O
D16 TOE
Y3
NC1
I/O
D20
I/O
D24
NC1
NC1
I/O
D30
I/O
D34
I/O
D36
NC1 GND
A
B
NC1
NC1
NC1
I/O
D2
I/O
D7
I/O
D11
NC1
I/O
D15
I/O
D19
NC1
BSCAN/
ispEN
I/O
D21
I/O
D25
I/O
D27
I/O
D29
I/O
D33
NC1
I/O
D39
NC1
NC1
B
C
I/O
C39
I/O
D1
NC1
I/O
D3
I/O
D6
I/O
D9
I/O
D12
I/O
D14
I/O
D18
Y2
NC1
I/O
D22
I/O
D26
I/O
D28
I/O
D32
I/O
D35
I/O
D38
NC1
NC1
I/O
A1
C
D
I/O
C36
I/O
C38
I/O
D0
GND NC1
I/O
I/O
I/O
1
D23 GND D31 VCC D37 GND NC
NC1
I/O
A2
D
E
I/O
C33
NC1
I/O
C37
NC1
F
I/O
C30
I/O
C32
I/O
C35 VCC
G
I/O
C28
I/O
C29
I/O
C31
H
NC1
I/O
C27
NC1 GND
J
I/O
C23
I/O
C24
I/O
C25
I/O
C26
GND GND GND GND
I/O
A13
K
NC1
I/O
C20
I/O
C21
I/O
C22
L
I/O
C19
I/O
C17
M
I/O
C16
N
VCC
I/O
I/O
GND
VCC
D10
D17
RESET
2
1
I/O
A0
I/O
A3
NC1
I/O
A4
E
ispGDX160A
VCC
I/O
A5
I/O
A7
I/O
A8
F
Bottom View
I/O
A6
I/O
A9
I/O
A10
I/O
A11
G
GND NC1
I/O
A12
NC1
H
I/O
A14
I/O
A15
I/O
A16
J
GND GND GND GND
I/O
VCC A18
I/O
A17
I/O
A19
K
I/O
C18 VCC
GND GND GND GND
I/O
A22
I/O
A21
I/O
A20
NC1
L
I/O
C15
I/O
C14
GND GND GND GND
I/O
A26
I/O
A25
I/O
A24
I/O
A23
M
NC1
I/O
C12
NC1 GND
GND NC1
I/O
A27
NC1
N
P
I/O
C11
I/O
C10
I/O
C9
I/O
C6
I/O
A31
I/O
A29
I/O
A28
P
R
I/O
C8
I/O
C7
I/O
C5
VCC
I/O
VCC A35
I/O
A32
I/O
A30
R
T
I/O
C4
NC1
I/O
C3
I/O
C0
NC1
I/O
A37
NC1
I/O
A33
T
U
I/O
C2
NC1
I/O
I/O
I/O
NC1 GND B36 VCC B30 GND B22
I/O
I/O
VCC B17 GND B10 VCC NC1 GND
I/O
B0
I/O
A38
I/O
A36
U
V
I/O
C1
NC1
NC1
I/O
B37
I/O
B34
I/O
B31
NC1
I/O
B25
I/O
B21
TMS/
MODE
Y0
I/O
B18
I/O
B14
I/O
B12
I/O
B9
I/O
B6
I/O
B3
NC1
I/O
B1
I/O
A39
V
W
NC1
NC1
I/O
B38
I/O
B35
I/O
B32
I/O
B28
NC1
I/O
B24
I/O
B20
TDO/
SDO
NC1
I/O
B19
I/O
B15
NC1
I/O
B11
I/O
B7
I/O
B2
NC1
NC1
NC1
W
Y
NC1
I/O
B39
NC1
I/O
B33
I/O
B29
I/O
B27
I/O
B26
I/O
B23
TDI/
SDI
NC1
Y1
NC1
I/O
B16
I/O
B13
NC1
I/O
B8
I/O
B5
I/O
B4
NC1
NC1
Y
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
I/O
C34
I/O
C13
I/O
A34
TCK/
SCLK
1. NCs are not to be connected to any active signals, Vcc or GND.
Note: Ball A1 indicator dot on top side of package.
16
Specifications ispGDX Family
Pin Configuration: ispGDX160A
Control
Data
VCC
I/O A 0
I/O A 1
I/O A 2
I/O A 3
GND
I/O A 4
I/O A 5
I/O A 6
I/O A 7
I/O A 8
I/O A 9
I/O A 10
I/O A 11
GND
I/O A 12
VCC
I/O A 13
I/O A 14
I/O A 15
I/O A 16
I/O A 17
I/O A 18
I/O A 19
GND
I/O A 20
I/O A 21
I/O A 22
I/O A 23
I/O A 24
I/O A 25
I/O A 26
VCC
I/O A 27
GND
I/O A 28
I/O A 29
I/O A 30
I/O A 31
I/O A 32
I/O A 33
I/O A 34
I/O A 35
GND
I/O A 36
I/O A 37
I/O A 38
I/O A 39
VCC
I/O B 0
I/O B 1
I/O B 2
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
Data
—
CLK
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
CLK
—
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
—
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
ispGDX160A
Top View
Data
I/O B 3
GND
I/O B 4
I/O B 5
I/O B 6
I/O B 7
I/O B 8
I/O B 9
I/O B 10
I/O B 11
GND
I/O B 12
VCC
I/O B 13
I/O B 14
I/O B 15
I/O B 16
I/O B 17
I/O B 18
I/O B 19
1NC
1NC
Y0
Y1
GND
TDO/SDO
TMS/MODE
TCK/SCLK
TDI/SDI
I/O B 20
I/O B 21
I/O B 22
I/O B 23
I/O B 24
I/O B 25
I/O B 26
VCC
I/O B 27
GND
I/O B 28
I/O B 29
I/O B 30
I/O B 31
I/O B 32
I/O B 33
I/O B 34
I/O B 35
GND
I/O B 36
I/O B 37
I/O B 38
I/O B 39
Control
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
CLK
—
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
—
—
—
—
—
—
—
—
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
—
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Control
I/O D 39
MUXsel2
I/O D 38
MUXsel1
I/O D 37
OE
I/O D 36
CLK
GND
—
I/O D 35
MUXsel2
I/O D 34
MUXsel1
I/O D 33
OE
I/O D 32
CLK
I/O D 31
MUXsel2
I/O D 30
MUXsel1
I/O D 29
OE
I/O D 28
CLK
GND
—
I/O D 27
MUXsel2
VCC
—
I/O D 26
MUXsel1
I/O D 25
OE
I/O D 24
CLK
I/O D 23
MUXsel2
I/O D 22
MUXsel1
I/O D 21
OE
I/O D 20
CLK
RESET
—
VCC
—
BSCAN/ispEN —
GND
—
Y3
—
Y2
—
NC1
—
TOE
—
I/O D 19
MUXsel2
I/O D 18
MUXsel1
I/O D 17
OE
I/O D 16
CLK
I/O D 15
MUXsel2
I/O D 14
MUXsel1
I/O D 13
OE
VCC
—
I/O D 12
CLK
GND
—
I/O D 11
MUXsel2
I/O D 10
MUXsel1
I/O D 9
OE
I/O D 8
CLK
I/O D 7
MUXsel2
I/O D 6
MUXsel1
I/O D 5
OE
I/O D 4
CLK
GND
—
I/O D 3
MUXsel2
I/O D 2
MUXsel1
ispGDX160A 208-Pin PQFP (with Heat Spreader) Pinout Diagram
1. No Connect Pins (NC) are not to be connected to any active signal, Vcc or GND.
17
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
Data
Control
NC1
I/O D1
I/O D 0
VCC
I/O C 39
I/O C 38
I/O C 37
I/O C 36
GND
I/O C 35
I/O C 34
I/O C 33
I/O C 32
I/O C 31
I/O C 30
I/O C 29
I/O C 28
GND
I/O C 27
VCC
I/O C 26
I/O C 25
I/O C 24
I/O C 23
I/O C 22
I/O C 21
I/O C 20
GND
I/O C 19
I/O C 18
I/O C 17
I/O C 16
I/O C 15
I/O C 14
I/O C 13
VCC
I/O C 12
GND
I/O C 11
I/O C 10
I/O C 9
I/O C 8
I/O C 7
I/O C 6
I/O C 5
I/O C 4
GND
I/O C 3
I/O C 2
I/O C 1
I/O C 0
VCC
—
OE
CLK
—
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
—
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
—
CLK
—
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
MUXsel1
OE
CLK
—
Specifications ispGDX Family
Signal Locations: ispGDX120A
Signal
176-Pin TQFP
160-Pin PQFP
TOE
150
136
RESET
156
142
Y0, Y1, Y2, Y3, 63, 64, 152, 153
57, 58, 138, 139
BSCAN/ispEN
154
140
TDI/SDI
69
63
TCK/SCLK
68
62
TMS/MODE
67
61
TDO/SDO
66
60
GND
8, 17, 27, 37, 50, 65, 77, 91, 101, 110, 120, 129,
144, 161, 170
6, 15, 25, 35, 44, 59, 71, 81, 91, 100, 110, 119, 130,
147, 156
VCC
3, 19, 35, 55, 79, 99, 115, 136, 155, 159
1, 17, 33, 49, 73, 89, 105, 122, 141, 145
1
1, 2, 43, 44, 45, 46, 61, 62, 87, 88, 89, 90, 130, 131, 55, 56, 120, 137
132, 133, 134, 151, 175, 176
NC
1. NC pins are not to be connected to any active signals, VCC or GND.
I/O Locations: ispGDX120A
Signal
I/O A0
I/O A1
I/O A2
I/O A3
I/O A4
I/O A5
I/O A6
I/O A7
I/O A8
I/O A9
I/O A10
I/O A11
I/O A12
I/O A13
I/O A14
I/O A15
I/O A16
I/O A17
I/O A18
I/O A19
I/O A20
I/O A21
I/O A22
I/O A23
176 160
TQFP PQFP
4
5
6
7
9
10
11
12
13
14
15
16
18
20
21
22
23
24
25
26
28
29
30
31
2
3
4
5
7
8
9
10
11
12
13
14
16
18
19
20
21
22
23
24
26
27
28
29
Signal
I/O A24
I/O A25
I/O A26
I/O A27
I/O A28
I/O A29
I/O B0
I/O B1
I/O B2
I/O B3
I/O B4
I/O B5
I/O B6
I/O B7
I/O B8
I/O B9
I/O B10
I/O B11
I/O B12
I/O B13
I/O B14
I/O B15
I/O B16
I/O B17
176 160
TQFP PQFP
32
33
34
36
38
39
40
41
42
47
48
49
51
52
53
54
56
57
58
59
60
70
71
72
30
31
32
34
36
37
38
39
40
41
42
43
45
46
47
48
50
51
52
53
54
64
65
66
Signal
I/O B18
I/O B19
I/O B20
I/O B21
I/O B22
I/O B23
I/O B24
I/O B25
I/O B26
I/O B27
I/O B28
I/O B29
I/O C0
I/O C1
I/O C2
I/O C3
I/O C4
I/O C5
I/O C6
I/O C7
I/O C8
I/O C9
I/O C10
I/O C11
176 160
TQFP PQFP
73
74
75
76
78
80
81
82
83
84
85
86
92
93
94
95
96
97
98
100
102
103
104
105
18
67
68
69
70
72
74
75
76
77
78
79
80
82
83
84
85
86
87
88
90
92
93
94
95
Signal
I/O C12
I/O C13
I/O C14
I/O C15
I/O C16
I/O C17
I/O C18
I/O C19
I/O C20
I/O C21
I/O C22
I/O C23
I/O C24
I/O C25
I/O C26
I/O C27
I/O C28
I/O C29
I/O D0
I/O D1
I/O D2
I/O D3
I/O D4
I/O D5
176 160
TQFP PQFP
106
107
108
109
111
112
113
114
116
117
118
119
121
122
123
124
125
126
127
128
135
137
138
139
96
97
98
99
101
102
103
104
106
107
108
109
111
112
113
114
115
116
117
118
121
123
124
125
Signal
I/O D6
I/O D7
I/O D8
I/O D9
I/O D10
I/O D11
I/O D12
I/O D13
I/O D14
I/O D15
I/O D16
I/O D17
I/O D18
I/O D19
I/O D20
I/O D21
I/O D22
I/O D23
I/O D24
I/O D25
I/O D26
I/O D27
I/O D28
I/O D29
176 160
TQFP PQFP
140
141
142
143
145
146
147
148
149
157
158
160
162
163
164
165
166
167
168
169
171
172
173
174
126
127
128
129
131
132
133
134
135
143
144
146
148
149
150
151
152
153
154
155
157
158
159
160
Specifications ispGDX Family
Pin Configuration: ispGDX120A
Control
Data
Data
1NC
1NC
VCC
I/O A 0
I/O A 1
I/O A 2
I/O A 3
GND
I/O A 4
I/O A 5
I/O A 6
I/O A 7
I/O A 8
I/O A 9
I/O A 10
I/O A 11
GND
I/O A 12
VCC
I/O A 13
I/O A 14
I/O A 15
I/O A 16
I/O A 17
I/O A 18
I/O A 19
GND
I/O A 20
I/O A 21
I/O A 22
I/O A 23
I/O A 24
I/O A 25
I/O A 26
VCC
I/O A 27
GND
I/O A 28
I/O A 29
I/O B 0
I/O B1
I/O B 2
1NC
1NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ispGDX120A
Top View
Data
1NC
Control
—
—
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
—
—
—
—
—
—
—
—
—
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
CLK
—
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
—
1NC
I/O B 3
I/O B 4
I/O B 5
GND
I/O B 6
I/O B 7
I/O B 8
I/O B 9
VCC
I/O B 10
I/O B 11
I/O B 12
I/O B 13
I/O B 14
1NC
1NC
Y0
Y1
GND
TDO/SDO
TMS/MODE
TCK/SCLK
TDI/SDI
I/O B 15
I/O B 16
I/O B 17
I/O B 18
I/O B 19
I/O B 20
I/O B 21
GND
I/O B 22
VCC
I/O B 23
I/O B 24
I/O B 25
I/O B 26
I/O B 27
I/O B 28
I/O B 29
1NC
1NC
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
—
—
—
CLK
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
CLK
—
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
—
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
—
—
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
Control
NC1
—
NC1
—
I/O D 29
MUXsel2
I/O D 28
MUXsel1
I/O D 27
OE
I/O D 26
CLK
GND
—
I/O D 25
MUXsel2
I/O D 24
MUXsel1
I/O D 23
OE
I/O D 22
CLK
I/O D 21
MUXsel2
I/O D 20
MUXsel1
I/O D 19
OE
I/O D 18
CLK
GND
—
I/O D 17
MUXsel2
VCC
—
I/O D 16
MUXsel1
I/O D 15
OE
RESET
—
VCC
—
2
BSCAN/ispEN —
Y3
—
Y2
—
NC
—
TOE
—
I/O D 14
CLK
I/O D 13
MUXsel2
I/O D 12
MUXsel1
I/O D 11
OE
I/O D 10
CLK
GND
—
I/O D 9
MUXsel2
I/O D 8
MUXsel1
I/O D 7
OE
I/O D 6
CLK
I/O D 5
MUXsel2
I/O D 4
MUXsel1
I/O D 3
OE
VCC
—
I/O D 2
CLK
1
NC
—
NC1
—
ispGDX120A 176-Pin TQFP Pinout Diagram
1. NC pins are not to be connected to any active signals, VCC or GND.
19
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
Data
Control
NC1
NC1
NC1
GND
I/O D 1
I/O D 0
I/O C 29
I/O C 28
I/O C 27
I/O C 26
I/O C 25
I/O C 24
GND
I/O C 23
I/O C 22
I/O C 21
I/O C 20
VCC
I/O C 19
I/O C 18
I/O C 17
I/O C 16
GND
I/O C 15
I/O C 14
I/O C 13
I/O C 12
I/O C 11
I/O C 10
I/O C 9
I/O C 8
GND
I/O C 7
VCC
I/O C 6
I/O C 5
I/O C 4
I/O C 3
I/O C 2
I/O C 1
I/O C 0
GND
NC1
NC1
—
—
—
—
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
—
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
—
—
—
Specifications ispGDX Family
Pin Configuration: ispGDX120A
Control
Data
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
I/O D 29
MUXsel2
I/O D 28
MUXsel1
I/O D 27
OE
I/O D 26
CLK
GND
—
I/O D 25
MUXsel2
I/O D 24
MUXsel1
I/O D 23
OE
I/O D 22
CLK
I/O D 21
MUXsel2
I/O D 20
MUXsel1
I/O D 19
OE
I/O D 18
CLK
GND
—
I/O D 17
MUXsel2
VCC
—
I/O D 16
MUXsel1
I/O D 15
OE
RESET
—
VCC
—
BSCAN/ispEN —
Y3
—
Y2
—
NC1
—
TOE
—
I/O D 14
CLK
I/O D 13
MUXsel2
I/O D 12
MUXsel1
I/O D 11
OE
I/O D 10
CLK
GND
—
I/O D 9
MUXsel2
I/O D 8
MUXsel1
I/O D 7
OE
I/O D 6
CLK
I/O D 5
MUXsel2
I/O D 4
MUXsel1
I/O D 3
OE
VCC
—
I/O D 2
CLK
ispGDX120A 160-Pin PQFP Pinout Diagram
Data
—
CLK
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
CLK
—
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
—
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
VCC
I/O A 0
I/O A 1
I/O A 2
I/O A 3
GND
I/O A 4
I/O A 5
I/O A 6
I/O A 7
I/O A 8
I/O A 9
I/O A 10
I/O A 11
GND
I/O A 12
VCC
I/O A 13
I/O A 14
I/O A 15
I/O A 16
I/O A 17
I/O A 18
I/O A 19
GND
I/O A 20
I/O A 21
I/O A 22
I/O A 23
I/O A 24
I/O A 25
I/O A 26
VCC
I/O A 27
GND
I/O A 28
I/O A 29
I/O B 0
I/O B1
I/O B 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ispGDX120A
Top View
Data
I/O B 3
I/O B 4
I/O B 5
GND
I/O B 6
I/O B 7
I/O B 8
I/O B 9
VCC
I/O B 10
I/O B 11
I/O B 12
I/O B 13
I/O B 14
1NC
1NC
Y0
Y1
GND
TDO/SDO
TMS/MODE
TCK/SCLK
TDI/SDI
I/O B 15
I/O B 16
I/O B 17
I/O B 18
I/O B 19
I/O B 20
I/O B 21
GND
I/O B 22
VCC
I/O B 23
I/O B 24
I/O B 25
I/O B 26
I/O B 27
I/O B 28
I/O B 29
Control
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
—
CLK
OE
MUXsel1
MUXsel2
CLK
—
—
—
—
—
—
—
—
—
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
—
CLK
—
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Control
1. NC pins are not to be connected to any active signals, VCC or GND.
20
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Data
Control
NC1
GND
I/O D 1
I/O D 0
I/O C 29
I/O C 28
I/O C 27
I/O C 26
I/O C 25
I/O C 24
GND
I/O C 23
I/O C 22
I/O C 21
I/O C 20
VCC
I/O C 19
I/O C 18
I/O C 17
I/O C 16
GND
I/O C 15
I/O C 14
I/O C 13
I/O C 12
I/O C 11
I/O C 10
I/O C 9
I/O C 8
GND
I/O C 7
VCC
I/O C 6
I/O C 5
I/O C 4
I/O C 3
I/O C 2
I/O C 1
I/O C 0
GND
—
—
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
—
MUXsel2
—
MUXsel1
OE
CLK
MUXsel2
MUXsel1
OE
CLK
—
Specifications ispGDX Family
Signal Locations: ispGDX80A
Signal
100-Pin TQFP
Y1/TOE
87
Y0
38
RESET
89
BSCAN/ispEN
35
TDI/SDI
39
TCK/SCLK
36
TMS/MODE
86
TDO/SDO
85
GND
6, 18, 29, 45, 56, 68, 79, 95
VCC
12, 37, 62, 88
I/O Locations: ispGDX80A
Signal
I/O A0
I/O A1
I/O A2
I/O A3
I/O A4
I/O A5
I/O A6
I/O A7
I/O A8
I/O A9
I/O A10
I/O A11
I/O A12
I/O A13
I/O A14
I/O A15
I/O A16
I/O A17
I/O A18
I/O A19
100 TQFP
1
2
3
4
5
7
8
9
10
11
13
14
15
16
17
19
20
21
22
23
Signal
I/O B0
I/O B1
I/O B2
I/O B3
I/O B4
I/O B5
I/O B6
I/O B7
I/O B8
I/O B9
I/O B10
I/O B11
I/O B12
I/O B13
I/O B14
I/O B15
I/O B16
I/O B17
I/O B18
I/O B19
100 TQFP Signal
100 TQFP Signal
24
25
26
27
28
30
31
32
33
34
40
41
42
43
44
46
47
48
49
50
I/O C0
I/O C1
I/O C2
I/O C3
I/O C4
I/O C5
I/O C6
I/O C7
I/O C8
I/O C9
I/O C10
I/O C11
I/O C12
I/O C13
I/O C14
I/O C15
I/O C16
I/O C17
I/O C18
I/O C19
51
52
53
54
55
57
58
59
60
61
63
64
65
66
67
69
70
71
72
73
21
I/O D0
I/O D1
I/O D2
I/O D3
I/O D4
I/O D5
I/O D6
I/O D7
I/O D8
I/O D9
I/O D10
I/O D11
I/O D12
I/O D13
I/O D14
I/O D15
I/O D16
I/O D17
I/O D18
I/O D19
100 TQFP
74
75
76
77
78
80
81
82
83
84
90
91
92
93
94
96
97
98
99
100
Specifications ispGDX Family
Pin Configuration: ispGDX80A
Data
I/O A0
I/O A1
I/O A2
I/O A3
I/O A4
GND
I/O A5
I/O A6
I/O A7
I/O A8
I/O A9
VCC
I/O A10
I/O A11
I/O A12
I/O A13
I/O A14
GND
I/O A15
I/O A16
I/O A17
I/O A18
I/O A19
I/O B0
I/O B1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O D19
MUXsel2
I/O D18
MUXsel1
I/O D17
OE
I/O D16
CLK
I/O D15
MUXsel2
GND
—
I/O D14
MUXsel1
I/O D13
OE
I/O D12
CLK
I/O D11
MUXsel2
I/O D10
MUXsel1
RESET
—
VCC
—
—
Y1/TOE1
TMS/MODE1 —
—
TDO/SDO1
OE
I/O D9
CLK
I/O D8
MUXsel2
I/O D7
MUXsel1
I/O D6
OE
I/O D5
—
GND
CLK
I/O D4
MUXsel2
I/O D3
MUXsel1
I/O D2
ispGDX80A
Top View
Data
Control
I/O B2
MUXsel1
I/O B3
MUXsel2
I/O B4
CLK
GND
—
I/O B5
OE
I/O B6
MUXsel1
I/O B7
MUXsel2
I/O B8
CLK
I/O B9
OE
— BSCAN/ispEN
1TCK/SCLK
—
VCC
—
Y0
—
1TDI/SDI
—
I/O B10
MUXsel1
I/O B11
MUXsel2
I/O B12
CLK
I/O B13
OE
I/O B14
MUXsel1
GND
—
I/O B15
MUXsel2
I/O B16
CLK
I/O B17
OE
I/O B18
MUXsel1
I/O B19
MUXsel2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Control
CLK
OE
MUXsel1
MUXsel2
CLK
—
OE
MUXsel1
MUXsel2
CLK
OE
—
MUXsel1
MUXsel2
CLK
OE
MUXsel1
—
MUXsel2
CLK
OE
MUXsel1
MUXsel2
CLK
OE
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Data
Control
ispGDX80A 100-Pin TQFP Pinout Diagram
1. Pins have dual function capability.
22
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Data
Control
I/O D1
I/O D0
I/O C19
I/O C18
I/O C17
I/O C16
I/O C15
GND
I/O C14
I/O C13
I/O C12
I/O C11
I/O C10
VCC
I/O C9
I/O C8
I/O C7
I/O C6
I/O C5
GND
I/O C4
I/O C3
I/O C2
I/O C1
I/O C0
OE
CLK
MUXsel2
MUXsel1
OE
CLK
MUXsel2
—
MUXsel1
OE
CLK
MUXsel2
MUXsel1
—
OE
CLK
MUXsel2
MUXsel1
OE
—
CLK
MUXsel2
MUXsel1
OE
CLK
Specifications ispGDX Family
Part Number Description
ispGDX XXXX – X XXXX X
Device Family
Grade
Blank = Commercial
Device Number
160A
120A
80A
Package
Q208 = PQFP (with Heat Spreader)
T176 = TQFP
Q160 = PQFP
B272 = BGA
T100 = TQFP
Speed
5 = 5ns Tpd
7 = 7ns Tpd
0212/ispGDX
Ordering Information
COMMERCIAL
I/O PINS
160A
120
80
tpd (ns)
ORDERING NUMBER
PACKAGE
5
ispGDX160A-5Q208
208-Pin PQFP
5
ispGDX160A-5B272
272-Ball BGA
7
ispGDX160A-7Q208
208-Pin PQFP
7
ispGDX160A-7B272
272-Ball BGA
5
ispGDX120A-5T176
176-Pin TQFP
5
ispGDX120A-5Q160
160-Pin PQFP
7
ispGDX120A-7T176
176-Pin TQFP
7
ispGDX120A-7Q160
160-Pin PQFP
5
ispGDX80A-5T100
100-Pin TQFP
7
ispGDX80A-7T100
100-Pin TQFP
Table 2-0041/ispGDX
23