HV62208 32-Channel 256 Gray-Shade High Voltage Driver Ordering Information Package Option Device 64-Lead 3-Sided Plastic Gullwing Die HV62208 HV62208PG HV62208X Features General Description ❏ HVCMOS® technology Not recommended for new designs. Please use HV632 instead. ❏ 5V CMOS inputs ❏ Up to 80V output voltage ❏ PWM gray shade conversion The HV622 is a 32-channel gray-shade column driver IC designed for driving electrofluorescent displays. Using Supertex’s unique HVCMOS® technology, it is capable of 256 levels of gray shading by PWM conversion. ❏ Capable of 256 levels of gray shading ❏ Balanced shift clock complies with RS-422 ❏ 8MHz shift and count clock frequency ❏ 16MHz data throughput rate ❏ 8 bit data bus ❏ 32 outputs per device ❏ BLANK function Absolute Maximum Ratings Supply voltage, VDD -0.5V to +7.5V Supply voltage, VPP -0.5V to +80V Supply voltage, VNN -15V to 0V Logic input levels Storage temperature range The BLANK input signal will reset the master counter to all ones (1111 1111) and set all high voltage outputs to low. -0.5 to VDD + 0.5V Continuous total power dissipation Operating temperature range The shift clock is a balanced clock with electrical characteristics complying with EIA RS-422 standard. Input data, in groups of eight, is latched into a set of data latches on both edges of the shift clock. The data shifted in the first data latch corresponds to HVOUT1, the second data latch corresponds to HVOUT2, and so on. These data are compared to the contents of the master binary counter which counts on both edges of the count clock. Each time the master counter begins to decrement from 1111 1111, the data in the data latches are compared with the contents of the counter; if they match, the corresponding outputs will go high. The master counter counts down to 0000 0001 and then starts to count up again. The outputs that are at high will stay at high until the contents of the counter match the data in the data latches again. Therefore, the higher the binary data in the data latches, the longer the outputs will stay at high. Thus, different high voltage pulse widths are produced. When the counter reaches its 1111 1111 count while counting up, the device is ready for the next operation cycle. A data value of 0000 0000 produces no pulse; the output stays low. 1.2W -40°C to +85°C -65°C to +150°C Notes: All voltages are referenced to GND. Maximum VPP to VNN voltage is 90V. For operation above 25°C ambient derate linearly to 85°C at 20mW/°C. 02/96/022 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the 1 refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, HV62208 Electrical Characteristics (Over recommended conditions of VDD = 5V, VPP = 70V, VNN = -10V, TA = 25°C unless otherwise noted) Low-Voltage DC Characteristics (Digital) Symbol Parameter Min Max Units 4.5 5.5 V Conditions VDD Low-voltage digital supply voltage IDD VDD supply current 25 mA fSC = 8MHz, fCC = 8MHz IDDQ Quiescent VDD supply current 100 µA All VIN = GND, Count Clock = VDD IIH High-level input current 10 µA VIN = VDD IIL Low-level input current -10 µA VIL = GND IOH High-level output current -1.0 mA IOL Low-level ouptut current 1.0 mA Low-Voltage DC Characteristics (Analog) Symbol Parameter Min Max Units 4.5 5.5 V Conditions VDD Low-voltage analog supply voltage IDD VDD supply current 100 µA fSC = 8MHz, fCC = 8MHz IDDQ Quiescent VDD supply current 100 µA All VIN = GND, Count Clock = VDD Max Units Conditions 100 µA High-Voltage DC Characteristics Symbol Parameter Min IPPQ Quiescent VPP supply current IOUT(p) P-channel output current -4.0 mA IOUT(n) N-channel output current 4.0 mA All HVOUT low or high AC Characteristics Symbol Parameter Min Max Units fSC Shift clock frequency 8.0 MHz fCC Count clock frequency 8.0 MHz fDIN Data In frequency 16 MHz tCW Chip select pulse width 80 ns tCSS Chip select to shift clock set-up time 15 ns tCSH Chip select to shift clock hold time 45 ns tSCC Shift clock cycle time 125 ns tDSS Data to shift clock set-up time 10 ns tDSH Data to shift clock hold time 52 ns tDW Data In pulse width 62 ns tLCW Load count pulse width 75 ns tCCW Count clock pulse width 62.5 ns tCCC Count clock cycle time 125 ns tLCD Load count to count clock delay 100 ns tCCD Count clock to HVOUT turn-on/turn-off tBLW BLANK pulse width tBLD BLANK to HVOUT delay tCDD Count clock delay between count down and count up cycles 600 700 2 CL = 15pF ns 500 500 ns Conditions ns ns CL = 15pF HV62208 Recommended Operating Conditions Symbol Parameter Min Max Units VDD Logic supply voltage 4.5 5.5 V VPP Positive high-voltage supply 12 70 V VNN Negative high-voltage supply -8 -10 V VIL Low-level input voltage 0 1 V VIH High-level input voltage VDD–1 VDD V fSC Shift clock frequency 8 MHz fCC Count clock frequency 8 MHz TA Operating temperature +85 °C -40 Conditions Pin Definitions Pin # Name I/O Function 27-30 36-29 D1 – D8 I Inputs for binary-format parallel data (D8 is the most significant bit) 34 Shift Clock I Triggers data on both edges 35 Shift Clock I Triggers data on both edges 31 Count Clock I Input to the counter 24 CSI I Chip select input to enable the device to accept data 25 CSO O Chip select output to enable the next device 33 Load Count I Input to initiate the counting 26 Blank I Input to reset the counter and HVOUT 4-19 46-61 HVOUT1 – HVOUT32 O High-voltage outputs 23,43 VPP — Positive high-voltage supply 41 VDD (Analog) — Low-voltage analog supply voltage 40 VDD (Digital) — Low-voltage digital supply voltage 22,44 VNN — Negative high-voltage supply 20-21 GND (Digital) — Digital ground 42 GND (Analog) Analog ground Input and Output Equivalent Circuits VDD VDD VPP Input Data Out GND GND Logic Inputs HVOUT VNN Logic Data Output 3 High Voltage Output HV62208 Functional Block Diagram VPP 8 8 Data Latch 1 > VPP > 8 Bit Data In Comparator & Latch 1 Logic L/T HVOUT1 Logic L/T HVOUT2 Logic L/T HVOUT3 ≈ ≈ • • • Logic L/T 8 8 Data Latch 2 > Comparator & Latch 2 8 8 Data Latch 3 > Comparator & Latch 3 8 ≈ ≈ ≈ 8 Data Latch 32 Comparator & Latch 32 HVOUT32 > > ≈ 8 Count Clock > > > > > 8 Bit Counter Logic > VNN VNN + Shift Clock – CSI Load Count CSO Blank L/T = Level Translator Shift Clock Timing Diagrams 1 2 3 4 16 1 2 3 VALID DATA ≈ Shift Clock ≈ CSI 4 VALID DATA CSO 253 252 255 254 253 252 HVOUT 4 1 1 1 1 ≈ 254 252 253 254 255 252 253 254 255 ≈ 255 ≈ Count Clock ≈ LC 16 HV62208 Timing Diagrams LOADING LAST DEVICE NEXT LOADING CYCLE t CW VIH 50% CSI VIL t CSH t CSS VIH t DSS DATA SET 1 DATA SET 2 t DSH SC16 DATA SET 3 DATA SET 31 SC1 DATA SET 32 DATA SET 1 DATA SET 2 ≈ ≈ ≈ 50% SC2 ≈ ≈ SC1 ≈ 50% Shift Clock Data 1–8 t SCC VIL SCN VIH DATA SET 2N -1 DATA SET 2N VIL t DW t LCW VIH 50% 50% VIL ≈ Load Count t LCD t CCW t CCC VIH ≈ Count Clock 50% 50% 50% 50% 50% t CCD ≈ t CCD 90% HVOUT VIL VPP 90% 10% VNN 10% t BLW VIH 50% 50% VIL ≈ BLANK t BLD HVOUT VPP 90% VNN t CDD Count Clock ≈ 50% 255 254 3 2 5 1 VIH 50% 1 2 3 VIL HV62208 Pin Configurations Pin Function Pin Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 N/C N/C N/C HVOUT17 HVOUT18 HVOUT19 HVOUT20 HVOUT21 HVOUT22 HVOUT23 HVOUT24 HVOUT25 HVOUT26 HVOUT27 HVOUT28 HVOUT29 HVOUT30 HVOUT31 HVOUT32 GND (Digital) GND (Digital) VNN VPP CSI CSO Blank D1 D2 D3 D4 Count Clock N/C 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Load Count Shift Clock Shift Clock D5 D6 D7 D8 VDD (Digital) VDD (Analog) GND (Analog) VPP VNN N/C HVOUT1 HVOUT 2 HVOUT 3 HVOUT 4 HVOUT 5 HVOUT 6 HVOUT 7 HVOUT 8 HVOUT 9 HVOUT10 HVOUT11 HVOUT12 HVOUT13 HVOUT14 HVOUT15 HVOUT16 N/C N/C N/C Package Outline 1 64 Index 24 41 40 25 top view 3-sided Plastic 64-pin Gullwing Package 02/06//02 ©2002 Supertex Inc. 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