Maxim MAX12559ETK-D Dual, 96msps, 14-bit, if/baseband adc Datasheet

19-3925; Rev 1; 4/07
KIT
ATION
EVALU
E
L
B
AVAILA
Dual, 96Msps, 14-Bit, IF/Baseband ADC
Features
♦ Direct IF Sampling Up to 350MHz
♦ Excellent Dynamic Performance
73dB/72.2dB SNR at fIN = 70MHz/175MHz
83.5dBc/78.8dBc SFDR at fIN = 70MHz/175MHz
♦ 3.3V Low-Power Operation
980mW (Differential Clock Mode)
952mW (Single-Ended Clock Mode)
♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Differential Analog Input Voltage
♦ 750MHz Input Bandwidth
♦ Adjustable, Internal or External, Shared Reference
♦ Differential or Single-Ended Clock
♦ Accepts 25% to 75% Clock Duty Cycle
♦ User-Selectable DIV2 and DIV4 Clock Modes
♦ Power-Down Mode
♦ CMOS Outputs in Two’s Complement or Gray
Code
♦ Out-of-Range and Data-Valid Indicators
♦ Small, 68-Pin Thin QFN Package
(10mm x 10mm x 0.8mm)
♦ 12-Bit, Pin-Compatible Version Available
(MAX12529)
♦ Evaluation Kit Available (Order MAX12559EVKIT)
Applications
IF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
I/Q Receivers
Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Low-Power Data Acquisition
Ordering Information
PART
MAX12559ETK-D
PKG
CODE
TEMP RANGE PIN-PACKAGE
-40°C to +85°C 68 Thin QFN-EP* T6800-4
MAX12559ETK+D -40°C to +85°C 68 Thin QFN-EP* T6800-4
*EP = Exposed paddle.
+Denotes lead-free package.
D = Dry pack.
Selector Guide
SAMPLING RATE
(Msps)
RESOLUTION
(Bits)
MAX12559
96
14
MAX12558
80
14
MAX12557
65
14
MAX12529
96
12
MAX12528
80
12
MAX12527
65
12
PART
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX12559
General Description
The MAX12559 is a dual, 3.3V, 14-bit analog-to-digital
converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12559 is optimized for low power, small size,
and high dynamic performance in intermediate frequency (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 980mW while delivering a typical 72.2dB signal-tonoise ratio (SNR) performance at a 175MHz input frequency. The T/H input stages accept single-ended or
differential inputs up to 350MHz. In addition to low operating power, the MAX12559 features a 0.5mW powerdown mode to conserve power during idle periods.
A flexible reference structure allows the MAX12559 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the reference to be shared between the two ADCs. The reference structure allows the full-scale analog input range
to be adjusted from ±0.35V to ±1.15V. The MAX12559
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
The MAX12559 supports either a single-ended or differential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibility and help to reduce the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).
The MAX12559 features two parallel, 14-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital outputs accepts a 1.7V to 3.6V voltage for flexible interfacing with various logic levels. The MAX12559 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.
For a 12-bit, pin-compatible version of this ADC, refer to
the MAX12529 data sheet. See the Selector Guide for
more selections.
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
ABSOLUTE MAXIMUM RATINGS
VDD to GND.................................................................-0.3V to +3.6V
OVDD to GND............-0.3V to the lower of (VDD + 0.3V) and +3.6V
INAP, INAN to GND....-0.3V to the lower of (VDD + 0.3V) and +3.6V
INBP, INBN to GND....-0.3V to the lower of (VDD + 0.3V) and +3.6V
CLKP, CLKN to
GND ........................-0.3V to the lower of (VDD + 0.3V) and +3.6V
REFIN, REFOUT
to GND ..................-0.3V to the lower of (VDD + 0.3V) and +3.6V
REFAP, REFAN,
COMA to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V
REFBP, REFBN,
COMB to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V
DIFFCLK/SECLK, G/T, PD, SHREF, DIV2,
DIV4 to GND .........-0.3V to the lower of (VDD + 0.3V) and +3.6V
D0A–D13A, D0B–D13B, DAV,
DORA, DORB to GND..............................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
68-Pin Thin QFN, 10mm x 10mm x 0.8mm
(derate 70mW/°C above +70°C) ....................................4000mW
Operating Temperature Range................................-40°C to +85°C
Junction Temperature ...........................................................+150°C
Storage Temperature Range .................................-65°C to +150°C
Lead Temperature (soldering, 10s)......................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA =
-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
14
Bits
Integral Nonlinearity
INL
fIN = 3MHz
±2.6
Differential Nonlinearity
DNL
fIN = 3MHz
±0.65
Offset Error
Gain Error
External reference, VREFIN = 2.048V
LSB
LSB
±0.05
±0.7
%FSR
±0.4
±5
%FSR
ANALOG INPUTS (INAP, INAN, INBP, INBN)
Differential Input Voltage Range
VDIFF
Differential or single-ended inputs
Common-Mode Input Voltage
Analog Input Resistance
RIN
CPAR
Each input, Figure 3
Fixed capacitance to ground,
each input, Figure 3
±1.024
V
VDD / 2
V
2.3
kΩ
2
Analog Input Capacitance
pF
CSAMPLE
Switched capacitance,
each input, Figure 3
4.5
CONVERSION RATE
Maximum Clock Frequency
fCLK
96
MHz
Minimum Clock Frequency
5
Data Latency
Figure 5
MHz
8
Clock
Cycles
dBFS
DYNAMIC CHARACTERISTICS (VIN = -1dBFS)
Small-Signal Noise Floor
Signal-to-Noise Ratio
SSNF
SNR
Input at -35dBFS
74.5
76.3
fIN = 3MHz
70.5
74.3
fIN = 48MHz
73.9
fIN = 70MHz
73
fIN = 175MHz
2
69.3
72.2
_______________________________________________________________________________________
dB
Dual, 96Msps, 14-Bit, IF/Baseband ADC
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA =
-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
fIN = 3MHz
Signal-to-Noise Plus Distortion
Spurious-Free Dynamic Range
SINAD
SFDR
Second Harmonic
THD
HD2
Third Harmonic
HD3
3rd-Order Intermodulation
Distortion
Full-Power Bandwidth
Aperture Delay
IM3
FPBW
tAD
Aperture Jitter
tAJ
Output Noise
nOUT
TYP
73.7
fIN = 48MHz
72.6
fIN = 70MHz
72.2
fIN = 175MHz
65.3
fIN = 3MHz
72.2
fIN = 70MHz
83.5
-82.1
fIN = 48MHz
-78.5
fIN = 70MHz
-80.3
fIN = 175MHz
-77.8
fIN = 3MHz
-85.9
fIN = 48MHz
-82.4
fIN = 70MHz
-86.1
fIN = 175MHz
-78.8
fIN = 3MHz
-89.4
fIN = 48MHz
-86.6
fIN = 70MHz
-84.4
fIN = 175MHz
-88.6
fIN1 = 69MHz at AIN1 = -7dBFS,
fIN2 = 72MHz at AIN2 = -7dBFS
-82
fIN1 = 173MHz at AIN1 = -7dBFS,
fIN2 = 177MHz at AIN2 = -7dBFS
-86
Input at -0.2dBFS, -3dB rolloff
750
INAP = INAN = COMA,
INBP = INBN = COMB
dB
dBc
78.8
fIN = 3MHz
Figure 5
UNITS
84.6
81.6
69
MAX
71.2
fIN = 48MHz
fIN = 175MHz
Total Harmonic Distortion
MIN
68.3
-69.8
dBc
-66.3
dBc
dBc
dBc
MHz
1.2
ns
< 0.1
psRMS
0.9
LSBRMS
_______________________________________________________________________________________
3
MAX12559
ELECTRICAL CHARACTERISTICS (continued)
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA =
-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Overdrive Recovery Time
CONDITIONS
MIN
TYP
±10% beyond full scale
1
fINA or fINB = 70MHz at -1dBFS
90
fINA or fINB = 175MHz at -1dBFS
83
MAX
UNITS
Clock
Cycle
INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
Gain Matching
±0.02
Offset Matching
±0.01
dB
±0.1
dB
%FSR
INTERNAL REFERENCE (REFOUT)
REFOUT Output Voltage
VREFOUT
REFOUT Load Regulation
REFOUT Temperature Coefficient
2.000
-1mA < IREFOUT < +1mA
TCREF
REFOUT Short-Circuit Current
2.048
2.080
V
35
mV/mA
55
ppm/°C
Short to VDD—sinking
0.24
Short to GND—sourcing
2.1
mA
BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source;
VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are generated internally)
REFIN Input Voltage
VREFIN
2.048
V
REFIN Input Resistance
RREFIN
> 50
MΩ
COM_ Output Voltage
VCOMA
VCOMB
VCOM_ = VDD / 2
REF_P Output Voltage
VREFAP
VREFBP
VREF_P = VDD / 2 + (VREFIN x 3/8)
2.418
V
REF_N Output Voltage
VREFAN
VREFBN
VREF_N = VDD / 2 - (VREFIN x 3/8)
0.882
V
Differential Reference Voltage
VREFA
VREFB
Differential Reference
Temperature Coefficient
TCREF
VREF_ = VREF_P - VREF_N
1.60
1.440
1.65
1.536
40
1.70
V
1.600
V
ppm/°C
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are applied
externally, VCOMA = VCOMB = VDD / 2)
REF_P Input Voltage
VREFAP
VREFBP
VREF_P - VCOM_
+0.768
V
REF_N Input Voltage
VREFAN
VREFBN
VREF_N - VCOM_
-0.768
V
COM_ Input Voltage
VCOM_
VCOM_ = VDD / 2
1.65
V
Differential Reference Voltage
VREFA
VREFB
VREF_ = VREF_P - VREF_N = VREFIN x 3/4
1.536
V
4
_______________________________________________________________________________________
Dual, 96Msps, 14-Bit, IF/Baseband ADC
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA =
-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REF_P Sink Current
IREFAP
IREFBP
VREF_P = 2.418V
1.2
mA
REF_N Source Current
IREFAN
IREFBN
VREF_N = 0.882V
0.85
mA
COM_ Sink Current
ICOMA
ICOMB
VCOM_ = 1.65V
0.85
mA
REF_P, REF_N Capacitance
CREF_P,
CREF_N
13
pF
COM_ Capacitance
CCOM_
6
pF
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input High
Threshold
Single-Ended Input Low
Threshold
VIH
DIFFCLK/SECLK = GND, CLKN = GND
VIL
DIFFCLK/SECLK = GND, CLKN = GND
0.8 x
VDD
V
0.2 x
VDD
V
Minimum Differential Clock Input
Voltage Swing
DIFFCLK/SECLK = OVDD
0.2
VP-P
Differential Input Common-Mode
Voltage
DIFFCLK/SECLK = OVDD
VDD / 2
V
5
kΩ
2
pF
CLKP, CLKN Input Resistance
RCLK
CLKP, CLKN Input Capacitance
CCLK
Figure 4
DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4, SHREF)
Input High Threshold
VIH
Input Low Threshold
VIL
V
0.2 x
OVDD
±5
OVDD applied to input
Input Leakage Current
Digital Input Capacitance
0.8 x
OVDD
Input connected to ground
±5
CDIN
5
V
µA
pF
DIGITAL OUTPUTS (D0A–D13A, D0B–D13B, DORA, DORB, DAV)
Output-Voltage Low
VOL
Output-Voltage High
Tri-State Leakage Current
(Note 2)
VOH
ILEAK
D0A–D13A, D0B–D13B, DORA, DORB:
ISINK = 200µA
0.2
DAV: ISINK = 600µA
0.2
D0A–D13A, D0B–D13B, DORA, DORB:
ISOURCE = 200µA
OVDD 0.2
DAV: ISOURCE = 600µA
OVDD 0.2
V
V
OVDD applied to input
±5
Input connected to ground
±5
µA
_______________________________________________________________________________________
5
MAX12559
ELECTRICAL CHARACTERISTICS (continued)
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA =
-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
D0A–D13A, DORA,
D0B–D13B, and DORB Tri-State
Output Capacitance (Note 2)
COUT
3
pF
DAV Tri-State Output
Capacitance (Note 2)
CDAV
6
pF
POWER REQUIREMENTS
Analog Supply Voltage
Digital Output Supply Voltage
Analog Supply Current
Analog Power Dissipation
Digital Output Supply Current
6
VDD
3.15
3.30
3.60
V
OVDD
1.70
2.0
VDD
V
IVDD
PVDD
IOVDD
Normal operating mode
fIN = 175MHz
single-ended clock
(DIFFCLK/SECLK = GND)
288.5
Normal operating mode
fIN = 175MHz
differential clock
(DIFFCLK/SECLK = OVDD)
297
Power-down mode (PD = OVDD)
clock idle
0.15
Normal operating mode
fIN = 175MHz
single-ended clock
(DIFFCLK/SECLK = GND)
952
Normal operating mode
fIN = 175MHz
differential clock
(DIFFCLK/SECLK = OVDD)
980
Power-down mode (PD = OVDD)
clock idle
0.5
Normal operating mode
fIN = 175MHz, CL ≈ 10pF
26.1
Power-down mode (PD = OVDD)
clock idle
0.001
mA
322
mW
1063
mA
_______________________________________________________________________________________
Dual, 96Msps, 14-Bit, IF/Baseband ADC
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA =
-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figure 5)
Clock Pulse-Width High
tCH
Clock Pulse-Width Low
5.1
tCL
Data-Valid Delay
ns
5.1
(Notes 3, 4)
3.15
Data Setup Time Before Rising
Edge of DAV
tSETUP
(Notes 3, 4)
3.60
ns
Data Hold Time After Rising Edge
of DAV
tHOLD
(Notes 3, 4)
3.55
ns
Data Setup Time Before Falling
Edge of Clock
tDATASETUP (Notes 3, 4)
2.25
ns
Data Hold Time After Falling
Edge of Clock
tDATAHOLD (Notes 3, 4)
3.25
ns
Wake-Up Time from Power-Down
Note 1:
Note 2:
Note 3:
Note 4:
tWAKE
5.8
ns
tDAV
VREFIN = 2.048V
6.65
ns
10
ms
Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization.
During power-down, D0A–D13A, D0B–D13B, DORA, DORB, and DAV are high impedance.
Data outputs settle to VIH or VIL.
Guaranteed by design and characterization.
Typical Operating Characteristics
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 5pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
-60
HD3
-80
-40
-60
HD3
-80
fCLK = 96MHz
fIN = 70.1001MHz
AIN = -0.99dBFS
SNR = 73.2dB
SINAD = 72.5dB
THD = -80.6dBc
SFDR = 84.4dBc
HD2 = -94.6dBc
HD3 = -86.4dBc
-20
-40
-60
MAX12559 toc03
FFT PLOT (65,536-POINT DATA RECORD)
0
AMPLITUDE (dBFS)
HD2
fCLK = 96MHz
fIN = 47.89893MHz
AIN = -0.98dBFS
SNR = 74dB
SINAD = 71.9dB
THD = -76dBc
SFDR = 80dBc
HD2 = -80.9dBc
HD3 = -86.3dBc
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-40
MAX12559 toc01
fCLK = 96MHz
fIN = 2.99919MHz
AIN = -1.01dBFS
SNR = 74.5dB
SINAD = 73.7dB
THD = -81.1dBc
SFDR = 85.1dBc
HD2 = -86.3dBc
HD3 = -91.41dBc
-20
FFT PLOT (65,536-POINT DATA RECORD)
0
MAX12559 toc02
FFT PLOT (65,536-POINT DATA RECORD)
0
HD3
-80
HD2
HD2
-100
-100
-120
-100
-120
0
10
20
30
40
ANALOG INPUT FREQUENCY (MHz)
48
-120
0
5
10 15 20 25
30 35 40 45
ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25
30 35 40 45
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
7
MAX12559
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 5pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
-80
-120
2fIN1 - fIN2
10 15 20 25
30 35 40 45
5
10 15 20 25
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
1.00
MAX12559 toc07
0.50
1
0.25
DNL (LSB)
2
0
-1
fIN = 2.99906MHz
0.75
0
-0.25
-0.50
-3
-0.75
1
2049 4097 6145 8193 10,241 12,28914,33716,381
30 35 40 45
80
75
SNR
70
65
SINAD
60
55
50
-1.00
-4
10 15 20 25
SNR, SINAD vs. ANALOG INPUT FREQUENCY
(fCLK = 96MHz, AIN = -1dBFS)
0
-2
5
ANALOG INPUT FREQUENCY (MHz)
SNR, SINAD (dB)
3
2fIN1 - fIN2
2fIN2 - fIN1
-80
30 35 40 45
ANALOG INPUT FREQUENCY (MHz)
fIN = 2.99906MHz
fIN1
-120
0
ANALOG INPUT FREQUENCY (MHz)
4
fIN2
-60
-100
MAX12559 toc08
5
-40
MAX12559 toc06
MAX12559 toc05
2fIN2 - fIN1
-80
-120
0
1
0
2049 4097 6145 8193 10,241 12,28914,33716,381
50
100
150
200
250
300
350
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
fIN (MHz)
-THD, SFDR vs. ANALOG INPUT FREQUENCY
(fCLK = 96MHz, AIN = -1dBFS)
SNR, SINAD vs. ANALOG INPUT AMPLITUDE
(fCLK = 96MHz, fIN = 70MHz)
-THD, SFDR vs. ANALOG INPUT AMPLITUDE
(fCLK = 96MHz, fIN = 70MHz)
SNR, SINAD (dB)
80
75
-THD
70
65
SNR
55
50
45
40
SINAD
35
30
25
60
55
20
15
50
0
50
100
150
200
fIN (MHz)
250
300
350
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
AIN (dBFS)
90
85
MAX12559 toc12
SFDR
85
75
70
65
60
MAX12559 toc10
90
-THD, SFDR (dBc)
INL (LSB)
-60
fIN1
-100
-100
8
-40
fCLK = 96MHz
fIN1 = 172.50146MHz
AIN1 = -7.04dBFS
fIN2 = 177.50244MHz
AIN2 = -6.99dBFS
IM3 = -84.6dBc
-20
MAX12559 toc09
-60
-20
0
AMPLITUDE (dBFS)
-40
fCLK = 96MHz
fIN1 = 68.50049MHz
AIN1 = -7.00dBFS
fIN2 = 71.50049MHz
AIN2 = -7.04dBFS
IM3 = -84.30dBc
fIN2
MAX12559 toc11
AMPLITUDE (dBFS)
-20
0
AMPLITUDE (dBFS)
fCLK = 96MHz
fIN = 175.00049MHz
AIN = -1.00dBFS
SNR = 72.4dB
SINAD = 71.4dB
THD = -78.3dBc
SFDR = 79.9dBc HD2
HD2 = -80.9dBc
HD3 = -91.3dBc
HD3
MAX12559 toc04
0
TWO-TONE IMD PLOT
(65,536-POINT DATA RECORD)
TWO-TONE IMD PLOT
(65,536-POINT DATA RECORD)
FFT PLOT (65,536-POINT DATA RECORD)
-THD, SFDR (dBc)
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
SFDR
80
75
70
65
60
55
50
45
40
35
30
-THD
-55 -50 -45 -40 -35 -30 -25 -20 15 -10 -5
AIN (dBFS)
_______________________________________________________________________________________
0
Dual, 96Msps, 14-Bit, IF/Baseband ADC
SINAD
65
-THD
60
55
50
SINAD
71
69
DIV4 = OVDD
DIV2 = GND
67
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
0
0
30
40
50
60
70
80
90
AIN (dBFS)
fCLK (MHz)
-THD, SFDR vs. CLOCK SPEED
(fIN = 70MHz, AIN = -1dBFS)
SNR, SINAD vs. CLOCK SPEED
(fIN = 175MHz, AIN = -1dBFS)
-THD, SFDR vs. CLOCK SPEED
(fIN = 175MHz, AIN = -1dBFS)
SNR
74
90
-THD
75
70
-THD, SFDR (dBc)
SNR, SINAD (dB)
80
70
SINAD
68
66
64
DIV4 = OVDD
DIV2 = GND
40
50
60
70
80
90
-THD
70
65
DIV4 = OVDD
DIV2 = GND
50
30
100
75
55
60
60
80
60
62
DIV4 = OVDD
DIV2 = GND
SFDR
85
72
85
100
MAX12559 toc18
90
95
MAX12559 toc17
76
MAX12559 toc16
SFDR
30
73
AIN (dBFS)
95
65
SNR
75
40
35
30
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
MAX12559 toc15
77
45
20
15
40
50
60
70
80
90
100
30
40
50
60
70
80
90
100
fCLK (MHz)
fCLK (MHz)
fCLK (MHz)
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 70MHz)
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 70MHz)
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 175MHz)
SNR
76
SFDR
90
MAX12559 toc21
75
100
MAX12559 toc19
77
MAX12559 toc20
-THD, SFDR (dBc)
SFDR
SNR, SINAD (dB)
SNR
85
80
75
70
MAX12559 toc14
90
MAX12559 toc13
75
70
65
60
55
50
45
40
35
30
25
SNR, SINAD vs. CLOCK SPEED
(fIN = 70MHz, AIN = -1dBFS)
-THD, SFDR vs. ANALOG INPUT AMPLITUDE
(fCLK = 96MHz, fIN = 175MHz)
-THD, SFDR (dBc)
SNR, SINAD (dB)
SNR, SINAD vs. ANALOG INPUT AMPLITUDE
(fCLK = 96MHz, fIN = 175MHz)
SNR
74
73
71
SINAD
69
SNR, SINAD (dB)
-THD, SFDR (dBc)
SNR, SINAD (dB)
72
80
-THD
70
60
64
62
40
3.1
3.2
3.3
3.4
VDD (V)
3.5
3.6
SINAD
68
66
50
67
70
3.1
3.2
3.3
3.4
VDD (V)
3.5
3.6
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
_______________________________________________________________________________________
9
MAX12559
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 5pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 5pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 70MHz)
SFDR
80
90
MAX12559 toc23
76
MAX12559 toc22
85
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 70MHz)
SNR
74
MAX12559 toc24
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 175MHz)
SFDR
85
75
-THD
70
72
-THD, SFDR (dBc)
SNR, SINAD (dB)
-THD, SFDR (dBc)
80
SINAD
70
65
68
60
66
55
64
75
-THD
70
65
60
50
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VDD (V)
OVDD (V)
OVDD (V)
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 175MHz)
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 175MHz)
PDISS, IVDD (ANALOG)
vs. ANALOG SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 175MHz)
3.6
90
MAX12559 toc25
SNR
85
68
66
75
-THD
70
65
64
60
62
55
60
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
OVDD (V)
OVDD (V)
PDISS (DIGITAL)
70
60
50
40
IOVDD
3.1
3.2
3.3
3.4
3.5
3.6
-THD, SFDR vs. CLOCK DUTY CYCLE
(fIN = 70MHz, AIN = -1dBFS)
SNR
80
75
SFDR
76
70
SINAD
65
60
72
-THD
68
30
20
64
55
10
SINGLE-ENDED CLOCK DRIVE
0
SINGLE-ENDED CLOCK DRIVE
50
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
OVDD (V)
10
IVDD
VDD (V)
80
SNR, SINAD (dB)
90
500
SNR, SINAD vs. CLOCK DUTY CYCLE
(fIN = 70MHz, AIN = -1dBFS)
MAX12559 toc28
100
700
100
50
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
110
900
300
PDISS, IOVDD (DIGITAL) vs. DIGITAL
SUPPLY VOLTAGE (fCLK = 96MHz, fIN = 175MHz)
80
PDISS, IVDD (mW, mA)
SINAD
PDISS (ANALOG)
1100
-THD, SFDR (dBc)
70
SFDR
80
-THD, SFDR (dBc)
72
1300
MAX12559 toc29
74
3.5
MAX12559 toc27
3.4
MAX12559 toc30
3.3
MAX12559 toc26
3.2
76
SNR, SINAD (dB)
55
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
3.1
PDISS, IOVDD (mW, mA)
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
60
25
30
35
40
45
50
55
60
CLOCK DUTY CYCLE (%)
65
70
25
30
35
40
45
50
55
60
CLOCK DUTY CYCLE (%)
______________________________________________________________________________________
65
70
Dual, 96Msps, 14-Bit, IF/Baseband ADC
-THD, SFDR vs. TEMPERATURE
(fIN = 175MHz, AIN = -1dBFS)
SNR, SINAD vs. TEMPERATURE
(fIN = 175MHz, AIN = -1dBFS)
69
85
SFDR
-THD, SFDR (dBc)
SNR, SINAD (dB)
71
SINAD
67
80
75
-THD
70
65
65
60
63
-40
-15
10
35
60
-40
85
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
GAIN ERROR vs. TEMPERATURE
(VREFIN = 2.048V)
OFFSET ERROR vs. TEMPERATURE
0.2
OFFSET ERROR (%FSR)
2
1
0
-1
MAX12559 toc34
0.3
MAX12559 toc33
3
GAIN ERROR (%FSR)
MAX12559 toc32
SNR
73
90
MAX12559 toc31
75
0.1
0
-0.1
-0.2
-2
-3
-0.3
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
______________________________________________________________________________________
11
MAX12559
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 5pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
Pin Description
PIN
NAME
1, 4, 5, 9,
13, 14, 17
GND
Converter Ground. Connect all ground pins and the exposed paddle (EP) together.
2
INAP
Channel A Positive Analog Input
3
INAN
Channel A Negative Analog Input
6
COMA
Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor.
REFAP
Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (VREFAP - VREFAN). Bypass
REFAP with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFAP
and REFAN. Place the 0.1µF REFAP-to-REFAN capacitor as close to the device as possible on the
same side of the PCB.
REFAN
Channel A Negative Reference I/O. Channel A conversion range is ±2/3 x (VREFAP - VREFAN). Bypass
REFAN with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFAP
and REFAN. Place the 0.1µF REFAP-to-REFAN capacitor as close to the device as possible on the
same side of the PCB.
REFBN
Channel B Negative Reference I/O. Channel B conversion range is ±2/3 x (VREFBP - VREFBN). Bypass
REFBN with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFBP
and REFBN. Place the 0.1µF REFBP-to-REFBN capacitor as close to the device as possible on the
same side of the PCB.
11
REFBP
Channel B Positive Reference I/O. Channel B conversion range is ±2/3 x (VREFBP - VREFBN). Bypass
REFBP with a 0.1µF capacitor to GND. Connect a 4.7µF and a 0.1µF bypass capacitor between REFBP
and REFBN. Place the 0.1µF REFBP-to-REFBN capacitor as close to the device as possible on the
same side of the PCB.
12
COMB
15
INBN
16
INBP
7
8
10
FUNCTION
Channel B Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1µF capacitor.
Channel B Negative Analog Input
Channel B Positive Analog Input
18
DIFFCLK/
SECLK
19
CLKN
20
CLKP
21
DIV2
Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock
input drives.
DIFFCLK/SECLK = GND: Selects single-ended clock input drive.
DIFFCLK/SECLK = OVDD: Selects differential clock input drive.
Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
the clock signal to CLKP and connect CLKN to GND.
Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
the single-ended clock signal to CLKP and connect CLKN to GND.
Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details.
22
DIV4
Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details.
23–26, 61,
62, 63
VDD
Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel
capacitor combination of ≥ 10µF and 0.1µF. Connect all VDD pins to the same potential.
27, 43, 60
OVDD
Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a
parallel capacitor combination of ≥ 10µF and 0.1µF.
12
______________________________________________________________________________________
Dual, 96Msps, 14-Bit, IF/Baseband ADC
PIN
NAME
FUNCTION
28
D0B
Channel B CMOS Digital Output, Bit 0 (LSB)
29
D1B
Channel B CMOS Digital Output, Bit 1
30
D2B
Channel B CMOS Digital Output, Bit 2
31
D3B
Channel B CMOS Digital Output, Bit 3
32
D4B
Channel B CMOS Digital Output, Bit 4
33
D5B
Channel B CMOS Digital Output, Bit 5
34
D6B
Channel B CMOS Digital Output, Bit 6
35
D7B
Channel B CMOS Digital Output, Bit 7
36
D8B
Channel B CMOS Digital Output, Bit 8
37
D9B
Channel B CMOS Digital Output, Bit 9
38
D10B
Channel B CMOS Digital Output, Bit 10
39
D11B
Channel B CMOS Digital Output, Bit 11
40
D12B
Channel B CMOS Digital Output, Bit 12
41
D13B
Channel B CMOS Digital Output, Bit 13 (MSB)
42
DORB
Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analog
input voltage is out of range.
DORB = 1: Digital outputs exceed full-scale range.
DORB = 0: Digital outputs are within full-scale range.
44
DAV
45
D0A
Data-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs.
The MAX12559 evaluation kit utilizes DAV to latch data into any external back-end digital logic.
Channel A CMOS Digital Output, Bit 0 (LSB)
46
D1A
Channel A CMOS Digital Output, Bit 1
47
D2A
Channel A CMOS Digital Output, Bit 2
48
D3A
Channel A CMOS Digital Output, Bit 3
49
D4A
Channel A CMOS Digital Output, Bit 4
50
D5A
Channel A CMOS Digital Output, Bit 5
51
D6A
Channel A CMOS Digital Output, Bit 6
52
D7A
Channel A CMOS Digital Output, Bit 7
53
D8A
Channel A CMOS Digital Output, Bit 8
54
D9A
Channel A CMOS Digital Output, Bit 9
55
D10A
Channel A CMOS Digital Output, Bit 10
56
D11A
Channel A CMOS Digital Output, Bit 11
57
D12A
Channel A CMOS Digital Output, Bit 12
58
D13A
59
DORA
64
G/T
Channel A CMOS Digital Output, Bit 13 (MSB)
Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analog
input voltage is out of range.
DORA = 1: Digital outputs exceed full-scale range.
DORA = 0: Digital outputs are within full-scale range.
Output Format Select Digital Input.
G/T = GND: Two’s-complement output format selected.
G/T = OVDD: Gray-code output format selected.
______________________________________________________________________________________
13
MAX12559
Pin Description (continued)
Dual, 96Msps, 14-Bit, IF/Baseband ADC
MAX12559
Pin Description (continued)
PIN
65
NAME
PD
66
SHREF
67
REFOUT
68
REFIN
—
EP
FUNCTION
Power-Down Digital Input.
PD = GND: ADCs are fully operational.
PD = OVDD: ADCs are powered down.
Shared Reference Digital Input.
SHREF = VDD: Shared reference enabled.
SHREF = GND: Shared reference disabled.
When sharing the reference, externally connect REFAP and REFBP together to ensure that VREFAP =
VREFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure
that VREFAN = VREFBN.
Internal Reference Voltage Output. The REFOUT output voltage is 2.048V and REFOUT can deliver 1mA.
For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from
REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥ 0.1µF capacitor.
For external reference operation, REFOUT is not required and must be bypassed to GND with a ≥ 0.1µF
capacitor.
Single-Ended Reference Analog Input. For internal reference and buffered external reference operation,
apply a 0.7V to 2.3V DC reference voltage to REFIN. Bypass REFIN to GND with a 4.7µF capacitor.
Within its specified operating voltage, REFIN has a > 50MΩ input impedance, and the differential
reference voltage (VREF_P - VREF_N) is generated from REFIN. For unbuffered external reference
operation, connect REFIN to GND. In this mode, REF_P, REF_N, and COM_ are high-impedance inputs
that accept the external reference voltages.
Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve the
specified dynamic performance.
+
MAX12559
Σ
x2
−
FLASH
ADC
DAC
IN_P
STAGE 1
STAGE 2
STAGE 9
IN_N
STAGE 10
END OF PIPELINE
DIGITAL ERROR CORRECTION
D0_ THROUGH D13_
Figure 1. Pipeline Architecture—Stage Blocks
Detailed Description
The MAX12559 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output the total latency is 8 clock cycles.
14
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital output code is multiplied and passed on to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12559 functional diagram.
______________________________________________________________________________________
Dual, 96Msps, 14-Bit, IF/Baseband ADC
MAX12559
CLOCK
INAP
T/H
INAN
REFAP
14-BIT
PIPELINE
ADC
CHANNEL A
REFERENCE
SYSTEM
COMA
REFAN
DIGITAL
ERROR
CORRECTION
DATA
FORMAT
OUTPUT
DRIVERS
D0A TO D13A
DORA
MAX12559
G/T
REFIN
INTERNAL
REFERENCE
GENERATOR
REFOUT
DAV
SHREF
REFBP
COMB
REFBN
INBP
T/H
INBN
OVDD
CHANNEL B
REFERENCE
SYSTEM
14-BIT
PIPELINE
ADC
DIGITAL
ERROR
CORRECTION
DATA
FORMAT
OUTPUT
DRIVERS
D0B TO D13B
DORB
CLOCK
VDD
DIFFCLK/SECLK
CLOCK
CLKP
CLKN
DIV2
DIV4
CLOCK
DIVIDER
DUTY-CYCLE
EQUALIZER
POWER
CONTROL
AND
BIAS CIRCUITS
PD
GND
Figure 2. Functional Diagram
______________________________________________________________________________________
15
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
Table 1. Reference Modes
BOND WIRE
INDUCTANCE
1.5nH
VDD
MAX12559
IN_P
BOND WIRE
INDUCTANCE
1.5nH
CPAR
2pF
*CSAMPLE
4.5pF
CPAR
2pF
*CSAMPLE
4.5pF
VDD
VREFIN
Internal Reference Mode. REFIN is driven by
REFOUT either through a direct short or a
35% VREFOUT
resistive divider.
to 100%
VCOM_ = VDD / 2
VREFOUT
VREF_P = VDD / 2 + 3/8 x VREFIN
VREF_N = VDD / 2 - 3/8 x VREFIN
IN_N
0.7V to 2.3V
SAMPLING
CLOCK
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS: RIN =
1
fCLK x CSAMPLE
Figure 3. Internal T/H Circuit
Analog Inputs and Input Track-and-Hold
(T/H) Amplifier
Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies (high IF) of 175MHz and
beyond and supports a VDD / 2 common-mode input
voltage.
The MAX12559 sampling clock controls the switchedcapacitor input T/H architecture (Figure 3) allowing the
analog input signals to be stored as charge on the
sampling capacitors. These switches are closed (track
mode) when the sampling clock is high and open (hold
mode) when the sampling clock is low (Figure 4). The
analog input signal source must be able to provide the
dynamic currents necessary to charge and discharge
the sampling capacitors. To avoid signal degradation,
these capacitors must be charged to one-half LSB
accuracy within one-half of a clock cycle. The analog
input of the MAX12559 supports differential or singleended input drive. For optimum performance with differential inputs, balance the input impedance of IN_P
and IN_N and set the common-mode voltage to midsupply (VDD / 2). The MAX12559 provides the optimum
common-mode voltage of VDD / 2 through the COM
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 9, 10, and 11.
16
REFERENCE MODE
< 0.5V
Buffered External Reference Mode. An
external 0.7V to 2.3V reference voltage is
applied to REFIN.
VCOM_ = VDD / 2
VREF_P = VDD / 2 + 3/8 x VREFIN
VREF_N = VDD / 2 - 3/8 x VREFIN
Unbuffered External Reference Mode. REF_P,
REF_N, and COM_ are driven by external
reference sources. The full-scale analog input
range is ±(VREF_P - VREF_N) x 2/3.
Reference Output
An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX12559. The power-down logic input (PD) enables
and disables the reference circuit. REFOUT has approximately 17kΩ to GND when the MAX12559 is powered
down. The reference circuit requires 10ms to power up
and settle to its final value when power is first applied to
the MAX12559 or when PD (power-down control line)
transitions from high to low.
The internal bandgap reference produces a buffered
reference voltage of 2.048V ±1% at the REFOUT pin
with a ±50ppm/°C temperature coefficient. Connect an
external ≥ 0.1µF bypass capacitor from REFOUT to
GND for stability. REFOUT sources up to 1mA and
sinks up to 0.1mA for external circuits with a 35mV/mA
load regulation. Short-circuit protection limits IREFOUT
to a 2.1mA source current when shorted to GND and a
0.24mA sink current when shorted to VDD. Similar to
REFOUT, REFIN should be bypassed with a 4.7µF
capacitor to GND.
Reference Configurations
The MAX12559 full-scale analog input range is ±2/3 x
VREF with a VDD / 2 ±0.5V common-mode input range.
VREF is the voltage difference between REFAP (REFBP)
and REFAN (REFBN). The MAX12559 provides three
modes of reference operation. Setting the voltage at
REFIN (VREFIN) selects the reference operation mode
(Table 1).
______________________________________________________________________________________
Dual, 96Msps, 14-Bit, IF/Baseband ADC
Buffered external reference mode is virtually identical to
the internal reference mode except that the reference
source is derived from an external reference and not the
MAX12559’s internal bandgap reference. In buffered
external reference mode, apply a stable reference voltage source between 0.7V to 2.3V at REFIN. Pins COM_,
REF_P, and REF_N are low-impedance outputs with
VCOM_ = VDD / 2, VREF_P = VDD / 2 + 3/8 x VREFIN, and
VREF_N = VDD / 2 - 3/8 x VREFIN. Bypass REF_P, REF_N,
and COM_ each with a 0.1µF capacitor to GND. Bypass
REF_P to REF_N with a 4.7µF capacitor.
Connect REFIN to GND to enter unbuffered external reference mode. Connecting REFIN to GND deactivates
the on-chip reference buffers for COM_, REF_P, and
REF_N. With their buffers deactivated, COM_, REF_P,
and REF_N become high-impedance inputs and must
be driven with separate, external reference sources.
Drive VCOM_ to VDD / 2 ±5%, and drive REF_P and
REF_N so VCOM_ = (VREF_P_ + VREF_N_) / 2. The analog
input range is ±(V REF_P_ - V REF_N ) x 2/3. Bypass
REF_P, REF_N, and COM_ each with a 0.1µF capacitor
to GND. Bypass REF_P to REF_N with a 4.7µF capacitor.
For all reference modes, bypass REFOUT with a 0.1µF
and REFIN with a 4.7µF capacitor to GND.
The MAX12559 also features a shared reference mode,
in which the user can achieve better channel-to-channel matching. When sharing the reference (SHREF =
VDD), externally connect REFAP and REFBP together to
ensure that VREFAP = VREFBP. Similarly, when sharing
the reference, externally connect REFAN to REFBN
together to ensure that VREFAN = VREFBN.
Connect SHREF to GND to disable the shared reference mode of the MAX12559. In this independent reference mode, a better channel-to-channel isolation is
achieved.
For detailed circuit suggestions and how to drive the
ADC in buffered/unbuffered external reference mode,
see the Applications Information section.
Clock Duty-Cycle Equalizer
The MAX12559 has an internal clock duty-cycle equalizer, which makes the converter insensitive to the duty
cycle of the signal applied to CLKP and CLKN. The converters allow clock duty-cycle variations from 25% to 75%
without negatively impacting the dynamic performance.
The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
duty-cycle independent. Due to this DLL, the
MAX12559 requires approximately 100 clock cycles to
acquire and lock to new clock frequencies.
Clock Input and Clock Control Lines
The MAX12559 accepts both differential and singleended clock inputs with a wide 25% to 75% input clock
duty cycle. For single-ended clock input operation,
connect DIFFCLK/SECLK and CLKN to GND. Apply an
external single-ended clock signal to CLKP. To reduce
clock jitter, the external single-ended clock must have
sharp falling edges. For differential clock input operation, connect DIFFCLK/SECLK to OV DD . Apply an
external differential clock signal to CLKP and CLKN.
Consider the clock input as an analog input and route it
away from any other analog inputs and digital signal
lines. CLKP and CLKN enter high impedance when the
MAX12559 is powered down (Figure 4).
Low clock jitter is required for the specified SNR performance of the MAX12559. The analog inputs are sampled on the falling (rising) edge of CLKP (CLKN),
requiring this edge to have the lowest possible jitter.
Jitter limits the maximum SNR performance of any ADC
according to the following relationship:
⎛
⎞
1
SNR = 20 × log ⎜
⎟
⎝ 2 × π × fIN × t J ⎠
where fIN represents the analog input frequency and tJ
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For instance,
assuming that clock jitter is the only noise source, to
obtain the specified 71.9dB of SNR with an input frequency of 175MHz, the system must have less than
0.23ps of clock jitter. However, in reality there are other
noise sources such as thermal noise and quantization
noise that contribute to the system noise requiring the
clock jitter to be less than 0.18ps to obtain the specified 71.9dB of SNR at 175MHz.
Clock-Divider Control Inputs (DIV2, DIV4)
The MAX12559 features three different modes of sampling/clock operation (see Table 2). Pulling both control
lines low, the clock-divider function is disabled and the
converters sample at full clock speed. Pulling DIV4 low
______________________________________________________________________________________
17
MAX12559
Connect REFOUT to REFIN either with a direct short or
through a resistive divider for internal reference mode.
COM_, REF_P, and REF_N are low-impedance outputs
with VCOM_ = VDD / 2, VREF_P = VDD / 2 + 3/8 x VREFIN,
and VREF_N = VDD / 2 - 3/8 x VREFIN. Bypass REF_P,
REF_N, and COM_ each with a 0.1µF capacitor to GND.
Bypass REF_P to REF_N with a 10µF capacitor. Bypass
REFIN and REFOUT to GND with a 0.1µF capacitor. The
REFIN input impedance is very large (> 50MΩ). When
driving REFIN through a resistive divider, use resistances
≥ 10kΩ to avoid loading REFOUT.
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
Table 2. Clock-Divider Control Inputs
VDD
S1H
DIV4
DIV2
0
0
Clock Divider Disabled
fSAMPLE = fCLK
0
1
Divide-by-Two Clock Divider
fSAMPLE = fCLK / 2
1
0
Divide-by-Four Clock Divider
fSAMPLE = fCLK / 4
1
1
Not Allowed
MAX12559
10kΩ
CLKP
10kΩ
S2H
S1L
DUTY-CYCLE
EQUALIZER
10kΩ
sampling provides design flexibility, relaxes clock
requirements, and can minimize clock jitter.
CLKN
System Timing Requirements
10kΩ
S2L
GND
Figure 5 shows the timing relationship between the
clock, analog inputs, DAV indicator, DOR_ indicators,
and the resulting output data. The analog input is sampled on the falling (rising) edge of CLKP (CLKN) and
the resulting data appears at the digital outputs 8 clock
cycles later.
The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end circuitry can be latched with the rising edge of the conversion clock (CLKP - CLKN).
SWITCHES S1_ AND S2_ ARE OPEN
DURING POWER-DOWN, MAKING
CLKP AND CLKN HIGH IMPEDANCE.
SWITCHES S2_ ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
Figure 4. Simplified Clock Input Circuit
and DIV2 high enables the divide-by-two feature, which
sets the sampling speed to one-half the selected clock
frequency. In divide-by-four mode, the converter sampling speed is set to one-fourth the clock speed of the
MAX12559. Divide-by-four mode is achieved by applying
a high level to DIV4 and a low level to DIV2. The option to
select either one-half or one-fourth of the clock speed for
DIFFERENTIAL ANALOG INPUT (IN_P - IN_N)
N+4
N-2
N-1
N
N+1
Data-Valid Output
DAV is a single-ended version of the input clock that is
compensated to correct for any input clock duty-cycle
variations. The MAX12559 output data changes on the
N+5
N+3
(VREF_P - VREF_N)x2/3 N - 3
FUNCTION
N+6
N+2
N+7
N+9
N+8
(VREF_P - VREF_N)x2/3
tAD
CLKN
CLKP
tDAV
tCL
tCH
DAV
tSETUP
D0_-D13_
tHOLD
N-3
N-2
N-1
N
N+1
N+2
N+4
N+5
N+6
tDATAHOLD
8 CLOCK CYCLE DATA LATENCY
DOR
N+3
tDATASETUP
Figure 5. System Timing Diagram
18
______________________________________________________________________________________
N+7
N+8
N+9
Dual, 96Msps, 14-Bit, IF/Baseband ADC
Data Out-of-Range Indicator
The DORA and DORB digital outputs indicate when the
analog input voltage is out of range. When DOR_ is high,
the analog input is out of range. When DOR_ is low, the
analog input is within range. The valid differential input
range is from (V REF_P - V REF_N ) x 2/3 to (V REF_N VREF_P) x 2/3. Signals outside of this valid differential
range cause DOR_ to assert high as shown in Table 1.
DOR is synchronized with DAV and transitions along
with the output data D13_–D0_. There is an 8 clockcycle latency in the DOR function as is with the output
data (Figure 5). DOR_ is high impedance when the
MAX12559 is in power-down (PD = high). DOR_ enters
a high-impedance state within 10ns after the rising edge
of PD and becomes active 10ns after PD’s falling edge.
Digital Output Data and Output Format Selection
The MAX12559 provides two 14-bit, parallel, tri-state
output buses. D0A/B–D13A/B and DORA/B update on
the falling edge of DAV and are valid on the rising edge
of DAV.
Table 3. Output Codes vs. Input Voltage
GRAY-CODE OUTPUT CODE
(G/T = 1)
BINARY
D13A–D0A
D13B–D0B
TWO’S-COMPLEMENT OUTPUT CODE
(G/T = 0)
DECIMAL
HEXADECIMAL
EQUIVALENT
EQUIVALENT
OF
DOR
OF
D13A–D0A
D13A–D0A
D13B–D0B
D13B–D0B
(CODE10)
BINARY
D13A–D0A
D13B–D0B
DECIMAL
HEXADECIMAL
EQUIVALENT
EQUIVALENT
OF
DOR
OF
D13A–D0A
D13A–D0A
D13B–D0B
D13B–D0B
(CODE10)
10 0000 0000 0000
1
0x2000
+16,383
01 1111 1111 1111
1
VIN_P - VIN_N
VREF_P = 2.418V
VREF_N = 0.882V
0x1FFF
+8191
> +1.023875V
(DATA OUT OF
RANGE)
10 0000 0000 0000
0
0x2000
+16,383
01 1111 1111 1111
0
0x1FFF
+8191
+1.023875V
10 0000 0000 0001
0
0x2001
+16,382
01 1111 1111 1110
0
0x1FFE
+8190
+1.023750V
11 0000 0000 0011
0
0x3003
+8194
00 0000 0000 0010
0
0x0002
+2
+0.000250V
11 0000 0000 0001
0
0x3001
+8193
00 0000 0000 0001
0
0x0001
+1
+0.000125V
11 0000 0000 0000
0
0x3000
+8192
00 0000 0000 0000
0
0x0000
0
+0.000000V
01 0000 0000 0000
0
0x1000
+8191
11 1111 1111 1111
0
0x3FFF
-1
-0.000125V
01 0000 0000 0001
0
0x1001
+8190
11 1111 1111 1110
0
0x3FFE
-2
-0.000250V
00 0000 0000 0001
0
0x0001
+1
10 0000 0000 0001
0
0x2001
-8191
-1.023875V
00 0000 0000 0000
0
0x0000
0
10 0000 0000 0000
0
0x2000
-8192
00 0000 0000 0000
1
0x0000
0
10 0000 0000 0000
1
0x2000
-8192
-1.024000V
< -1.024000V
(DATA OUT OF
RANGE)
______________________________________________________________________________________
19
MAX12559
falling edge of DAV, and DAV rises once the output
data is valid. The falling edge of DAV is synchronized
to have a 5.8ns delay from the falling edge of the input
clock. Output data at D0A/B–D13A/B and DORA/B are
valid from 3.6ns before the rising edge of DAV to
3.55ns after the rising edge of DAV.
DAV enters high impedance when the MAX12559 is
powered down (PD = OV DD ). DAV enters its highimpedance state 10ns after the rising edge of PD and
becomes active again 10ns after PD transitions low.
DAV can sink and source 600µA and has three times the
driving capabilities of D0A/B–D13A/B and DORA/B. DAV
is typically used to latch the MAX12559 output data into
an external digital back-end circuit. Keep the capacitive
load on DAV as low as possible (< 15pF) to avoid large
digital currents feeding back into the analog portion of
the MAX12559, thereby degrading its dynamic performance. Buffering DAV externally isolates it from heavy
capacitive loads. Refer to the MAX12559 EV kit schematic for recommendations of how to drive the DAV signal
through an external buffer.
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
1 LSB = 4/3 x (VREFP - VREFN) / 16,384
1 LSB = 4/3 x (VREFP - VREFN) / 16,384
2/3 x (VREFP - VREFN)
2/3 x (VREFP - VREFN)
0x2000
0x2001
0x1FFD
0x2003
GRAY OUTPUT CODE (LSB)
TWO'S-COMPLEMENT OUTPUT CODE (LSB)
2/3 x (VREFP - VREFN)
0x1FFF
0x1FFE
0x0001
0x0000
0x3FFF
0x3001
0x3000
0x1000
0x2003
0x2002
0x0002
0x0003
0x2001
0x2000
0x0001
0x0000
-8191 -8189
-1 0 +1
+8189 +8191
DIFFERENTIAL INPUT VOLTAGE (LSB)
2/3 x (VREFP - VREFN)
-8191 -8189
-1 0 +1
+8189 +8191
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 6. Two’s-Complement Transfer Function (G/T = 0)
Figure 7. Gray-Code Transfer Function (G/T = 1)
The MAX12559 output data format is either Gray code
or two’s complement depending on the logic input G/T.
With G/T high, the output data format is Gray code.
With G/T low, the output data format is set to two’s complement. See Figure 8 for a binary-to-Gray and Gray-tobinary code conversion example.
The following equations, Table 3, Figure 6, and Figure 7
define the relationship between the digital output and
the analog input.
Gray Code (G/T = 1):
VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x
(CODE10 - 8192) / 16,384
performance. Adding external digital buffers on the digital outputs helps isolate the MAX12559 from heavy
capacitive loads. To improve the dynamic performance
of the MAX12559, add 220Ω resistors in series with the
digital outputs close to the MAX12559. Refer to the
MAX12559 EV kit schematic for guidelines of how to
drive the digital outputs through 220Ω series resistors
and external digital output buffers.
Two’s Complement (G/T = 0):
VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x
CODE10 / 16,384
where CODE10 is the decimal equivalent of the digital
output code as shown in Table 3.
The digital outputs D0A/B–D13A/B are high impedance
when the MAX12559 is in power-down (PD = 1) mode.
D0A/B–D13A/B enter this state 10ns after the rising
edge of PD and become active again 10ns after PD
transitions low.
Keep the capacitive load on the MAX12559 digital outputs D0A/B–D13A/B as low as possible (< 15pF) to
avoid large digital currents feeding back into the analog portion of the converter and degrading its dynamic
20
Power-Down Input
The MAX12559 has two power modes that are controlled with a power-down digital input (PD). With PD
low, the converter is in its normal operating mode. With
PD high, the MAX12559 is in power-down mode.
The power-down mode allows the MAX12559 to efficiently use power by transitioning to a low-power state
when conversions are not required. Additionally, the
MAX12559 parallel output bus goes high impedance in
power-down mode, allowing other devices on the bus
to be accessed.
In power-down mode all internal circuits are off, the
analog supply current reduces to less than 50µA, and
the digital supply current reduces to 1µA. The following
list shows the state of the analog inputs and digital outputs in power-down mode.
1) INAP/B, INAN/B analog inputs are disconnected
from the internal input amplifier (Figure 3).
______________________________________________________________________________________
Dual, 96Msps, 14-Bit, IF/Baseband ADC
GRAY-TO-BINARY CODE CONVERSION
1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME
AS THE MOST SIGNIFICANT BINARY BIT.
1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE
MOST SIGNIFICANT GRAY-CODE BIT.
D13
0
D7
D11
1
1
1
0
1
D3
0
1
0
0
1
D0
1
0
0
0
BIT POSITION
D13
BINARY
0
GRAY CODE
0
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:
0 1
1
1
0
1
D3
1
1
BINARY12 = BINARY13 + GRAY12
BINARY12 = 0 + 1
GRAY12 = 1
BINARY12 = 1
1
1
D7
0
1
1
0
D3
1
0
1
0
GRAY CODE
WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
GRAY12 = BINARY12 + BINARY13
+
0
BINARYX = BINARYX+1 + GRAYX
GRAY12 = 1 + 0
D11
1
BIT POSITION
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO
THE FOLLOWING EQUATION:
WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
D13
0
D0
BINARY
GRAYX = BINARYX + BINARYX + 1
0
D7
D11
MAX12559
BINARY-TO-GRAY CODE CONVERSION
0
1
D0
1
0
0
BIT POSITION
D13
BINARY
0
D7
D11
1
0
1 1
0
1
D3
1
1
0
1
D0
0
1
0
BIT POSITION
GRAY CODE
+
0
GRAY CODE
1
0
3) REPEAT STEP 2 UNTIL COMPLETE:
BINARY
1
3) REPEAT STEP 2 UNTIL COMPLETE:
GRAY11 = BINARY11 + BINARY12
BINARY11 = BINARY12 + GRAY11
GRAY11 = 1 + 1
BINARY11 = 1 + 0
GRAY11 = 0
BINARY11 = 1
D13
0
D7
D11
+
1
0 1
1
1
0
D3
1
0
0
1
D0
1
0
0
BIT POSITION
D13
BINARY
0
D7
D11
1
0
1
1
0
1
D3
1
1
0
1
D0
0
1
0
BIT POSITION
GRAY CODE
+
1
0
0
0
GRAY CODE
4) THE FINAL GRAY-CODE CONVERSION IS:
1
1
BINARY
4) THE FINAL BINARY CONVERSION IS:
BIT POSITION
D13
0
1
1
0
1
1
0
1
0
0
1
1
0
0
BINARY
0
1
0
1
1
0
1
1
1
0
1
0
1
0
GRAY CODE
0
1
0
1
1
0
1
1
1
0
1
0
1
0
GRAY CODE
0
1
1
0
1
1
0
1
0
0
1
1
0
0
BINARY
D13
D7
D11
D3
D0
D7
D11
D3
D0
BIT POSITION
EXCLUSIVE OR TRUTH TABLE
FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAY
CODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUT
FORMAT OF THE MAX12559 IS TWO'S-COMPLEMENT BINARY,
HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODE
MUST BE INVERTED TO REFLECT TRUE OFFSET BINARY FORMAT.
A
B
0
0
1
1
0
1
0
1
Y
=
A
+
B
0
1
1
0
Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion
______________________________________________________________________________________
21
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
IN_P
5.6pF
0.1μF
1
VIN
6
49.9Ω
0.5%
24.9Ω
MAX12559
T1
N.C.
5
2
COM_
N.C.
0.1μF
3
4
MINI-CIRCUITS 49.9Ω
0.5%
ADT1-1WT
IN_N
5.6pF
24.9Ω
Figure 9. Transformer-Coupled Input Drive for Input Frequencies
Up to Nyquist
2) REFOUT has approximately 17kΩ to GND.
3) REFAP/B, COMA/B, REFAN/B enter a high-impedance state with respect to VDD and GND, but there
is an internal 4kΩ resistor between REFAP/B and
COMA/B as well as an internal 4kΩ resistor
between REFAN/B and COMA/B.
4) D0A–D13A, D0B–D13B, DORA, and DORB enter a
high-impedance state.
5) DAV enters a high-impedance state.
6) CLKP, CLKN clock inputs enter a high-impedance
state (Figure 4).
The wake-up time from power-down mode is dominated
by the time required to charge the capacitors at REF_P,
REF_N, and COM_. In internal reference mode and
buffered external reference mode the wake-up time is
typically 10ms. When operating in the unbuffered external reference mode the wake-up time is dependent on
the external reference drivers.
Applications Information
Using Transformer Coupling
In general, the MAX12559 provides better SFDR and
THD with fully differential input signals than singleended input drive, especially for input frequencies
above 125MHz. In differential input mode, even-order
harmonics are lower as both inputs are balanced, and
each of the ADC inputs only requires half the signal
swing compared to single-ended input mode.
22
An RF transformer (Figure 9) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX12559
for optimum performance. Connecting the center tap of
the transformer to COM provides a VDD / 2 DC level
shift to the input. Although a 1:1 transformer is shown, a
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the
overall distortion. The configuration of Figure 9 is good
for frequencies up to Nyquist (fCLK / 2).
The circuit of Figure 10 converts a single-ended input
signal to fully differential just as Figure 9. However,
Figure 10 utilizes an additional transformer to improve
the common-mode rejection allowing high-frequency
signals beyond the Nyquist frequency. A set of 75Ω
and 110Ω termination resistors provide an equivalent
50Ω termination to the signal source. The second set of
termination resistors connects to COM_ providing the
correct input common-mode voltage. Two 0Ω resistors
in series with the analog inputs allow high-IF input frequencies. These 0Ω resistors can be replaced with lowvalue resistors to limit the input bandwidth.
The input network in Figure 10 can be modified to enhance
the frequency-range-specific AC performance of the
MAX12559 by simply replacing the input capacitance with
a series network of resistor (RIN) and capacitor (CIN).
Table 4 displays a selection of resistors and capacitors
that are recommended to help improve the already
excellent performance of this ADC for specific applications requiring only a certain range of input frequencies.
Single-Ended AC-Coupled Input Signal
Figure 11 shows an AC-coupled, single-ended input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity.
Buffered External Reference Drives
Multiple ADCs
The buffered external reference mode allows for more
control over the MAX12559 reference voltage and
allows multiple converters to use a common reference.
The REFIN input impedance is > 50MΩ.
Figure 12 shows the MAX6029 precision 2.048V bandgap
reference used as a common reference for multiple converters. The 2.048V output of the MAX6029 passes
through a single-pole 10Hz LP filter to the MAX4230.
The MAX4250 buffers the 2.048V reference and provides additional 10Hz LP filtering before its output is
applied to the REFIN input of the MAX12559.
______________________________________________________________________________________
Dual, 96Msps, 14-Bit, IF/Baseband ADC
MAX12559
0Ω*
IN_P
CIN
0.1μF
1
VIN
N.C.
5
T1
6
2
1
75Ω
0.5%
N.C.
N.C.
T2
5
110Ω
0.5%
6
RIN
MAX12559
2
COM_
N.C.
0.1μF
3
4
MINI-CIRCUITS
ADT1-1WT
75Ω
0.5%
3
4
MINI-CIRCUITS
ADT1-1WT
110Ω
0.5%
0Ω*
IN_N
*0Ω RESISTORS CAN BE REPLACED WITH
LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH.
CIN
RIN
Figure 10. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
Unbuffered External Reference Drives
Multiple ADCs
The unbuffered external reference mode allows for precise control over the MAX12559 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal reference, allowing REF_P, REF_N, and COM_ to be driven
directly by a set of external reference sources.
Figure 13 uses a MAX6029 precision 3.000V bandgap
reference as a common reference for multiple converters. A seven-component resistive divider chain follows
the MAX6029 voltage reference. The 0.47µF capacitor
along this chain creates a 10Hz LP filter. Three
MAX4230 amplifiers buffer taps along this resistor
chain providing 2.413V, 1.647V, and 0.880V to the
MAX12559 REF_P, REF_N, and COM_ reference inputs.
The feedback around the MAX4230 op amps provides
additional 10Hz LP filtering. Reference voltages 2.413V
and 0.880V set the full-scale analog input range for the
converter to ±1.022V (±[VREF_P - VREF_N] x 2/3).
Note that one single power supply for all active circuit
components removes any concern regarding powersupply sequencing when powering up or down.
Table 4. Component Selection to
Enhance the Frequency-Range-Specific
AC Performance
INPUT
FREQUENCY
RANGE
CIN
COMPONENT
VALUES
< 10MHz
RIN
COMPONENT
VALUES
12pF to 22pF
0Ω
10MHz to 125MHz
12pF
50Ω
> 125MHz
5.6pF
0Ω
VIN
0.1μF
0Ω
IN_P
MAX4108
5.6pF
100Ω
24.9Ω
MAX12559
COM_
0.1μF
100Ω
24.9Ω
IN_N
5.6pF
Figure 11. Single-Ended, AC-Coupled Input Drive
______________________________________________________________________________________
23
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
3.3V
0.1μF
2.2μF
VDD
REF_P
REFIN
0.1μF
0.1μF
1
5
16.2kΩ
3
0.1μF
1
47Ω
300μF
6V
0.1μF
REF_N
MAX4230
4
10μF
MAX12559
5
1μF
MAX6029
(EUK21)
2.048V
0.1μF
2
2
COM_
REFOUT
1.47kΩ
GND
0.1μF
0.1μF
NOTE: ONE FRONT-END REFERENCE CIRCUIT
CAN SOURCE UP TO 15mA AND SINK UP TO
30mA OF OUTPUT CURRENT.
3.3V
0.1μF
2.2μF
VDD
REF_P
REFIN
0.1μF
10μF
MAX12559
0.1μF
REF_N
0.1μF
COM_
REFOUT
0.1μF
GND
Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference
24
______________________________________________________________________________________
0.1μF
Dual, 96Msps, 14-Bit, IF/Baseband ADC
3V
0.1μF
0.1μF
1
2.2μF
5
20kΩ
1%
MAX6029
(EUK30)
REF_P
VDD
REFOUT
0.1μF
20kΩ
1%
2
10μF
MAX12559
2.413V
1
4
REF_N
47Ω
0.1μF
MAX4230
3
0.47μF
330μF
6V
10μF
6V
1.47kΩ
52.3kΩ
1%
COM_
0.1μF
REFIN
4
47Ω
MAX4230
3
3.3V
330μF
6V
10μF
6V
52.3kΩ
1%
1.47kΩ
0.1μF
4
47Ω
REF_P
MAX4230
3
2.2μF
0.880V
1
20kΩ
1%
GND
1.647V
1
20kΩ
1%
0.1μF
0.1μF
VDD
REFOUT
0.1μF
10μF
6V
330μF
6V
10μF
0.1μF
0.1μF
MAX12559
1.47kΩ
REF_N
0.1μF
20kΩ
1%
COM_
0.1μF
GND
REFIN
Figure 13. External Unbuffered Reference Driving Multiple ADCs
______________________________________________________________________________________
25
MAX12559
3.3V
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
Grounding, Bypassing, and
Board Layout
The MAX12559 requires high-speed board layout design
techniques. Refer to the MAX12527/MAX12528/
MAX12529/MAX12557/MAX12558/MAX12559 EV kit data
sheet for a board layout reference. Locate all bypass
capacitors as close to the device as possible, preferably
on the same side as the ADC, using surface-mount
devices for minimum inductance. Bypass VDD to GND
with a 220µF ceramic capacitor in parallel with at least
one 10µF, one 4.7µF, and one 0.1µF ceramic capacitor.
Bypass OVDD to GND with a 220µF ceramic capacitor in
parallel with at least one 10µF, one 4.7µF, and one 0.1µF
ceramic capacitor. High-frequency bypassing/decoupling
capacitors should be located as close as possible to the
converter supply pins.
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. All grounds
and the exposed backside paddle of the MAX12559
must be connected to the same ground plane. The
MAX12559 relies on the exposed backside paddle connection for a low-inductance ground connection. Isolate
the ground plane from any noisy digital system ground
planes such as a DSP or output buffer ground.
Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90° turns.
Ensure that the differential, analog input network layout is
symmetric and that all parasitic components are balanced equally. Refer to the MAX12527/MAX12528/
MAX12529/MAX12557/MAX12558/MAX12559 EV kit data
sheet for an example of symmetric input layout.
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For the MAX12559, this
straight line is between the endpoints of the transfer
function, once offset and gain errors have been nullified.
INL deviations are measured at every step of the transfer
function and the worst-case deviation is reported in the
Electrical Characteristics table.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
less than 1 LSB guarantees no missing codes and a
monotonic transfer function. For the MAX12559, DNL
deviations are measured at every step of the transfer
function and the worst-case deviation is reported in the
Electrical Characteristics table.
26
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally the midscale
MAX12559 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation
between the measured midscale transition point and
the ideal midscale transition point.
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope of
the ideal transfer function. The slope of the actual transfer
function is measured between two data points: positive
full scale and negative full scale. Ideally, the positive fullscale MAX12559 transition occurs at 1.5 LSBs below positive full scale, and the negative full-scale transition
occurs at 0.5 LSB above negative full scale. The gain
error is the difference of the measured transition points
minus the difference of the ideal transition points.
Small-Signal Noise Floor (SSNF)
SSNF is the integrated noise and distortion power in the
Nyquist band for small-signal inputs. The DC offset is
excluded from this noise calculation. For this converter,
a small signal is defined as a single tone with a -35dBFS
amplitude. This parameter captures the thermal and
quantization noise characteristics of the data converter
and can be used to help calculate the overall noise figure of a digital receiver signal path.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNR[max] = 6.02 × N + 1.76
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the
fundamental, the first six harmonics (HD2 through
HD7), and the DC offset.
SNR = 20 x log (SIGNALRMS / NOISERMS)
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
______________________________________________________________________________________
Dual, 96Msps, 14-Bit, IF/Baseband ADC
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is
expressed as:
⎛
V22 + V32 + V4 2 + V52 + V62 + V72
THD = 20 × log ⎜
⎜
V1
⎝
⎞
⎟
⎟
⎠
where V1 is the fundamental amplitude, and V2 through
V7 are the amplitudes of the 2nd- through 7th-order
harmonics (HD2 through HD7).
MAX12559
Nyquist frequency excluding the fundamental and the
DC offset.
CLKN
CLKP
tAD
ANALOG
INPUT
tAJ
SAMPLED
DATA
T/H
HOLD
TRACK
HOLD
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious
component, excluding DC offset.
3rd-Order Intermodulation (IM3)
IM3 is the power of the 3rd-order intermodulation product relative to the input power of either of the input tones
fIN1 and fIN2. The individual input tone power levels are
set to -7dBFS for the MAX12559. The 3rd-order intermodulation products are 2 x fIN1 - fIN2 and 2 x fIN2 - fIN1.
Aperture Jitter
Figure 14 shows the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 14).
Full-Power Bandwidth
A large -0.2dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as the
full-power input bandwidth frequency.
Output Noise (nOUT)
The output noise (nOUT) parameter is similar to thermal
plus quantization noise and is an indication of the converter’s overall noise performance.
No fundamental input tone is used to test for nOUT.
IN_P, IN_N, and COM_ are connected together and
1024k data points are collected. nOUT is computed by
taking the RMS value of the collected data points after
the mean is removed.
Figure 14. T/H Aperture Timing
Overdrive Recovery Time
Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The MAX12559 specifies overdrive
recovery time using an input transient that exceeds the
full-scale limits by ±10%. The MAX12559 requires one
clock cycle to recover from the overdrive condition.
Crosstalk
Crosstalk indicates how well each channel is isolated
from the other channel. In case of the MAX12559,
crosstalk specifies the coupling onto one channel
being driven by a (-1dBFS) signal when the adjacent
interfering channel is driven by a full-scale signal.
Measurement includes all spurs resulting from both
direct coupling and mixing components.
Gain Matching
Gain matching is a figure of merit that indicates how
well the gains between the two channels are matched
to each other. The same input signal is applied to both
channels and the maximum deviation in gain is reported (typically in dB) as gain matching.
Offset Matching
Like gain matching, offset matching is a figure of merit
that indicates how well the offsets between the two channels are matched to each other. The same input signal is
applied to both channels and the maximum deviation in
offset is reported (typically in %FSR) as offset matching.
______________________________________________________________________________________
27
Dual, 96Msps, 14-Bit, IF/Baseband ADC
MAX12559
Pin Configuration
46 45 44 43 42 41
D7B
D9B
D8B
D10B
D12B
D11B
D13B
DORB
OVDD
DAV
D0A
50 49 48 47
D1A
D3A
51
D2A
D5A
D4A
D6A
TOP VIEW
40 39 38 37 36 35
D7A 52
34
D6B
D8A 53
33
D5B
D9A 54
32
D4B
D10A 55
31
D3B
D11A 56
30
D2B
D12A 57
29
D1B
D13A 58
28
D0B
DORA 59
27
OVDD
OVDD 60
26
VDD
25
VDD
62
24
VDD
VDD 63
23
VDD
G/T 64
22
DIV4
PD 65
21
DIV2
SHREF 66
20
CLKP
REFOUT 67
19
CLKN
68
18
DIFFCLK/SECLK
MAX12559
VDD 61
8
9
10 11 12 13 14 15 16
INAN
GND
GND
COMA
REFAP
REFAN
GND
REFBN
17
GND
7
INBP
6
GND
5
INBN
4
GND
3
COMB
2
REFBP
1
GND
REFIN
EXPOSED PADDLE (GND)
INAP
VDD
THIN QFN
28
______________________________________________________________________________________
Dual, 96Msps, 14-Bit, IF/Baseband ADC
68L QFN THIN.EPS
PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
21-0142
E
1
2
______________________________________________________________________________________
29
MAX12559
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX12559
Dual, 96Msps, 14-Bit, IF/Baseband ADC
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
21-0142
E
2
2
Revision History____________________
Pages changed at Rev 1: 1–4, 7–12, 26, 29, 30
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.