Microchip MCP65R46T-24CHY 3 ua comparator with integrated reference voltage Datasheet

MCP65R41/6
3 µA Comparator with Integrated Reference Voltage
Features
Description
• Factory Set Reference Voltage
- Available Voltage: 1.21V and 2.4V
- Tolerance: ±1% (typical)
• Low Quiescent Current: 2.5 µA (typical)
• Propagation Delay: 4 µs with 100 mV overdrive
• Input Offset Voltage: ±3mV (typical)
• Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V
• Output Options:
- MCP65R41  Push-Pull
- MCP65R46 Open-Drain
• Wide Supply Voltage Range: 1.8V to 5.5V
• Packages: SOT23-6
The Microchip Technology Inc. MCP65R41/6 family of
push-pull and open-drain output comparators are
offered with integrated Reference Voltages of 1.21V
and 2.4V. This family provides ±1% (typical) tolerance
while consuming 2.5 µA (typical) current. These
comparators operate with a single-supply voltage as
low as 1.8V to 5.5V, which makes them ideal for low
cost and/or battery powered applications.
Typical Applications
•
•
•
•
•
•
•
Laptop computers
Mobile Phones
Hand-held Metering Systems
Hand-held Electronics
RC Timers
Alarm and Monitoring Circuits
Window Comparators
These comparators are optimized for low power,
single-supply applications with greater than rail-to-rail
input operation. The output limits supply current surges
and dynamic power consumption while switching. The
internal input hysteresis eliminates output switching
due to internal noise voltage, reducing current draw.
The MCP65R41 output interfaces to CMOS/TTL logic.
The open-drain output device MCP65R46 can be used
as a level-shifter from 1.6V to 10V using a pull-up
resistor. It can also be used as a wired-OR logic.
This family of devices is available with 6 lead SOT-23
package.
Package Types
MCP65R41/6
SOT23-6
Design Aids
6 VDD
VSS 2
+IN 3
5 VREF
-
OUT 1
+
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
4 -IN
Typical Application
Over Temperature Alert
VREF
Thermistor
VPU
VDD
R4
RPU*
VOUT
VREF
R2
R3
RF
* Pull-up resistor required for the MCP65R46 only.
 2010 Microchip Technology Inc.
DS22269A-page 1
MCP65R41/6
NOTES:
DS22269A-page 2
 2010 Microchip Technology Inc.
MCP65R41/6
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Absolute Maximum Ratings†
†Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
VDD - VSS ....................................................................... 7.0V
All other inputs and outputs...........VSS – 0.3V to VDD + 0.3V
Difference Input voltage ......................................|VDD - VSS|
Output Short Circuit Current .................................... ±25 mA
Current at Input Pins .................................................. ±2 mA
Current at Output and Supply Pins .......................... ±50 mA
Storage temperature ................................... -65°C to +150°C
Ambient temperature with power applied.... -40°C to +125°C
Junction temperature ................................................ +150°C
ESD protection on all pins (HBM/MM)4 kV/200V
ESD protection on MCP65R46 OUT pin (HBM/MM).............
4 kV/175V
DC CHARACTERISTICS
Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ =
VDD/2, VIN- = VSS, RL = 100 k to VDD/2 (MCP65R41 only), and RPull-Up = 2.74 k to VDD (MCP65R46 only),
and TA = -40°C to 125°C.
Parameters
Sym
Min
Typ
Max
VDD
IQ
Input Voltage Range
VCMR
Common-Mode Rejection Ratio
VDD = 5V
CMRR
Units
Conditions
1.8
—
5.5
V
—
2.5
4
µA
VSS0.3
—
VDD+0.3
V
55
70
—
dB
VCM = -0.3V to 5.3V
50
65
—
dB
VCM = 2.5V to 5.3V
55
70
—
dB
MCP65R41,
VCM = -0.3V to 2.5V
50
70
—
dB
MCP65R46,
VCM = -0.3V to 2.5V
PSRR
63
80
—
dB
VCM = VSS
mV
VCM = VSS (Note 1)
Power Supply
Supply Voltage
Quiescent Current per Comparator
IOUT = 0
Input
Power Supply Rejection Ratio
Input Offset Voltage
Drift with Temperature
Input Hysteresis Voltage
VOS
-10
±3
+10
VOS/T
—
±10
—
VHYST
1
3.3
5
µV/°C VCM = VSS
mV
VCM = VSS (Note 1)
Drift with Temperature
VHYST/T
—
6
—
µV/°C VCM = VSS
Drift with Temperature
VHYST/T
—
5
—
µV/°C2 VCM = VSS
IB
—
1
—
TA = +85°C
IB
—
50
—
pA
VCM = VSS
TA = +125°C
IB
—
—
5000
pA
VCM = VSS
Input Offset Current
IOS
—
±1
—
pA
VCM= VSS
Input Bias Current
Note 1:
2:
3:
4:
2
pA
VCM = VSS
The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the
difference between the input-referred trip points.
Limit the output current to Absolute Maximum Rating of 30 mA.
Do not short the output of the MCP65R46 comparators above VSS + 10V.
The low power reference voltage pin is designed to drive small capacitive loads. See Section 4.5.2.
 2010 Microchip Technology Inc.
DS22269A-page 3
MCP65R41/6
DC CHARACTERISTICS (CONTINUED)
Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ =
VDD/2, VIN- = VSS, RL = 100 k to VDD/2 (MCP65R41 only), and RPull-Up = 2.74 k to VDD (MCP65R46 only),
and TA = -40°C to 125°C.
Parameters
Min
Typ
Max
Units
ZCM/ZDIFF
—
13
10 ||4
—
||pF
High Level Output Voltage
VOH
VDD0.2
—
—
V
IOUT = -2 mA, VDD = 5V
Low Level Output Voltage
VOL
—
—
VSS+0.2
V
IOUT = 2 mA, VDD = 5V
ISC
—
±50
—
mA
(Note 2) MCP65R41
ISC
—
±1.5
—
mA
(Note 2) MCP65R46
VOL
—
—
VSS+0.2
V
Common Mode/
Differential Input Impedance
Sym
Conditions
Push Pull Output
Short Circuit Current
Open Drain Output (MCP65R46)
Low Level Output Voltage
IOUT = 2 mA
Short Circuit Current
ISC
—
±50
—
mA
High-Level Output Current
IOH
-100
—
—
nA
VPU= 10V
Pull-up Voltage
VPU
1.6
—
10
V
Note 3
Output Pin Capacitance
COUT
—
8
—
pF
VTOL
-2
±1
+2
%
IREF = 0A,
VREF = 1.21V and 2.4V
VREF
1.185
1.21
1.234
V
IREF = 0A
2.352
2.4
2.448
V
—
±500
—
µA
—
27
100
ppm
VREF = 1.21V, VDD = 1.8V
—
22
100
ppm
VREF = 1.21V, VDD = 5.5V
—
23
100
ppm
VREF = 2.4V, VDD = 5.5V
—
200
—
pF
Reference Voltage Output
Initial Reference Tolerance
Reference Output Current
Drift with Temperature (characterized but not production tested)
Capacitive Load
Note 1:
2:
3:
4:
IREF
VREF/T
CL
VTOL = ±2% (maximum)
Note 4
The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the
difference between the input-referred trip points.
Limit the output current to Absolute Maximum Rating of 30 mA.
Do not short the output of the MCP65R46 comparators above VSS + 10V.
The low power reference voltage pin is designed to drive small capacitive loads. See Section 4.5.2.
DS22269A-page 4
 2010 Microchip Technology Inc.
MCP65R41/6
AC CHARACTERISTICS
Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C,
VIN+ = VDD/2, Step = 200 mV, Overdrive = 100 mV, RL = 100 k to VDD/2 (MCP65R41 only),
RPull-Up = 2.74 k to VDD (MCP65R46 only), and CL = 50 pF.
Parameters
Sym
Min
Typ
Max
Units
Rise Time
tR
—
0.85
—
µs
Fall Time
tF
—
0.85
—
µs
Propagation Delay (High to Low)
tPHL
—
4
8.0
µs
Propagation Delay (Low to High)
tPLH
—
4
8.0
µs
Propagation Delay Skew
tPDS
—
±0.2
—
µs
Maximum Toggle Frequency
fMAX
—
160
—
kHz
VDD = 1.8V
fMAX
—
120
—
kHz
VDD = 5.5V
EN
—
200
—
Input Noise Voltage
Note 1:
Conditions
Note 1
µVP-P 10 Hz to 100 kHz
Propagation Delay Skew is defined as: tPDS = tPLH - tPHL.
TEMPERATURE SPECIFICATIONS
Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V and VSS = GND.
Symbo
l
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
JA
—
190.5
—
°C/W
Parameters
Conditions
Temperature Ranges
Thermal Package Resistances
Thermal Resistance, SOT23-6
1.2
Test Circuit Configuration
VDD
VDD
200k
200k
2.74k
MCP65R41
200k
VIN = VSS
VOUT
50p
FIGURE 1-1:
Test Circuit for the Push-pull
Output Comparators.
 2010 Microchip Technology Inc.
VOUT
200k
200k
200k
VSS = 0V
MCP65R46
VIN = VSS
100k
VSS = 0V
50p
FIGURE 1-2:
Test Circuit for the Open
Drain Comparators.
DS22269A-page 5
MCP65R41/6
NOTES:
DS22269A-page 6
 2010 Microchip Technology Inc.
MCP65R41/6
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 100 k to VDD /2 (MCP65R41 only), RPull-Up = 2.74 k to VDD /2 (MCP65R46 only) and CL = 50 pF.
60%
VDD = 5.5V
VCM = VSS
Avg. = 0.61 mV
StDev = 1.48 mV
850 units
VDD = 1.8V
VCM = VSS
Avg. = 1.09 mV
StDev = 1.59 mV
850 units
40%
30%
20%
10%
30%
20%
0%
-10
-8
-6
-4
FIGURE 2-1:
-2 0
2
VOS (mV)
4
6
8
FIGURE 2-4:
Input Offset Voltage.
10.0
8.0
6.0
4.0
2.0
0.0
-2.0
-4.0
-6.0
-8.0
-10.0
-60 -48 -36 -24 -12 0 12 24
VOS Drift (µV/°C)
10
36
48
60
Input Offset Voltage Drift.
3.0
VCM = VSS
2.0
VOS (mV)
VDD= 1.8V
VDD= 5.5V
1.0
0.0
-1.0
-2.0
T A= -40°C to +125°C
-3.0
-50
-25
FIGURE 2-2:
vs. Temperature.
0
25
50
75
Temperature(°C)
100
2.5
3.5
VDD (V)
4.5
5.5
FIGURE 2-5:
Input Offset Voltage vs.
Supply Voltage vs. Temperature.
Input Offset Voltage
10.0
8.0
TA= -40°C
6.0
TA= +25°C
4.0
2.0
0.0
-2.0
TA= +85°C
TA= +125°C
-4.0
-6.0
-8.0
-10.0
-0.3 0.0 0.3 0.6
1.5
125
10.0
VDD = 1.8V
TA = -40°C to +125°C
VDD = 5.5V
7.5
5.0
VOS (mV)
VOS (mV)
40%
10%
0%
VOS (mV)
VCM = VSS
Avg. = 9.86 µV/°C
StDev = 4.97 µV/°C
850 Units
TA = -40°C to +125°C
50%
Occurrences (%)
Occurrences (%)
50%
2.5
0.0
-2.5
-5.0
-7.5
0.9 1.2
VCM (V)
1.5
1.8
FIGURE 2-3:
Input Offset Voltage
vs. Common-Mode Input Voltage.
 2010 Microchip Technology Inc.
2.1
-10.0
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VCM (V)
FIGURE 2-6:
Input Offset Voltage vs.
Common-Mode Input Voltage.
DS22269A-page 7
MCP65R41/6
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 100 k to VDD /2 (MCP65R41 only), RPull-Up = 2.74 k to VDD /2 (MCP65R46 only) and CL = 50 pF.
Occurrences (%)
25%
VDD = 5.5V
Avg. = 2.3 mV
StDev = 0.17 mV
850 units
VDD = 1.8V
Avg. = 2.4 mV
StDev = 0.17 mV
850 units
20%
15%
10%
80%
5%
0%
2.0
Occurrences (%)
2.5 3.0 3.5
VHYST (mV)
4.0
4.5
VDD = 1.8V
Avg. = 6.1 µV/°C
StDev = 0.55 µV/°C
40%
30%
20%
5.0
850 Units
T A = -40°C to +125°C
VCM = V SS
Input Hysteresis Voltage
VDD = 1.8V
Avg. = 3.0 mV
StDev = 0.17 mV
850 units
V DD = 5.5V
Avg. = 2.8 mV
StDev = 0.17 mV
850 units
15%
10%
5%
0
2
4
6
8 10 12 14 16
VHYST Drift, TC1 (µV/°C)
18
20
FIGURE 2-10:
Input Hysteresis Voltage
Drift - Linear Temperature Compensation (TC1).
30%
VDD = 1.8V
Occurrences (%)
1.5
FIGURE 2-7:
at -40°C.
20%
50%
0%
1.0
25%
60%
10%
TA = -40°C
30%
VDD = 5.5V
Avg. = 5.7 µV/°C
StDev = 0.50 µV/°C
70%
Occurrences (%)
30%
2
VDD = 5.5V
2
20%
Avg. = 0.25 µV/°C
StDev = 0.1 µV/°C2
10%
1380 Units
TA = -40°C to +125°C
VCM = VSS
Avg. = 0.3 µV/°C
StDev = 0.2 µV/°C2
V DD = 5.5V
V CM = VSS
Avg. = 10.4 µV/°C
StDev = 0.6 µV/°C
TA = +25°C
0%
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0%
-0.50
5.0
-0.25
VHYST (mV)
FIGURE 2-8:
at +25°C.
Input Hysteresis Voltage
1.00
FIGURE 2-11:
Input Hysteresis Voltage
Drift - Quadratic Temperature Compensation
(TC2).
5.0
30%
VDD = 1.8V
Avg. = 3.4 mV
StDev = 0.14 mV
850 units
20%
VCM = VSS
4.0
VHYST (mV)
VDD = 5.5V
Avg. = 3.2 mV
StDev = 0.13 mV
850 units
25%
Occurrences (%)
0.00
0.25
0.50
0.75
VHYST Drift, TC2 (µV/°C2)
15%
10%
VDD = 1.8V
3.0
2.0
VDD= 5.5V
5%
T A = +125°C
0%
1.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-50
-25
VHYST (mV)
FIGURE 2-9:
at +125°C.
DS22269A-page 8
Input Hysteresis Voltage
FIGURE 2-12:
vs. Temperature.
0
25
50
75
Temperature (°C)
100
125
Input Hysteresis Voltage
 2010 Microchip Technology Inc.
MCP65R41/6
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 100 k to VDD /2 (MCP65R41 only), RPull-Up = 2.74 k to VDD /2 (MCP65R46 only) and CL = 50 pF.
VDD = 1.8V
Occurrences (%)
5.0
VHYST (mV)
4.0
3.0
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
2.0
1.0
-0.3
0.0
0.3
0.6
0.9 1.2
VCM (V)
1.5
1.8
5.0
IQ (µA)
VHYST (mV)
4.0
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
2.0
1.0
-0.5
0.5
1.5
2.5
3.5
VCM (V)
4.5
5.5
IQ (µA)
VHYST (mV)
3.0
2.0
1.0
1.5
2.5
3.5
VDD (V)
4.5
5.5
FIGURE 2-15:
Input Hysteresis Voltage vs.
Supply Voltage vs. Temperature.
 2010 Microchip Technology Inc.
3.0
VDD = 1.8V
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
-0.5
0.0
1.0
2.0
3.0
IQ (µV/V)
4.0
5.0
Quiescent Current.
Sweep VIN+ ,VIN- = VDD/2
Sweep VIN- ,VIN+ = VDD/2
0.5
1.0
1.5
2.0
2.5
FIGURE 2-17:
Quiescent Current vs.
Common-Mode Input Voltage.
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
4.0
Temp +25°C
Avg. = 2.52 µA
StDev= 0.08 µA
VDD = 1.8V
850 units
VCM (V)
FIGURE 2-14:
Input Hysteresis Voltage vs.
Common-Mode Input Voltage.
5.0
Temp +125°C
Avg. = 3.51 µA
StDev= 0.07 µA
Temp +85°C
Avg. = 3 µA
StDev= 0.07 µA
FIGURE 2-16:
VDD = 5.5V
3.0
Temp -40°C
Avg. = 1.93 µA
StDev= 0.08 µA
0.0
2.1
FIGURE 2-13:
Input Hysteresis Voltage vs.
Common-Mode Input Voltage.
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
3.0
VDD = 5.5V
2.9
2.8
2.7
2.6
2.5
2.4
Sweep VIN- ,VIN+ = VDD/2
2.3
Sweep VIN+ ,V IN- = VDD/2
2.2
2.1
2.0
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VCM (V)
FIGURE 2-18:
Quiescent Current vs.
Common-Mode Input Voltage.
DS22269A-page 9
MCP65R41/6
4.5
4.0
4.0
3.5
3.0
2.5
3.0
2.0
1.5
1.0
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
0.5
0.0
0.0
1.0
2.0
14
3.0
VDD (V)
4.0
5.0
1.5
Sweep VIN+ ,VIN - = V DD/2
0.0
1.0
2.0
3.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0 dB Output Attenuation
VDD = 5.5V
VDD = 1.8V
4
2
0
1k
10k
100
1000
10000
Toggle Frequency (Hz)
VDD = 5.5V
VDD = 4.5V
VDD = 3.5V
VDD = 2.5V
VDD = 1.8V
FIGURE 2-23:
Up Voltage.
T A = -40°C
TA = +25°C
TA = +85°C
3.0
VDD (V)
4.0
8
9
10
Quiescent Current vs. Pull
VIN+ = VDD/2
VOUT (V)
4.0
3.0
2.0
VOUT
VIN-
0.0
5.0
6.0
FIGURE 2-21:
Short Circuit Current vs.
Supply Voltage vs. Temperature.
DS22269A-page 10
7
1.0
-120
2.0
6
5.0
-40
1.0
5
VDD = 5.5V
TA = +125°C
0.0
4
6.0
TA = +85°C
-80
3
7.0
40
0
2
VPU (V)
TA = -40°C
TA = +25°C
80
1
100k
100000
FIGURE 2-20:
Quiescent Current vs.
Toggle Frequency.
120
6.0
MCP65R46
0
10
5.0
FIGURE 2-22:
Quiescent Current vs.
Common-Mode Input Voltage.
IQ (µA)
8
4.0
VCM (V)
10
6
ISC (mA)
Sweep VIN- ,VIN+ = VDD/2
0.0
-1.0
6.0
12
IQ (µA)
2.0
0.5
18
100 mV Over-Drive
VCM = VDD/2
RL = Open
2.5
1.0
FIGURE 2-19:
Quiescent Current vs.
Supply Voltage vs. Temperature.
16
MCP65R46
VDD = 5.5V
3.5
IQ (mA)
IQ (µA)
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 100 k to VDD /2 (MCP65R41 only), RPull-Up = 2.74 k to VDD /2 (MCP65R46 only) and CL = 50 pF.
-1.0
Time (3 µs/div)
FIGURE 2-24:
No Phase Reversal.
 2010 Microchip Technology Inc.
MCP65R41/6
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 100 k to VDD /2 (MCP65R41 only), RPull-Up = 2.74 k to VDD /2 (MCP65R46 only) and CL = 50 pF.
3.0
2.5
2.0
VOL, VDD - VOH (V)
VOL, VDD - VOH (V)
VDD = 1.8V
VOL
TA = +125°C
TA = -40°C
1.5
1.0
VDD - VOH
TA = +125°C
TA = -40°C
0.5
0.0
2.0
4.0
6.0
IOUT (mA)
Occurrences (%)
FIGURE 2-25:
Output Current.
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
8.0
Output Headroom vs.
VDD - VOH
T A = +125°C
T A = -40°C
VOL
TA = +125°C
TA = -40°C
5
10
FIGURE 2-28:
Output Current.
20
tPLH
Avg. = 3.92 µs
StDev= 0.45 µs
850 units
60%
25
Output Headroom vs.
MCP65R46
tPLH
Avg. = 2.5 µs
StDev= 0.15 µs
850 units
70%
tPHL
Avg. = 3.6 µs
StDev= 0.19 µs
850 units
50%
40%
30%
20%
VDD= 1.8V
100 mV Over-Drive
VCM = VDD/2
10%
MCP65R41
0%
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
Prop. Delay (µs)
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
5
6
7
8
9
10
FIGURE 2-29:
Low-to-High and
High-to-Low Propagation Delays.
80%
VDD = 5.5V
100 mV Over-Drive
VCM = VDD/2
MCP65R46
70%
Occurrences (%)
tPHL
Avg. = 4.76 µs
StDev = 0.38 µs
850 units
4
Prop. Delay (µs)
FIGURE 2-26:
Low-to-High and
High-to-Low Propagation Delays.
Occurrences (%)
15
IOUT (mA)
80%
VDD = 1.8V
100 mV Over-Drive
VCM = VDD/2
t PHL
Avg. = 3.53 µs
StDev= 0.27 µs
850 units
VDD = 5.5V
0
10.0
Occurrences (%)
0.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
tPLH
Avg. = 4.97 µs
StDev = 0.41 µs
850 units
tPLH
Avg. = 3.1 µs
StDev = 0.16 µs
850 units
60%
50%
tPHL
Avg. = 4.9 µs
StDev = 0.26 µs
850 units
40%
30%
VDD = 5.5V
100 mV Over-Drive
VCM = VDD/2
20%
10%
MCP65R41
0%
0
1
2
3
4
5
6
7
Prop. Delay (µs)
8
FIGURE 2-27:
Low-to-High and
High-to-Low Propagation Delays.
 2010 Microchip Technology Inc.
9
10
0
1
2
3
4
5
6
7
8
9
10
Prop. Delay (µs)
FIGURE 2-30:
Low-to-High and
High-to-Low Propagation Delays .
DS22269A-page 11
MCP65R41/6
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 100 k to VDD /2 (MCP65R41 only), RPull-Up = 2.74 k to VDD /2 (MCP65R46 only) and CL = 50 pF.
8
tPLH
5
tPHL
4
3
2
5
4
tPLH
3
tPHL
2
0
0
0.00
0.50
1.00
VCM (V)
1.50
0.0
2.00
7
tPHL
6
Prop.
Prop.Delay
Delay(µs)
(ns)
tPLH
5
4
3
2
VDD = 5.5V
100 mV Over-Drive
1
1.5
2.0
8
MCP65R41
6
1.0
FIGURE 2-34:
Propagation Delay vs.
Common-Mode Input Voltage.
8
7
0.5
VCM (V)
FIGURE 2-31:
Propagation Delay vs.
Common-Mode Input Voltage.
Prop.
Prop.Delay
Delay(µs)
(ns)
6
1
1
MCP65R46
VDD = 5.5V
100 mV Over-Drive
tPLH
tPHL
5
4
3
2
1
0
0
0.0
1.0
2.0
3.0
VCM (V)
4.0
5.0
0.0
6.0
4.0
5.0
6.0
MCP65R46
VCM = VDD/2
Prop. Delay
Delay (µs)
(ns)
Prop.
12
tPHL, 100 mV Over-Drive
tPLH, 100 mV Over-Drive
8
3.0
25
VCM = VDD/2
tPHL, 10 mV Over-Drive
tPLH, 10 mV Over-Drive
16
2.0
FIGURE 2-35:
Propagation Delay vs.
Common-Mode Input Voltage.
20
MCP65R41
1.0
VCM (V)
FIGURE 2-32:
Propagation Delay vs.
Common-Mode Input Voltage.
Prop.Delay
Delay(µs)
(ns)
Prop.
MCP65R46
VDD = 1.8V
100 mV Over-Drive
7
Prop.
Prop.Delay
Delay(µs)
(ns)
Prop.
Prop.Delay
Delay(µs)
(ns)
6
8
MCP65R41
VDD = 1.8V
100 mV OverD i
7
4
20
tPHL, 10 mV Over-Drive
tPLH, 10 mV Over-Drive
15
10
tPHL, 100 mV Over-Drive
tPLH, 100 mV Over-Drive
5
0
0
1.5
FIGURE 2-33:
Supply Voltage.
DS22269A-page 12
2.5
3.5
VDD (V)
4.5
Propagation Delay vs.
5.5
1.5
2.5
3.5
4.5
5.5
VDD (V)
FIGURE 2-36:
Supply Voltage.
Propagation Delay vs.
 2010 Microchip Technology Inc.
MCP65R41/6
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 100 k to VDD /2 (MCP65R41 only), RPull-Up = 2.74 k to VDD /2 (MCP65R46 only) and CL = 50 pF.
10
100 mV Over-Drive
VCM = VDD/2
tPHL, VDD = 5.5V
tPHL, VDD = 1.8V
4
2
tPLH, VDD = 5.5V
tPLH, VDD = 1.8V
0
-25
0
25
50
75
Temperature (°C)
FIGURE 2-37:
Temperature.
100
125
4
2
tPLH , VDD = 5.5V
tPLH , VDD = 1.8V
Propagation Delay vs.
-50
100 mV Over-Drive
VCM = VDD/2
VDD = 5.5V, tPLH
VDD = 5.5V, tPHL
0.1
0.1
50
45
40
35
30
25
20
15
10
5
0
0.001
FIGURE 2-39:
Input Over-Drive.
100
125
Propagation Delay vs.
MCP65R46
100
10
VDD = 1.8V, tPLH
VDD = 5.5V, tPLH
VDD = 1.8V, tPHL
VDD = 5.5V, tPHL
11
Capacitive Load (nf)
10
10
Propagation Delay vs.
MCP65R41
VCM = VDD/2
tPLH, VDD = 5.5V
tPLH, VDD = 1.8V
0.01
0.1
Over-Drive (mV)
Propagation Delay vs.
0.1
FIGURE 2-41:
Capacitive Load.
tPHL, VDD = 5.5V
tPHL, VDD = 1.8V
 2010 Microchip Technology Inc.
1
0.01
100
100
Prop.
Delay
(µs)
Prop.
Delay
(ns)
FIGURE 2-38:
Capacitive Load.
25
50
75
Temperature (°C)
100 mV Over-Drive
VCM = VDD/2
VDD = 1.8V, tPLH
VDD = 1.8V, tPHL
1
0.01
0.01
0
1000
MCP65R41
Prop. Delay (µs)
10
-25
FIGURE 2-40:
Temperature.
100
Prop. Delay (µs)
tPHL , VDD = 5.5V
tPHL , VDD = 1.8V
6
0
-50
Prop.
Delay
(µs)
Prop.
Delay
(ns)
MCP65R46
8
Prop. Delay (ns)
8
6
100mV Over-Drive
VCM = VDD/2
MCP65R41
Prop. Delay (µs)
Prop.
Delay
(µs)
Prop.
Delay
(ns)
10
1
50
45 MCP65R46
40
35
30
25
20
15
10
5
0
0.001
1
10
Capacitive Load (nf)
100
Propagation Delay vs.
VCM = VDD/2
tPHL, VDD = 5.5V
tPHL, VDD = 1.8V
tPLH, VDD = 5.5V
tPLH, VDD = 1.8V
0.01
0.1
1
Over-Drive (mV)
FIGURE 2-42:
Input Over-Drive.
Propagation Delay vs.
DS22269A-page 13
MCP65R41/6
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 100 k to VDD /2 (MCP65R41 only), RPull-Up = 2.74 k to VDD /2 (MCP65R46 only) and CL = 50 pF.
60%
80%
MCP65R41
30%
20%
100 mV Over-Drive
VCM = VDD/2
10%
-0.5
0.0
0.5
Prop. Delay Skew (µs)
FIGURE 2-43:
90
VDD = 5.5V
Avg. = 1.81 µs
StDev = 0.14 µs
850 units
20%
65
60
VCM = -0.3V to VDD + 0.3V
VDD = 5.5V
Input Referred
0
25
50
75
Temperature (°C)
100
3
Propagation Delay Skew.
VCM = VSS
VDD = 1.8V to 5.5V
MCP65R46
80
CMRR
PSRR
75
70
65
VCM = -0.3V to VDD + 0.3V
VDD = 5.5V
Input Referred
60
55
50
50
-25
-1.5
0
1.5
Prop. Delay Skew (ns)
FIGURE 2-46:
85
55
-50
125
-25
0
25
50
75
100
125
Temperature (°C)
FIGURE 2-44:
Common-Mode Rejection
Ratio and Power Supply Rejection Ratio vs.
Temperature.
FIGURE 2-47:
Common-Mode Rejection
Ratio and Power Supply Rejection Ratio vs.
Temperature.
40%
40%
30%
VCM = VDD/2 to VDD+ 0.3V
Avg. = -0.02 mV/V
StDev = 0.54 mV/V
Occurrences (%)
VCM = -0.3V to VDD + 0.2V
Avg. = 0.23 mV/V
StDev = 0.68 mV/V
VDD = 1.8V
850 units
Occurrences (%)
30%
90
70
20%
40%
-3
MCP65R41
PSRR
CMRR
-50
50%
1.0
80
75
VDD = 1.8V
Avg. = 1.1 µs
StDev = 0.11 µs
850 units
60%
10%
Propagation Delay Skew.
VCM = VSS
VDD = 1.8V to 5.5V
85
MCP65R46
0%
0%
-1.0
CMRR/PSRR (dB)
Occurrences (%)
40%
100 mV Over-Drive
VCM = VDD/2
70%
VDD= 5.5V
Avg. = -0.21 µs
StDev = 0.07 µs
850 units
VDD= 1.8V
Avg. = -0.36 µs
StDev = 0.07 µs
850 units
CMRR/PSRR (dB)
Occurrences (%)
50%
VCM = -0.3V to VDD/2
Avg. = 0.5 mV/V
StDev = 1.14 mV/V
10%
0%
-5
-4
FIGURE 2-45:
Ratio.
DS22269A-page 14
-3
-2
-1 0
1
2
CMRR (mV/V)
3
4
5
Common-Mode Rejection
30%
VCM = -0.3V to VDD/2
Avg. = 0.05 mV/V
StDev = 0.46 mV/V
20%
VCM = VDD/2 to VDD+ 0.3V
Avg. = 0.02 mV/V
StDev = 0.25 mV/V
10%
VCM = -0.3V to VDD + 0.3V
Avg. = 0.03 mV/V
StDev = 0.3 mV/V
VDD = 5.5V
850 units
0%
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
CMRR (mV/V)
FIGURE 2-48:
Ratio.
Common-Mode Rejection
 2010 Microchip Technology Inc.
MCP65R41/6
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 100 k to VDD /2 (MCP65R41 only), RPull-Up = 2.74 k to VDD /2 (MCP65R46 only) and CL = 50 pF.
100
25%
10
Occurrences (%)
30%
IOS & IB (pA)
1000
IB
1
|IOS|
0.1
15%
10%
0%
25
50
75
100
Temperature (°C)
125
FIGURE 2-49:
Input Offset Current and
Input Bias Current vs. Temperature.
-500
VDD = 5.5V
IB @ TA = +125°C
100
IB @ TA = +85°C
VREF (V)
10
|IOS| @ TA = +125°C
1
0.1
|IOS| @ TA = +85°C
0.01
0.0
1.0
2.0
3.0
VCM (V)
4.0
5.0
0
250
PSRR (µV/V)
500
Power Supply Rejection
IREF = 0A
TA = +85°C
TA = +25°C
TA = -40°C
TA = +125°C
1.0 1.5 2.0
FIGURE 2-53:
2.5 3.0 3.5 4.0
VDD (V)
4.5 5.0
5.5
VREF vs. VDD.
2.45
IREF = 0A
2.43
VREF (V)
10m
1E+10
1m
1E+09
100µ
1E+08
10µ
1E+07
1µ
1E+06
100n
1E+05
10n
1E+04
1n
1E+03
100p
1E+02
10p
1E+01
1p
1E+00
-0.8
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
6.0
FIGURE 2-50:
Input Offset Current and
Input Bias Current vs. Common-Mode Input
Voltage vs. Temperature.
-250
FIGURE 2-52:
Ratio.
1000
IOS & IB (pA)
20%
5%
0.01
Input Current (A)
VCM = VSS
Avg. = -127.9 µV/V
StDev = 99.88 µV/V
3588 units
TA= -40°C
TA = +85°C
TA = +25°C
2.41
2.39
TA= +25°C
TA= +85°C
TA= +125°C
TA = -40°C
TA = +125°C
2.37
2.35
-0.6
-0.4
Input Voltage (V)
FIGURE 2-51:
Input Bias Current vs.
Input Voltage vs. Temperature.
 2010 Microchip Technology Inc.
-0.2
1.0
1.5 2.0
FIGURE 2-54:
2.5 3.0 3.5 4.0
VDD (V)
4.5 5.0
5.5
VREF vs. VDD.
DS22269A-page 15
MCP65R41/6
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
-0.5
VDD = 1.8V
TA = +85°C
TA = +25°C
VREF (V)
VREF (V)
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 100 k to VDD /2 (MCP65R41 only), RPull-Up = 2.74 k to VDD /2 (MCP65R46 only) and CL = 50 pF.
T A = -40°C
T A = +125°C
-0.3
-0.1
0.1
0.3
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
0.5
VDD = 1.8V
Temp. Co. = 27ppm
VDD = 5.5V
Temp. Co. = 22ppm
-50
-25
0
25
50
75
Temperature (°C)
IREF (µA)
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
-0.5
FIGURE 2-58:
VREF vs. IREF over
VREF vs. Temperature.
VDD = 5.5V
Temp. Co. = 23ppm
2.43
TA = +85°C
TA = +25°C
TA = -40°C
TA = +125°C
2.41
2.39
2.37
2.35
-0.3
-0.1
0.1
0.3
0.5
-50
-25
0
IREF (µA)
FIGURE 2-56:
Temperature.
VREF vs. IREF over
FIGURE 2-59:
20.0
2.45
15.0
VDD = 5.5V
2.43
25
50
75
Temperature (°C)
100
125
VREF vs. Temperature.
VREF = 1.21V
10.0
TA = +85°C
TA = +25°C
2.41
ISC (mA)
VREF (V)
125
2.45
VDD = 5.5V
VREF (V)
VREF (V)
FIGURE 2-55:
Temperature.
100
2.39
TA = -40°C
TA = +125°C
2.37
5.0
Sourcing
Sinking
0.0
-5.0
-10.0
-15.0
2.35
-0.5
-20.0
-0.3
-0.1
0.1
0.3
0.5
1.5
IREF (µA)
FIGURE 2-57:
Temperature.
DS22269A-page 16
VREF vs. IREF over
2.5
3.5
4.5
5.5
VDD (V)
FIGURE 2-60:
VDD.
Short Circuit Current vs.
 2010 Microchip Technology Inc.
MCP65R41/6
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 100 k to VDD /2 (MCP65R41 only), RPull-Up = 2.74 k to VDD /2 (MCP65R46 only) and CL = 50 pF.
Occurrences (%)
50%
VDD = 1.8V
VREF = 1.21V
Avg. = 0.06%
850 units
40%
VDD = 5.5V
VREF = 1.21V
Avg. = 0.02%
850 units
30%
20%
10%
0%
2.0%
1.2%
0.4%
-0.4%
-1.2%
-2.0%
VTOL (mV)
FIGURE 2-61:
Tolerance.
Occurrences (%)
50%
40%
Reference Voltage
VDD = 5.5V
VREF = 2.4V
Avg. = -0.22%
850 units
30%
20%
10%
0%
2.0%
1.2%
0.4%
-0.4%
-1.2%
-2.0%
VTOL (mV)
FIGURE 2-62:
Tolerance.
Reference Voltage
 2010 Microchip Technology Inc.
DS22269A-page 17
MCP65R41/6
NOTES:
DS22269A-page 18
 2010 Microchip Technology Inc.
MCP65R41/6
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP65R41/6
Symbol
Description
SOT23-6
3.1
1
OUT
Digital Output
2
VSS
Ground
3
VIN+
Non-inverting Input
4
VIN–
Inverting Input
5
VREF
Reference Voltage Output
6
VDD
Positive Power Supply
Analog Inputs
The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.2
Digital Outputs
The comparator outputs are CMOS/TTL compatible
push-pull and open-drain digital outputs. The push-pull
is designed to directly interface to a CMOS/TTL compatible pin while the open-drain output is designed for
level shifting and wired-OR interfaces.
3.3
Analog Outputs
3.4
Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 1.8V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These can share a
bulk capacitor with the nearby analog parts (within
100 mm), but it is not required.
The VREF Output pin outputs a reference voltage of
1.21V or 2.4V.
 2010 Microchip Technology Inc.
DS22269A-page 19
MCP65R41/6
NOTES:
DS22269A-page 20
 2010 Microchip Technology Inc.
MCP65R41/6
4.0
APPLICATIONS INFORMATION
The MCP65R41/6 family of Push-Pull and Open-Drain
output comparators are fabricated on Microchip’s stateof-the-art CMOS process. They are suitable for a wide
range of high-speed applications requiring low power
consumption.
4.1
Comparator Inputs
4.1.1
NORMAL OPERATION
The input stage of this family of devices uses three
differential input stages in parallel: one operates at low
input voltages, one at high input voltages, and one at
mid input voltages. With this topology, the input voltage
range is 0.3V above VDD and 0.3V below VSS, while
providing low offset voltage throughout the Common
mode range. The input offset voltage is measured at
both VSS - 0.3V and VDD + 0.3V to ensure proper
operation.
9
8
7
6
5
4
3
2
1
0
-1
-2
-3
30
VDD = 5.0V
25
20
VIN-
15
10
VOUT
5
0
-5
Hysteresis
-10
-15
-20
Input Voltage (10 mV/div)
Output Voltage (V)
The MCP65R41/6 family has internally-set hysteresis
VHYST that is small enough to maintain input offset
accuracy, and large enough to eliminate the output
chattering caused by the comparator’s own input noise
voltage ENI. Figure 4-1 depicts this behavior. Input
offset voltage (VOS) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points.
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize the input
bias current (IB). The input ESD diodes clamp the
inputs when trying to go more than one diode drop
below VSS. They also clamp any voltages that go too
far above VDD; their breakdown voltage is high enough
to allow a normal operation, and low enough to bypass
the ESD events within the specified limits.
VDD
Bond
Pad
VIN+ Bond
Pad
Input
Stage
100
2 00
300
40 0
500
600
700
800
900
VIN–
VSS Bond
Pad
FIGURE 4-2:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these comparators, the circuit they are connected to
limit the currents (and voltages) at the VIN+ and VIN–
pins (see Absolute Maximum Ratings†). Figure 4-3
shows the recommended approach to protect these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pin. Diodes D1 and D2 prevent the input
pin (VIN+ and VIN–) from going too far above VDD.
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
VDD
-25
0
Bond
Pad
VPU
-30
10 00
Time (100 ms/div)
D1
FIGURE 4-1:
The MCP65R41/6
Comparators’ Internal Hysteresis Eliminates
Output Chatter Caused by Input Noise Voltage.
RPU*
V1
+
R1
VOUT
–
D2
V2
R2
R3
VSS – (minimum expected V1)
R1 
2 mA
VSS – (minimum expected V2)
R2 
2 mA
* Pull-up resistor required for the MCP65R46 only.
FIGURE 4-3:
Inputs.
 2010 Microchip Technology Inc.
Protecting the Analog
DS22269A-page 21
MCP65R41/6
It is also possible to connect the diodes to the left of the
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistor then serves as an in-rush current limiter; the DC current into the input pins (VIN+ and
VIN–) should be very small.
4.3.1
NON-INVERTING CIRCUIT
Figure 4-4 shows a non-inverting circuit for singlesupply applications using just two resistors. The
resulting hysteresis diagram is shown in Figure 4-5.
VREF
A significant amount of current can flow out of the
inputs when the Common mode voltage (VCM) is below
ground (VSS); see Figure 4-3. The applications that are
high impedance may need to limit the usable voltage
range.
4.1.3
4.2
Push-Pull Output
The push-pull output is designed to be compatible with
CMOS and TTL logic, while the output transistors are
configured to give a rail-to-rail output performance.
They are driven with circuitry that minimizes any
switching current (shoot-through current from supplyto-supply) when the output is transitioned from high-tolow, or from low-to-high (see Figures 2-18 and 2-19 for
more information).
4.3
VREF
Externally Set Hysteresis
A greater flexibility in selecting the hysteresis (or the
input trip points) is achieved by using external resistors.
Hysteresis reduces output chattering when one input is
slowly moving past the other. It also helps in systems
where it is best not to cycle between high and low
states too frequently (e.g., air conditioner thermostatic
control). Output chatter also increases the dynamic
supply current.
RPU*
-
VOUT
PHASE REVERSAL
The MCP65R41/6 comparator family uses CMOS transistors at the input. They are designed to prevent
phase inversion when the input pins exceed the supply
voltages. Figure 2-3 shows an input voltage exceeding
both supplies with no resulting phase inversion.
VPU
VDD
+
VIN
R1
RF
* Pull-up resistor required for the MCP65R46 only.
FIGURE 4-4:
Non-inverting Circuit with
Hysteresis for Single-Supply.
VOUT
VDD
VOH
High-to-Low
VOL
VSS
VSS
Low-to-High
VIN
VTHL VTLH
VDD
FIGURE 4-5:
Hysteresis Diagram for the
Non-Inverting Circuit.
The trip points for Figures 4-4 and 4-5 are:
EXAMPLE 4-1:
R1 
 R1 

VTLH = V REF  1 + -------  – V OL ------- 
R
RF 

F
R1 
R 1 

VTHL = V REF  1 + -------  – V OH ------- 
R
RF 

F
Where:
VTLH = trip voltage from low to high
VTHL = trip voltage from high to low
DS22269A-page 22
 2010 Microchip Technology Inc.
MCP65R41/6
4.3.2
INVERTING CIRCUIT
Figure 4-6 shows an inverting circuit for single-supply
using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.
By using this simplified circuit, the trip voltage can be
calculated using the following equation:
EQUATION 4-1:
RF
 R 23 
VTHL = VOH  ----------------------- + V23  ----------------------


R
+
R
R
 23
23 + R F
F
VPU
VDD
VIN
RF
 R 23 
VTLH = V OL  ----------------------- + V23  ----------------------


R
+
R
R
 23
23 + R F
F
RPU*
VREF
VOUT
Where:
R2
VTLH = trip voltage from low to high
VTHL = trip voltage from high to low
RF
R3
Figures 2-23 and 2-26 can be used to determine the
typical values for VOH and VOL.
* Pull-up resistor required for the MCP65R46 only.
FIGURE 4-6:
Hysteresis.
Inverting Circuit with
4.4
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
VOUT
VDD
VOH
4.5
Low-to-High
4.5.1
High-to-Low
VIN
VOL
VSS
VSS
VTLH VTHL
FIGURE 4-7:
Inverting Circuit.
VDD
Hysteresis Diagram for the
In order to determine the trip voltages (VTHL and VTLH)
for the circuit shown in Figure 4-6, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VREF, as shown in Figure 4-8:
VPU
VDD
RPU*
-
Bypass Capacitors
Capacitive Loads
OUT PIN
Reasonable capacitive loads (e.g., logic gates) have
little impact on the propagation delay (see Figure 2-34).
The supply current increases with the increasing toggle
frequency (Figure 2-22), especially with higher
capacitive loads. The output slew rate and propagation
delay performance will be reduced with higher capacitive loads.
4.5.2
VREF PIN
The reference output is designed to interface to the
comparator input pins, either directly or with some
resistive network, such as voltage divider network, with
minimal capacitive load. The recommended capacitive
load is 200 pF (typical). Capacitive loads greater than
2000 pF may cause the VREF output to oscillate at
power up.
VOUT
+
VSS
V23
R23
Where:
RF
R2 R3
R 23 = ------------------R2 + R3
R3
V 23 = -------------------  V REF
R2 + R3
* Pull-up resistor required for the MCP65R46 only.
FIGURE 4-8:
Thevenin Equivalent Circuit.
 2010 Microchip Technology Inc.
DS22269A-page 23
MCP65R41/6
4.6
PCB Surface Leakage
VDD
In applications where the low input bias current is
critical, the Printed Circuit Board (PCB) surface
leakage effects need to be considered. Surface
leakage is caused by humidity, dust or other type of
contamination on the board. Under low humidity
conditions, a typical resistance between nearby traces
is 1012. A 5V difference would cause 5 pA of current
to flow. This is greater than the MCP65R41/6 family’s
bias current at +25°C (1 pA, typical).
The easiest way to reduce the surface leakage is to use
a guard ring around the sensitive pins (or traces). The
guard ring is biased at the same voltage as the
sensitive pin. An example of this type of layout is shown
in Figure 4-9.
IN-
IN+
VSS
VREF
MCP6041
VPU
VREF V
DD
RPU
VIN
R1
R2
VOUT
VREF
FIGURE 4-10:
Comparator.
4.7.2
MCP65R46
Precise Inverting
BISTABLE MULTI-VIBRATOR
A simple bistable multi-vibrator design is shown in
Figure 4-11. VREF needs to be between ground and the
maximum comparator internal VREF of 2.4V to achieve
oscillation. The output duty cycle changes with VREF.
R1
R2
VREF
VDD
VOUT
MCP65R41
Guard Ring
FIGURE 4-9:
Example Guard Ring Layout
for Inverting Circuit.
1.
2.
Inverting Configuration (Figures 4-6 and 4-9):
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
pad without touching the guard ring.
Non-inverting Configuration (Figure 4-4):
a) Connect the non-inverting pin (VIN+) to the
input pad without touching the guard ring.
b) Connect the guard ring to the inverting input
pin (VIN–).
4.7
C1
FIGURE 4-11:
4.7.3
R3
Bistable Multi-Vibrator.
OVER TEMPERATURE
PROTECTION CIRCUIT
The MCP65R41 device can be used as an over
temperature protection circuit using a thermistor. The
2.4V VREF can be used as stable reference to the
thermistor, the alert threshold and hysteresis threshold.
This is ideal for battery powered applications, where
the change in temperature and output toggle
thresholds would remain fixed as battery voltage
decays over time.
Typical Applications
VREF
4.7.1
PRECISE COMPARATOR
Some applications require a higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6041, a 600 nA low power and
14 kHz bandwidth op amp) to gain-up the input signal
before it reaches the comparator. Figure 4-10 shows
an example of this approach, which also level shifts to
VPU using the Open-Drain option, MCP65R46.
VREF
R4
VPU
RPU*
VREF
VOUT
Thermistor
R2
R3
FIGURE 4-12:
Circuit.
DS22269A-page 24
VDD
RF
* Pull-up resistor required for the
MCP65R46 only.
Over Temperature Alert
 2010 Microchip Technology Inc.
MCP65R41/6
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
6-Lead SOT-23
Example
Part Number
XXNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Code
MCP65R41T-1202E/CHY
HVNN
MCP65R41T-2402E/CHY
HWNN
MCP65R46T-1202E/CHY
HXNN
MCP65R46T-2402E/CHY
HYNN
HV25
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2010 Microchip Technology Inc.
DS22269A-page 25
MCP65R41/6
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
b
4
N
E
E1
PIN 1 ID BY
LASER MARK
1
2
3
e
e1
D
A
A2
c
φ
L
A1
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
6
Pitch
e
0.95 BSC
Outside Lead Pitch
e1
1.90 BSC
Overall Height
A
0.90
–
Molded Package Thickness
A2
0.89
–
1.45
1.30
Standoff
A1
0.00
–
0.15
Overall Width
E
2.20
–
3.20
Molded Package Width
E1
1.30
–
1.80
Overall Length
D
2.70
–
3.10
Foot Length
L
0.10
–
0.60
Footprint
L1
0.35
–
0.80
Foot Angle
0°
–
30°
Lead Thickness
c
0.08
–
0.26
Lead Width
b
0.20
–
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-028B
DS22269A-page 26
 2010 Microchip Technology Inc.
MCP65R41/6
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010 Microchip Technology Inc.
DS22269A-page 27
MCP65R41/6
NOTES:
DS22269A-page 28
 2010 Microchip Technology Inc.
MCP65R41/6
APPENDIX A:
REVISION HISTORY
Revision A (December 2010)
• Original Release of this Document.
 2010 Microchip Technology Inc.
DS22269A-page 29
MCP65R41/6
NOTES:
DS22269A-page 30
 2010 Microchip Technology Inc.
MCP65R41/6
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
XX
-XX
X
/XX
Examples:
a) MCP65R41T-1202E/CHY:
Device Tape and Reference Reference Temperature Package
Range
Tolerance
Voltage
b) MCP65R41T-2402E/CHY:
Device
MCP65R41T: Push-pull Output Comparator
MCP65R46T: Open-drain Output Comparator
Reference Voltage
12
24
= 1.21V (typical) Initial Reference Voltage
= 2.4V (typical) Initial Reference Voltage
a) MCP65R46T-1202E/CHY:
Reference Tolerance 02
= 2% Reference Voltage Tolerance
b) MCP65R46T-2402E/CHY:
Temperature Range
E
= -40C to +125C
Package
CHY
=
(Extended)
Push-Pull Output,
1.2VREF,
Tape and Reel,
6LD SOT-23 Pkg.
Push-Pull Output,
2.4VREF,
Tape and Reel,
6LD SOT-23 Pkg.
Open-Drain Output,
1.2VREF,
Tape and Reel,
6LD SOT-23 Pkg.
Open-Drain Output,
2.4VREF,
Tape and Reel,
6LD SOT-23 Pkg.
Plastic Small OutlineTransistor, 6-Lead
 2010 Microchip Technology Inc.
DS22269A-page 31
MCP65R41/6
NOTES:
DS22269A-page 32
 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-781-1
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2010 Microchip Technology Inc.
DS22269A-page 33
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Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
08/04/10
DS22269A-page 34
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