TI BQ2014H Low-cost nicd/nimh gas gauge ic Datasheet

Preliminary
bq2014H
Low-Cost NiCd/NiMH Gas Gauge IC
Features
General Description
➤ Accurate measurement of available capacity in NiCd or NiMH
batteries
T he b q 2 0 1 4 H N iC d / N iM H G a s
Gauge IC is intended for batterypack or in-system installation to
maintain an accurate record of
available battery capacity. The IC
monitors a voltage drop across a
sense resistor connected in series
between the negative battery termina l a n d g r ou n d t o d e t e r m i n e
charge and discharge activity of
the battery. Compensations for battery temperature, self-discharge,
and rate of discharge are applied to
the charge counter to provide available capacity information across a
wide range of operating conditions.
Battery capacity is automatically recalibrated, or “learned,” in the
course of a discharge cycle from full
to empty.
➤ Low-cost battery management solution for pack integration
-
As little as 1 2 square inch of
PCB for complete circuit
-
Low operating current (120µA
typical)
-
Less than 100nA of data
retention current
➤ High-speed (5kb/s) single-wire
communication interface (HDQ
bus) for critical battery
parameters
➤ Communication with an external
charge controller such as the
bq2004
➤ Direct drive of remaining capacity
LEDs
bidirectional serial link to an external processor (common ground). The
5kb/s HDQ bus interface reduces
communications overhead in the
external microcontroller.
Internal registers include available
capacity and energy, temperature,
voltage and current, and battery
status. The external processor may
also overwrite some of the bq2014H
gas gauge data registers.
The bq2014H can operate from the
batteries in the pack. The REF output and an external transistor allow
a simple, inexpensive voltage regulator to supply power to the circuit
from the cells.
Nominal available capacity may be
directly indicated using a fivesegment LED display. The bq2014H
also supports a simple single-line
➤ Automatic rate and temperature
compensation of measurements
➤ 16-pin narrow SOIC
Pin Connections
Pin Names
LCOM
LCOM
1
16
VCC
SEG1/PROG1
2
15
REF
SEG2/PROG2
3
14
NC
SEG3/PROG3
4
13
HDQ
SEG4/PROG4
5
12
RBI
SEG5/PROG5
6
11
SB
DONE
7
10
DISP
VSS
8
9
SR
16-Pin Narrow SOIC
PN20140H..eps
LED common output
SEG1/PROG1 LED segment 1/
program 1 input
SEG2/PROG2 LED segment 2/
program 2 input
SEG3/PROG3 LED segment 3/
program 3 input
SEG4/PROG4 LED segment 4/
program 4 input
SEG5/PROG5 LED segment 5/
program 5 input
DONE
Charge complete
input
SLUS030–JUNE 1999
1
VSS
System ground
SR
Sense resistor input
DISP
Display control input
SB
Battery sense input
RBI
Register backup input
HDQ
Serial communications
input/output
NC
No connect
REF
Voltage reference output
VCC
Supply voltage
bq2014H Preliminary
DISP
Pin Descriptions
LCOM
DISP high disables the LED display. DISP
tied to VCC allows PROGX to connect directly to VCC or VSS instead of through a
pull-up or pull-down resistor. DISP floating
allows the LED display to be active during
charge. DISP low activates the display. See
Table 1.
LED common output
Open-drain output that switches V CC to
source current for the LEDs. The switch is
off during initialization to allow reading of
the soft pull-up or pull-down program resistors. LCOM is also high impedance when the
display is off.
SEG1–
SEG5
SB
RBI
Programmed full count selection inputs
(dual function with SEG1–SEG2)
HDQ
NC
No connect
REF
Voltage reference output
Self-discharge rate selection (dual function with SEG5)
REF provides a voltage reference output for
an optional microregulator.
Three-level input pin that defines the
self-discharge and battery-compensation factors as shown in Table 1.
DONE
VCC
Charge complete input
Communicates the status of an external
charge-controller such as the bq2004 FastCharge IC to the bq2014H. Note: This pin
must be pulled down to VSS using a 200kΩ
resistor.
VSS
Ground
SR
Sense resistor input
Serial communication input/output
This is the open-drain bidirectional communications port.
Power gauge scale selection inputs (dual
function with SEG3–SEG4)
Three-level input pins that define the scale
factor described in Table 2.
PROG5
Register backup input
Provides backup potential to the bq2014H registers while VCC ≤ 3V. A storage capacitor or
a battery can be connected to RBI.
Three-level input pins that define the programmed full count (PFC) thresholds described in Table 2.
PROG3–
PROG4
Secondary battery input
Monitors the battery cell-voltage potential
through a high-impedance resistive divider
network for end-of-discharge voltage (EDV)
t h r es h old s a n d f or b a t t er y - r em ov e d
detection.
LED display segment outputs (dual function with PROG1–PROG5)
Outputs that each may activate an LED to
sink the current sourced from LCOM.
PROG1–
PROG2
Display control input
The voltage drop (VSR) across the sense resistor RS is monitored and integrated over
time to interpret charge and discharge activity. VSR < VSS indicates discharge, and VSR >
VSS indicates charge. The effective voltage
drop, VSRO, as seen by the bq2014H is VSR +
VOS .
2
Supply voltage input
Preliminary bq2014H
capacity to drive the LED display. In addition, the
bq2014H estimates the available energy using the average battery voltage during the discharge cycle and remaining compensated available capacity.
Functional Description
General Operation
Figure 1 shows a typical battery pack application of the
bq2014H using the LED display capability as a chargestate indicator. The bq2014H is configured to display
capacity in relative display mode. The relative display
mode uses the last measured discharge capacity of the
battery as the battery “full” reference. A push-button
display feature is available for momentarily enabling
the LED display.
The bq2014H determines battery capacity by monitoring the amount of current input to or removed
from a rechargeable battery. The bq2014H measures discharge and charge currents, measures battery voltage, estimates self-discharge, monitors the
battery for low battery-voltage thresholds, and compensates for temperature and charge/discharge rate.
Current measurement is made by monitoring the
voltage across a small-value series sense resistor between the negative battery terminal and ground.
The bq2014H compensates the nominal available
capacity register for discharge rate and temperature and reports the compensated available
capacity. The bq2014H uses the compensated available
The bq2014H monitors the charge and discharge currents as a voltage across a sense resistor. (See RS in Figure 1.) A filter between the negative battery terminal
and the SR pin is required.
R1
bq2014H
Gas-Gauge IC
Q1
ZVNL110A
REF
C1
LCOM
SEG1/PROG1
VCC
SB
VCC
SEG2/PROG2
C2
RB2
SEG3/PROG3
DISP
SEG4/PROG4
SR
100K
0.1µF
SEG5/PROG5
DONE
RB1
VCC
RS
VSS
RBI
1M
HDQ
See note 4
Notes:
1.
Charger
Indicates optional.
2. Programming resistors (5 max.) and ESD-protection diodes are not shown.
Load
3. RC on SR is required.
4. A series diode is required on RBI if the bottom series cell is used as the backup source.
If the cell is used, the backup capacitor is not required, and the anode is connected to the
positive terminal of the cell.
F2014HBP.eps
Figure 1. Battery Pack Application Diagram—LED Display
3
bq2014H Preliminary
Voltage Thresholds
In conjunction with monitoring VSR for charge/discharge
currents, the bq2014H monitors the battery potential
through the SB pin for the end-of-discharge voltage (EDV)
thresholds.
TMP (hex)
Temperature Range
0x
< -30°C
1x
-30°C to -20°C
The EDV threshold levels are used to determine when
the battery has reached an “empty” state.
2x
-20°C to -10°C
The EDV thresholds for the bq2014H are programmable
with the default values fixed as follows:
3x
-10°C to 0°C
EDV1 (first) = 0.76V
4x
0°C to 10°C
5x
10°C to 20°C
6x
20°C to 30°C
7x
30°C to 40°C
8x
40°C to 50°C
9x
50°C to 60°C
Ax
60°C to 70°C
Bx
70°C to 80°C
Cx
> 80°C
EDVF (final) = EDV1 - 0.025V = 0.735V
The battery voltage divider (RB1 and RB2 in Figure 1) is
used to scale these values to the desired threshold.
If VSB is below either of the two EDV thresholds, the associated flag is latched and remains latched, independent of VSB, until the next valid charge.
EDV monitoring is disabled if the discharge rate is
greater than 2C (OVLD Flag = 1) and resumes 1 2 second
after the rate falls below 2C. The VSB value is available
over the serial port.
RBI Input
The RBI input pin is used with a storage capacitor or external supply to provide backup potential to the internal
bq2014H registers when VCC drops below 3.0V. VCC is
output on RBI when VCC is above 3.0V. If using an external supply (such as the bottom series cell) as the backup
source, an external diode is required for isolation.
Layout Considerations
Reset
The bq2014H can be reset by removing VCC and grounding the RBI pin for 15 seconds or by commands over the
serial port. The serial port reset command sequence requires writing 00h to register PPFC (address = 1Eh) and
then writing 00h to register LMD (address = 05h).
The bq2014H measures the voltage differential between
the SR and VSS pins. VOS (the offset voltage at the SR
pin) is greatly affected by PC board layout. For optimal
results, the PC board layout should follow the strict rule
of a single-point ground return. Sharing high-current
ground with small-signal ground causes undesirable
noise on the small-signal nodes. Additionally:
Temperature
■
The bq2014H internally determines the temperature in
10°C steps centered from approximately -35°C to +85°C.
The temperature steps are used to adapt charge and discharge rate compensations, self-discharge counting, and
available charge display translation.
The capacitors (C1 and C2) should be placed as
close as possible to the VCC and SB pins,
respectively, and their paths to VSS should be as
short as possible. A high-quality ceramic capacitor
of 0.1µF is recommended for VCC.
■
The temperature range is available over the serial port
in 10°C increments, as shown in the following table
The sense-resistor capacitor should be placed as close
as possible to the SR pin.
■
The sense resistor (RS) should be as close as possible to
the bq2014H.
4
Preliminary bq2014H
The battery's initial capacity equals the Programmed
Full Count (PFC) shown in Table 2. Until LMD is updated, NAC counts up to but not beyond this threshold
during subsequent charges. This approach allows the
gas gauge to be charger-independent and compatible
with any type of charge regime.
Gas Gauge Operation
The operational overview diagram in Figure 2 illustrates
the operation of the bq2014H. The bq2014H accumulates a measure of charge and discharge currents, as
well as an estimation of self-discharge. The accumulated charge and discharge currents are adjusted for
temperature and rate to provide the indication of compensated available capacity to the host system or user.
1.
LMD is the last measured discharge capacity of the
battery. On initialization (application of VCC or battery replacement), LMD = PFC. During subsequent
discharges, the LMD is updated with the latest
measured capacity in the Discharge Count Register
representing a discharge from full to below EDV1.
A qualified discharge is necessary for a capacity
transfer from the DCR to the LMD register. The
LMD also serves as the 100% reference threshold
used by the relative display mode.
The main counter, Nominal Available Capacity (NAC),
represents the available battery capacity at any given
time. Battery charging increments the NAC register,
while battery discharging and self-discharge decrement
the NAC register and increment the DCR (Discharge
Count Register).
The Discharge Count Register is used to update the Last
Measured Discharge (LMD) register only if a complete
battery discharge from full to empty occurs without any
partial battery charges. Therefore, the bq2014H adapts
its capacity determination based on the actual conditions of discharge.
Inputs
Last Measured Discharge (LMD) or learned
battery capacity:
Charge
Current
Discharge
Current
Rate and
Temperature
Compensation
Temperature
Compensation
+
Main Counters
and Capacity
Reference (LMD)
+
-
Nominal
Available
Charge
(NAC)
Last
Measured
< Discharged
(LMD)
Rate and
Temperature
Compensation
Outputs
Self-Discharge
Timer
Compensated
Available Charge
LED Display, etc.
Discharge
Count
Qualified Register
(DCR)
Transfer
Temperature Step,
Other Data
Serial
Port
Figure 2. Operational Overview
5
+
F2014HOO.eps
bq2014H Preliminary
2.
Programmed Full Count (PFC) or initial battery capacity:
Example: Selecting a PFC Value
Given:
The initial LMD and gas gauge rate values are programmed by using PROG1–PROG4. The bq2014H
is configured for a given application by selecting a
PFC value from Table 2. The correct PFC may be
determined by multiplying the rated battery capacity in mAh by the sense resistor value:
Sense resistor = 0.05Ω
Number of cells = 10
Capacity = 3500mAh, NiMH
Current range = 50mA to 1A
Relative display mode
Self-discharge = NAC 47 per day @ 25°C
Voltage drop over sense resistor = 2.5mV to 50mV
Nominal discharge voltage = 1.2V
Battery capacity (mAh) * sense resistor (Ω) =
PFC (mVh)
Therefore:
Selecting a PFC slightly less than the rated capacity provides a conservative capacity reference until
the bq2014H “learns” a new capacity reference.
3500mAh * 0.05Ω = 175mVh
Table 1. Self-Discharge and Capacity Compensation
Pin
Connection
PROG5
Self-Discharge Rate
DISP
Display State
H
Disabled
LEDs disabled
Z
NAC
L
NAC
64
LEDs on when charging
47
LEDs on for 4s
Table 2. bq2014H Programmed Full Count mVh, VSR Gain Selections
PROGx
1
2
Programmed
Full
Count
(PFC)
PROG4 = L
PROG3 = H
PROG4 = Z or H
PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L
Units
-
-
-
SCALE =
1/80
H
H
49152
614
307
154
76.8
38.4
19.2
mVh
H
Z
45056
563
282
141
70.4
35.2
17.6
mVh
H
L
40960
512
256
128
64.0
32.0
16.0
mVh
Z
H
36864
461
230
115
57.6
28.8
14.4
mVh
Z
Z
33792
422
211
106
53.0
26.4
13.2
mVh
Z
L
30720
384
192
96.0
48.0
24.0
12.0
mVh
L
H
27648
346
173
86.4
43.2
21.6
10.8
mVh
L
Z
25600
320
160
80.0
40.0
20.0
10.0
mVh
L
L
22528
282
141
70.4
35.2
17.6
8.8
mVh
90
45
22.5
11.25
5.6
2.8
mV
VSR equivalent to 2
counts/s (nom.)
SCALE =
1/160
SCALE =
1/320
SCALE =
1/640
SCALE =
1/1280
SCALE =
1/2560
mVh/
count
6
Preliminary bq2014H
capacity reference in battery chemistries with
sloped voltage profiles during discharge. SAE may
be converted to an mWh value using the following
formula:
Select:
PFC = 27648 counts or 173mVh
PROG1 = low
PROG2 = high
PROG3 = float
PROG4 = low
PROG5 = low
E(mWh) = (SAEH ∗ 256 + SAEL) ∗
1.2 ∗ SCALE ∗ (RB1 + RB2)
RS ∗ RB2
The initial full battery capacity is 173mVh
(3460mAh) until the bq2014H “learns” a new capacity with a qualified discharge from full to EDV1.
3.
where RB1, RB2, and RS are resistor values in
ohms, as shown in Figure 1. SCALE is the selected
scale from Table 2.
Nominal Available Capacity (NAC):
6. Compensated Available Capacity (CACT)
NAC counts up during charge to a maximum value
of LMD and down during discharge and self-discharge to 0. NAC is reset to 0 on initialization and
on the first valid charge following discharge to
EDV1. To prevent overstatement of charge during
periods of overcharge, NAC stops incrementing
when NAC = LMD or 0.94 ∗ LMD if T < 0°C.
4.
CACT counts similarly to NAC, but contains the
available capacity compensated for discharge rate
and temperature.
Charge Counting
Charge activity is detected based on a positive voltage
on the SR input. If charge activity is detected, the
bq2014H increments NAC at a rate proportional to VSR
and, if enabled, activates the LED display.
Discharge Count Register (DCR):
The DCR counts up during discharge independent
of NAC and could continue increasing after NAC
has decremented to 0. Prior to NAC = 0 (empty
battery), both discharge and self-discharge increment the DCR. After NAC = 0, only discharge
increments the DCR. The DCR resets to 0 when
NAC ≥ 0.94 ∗ LMD and a discharge is detected. The
DCR does not roll over but stops counting when it
reaches FFh.
The bq2014H counts charge activity when the voltage at
the SR input (V SRO ) exceeds the minimum charge
threshold (VSRQ). A valid charge is detected when NAC
has been updated twice without discharging or reaching
the digital magnitude filter time-out. Once a valid
charge is detected, charge counting continues until VSR,
including offset, falls below VSRQ.
Discharge Counting
The DCR value becomes the new LMD value on the
first charge after a valid discharge to VEDV1 if all
the following conditions are met:
■
No valid charge initiations (charges greater than
2 NAC updates where VSRO > VSRQ) occurred
during the period between NAC ≥ 0.94 ∗ LMD and
EDV1.
■
The self-discharge is less than 6.25% of NAC.
■
Discharge activity is indicated by a negative voltage on
the SR input. All discharge counts where VSRO is less
than the minimum discharge threshold (VSRD) cause
the NAC register to decrement and the DCR to
increment.
Self-Discharge Counting
The bq2014H continuously decrements NAC and increments DCR for self-discharge on the basis of time and temperature.
The temperature is ≥ 0°C when the EDV1 level
is reached during discharge.
■
The discharge begins when NAC ≥ 0.94 ∗ LMD.
■
VDQ is set.
Charge/Discharge Current
The bq2014H current-scale registers, VSRH and VSRL,
can be used to determine the battery charge or discharge current. See the Current Scale Register description for details.
The valid discharge flag (VDQ) indicates whether
the present discharge is valid for LMD update. If
the DCR update value is less than 0.94 ∗ LMD,
LMD will only be modified by 0.94 ∗ LMD. This prevents invalid DCR values from corrupting LMD.
5.
Scaled Available Energy (SAE):
SAE is useful in determining the available energy
within the battery, and may provide a more useful
7
bq2014H Preliminary
Count Compensations
Self-Discharge Compensation
The self-discharge compensation is programmed for a
nominal rate of 1 64 * NAC per day, 1 47 ∗ NAC per day, or
disabled. This is the rate for a battery within the
20°C–30°C temperature range (TMPGG = 6x). This rate
varies across 8 ranges from <10°C to >70°C, doubling
Charge Compensation
Two charge efficiency compensation factors are used for
trickle and fast charge. Trickle charge is defined as a rate
of charge < C/3. The compensation defaults to the fastcharge factor until the actual charge rate is determined.
Temperature adapts the charge rate compensation factors over two ranges between nominal and hot temperatures. The compensation factors are shown below.
Charge
Temperature
Trickle-Charge
Compensation
< 40°C
> 40°C
Table 3. Self-Discharge Compensation
Temperature
Step
Fast-Charge
Compensation
0.81
0.94
0.75
0.88
Compensated Available Capacity
NAC is adjusted for rate of discharge and temperature
to derive the CACD and CACT values.
Corrections for the rate of discharge are made by adjusting an internal discharge compensation factor. The discharge factor is based on the discharge rate. This compensation is applied to NAC to derive the value in the
CACD register.
Rate Efficiency
Factor
< 2C
100%
> 2C
95%
< 10°C
NAC
10–20°C
NAC
20–30°C
NAC
30–40°C
NAC
40–50°C
NAC
50–60°C
NAC
60–70°C
NAC
> 70°C
NAC
256
128
64
32
16
8
4
2
PROG5 = L
NAC
188
NAC
NAC
NAC
NAC
NAC
NAC
NAC
94
47
23 .5
11 .8
5 .88
2 .94
1 .47
with each higher temperature step (10°C). See Table 3.
Digital Magnitude Filter
The bq2014H has a digital filter to eliminate charge and
discharge counting below a set threshold. The threshold
for both VSRD and VSRQ is 250µV.
The compensation factors during discharge are:
Approximate
Discharge Rate
Typical Rate
PROG5 = Z
Temperature compensation during discharge also takes
place. At lower temperatures, the compensation factor
increases by 0.05 for each 10°C temperature range below
10°C. This compensation is applied to CACD to derive
the value in the CACT register. The temperature compensation factor follows the equation
Temperature Efficiency Factor = 1.00 - (0.05 ∗ N)
where N = number of 10°C steps below 10°C.
For example,
T > 10°C: Nominal compensation, N = 0
0°C < T < 10°C: N = 1 (temperature efficiency = 95%)
-10°C < T < 0°C: N = 2 (temperature efficiency = 90%)
-20°C < T < -10°C: N = 3 (temperature efficiency = 85%)
-20°C < T < -30°C: N = 4 (temperature efficiency = 80%)
8
Preliminary bq2014H
Table 6. bq2014H Current-Sensing Errors
Symbol
Parameter
Typical
INL
Integrated non-linearity
error
±2
INR
Integrated nonrepeatability error
±1
Maximum
Units
Notes
±4
%
Add 0.1% per °C above or below 25°C
and 1% per volt above or below 4.25V.
±2
%
Measurement repeatability given
similar operating conditions.
Done Input
Error Summary
A charge-control IC or a microcontroller uses the DONE
input to communicate charge status to the bq2014H.
When the DONE input is asserted high on charge completion, the bq2014H sets NAC = LMD and VDQ = 1.
The DONE input should be maintained high as long as
the charge controller or microcontroller keeps the batteries full; otherwise, the pin should be held low.
Capacity Inaccurate
The LMD is susceptible to error on initialization or if no
updates occur. On initialization, the LMD value includes the error between the programmed full capacity
and the actual capacity. This error is present until a
valid discharge occurs and LMD is updated. (See the
DCR description.) The other cause of LMD error is battery wear-out. As the battery ages, the measured capacity must be adjusted to account for changes in actual
battery capacity.
Communicating with the bq2014H
The bq2014H includes a simple single-pin (HDQ plus return) serial data interface. A host processor uses the interface to access various bq2014H registers. Battery
characteristics may be easily monitored by adding a single contact to the battery pack. The open-drain HDQ
pin on the bq2014H should be pulled up by the host system, or may be left floating if the serial interface is not
used.
A Capacity Inaccurate counter (CPI) is maintained and
incremented each time a valid charge occurs (qualified
by NAC; see the CPI register description). It is reset
whenever LMD is updated from the DCR. The counter
does not wrap around but stops counting at 255. The capacity inaccurate flag (CI) is set if LMD has not been updated following 64 valid charges.
The interface uses a command-based protocol, in which
the host processor sends a command byte to the
bq2014H. The command directs the bq2014H to either
store the next eight bits of data received to a register
specified by the command byte or output the eight bits
of data specified by the command byte. (See Figure 4.)
Current-Sensing Error
Table 6 shows the non-linearity and non-repeatability
errors associated with the bq2014H current sensing.
Table 7 illustrates the current-sensing error as a function of VOS. A digital filter prevents charge and discharge counts to the NAC register when VSRO is between VSRQ and VSRD.
The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of
eight bits that have a maximum transmission rate of
5K bits/sec. The least-significant bit of a command or
data byte is transmitted first. The protocol is simple
enough that it can be implemented by most host processors using either polled or interrupt processing. Data
input from the bq2014H may be sampled using the
pulse-width capture timers available on some microcontrollers.
Table 7. VOS-Related Current Sense Error
(Current = 1A)
VOS
(µV)
50
100
150
180
20
0.25
0.50
0.75
0.90
Sense Resistor
50
100
0.10
0.05
0.20
0.10
0.30
0.15
0.36
0.18
mΩ
%
%
%
%
If a communication error occurs (e.g., tCYCB > 250µs),
the bq2014H should be sent a BREAK to reinitiate the
serial interface. A BREAK is detected when the HDQ
pin is driven to a logic-low state for a time, tB or greater.
The HDQ pin should then be returned to its normal
ready-high logic state for a time, tBR. The bq2014H is
now ready to receive a command from the host processor.
9
bq2014H Preliminary
The return-to-one data bit frame consists of three distinct sections:
1.
The first section is used to start the transmission
by either the host or the bq2014H taking the HDQ
pin to a logic-low state for a period, tSTRH;B.
2.
The next section is the actual data transmission,
where the data should be valid by a period, tDSU;B,
after the negative edge used to start communication. The data should be held for a period, tDH;DV,
to allow the host or bq2014H to sample the data bit.
3.
The final section is used to stop the transmission by
returning the HDQ pin to a logic-high state by at
least a period, tSSU;B, after the negative edge used
to start communication. The final logic-high state
should be until a period tCYCH;B, to allow time to ensure that the bit transmission was stopped properly. The timings for data and break communication
are given in the serial communication timing specification and illustration sections.
Communication with the bq2014H is always performed
with the bit transmitted first. Figure 5 shows an example
of a communication sequence to read the bq2014H NACH
register.
The bq2014H latches the command code when eight
valid command bits have been received by the bq2014H.
The command code contains two fields:
Command address
The following eight bits should be written
to the register specified by the address portion of command code.
Command Code Bits
7
-
6
5
AD6 AD5
4
3
2
1
0
AD4
AD3
AD2
AD1
AD0
(LSB)
Primary Status Flags Register (FLGS1)
The FLGS1 register (address = 01h) contains the primary bq2014H flags.
The charge status flag (CHGS) is asserted when a
valid charge rate is detected. Charge rate is deemed
valid when VSRO > VSRQ. A VSRO of less than VSRQ or
discharge activity clears CHGS.
The CHGS values are
The W/R bit of the command code is used to select whether
the received command is for a read or a write function:
7
6
5
4
3
2
1
0
CHGS
-
-
-
-
-
-
-
where CHGS is
Command Code
■
1
FLGS1 Bits
The bq2014H status registers are listed in Table 8 and described below. All registers are Read/Write in the bq2014H.
Caution: When writing to bq2014H registers ensure
that proper data are written. A write-verify read is
recommended.
W/R bit
The bq2014H outputs the requested register contents specified by the address portion of command code.
The lower 7-bit field of the command code contains the
address portion of the register to be accessed:
bq2014H Command Code and
Registers
■
0
0
Either discharge activity detected or VSRO
≤ VSRQ
1
VSRO > VSRQ
The battery replaced flag (BRP) is asserted whenever
the bq2014H is reset either by application of VCC or by
a serial port command. BRP is reset when either a valid
charge action increments NAC to be equal to LMD, or a
valid charge action is detected after the EDV1 flag is asserted. BRP = 1 signifies that the device has been reset.
The BRP values are
FLGS1 Bits
The W/R values are
Command Code Bits
7
6
5
4
3
2
1
0
W/R
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
-
BRP
-
-
-
-
-
-
where BRP is
0
Battery is charged until NAC = LMD or discharged until the EDV1 flag is asserted
1
bq2014H is reset
where W/R is
4-10
Preliminary bq2014H
Send Host to bq-HDQ
Send Host to bq-HDQ or
Receive from bq-HDQ
Data
CDMR
R/W
MSB
Bit7
Address
Break
tRR
LSB
Bit0
tRSPS
Start-bit
Address-Bit/
Data-Bit
Stop-Bit
TD201807.eps
Figure 4. bq2014H Communication Example
Written by Host to bq2014H
CMDR = 03h
LSB
MSB
Break 1 1 0 0 0 0 0 0
Received by Host to bq2014H
NACH = 65h
LSB
MSB
1 01 0 011 0
HDQ
tRSPS
TD2014Hcom.eps
Figure 5. Typical Communication with the bq2014H
11
bq2014H Preliminary
Table 8. bq2014H Command and Status Registers
Symbol
Register Name
Loc. Read/ Control Field
(hex) Write 7(MSB)
6
5
4
3
2
1
0(LSB)
Primary status flags
FLGS1
01h
R
CHGS
BRP
0
CI
VDQ
1
EDV1 EDVF
register
TMP
Temperature register
02h
R
TMP3 TMP2 TMP1 TMP0
GG3
GG2
GG1
GG0
Nominal available capacNACH
03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0
ity high byte register
Nominal available
NACL
17h R/W NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0
capacity low byte register
Battery identification
BATID
04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0
register
Last measured
LMD
05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0
discharge register
Secondary status flags
FLGS2
06h
R
RSVD
DR2
DR1
DR0 ENINT VQ
RSVD OVLD
register
Program pin pull-down
PPD
07h
R
RSVD RSVD RSVD PPD5 PPD4 PPD3 PPD2 PPD1
register
Program pin pull-up
PPU
08h
R
RSVD RSVD RSVD PPU5 PPU4 PPU3 PPU2 PPU1
register
Capacity
CPI
09h R/W
CPI7
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
CPI0
inaccurate count register
Battery voltage
VSB
0bh
R
VSB7
VSB6 VSB5 VSB4 VSB3 VSB2 VSB1
VSB0
register
End-of-discharge threshVTS
0ch R/W VTS7
VTS6
VTS5
VTS4 VTS3 VTS2 VTS1
VTS0
old select register
Temperature and disCACT charge rate compensated 0dh R/W CACT7 CACT6 CACT5 CACT4 CACT3 CACT2 CACT1 CACT0
available capacity
Discharge rate comCACD pensated available
0eh R/W CACD7 CACD6 CACD5 CACD4 CACD3 CACD2 CACD1 CACD0
capacity
Scaled available energy
SAEH
0fh
R
SAEH7 SAEH6 SAEH5 SAEH4 SAEH3 SAEH2 SAEH1 SAEH0
high byte register
Scaled available energy
SAEL
10h
R
SAEL7 SAEL6 SAEL5 SAEL4 SAEL3 SAEL2 SAEL1 SAEL0
low byte register
RCAC Relative CAC
11h
R
RCAC6 RCAC5 RCAC4 RCAC3 RCAC2 RCAC1 RCAC0
VSRH Current scale high
12h
R
VSRH7 VSRH6 VSRH5 VSRH4 VSRH3 VSRH2 VSRH1 VSRH0
VSRL
Current scale low
13h
R
VSRL7 VSRL6 VSRL5 VSRL4 VSRL3 VSRL2 VSRL1 VSRL0
DCR
Discharge register
18h R/W DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
PPFC
Program pin data
1eh R/W RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
INTSS VOS Interrupt
38h R/W RSVD RSVD RSVD RSVD DCHGI RSVD RSVD CHGI
Notes:
RSVD = reserved.
All other registers not documented are reserved.
12
Preliminary bq2014H
The EDV1 values are
The capacity inaccurate flag (CI) is used to warn the
user that the battery has been charged a substantial
number of times since LMD has been updated. The CI
flag is asserted on the 64th charge after the last LMD
update or when the bq2014H is reset. The flag is cleared
after an LMD update.
FLGS1 Bits
6
5
4
3
2
1
0
-
-
-
-
-
-
EDV1
-
where EDV1 is
The CI values are
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
-
CI
-
-
-
-
0
When LMD is updated with a valid full discharge
1
After the 64th valid charge action with no
LMD updates or the bq2014H is reset
0
Valid charge action detected, VSB ≥ VTS
1
VSB < VTS providing that the discharge rate
is < 2C (OVLD not set)
The final end-of-discharge warning flag (EDVF) flag
is used to warn that battery power is at a failure condition. All segment drivers are turned off. The EDVF flag
is latched until a valid charge has been detected. The
EDVF threshold is set 25mV below the EDV1 threshold.
where CI is
The EDVF values are
FLGS1 Bits
The valid discharge flag (VDQ) is asserted when the
bq2014H is discharged from NAC = 0.94 ∗ LMD. The
flag remains set until either LMD is updated or one of
three actions that can clear VDQ occurs:
■
7
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
EDVF
where EDVF is
When NAC has been reduced by more than 6.25%
because of self-discharge since VDQ was set.
■
A valid charge action is sustained at VSRO > VSRQ
for at least 2 NAC updates.
■
The EDV1 flag was set at a temperature below 0°C
0
Valid charge action detected, VSB ≥ (VTS - 25mV)
1
VSB < (VTS -25mV) providing the discharge
rate is < 2C
Temperature Register (TMP)
The VDQ values are
The TMP register (address=02h) contains the battery
temperature.
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
-
-
VDQ
-
-
-
The bq2014H contains an internal temperature sensor.
The temperature is used to set charge and discharge efficiency factors as well as to adjust the self-discharge coefficient. The temperature register contents may be
translated as shown in Table 9.
where VDQ is
0
Self-discharge of more than 6.25% of NAC,
valid charge action detected, EDV1 asserted
with the temperature less than 0°C, or reset
1
On first discharge after NAC ≥ 0.94 ∗ LMD
TMP Temperature Bits
7
6
5
4
3
2
1
0
-
-
-
-
TMP3 TMP2 TMP1 TMP0
The first end-of-discharge warning flag (EDV1)
warns the user that the battery is almost empty. The
first segment pin, SEG1, is modulated at a 4Hz rate if
the display is enabled once EDV1 is asserted, which
should warn the user that loss of battery power is imminent. The EDV1 flag is latched until a valid charge has
been detected. The EDV1 threshold is externally controlled via the VTS register (see Voltage Threshold Register).
The bq2014H calculates the gas gauge bits, GG3-GG0 as a
function of CACT and LMD. The results of the calculation
give available capacity in 1 16 increments from 0 to 15 16.
TMP Gas Gauge Bits
13
7
6
5
4
3
2
1
0
-
-
-
-
GG3
GG2
GG1
GG0
bq2014H Preliminary
If DCR < 0.94 LMD, then LMD is set to 0.94 ∗ LMD.
Table 9. Temperature Register
TMP3
TMP2
TMP1
TMP0
Temperature
0
0
0
0
T < -30°C
0
0
0
1
-30°C < T < -20°C
0
0
1
0
-20°C < T < -10°C
0
0
1
1
-10°C < T < 0°C
0
1
0
0
0°C < T < 10°C
0
1
0
1
10°C < T < 20°C
0
1
1
0
20°C < T < 30°C
0
1
1
1
30°C < T < 40°C
1
0
0
0
40°C < T < 50°C
1
0
0
1
50°C < T < 60°C
1
0
1
0
60°C < T < 70°C
1
0
1
1
70°C < T < 80°C
1
1
0
0
T > 80°C
Secondary Status Flags Register (FLGS2)
The FLGS2 register (address=06h) contains the secondary bq2014H flags.
Bit 7 and bit 1 of FLGS2 are reserved. Do not write to
these bits.
The discharge rate flags, DR2–0, are bits 6–4.
7
-
6
DR2
FLGS2 Bits
5
4
3
DR1
DR0
-
2
-
1
-
0
They are used to determine the current discharge regime as follows:
DR2
0
0
0
DR1
0
0
1
DR0
0
1
0
Discharge Rate
DRATE < 0.5C
0.5C ≤ DRATE < 2C
2C < DRATE
The enable interrupt flag (ENINT) is a test bit used to
determine VSR activity sensed by the bq2014H. The
state of this bit will vary and should be ignored by the
system.
Nominal Available Capacity Registers
(NACH/NACL)
The NACH high-byte register (address=03h) and the
NACL low-byte register (address=17h) are the main gas
gauging registers for the bq2014H. The NAC registers are
incremented during charge actions and decremented during discharge and self-discharge actions. NACH and
NACL are set to 0 during a bq2014H reset.
7
-
6
-
5
-
FLGS2 Bits
4
3
ENINT
2
-
1
-
0
The valid charge flag (VQ), bit 2 of FLGS2, is used to
indicate whether the bq2014H recognizes a valid charge
condition. This bit is reset on the first discharge after
NAC = LMD.
Writing to the NAC registers affects the available charge
counts and, therefore, affects the bq2014H gas gauge operation. Do not write the NAC registers to a value greater than
LMD.
The VQ values are
Battery Identification Register (BATID)
The BATID register (address=04h) is available for use
by the system to determine the type of battery pack.
The BATID contents are retained as long as VRBI is
greater than 2V. The contents of BATID have no effect
on the operation of the bq2014H. There is no default
setting for this register.
7
-
6
-
5
-
FLGS2 Bits
4
3
-
2
VQ
1
-
0
where VQ is
0
Valid charge action not detected between a
discharge from NAC = LMD and EDV1
1
Valid charge action detected
Last Measured Discharge Register (LMD)
LMD is the register (address=05h) that the bq2014H
uses as a measured full reference. The bq2014H adjusts
LMD based on the measured discharge capacity of the
battery from full to empty. In this way the bq2014H updates the capacity of the battery. LMD is set to PFC
during a bq2014H reset.
The overload flag (OVLD) is asserted when a discharge
rate in excess of 2C is detected. OVLD remains asserted
as long as the condition persists and is cleared 0.5 seconds after the rate drops below 2C. The overload condition is used to stop sampling of the battery terminal characteristics for end-of-discharge determination.
LMD is set to DCR upon the first valid charge after EDV
is set if VDQ is set.
14
Preliminary bq2014H
7
-
6
-
FLGS2 Bits
4
3
-
5
-
2
-
1
-
Battery Voltage Register (VSB)
0
OVLD
The battery voltage register is used to read the single-cell
battery voltage on the SB pin. The VSB register (address
= 0Bh) is updated approximately once per second with the
present value of the battery voltage.
VSB = 1.2V * (VSB/256).
Program Pin Pull-Down Register (PPD)
The PPD register (address=07h) contains some of the programming pin information for the bq2014H. The segment
drivers, SEG1–5, have a corresponding PPD register location, PPD1–5. A given location is set if a pull-down resistor
has been detected on its corresponding segment driver.
For example, if SEG1 and SEG4 have pull-down resistors,
the contents of PPD are xxx01001.
VSB Register Bits
7
6
5
4
3
2
1
0
VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0
Voltage Threshold Register (VTS)
Program Pin Pull-Up Register (PPU)
The end-of-discharge threshold voltages (EDV1 and
EDVF) can be set using the VTS register (address =
0Ch). The VTS register sets the EDV1 trip point. EDVF
is set 25mV below EDV1. The default value in the VTS
register is A2h, representing EDV1 = 0.76V and EDVF =
0.735V. EDV1 = 1.2V * (VTS/256).
The PPU register (address=08h) contains the rest of the
programming pin information for the bq2014H. The segment drivers, SEG1–5, have a corresponding PPU register
location, PPU1–5. A given location is set if a pull-up resistor has been detected on its corresponding segment driver.
For example, if SEG3 and SEG5 have pull-up resistors, the
contents of PPU are xxx10100.
VTS Register Bits
7
PPD/PPU Bits
6
5
4
3
2
1
0
VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0
7
6
5
4
3
2
1
0
Compensated Available Charge Registers
(CACT/CACD)
RSVD RSVD RSVD PPU5 PPU4 PPU3 PPU2 PPU1
RSVD RSVD RSVD PPD5 PPD4 PPD3 PPD2 PPD1
The CACD register (address = 0Eh) contains the NAC
value compensated for discharge rate. This is a monotonicly decreasing value during discharge. If the discharge rate is > 2C then this value is lower than NAC.
CACD is updated only when the discharge rate compensated NAC value is a lower value than CACD during
discharge. During charge, CACD is continuously updated with the NAC value.
Capacity Inaccurate Count Register (CPI)
The CPI register (address=09h) is used to indicate the
number of times a battery has been charged without an
LMD update. Because the capacity of a rechargeable
battery varies with age and operating conditions, the
bq2014H adapts to the changing capacity over time. A
complete discharge from full (NAC ≥ 0.94 ∗ LMD) to
empty (EDV1=1) is required to perform an LMD update
assuming there have been no intervening valid charges,
the temperature is greater than or equal to 0°C, and
there has been no more than a 6% self-discharge
reduction.
The CACT register (address = 0Dh) contains the CACD
value compensated for temperature. CACT will contain
a value lower than CACD when the battery temperature
is below 10°C. The CACT value is also used in calculating the LED display pattern.
Scaled Available Energy Registers
(SAEH/SAEL)
The CPI register is incremented every time a valid
charge is detected. When NAC ≥ 0.94 * LMD, however,
the CPI register increments on the first valid charge;
CPI does not increment again for a valid charge until
NAC < 0.94 * LMD. This prevents continuous trickle
charging from incrementing CPI if self-discharge decrements NAC. The CPI register increments to 255 without rolling over. When the contents of CPI are incremented to 64, the capacity inaccurate flag, CI, is asserted in the FLGS1 register. The CPI register is reset
whenever an update of the LMD register is performed,
and the CI flag is also cleared.
The SAEH high-byte register (address = 0Fh) and the
SAEL low-byte register (address = 10h) are used to scale
battery voltage and CACT to a value that can be translated to watt-hours remaining under the present conditions.
Relative CAC Register (RCAC)
The RCAC register (address = 11h) provides the relative
battery state-of-charge by dividing CACT by LMD.
15
bq2014H Preliminary
Voltage Offset (VOS) Interrupt (INTSS)
RCAC varies from 0 to 64h representing relative stateof-charge from 0 to 100%.
The INTSS register (address = 38h) is useful during intial characterization of bq2014H designs. When the
bq2014H counts a charge pulse, CHGI (bit 0) will be set
to 1. When the bq2014H counts a discharge pulse,
DCHGI (bit 3) will be set to 1. All other locations in the
INTSS register are reserved.
Current Scale Register (VSRH/VSRL)
The VSRH register (address = 12h) and the VSRL register (address = 13h) report the average signal across the
SR and VSS pins. The bq2050H updates this register
pair every 22.5s. VSRH (high-byte) and VSRL (low-byte)
form a 16-bit signed integer value representing the average current during this time. The battery pack current
can be calculated from:
Display
The bq2014H can directly display capacity information
using low-power LEDs. If LEDs are used, the program
pins should be resistively tied to VCC or VSS for a program high or program low, respectively.
|I(mA)| = (VSRH ∗ 256 + VSRL)/(8 ∗RS)
where:
The bq2014H displays the battery charge state in relative
mode. In relative mode, the battery charge is represented
as a percentage of the LMD. Each LED segment represents 20% of the LMD.
RS = sense resistor value in Ω.
VSRH = high-byte value of battery current
VSRL = low-byte value of battery current
The bq2014H indicates an average discharge current
with a “1” in the MSB position of the VSRH register. To
calculate discharge current, use the 2’s complement if
the concatenated register contents in the above equation.
The capacity display is also adjusted for the present battery temperature and discharge rate. The temperature
adjustment reflects the available capacity at a given
temperature but does not affect the NAC register. The
temperature adjustments are detailed in the CACT and
CACD register descriptions.
Discharge Count Register (DCR)
When DISP is tied to VCC, the SEG1–5 outputs are inactive. When DISP is left floating, the display becomes active whenever the bq2014H detects a charge in progress
VSRO > VSRQ. When pulled low, the segment outputs become active for a period of four seconds, ± 0.5 seconds.
The DCR register (address = 18h) stores the high-byte of
the discharge count. DCR is reset to zero at the start of
a valid discharge cycle and can count to a maximum of
FFh. DCR will not increment if EDV1 = 1 and will not
roll over from FFh.
The segment outputs are modulated as two banks, with
segments 1, 3, and 5 alternating with segments 2 and 4.
The segment outputs are modulated at approximately
100Hz with each segment bank active for 30% of the period.
Program Pin Full Count (PPFC)
The PPFC register contains information concerning the
program pin configuration. This information is used to
determine the data integrity of the bq2014H. The only
approved user application for this register is to
write a zero to this register as part of a reset request.
SEG1 blinks at a 4Hz rate whenever VSB has been detected to be below VEDV1 (EDV1 = 1), indicating a lowbattery condition. VSB below VEDVF (EDVF = 1) disables
the display output.
The recommended reset method for the bq2014H is
■
Write PPFC to zero
■
Write LMD to zero
Microregulator
A micropower source for the bq2014H can be inexpensively built using a FET and an external resistor. (See
Figure 1.)
After these operations, a software reset will occur.
Resetting the bq2014H sets the following:
■
LMD = PFC
■
CPI, VDQ, RCAC, NACH/L, CACH/L, SAEH/L,
NMCV = 0
■
CI and BRP = 1
16
Preliminary bq2014H
Absolute Maximum Ratings
Symbol
Parameter
Minimum
Maximum
Unit
Notes
VCC
Relative to VSS
-0.3
+7.0
V
All other pins
Relative to VSS
-0.3
+7.0
V
REF
Relative to VSS
-0.3
+8.5
V
Current limited by R1 (see Figure 1)
VSR
Relative to VSS
-0.3
Vcc+0.7
V
100kΩ series resistor should be used to
protect SR in case of a shorted battery.
TOPR
Operating temperature
0
+70
°C
Commercial
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional
operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
DC Voltage Thresholds (TA = TOPR; V = 3.0 to 6.5V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Notes
VEDV1
First empty warning
0.73
0.76
0.79
V
SB, default
VEDVF
Final empty warning
VEDV1 - 0.035
VEDV1 - 0.025
VEDV1 - 0.015
V
SB, default
VSRO
SR sense range
-300
-
+500
mV
SR, VSR + VOS
VSRQ
Valid charge
250
-
-
µV
VSR + VOS (see note)
VSRD
Valid discharge
-
-
-250
µV
VSR + VOS (see note)
Note:
VOS is affected by PC board layout. Proper layout guidelines should be followed for optimal performance.
See “LayoutConsiderations.”
17
bq2014H Preliminary
DC Electrical Characteristics (TA = TOPR)
Symbol
Parameter
VCC
Supply voltage
VOS
Offset referred to VSR
Minimum
Typical Maximum Unit
3.0
4.25
6.5
V
5.7
4.5
2.0
0
10
-0.2
500
10
VCC - 0.2
float
±50
6.0
5.0
90
120
170
-
±150
6.3
7.5
135
180
250
VCC
5
0.2
100
VSS + 0.2
float
µV
V
V
MΩ
µA
µA
µA
V
MΩ
µA
µA
nA
KΩ
MΩ
V
V
V
Notes
VCC excursion from < 2.0V to ≥
3.0V initializes the unit.
DISP = VCC
IREF = 5µA
IREF = 5µA
VREF = 3V
VCC = 3.0V, HDQ = 0
VCC = 4.25V, HDQ = 0
VCC = 6.5V, HDQ = 0
RREF
Reference at 25°C
Reference at -40°C to +85°C
Reference input impedance
ICC
Normal operation
VSB
RSBmax
IDISP
ILCOM
IRBI
RHDQ
RSR
VIHPFC
VILPFC
VIZPFC
Battery input
SB input impedance
DISP input leakage
LCOM input leakage
RBI data retention current
Internal pulldown
SR input impedance
Logic input high
Logic input low
Logic input Z
VOLSL
SEG output low, low VCC
-
0.1
-
V
VOLSH
SEG output low, high VCC
-
0.4
-
V
VOHML
VOHMH
IOLS
IOL
VOL
VIHDQ
VILDQ
LCOM output high, low VCC
VCC - 0.3
LCOM output high, high VCC VCC - 0.6
SEG sink current
11.0
Open-drain sink current
5.0
Open-drain output low
HDQ input high
2.5
HDQ input low
Soft pull-up or pull-down resistor value (for programming)
Float state external impedance
-
-
0.3
0.8
V
V
mA
mA
V
V
V
-200mV < VSR < VCC
PROG1–5
PROG1–5
PROG1–5
VCC = 3V, IOLS ≤ 1.75mA
SEG1–SEG5
VCC = 6.5V, IOLS ≤ 11.0mA
SEG1–SEG5
VCC = 3V, IOHLCOM = -5.25mA
VCC > 3.5V, IOHLCOM = -33.0mA
At VOLSH = 0.4V, VCC = 6.5V
At VOL = VSS + 0.3V, HDQ
IOL ≤ 5mA, HDQ
HDQ
HDQ
-
200
KΩ
PROG1–5
5
-
MΩ
PROG1–5
VREF
RPROG
RFLOAT
Note:
All voltages relative to VSS.
18
0 < VSB < VCC
VDISP = VSS
DISP = VCC
VRBI > VCC < 3V
Preliminary bq2014H
High-Speed Serial Communication Timing Specification (TA = TOPR)
Parameter
Minimum
tCYCH
Symbol
Cycle time, host to bq2014H (write)
190
-
-
µs
tCYCB
Cycle time, bq2014H to host (read)
190
205
250
µs
tSTRH
Start hold, host to bq2014H (write)
5
-
-
ns
tSTRB
Start hold, bq2014H to host (read)
32
-
-
µs
tDSU
Data setup
-
-
50
µs
tDSUB
Data setup
-
-
50
µs
tDH
Data hold
90
-
-
µs
tDV
Data valid
-
-
80
µs
tSSU
Stop setup
-
-
145
µs
tSSUB
Stop setup
-
-
145
µs
tRSPS
Response time, bq2014H to host
190
-
320
µs
tB
Break
190
-
-
µs
tBR
Break recovery
40
-
-
µs
Note:
Typical Maximum
Unit
Notes
See note
The open-drain HDQ pin should be pulled to at least VCC by the host system for proper HDQ operation.
HDQ may be left floating if the serial interface is not used.
19
bq2014H Preliminary
Break Timing
tBR
tB
TD201803.eps
Host to bq2014H
Write "1"
Write "0"
tSTRH
tDSU
tDH
tSSU
tCYCH
bq2014H to Host
Read "1"
Read "0"
tSTRB
tDSUB
tDV
tSSUB
tCYCB
20
Preliminary bq2014H
16-Pin SOIC Narrow (SN)
16-Pin SN (0.150" SOIC)
D
e
Inches
B
Min.
Max.
Min.
Max.
A
0.060
0.070
1.52
1.78
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.18
0.25
D
0.385
0.400
9.78
10.16
E
0.150
0.160
3.81
4.06
E
H
A
C
A1
e
0.045
0.055
1.14
1.40
H
0.225
0.245
5.72
6.22
L
0.015
0.035
0.38
0.89
.004
L
Ordering Information
bq2014H
Temperature Range:
blank = Commercial (0 to +70°C)
Package Option:
SN = 16-pin narrow SOIC
Device:
bq2014H Gas-Gauge IC
21
Millimeters
Dimension
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any
product or service without notice, and advise customers to obtain the latest version of relevant information to verify,
before placing orders, that information being relied on is current and complete. All products are sold subject to the
terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty,
patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH,
PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI
SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI
PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards
must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor
products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright © 1999, Texas Instruments Incorporated
22