Freescale MPC7457EC Risc microprocessor hardware specification Datasheet

Freescale Semiconductor
MPC7457EC
Rev. 5, 09/2004
Technical Data
MPC7457
RISC Microprocessor
Hardware Specifications
This hardware specification is primarily concerned with the
MPC7457; however, unless otherwise noted, all information here
also applies to the MPC7447. The MPC7457 and MPC7447 are
implementations of the PowerPC™ microprocessor family of
reduced instruction set computer (RISC) microprocessors. This
hardware specification describes pertinent electrical and physical
characteristics of the MPC7457. For functional characteristics of
the processor, refer to the MPC7450 RISC Microprocessor Family
User’s Manual.
To locate any published updates for this hardware specification,
refer to the website at http://www.Freescale.com.
1
Overview
The MPC7457 is the fourth implementation of the fourth
generation (G4) microprocessors from Freescale. The MPC7457
implements the full PowerPC 32-bit architecture and is targeted at
networking and computing systems applications. The MPC7457
consists of a processor core, a 512-Kbyte L2, and an internal L3
tag and controller that support a glueless backside L3 cache
through a dedicated high-bandwidth interface. The MPC7447 is
identical to the MPC7457 except that it does not support the L3
cache interface.
Figure 1 shows a block diagram of the MPC7457. The core is a
high-performance superscalar design supporting a
double-precision floating-point unit and a SIMD multimedia unit.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Comparison with the MPC7455, MPC7445,
MPC7450, MPC7451, and MPC7441 . . . . . . . . . . . . 7
4. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5. Electrical and Thermal Characteristics . . . . . . . . . . . 10
6. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 41
9. System Design Information . . . . . . . . . . . . . . . . . . . 47
10. Document Revision History . . . . . . . . . . . . . . . . . . . 61
11. Part Numbering and Marking . . . . . . . . . . . . . . . . . . 63
2
Completes up
to three
instructions
per clock
96-Bit (3 Instructions)
Vector
Integer
Unit 2
128-Bit
Dispatch
Unit
+++
x÷
32-Bit
Integer
Integer
Integer
Unit
122
Unit
Unit
(3)
Integer
Unit 2
Notes: 1. The L3 cache interface is not implemented on the MPC7447.
2. The Castout Queue and Push Queue share resources such for a combined total of 10 entries.
The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.
L2 Store Queue (L2SQ)
Snoop Push/
L1 Castouts
Interventions
(4)
Line Block 0 (32-Byte)
Block 1 (32-Byte)
Tags Status
Status
19-Bit Address
Bus Accumulator
128-Entry
ITLB
Load/Store Unit
Completed
Stores
L1 Push
Finished
Stores
External SRAM
(1, 2, or 4 Mbytes)
64-Bit Data
(8-Bit Parity)
L3CR
FPR File
Tags
64-Bit
FPSCR
+ x÷
FloatingPoint Unit
Reservation
Stations (2)
36-Bit
Address Bus
64-Bit
Data Bus
Bus Accumulator
Bus Store Queue
Castout
Queue (9)/
Push
Queue (10) 2
System Bus Interface
64-Bit
32-Kbyte
I Cache
32-Kbyte
D Cache
Tags
128-Bit (4 Instructions)
16 Rename
Buffers
PA
Load
Queue (11)
Load Miss
L1 Castout
+ (EA Calculation)
Vector Touch Engine
EA
128-Entry
DTLB
DBAT Array
SRs
(Original)
Data MMU
IBAT Array
SRs
(Shadow)
Instruction MMU
Reservation
Stations (2-Entry)
L3 Cache Controller 1
Line Block 0/1
Tags Status
32-Bit
32-Bit
16 Rename
Buffers
GPR File
Vector
Touch
Queue
FPR Issue
(2-Entry/1-Issue)
Instruction Queue
(12-Word)
Reservation
Reservation
Reservation
Station
Station
Station
512-Kbyte Unified L2 Cache Controller
128-Bit
Vector
FPU
L2 Prefetch (3)
L1 Service
Queues
Vector
Integer
Unit 1
Instruction Fetch (2)
Cacheable Store Request(1)
L1 Load Miss (5)
L1 Load Queue (LLQ)
L1 Store Queue
(LSQ)
Memory Subsystem
Vector
Permute
Unit
16 Rename
Buffers
VR File
Reservation
Stations (2)
LR
BHT (2048-Entry)
VR Issue
(4-Entry/2-Issue)
CTR
BTIC (128-Entry)
Fetcher
GPR Issue
(6-Entry/3-Issue)
Instruction Unit
Branch Processing Unit
Reservation Reservation Reservation Reservation
Station
Station
Station
Station
Completion Queue
(16-Entry)
Completion Unit
• Time Base Counter/Decrementer
• Clock Multiplier
• JTAG/COP Interface
• Thermal/Power Management
• Performance Monitor
Additional Features
Overview
Figure 1. MPC7457 Block Diagram
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
Features
The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory
and other system resources. The L3 interface supports 1, 2, or 4 Mbytes of external SRAM for L3 cache and/or
private memory data. For systems implementing 4 Mbytes of SRAM, a maximum of 2 Mbytes may be used as cache;
the remaining 2 Mbytes must be private memory.
Note that the MPC7457 is a footprint-compatible, drop-in replacement in a MPC7455 application if the core power
supply is 1.3 V.
2
Features
This section summarizes features of the MPC7457 implementation of the PowerPC architecture.
Major features of the MPC7457 are as follows:
•
•
High-performance, superscalar microprocessor
— As many as four instructions can be fetched from the instruction cache at a time.
— As many as three instructions can be dispatched to the issue queues at a time.
— As many as 12 instructions can be in the instruction queue (IQ).
— As many as 16 instructions can be at some stage of execution simultaneously.
— Single-cycle execution for most instructions
— One instruction per clock cycle throughput for most instructions
— Seven-stage pipeline control
Eleven independent execution units and three register files
— Branch processing unit (BPU) features static and dynamic branch prediction
– 128-entry (32-set, four-way set associative) branch target instruction cache (BTIC), a cache of
branch instructions that have been encountered in branch/loop code sequences. If a target instruction
is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available
from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions
in the target stream.
– 2048-entry branch history (BHT) with 2 bits per entry for 4 levels of prediction—not-taken, strongly
not-taken, taken, and strongly taken
– Up to three outstanding speculative branches
– Branch instructions that do not update the count register (CTR) or link register (LR) are often
removed from the instruction stream.
– Eight-entry link register stack to predict the target address of Branch Conditional to Link Register
(bclr) instructions
— Four integer units (IUs) that share 32 GPRs for integer operands
– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply,
divide, and move to/from special-purpose register instructions
– IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication
and division instructions, and move to/from special-purpose register instructions
— Five-stage FPU and a 32-entry FPR file
– Fully IEEE 754-1985 compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
3
Features
•
•
•
•
– Hardware support for denormalized numbers
– Thirty-two 64-bit FPRs for single- or double-precision operands
— Four vector units and 32-entry vector register file (VRs)
– Vector permute unit (VPU)
– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as vector add
instructions (for example, vaddsbs, vaddshs, and vaddsws)
– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector
multiply add instructions (for example, vmhaddshs, vmhraddshs, and vmladduhm)
– Vector floating-point unit (VFPU)
— Three-stage load/store unit (LSU)
– Supports integer, floating-point, and vector instruction load/store traffic
– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream operations
– Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle
throughput
– Four-cycle FPR load latency (single, double) with one-cycle throughput
– No additional delay for misaligned access within double-word boundary
– Dedicated adder calculates effective addresses (EAs)
– Supports store gathering
– Performs alignment, normalization, and precision conversion for floating-point data
– Executes cache control and TLB instructions
– Performs alignment, zero padding, and sign extension for integer data
– Supports hits under misses (multiple outstanding misses)
– Supports both big- and little-endian modes, including misaligned little-endian accesses
Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions, respectively,
in a cycle. Instruction dispatch requires the following:
— Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2
— A maximum of three instructions can be dispatched to the issue queues per clock cycle
— Space must be available in the CQ for an instruction to dispatch (this includes instructions that are
assigned a space in the CQ but not in an issue queue)
Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers
Dispatch unit
— Decode/dispatch stage fully decodes each instruction
Completion unit
— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no exceptions
are pending.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Freescale Semiconductor
Features
•
•
•
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set associative instruction and data caches
— Pseudo least recently used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four words per
clock cycle
— Caches can be disabled in software.
— Caches can be locked in software.
— MESI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— Parity support on cache and tags
— No snooping of instruction cache except for icbi instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding
is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding.
Level 2 (L2) cache interface
— On-chip, 512-Kbyte, eight-way set associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total nine-cycle load latency for an L1 data cache miss that hits in L2
— PLRU replacement algorithm
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity support on cache
Level 3 (L3) cache interface (not implemented on MPC7447)
— Provides critical double-word forwarding to the requesting unit
— Internal L3 cache controller and tags
— External data SRAMs
— Support for 1-, 2-, and 4-Mbyte (MB) total SRAM space
— Support for 1- or 2-MB of cache space
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte (1-MB) or 128-byte (2-MB) sectored line size
— Private memory capability for half (1 MB minimum) or all of the L3 SRAM space for a total of 1-, 2-,
or 4-MB of private memory
— Supports MSUG2 dual data rate (DDR) synchronous burst SRAMs, PB2 pipelined synchronous burst
SRAMs, and pipelined (register-register) late write synchronous burst SRAMs
— Supports parity on cache and tags
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
5
Features
•
•
•
•
— Configurable core-to-L3 frequency divisors
— 64-bit external L3 data bus sustains 64 bits per L3 clock cycle
Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address; 32- or 36-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and memory
coherency enforced/memory coherency not enforced on a page or block basis
— Separate IBATs and DBATs (eight each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
– Both TLBs are 128-entry, two-way set associative, and use LRU replacement algorithm
– TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is performed
in hardware or by system software)
Efficient data flow
— Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits
— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs
— L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache
— As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data cache and
L2/L3 bus
— As many as 16 out-of-order transactions can be present on the MPX bus
— Store merging for multiple store misses to the same line. Only coherency action taken (address-only)
for store misses merged to all 32 bytes of a cache block (no data tenure needed).
— Three-entry finished store queue and five-entry completed store queue between the LSU and the L1 data
cache
— Separate additional queues for efficient buffering of outbound data (such as castouts and write-through
stores) from the L1 data cache and L2 cache
Multiprocessing support features include the following:
— Hardware-enforced, MESI cache coherency protocols for data cache
— Load/store with reservation instruction pair for atomic memory references, semaphores, and other
multiprocessor operations
Power and thermal management
— 1.3-V processor core
— The following three power-saving modes are available to the system:
– Nap—Instruction fetching is halted. Only those clocks for the time base, decrementer, and JTAG
logic remain running. The part goes into the doze state to snoop memory operations on the bus and
back to nap using a QREQ/QACK processor-system handshake protocol.
– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the PLL in a
locked and running state. All internal functional units are disabled.
– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system can then
disable the SYSCLK source for greater system power savings. Power-on reset procedures for
restarting and relocking the PLL must be followed on exiting the deep sleep state.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
6
Freescale Semiconductor
Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441
•
•
•
•
3
— Thermal management facility provides software-controllable thermal management. Thermal
management is performed through the use of three supervisor-level registers and an MPC7457-specific
thermal management exception.
— Instruction cache throttling provides control of instruction fetching to limit power consumption
Performance monitor can be used to help debug system designs and improve software efficiency
In-system testability and debugging features through JTAG boundary-scan capability
Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
— Array built-in self test (ABIST)—factory test only
Reliability and serviceability
— Parity checking on system bus and L3 cache bus
— Parity checking on the L2 and L3 cache tag arrays
Comparison with the MPC7455, MPC7445, MPC7450,
MPC7451, and MPC7441
Table 1 compares the key features of the MPC7457 with the key features of the earlier MPC7455, MPC7445,
MPC7450, MPC7451, and MPC7441. To achieve a higher frequency, the number of logic levels per cycle is
reduced. Also, to achieve this higher frequency, the pipeline of the MPC7457 is extended (compared to the
MPC7400), while maintaining the same level of performance as measured by the number of instructions executed
per cycle (IPC).
Table 1. Microarchitecture Comparison
Microarchitectural Specs
MPC7457/MPC7447
MPC7455/MPC7445
MPC7450/MPC7451/
MPC7441
Basic Pipeline Functions
Logic inversions per cycle
18
18
18
Pipeline stages up to execute
5
5
5
Total pipeline stages (minimum)
7
7
7
3 + Branch
3 + Branch
3 + Branch
Pipeline maximum instruction throughput
Pipeline Resources
Instruction buffer size
12
12
12
Completion buffer size
16
16
16
16, 16, 16
16, 16, 16
16, 16, 16
3
3
3
2 (any 2 of 4 units)
2 (any 2 of 4 units)
2 (any 2 of 4 units)
1
1
1
Renames (integer, float, vector)
Maximum Execution Throughput
SFX
Vector
Scalar floating-point
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
7
Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441
Table 1. Microarchitecture Comparison (continued)
Microarchitectural Specs
MPC7457/MPC7447
MPC7455/MPC7445
MPC7450/MPC7451/
MPC7441
Out-of-Order Window Size in Execution Queues
1 entry × 3 queues
1 entry × 3 queues
1 entry × 3 queues
In order, 4 queues
In order, 4 queues
In order, 4 queues
In order
In order
In order
BTIC, BHT, link stack
BTIC, BHT, link stack
BTIC, BHT, link stack
128-entry, 4-way
128-entry, 4-way
128-entry, 4-way
2K-entry
2K-entry
2K-entry
Link stack depth
8
8
8
Unresolved branches supported
3
3
3
Branch taken penalty (BTIC hit)
1
1
1
Minimum misprediction penalty
6
6
6
SFX integer units
Vector units
Scalar floating-point unit
Branch Processing Resources
Prediction structures
BTIC size, associativity
BHT size
Execution Unit Timings (Latency-Throughput)
Aligned load (integer, float, vector)
3-1, 4-1, 3-1
3-1, 4-1, 3-1
3-1, 4-1, 3-1
Misaligned load (integer, float, vector)
4-2, 5-2, 4-2
4-2, 5-2, 4-2
4-2, 5-2, 4-2
9 data/13 instruction
9 data/13 instruction
9 data/13 instruction
SFX (aDd Sub, Shift, Rot, Cmp, logicals)
1-1
1-1
1-1
Integer multiply (32 × 8, 32 × 16, 32 × 32)
3-1, 3-1, 4-2
3-1, 3-1, 4-2
3-1, 3-1, 4-2
Scalar float
5-1
5-1
5-1
VSFX (vector simple)
1-1
1-1
1-1
VCFX (vector complex)
4-1
4-1
4-1
VFPU (vector float)
4-1
4-1
4-1
VPER (vector permute)
2-1
2-1
2-1
128-entry, 2-way
128-entry, 2-way
128-entry, 2-way
Hardware + software
Hardware + software
Hardware + software
8/8
8/8
4/4
32K/32K
32K/32K
32K/32K
8-way
8-way
8-way
Way
Way
Way
L1 miss, L2 hit latency
MMUs
TLBs (instruction and data)
Tablewalk mechanism
Instruction BATs/data BATs
L1 I Cache/D Cache Features
Size
Associativity
Locking granularity
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Freescale Semiconductor
Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441
Table 1. Microarchitecture Comparison (continued)
MPC7457/MPC7447
MPC7455/MPC7445
MPC7450/MPC7451/
MPC7441
Parity on I cache
Word
Word
Word
Parity on D cache
Byte
Byte
Byte
Number of D cache misses (load/store)
5/1
5/1
5/1
4 streams
4 streams
4 streams
L2
L2
L2
512-Kbyte/8-way
256-Kbyte/8-way
256-Kbyte/8-way
256 bits
256 bits
256 bits
2
2
2
Byte
Byte
Byte
L3
L3
1 MB, 2 MB
1 MB, 2 MB
1 MB, 2 MB
1 MB, 2 MB
1 MB, 2 MB
8-way
8-way
8-way
2, 4
2, 4
2, 4
MSUG2 DDR, LW, PB2
MSUG2 DDR, LW, PB2
MSUG2 DDR, LW, PB2
64
64
64
1 MB, 2 MB, 4 MB
1 MB, 2 MB
1 MB, 2 MB
Byte
Byte
Byte
Microarchitectural Specs
Data stream touch engines
On-Chip Cache Features
Cache level
Size/associativity
Access width
Number of 32-byte sectors/line
Parity
Off-Chip Cache Support 1
Cache level
L3
Total SRAM space supported
On-chip tag logical size (cache space)
Associativity
Number of 32-byte sectors/line
Off-Chip data SRAM support
Data path width
Direct mapped SRAM sizes
Parity
1 MB, 2MB, 4 MB
2
Notes:
1. Not implemented on MPC7447, MPC7445, or MPC7441.
2. The MPC7457 supports up to 4 MB of SRAM, of which a maximum of 2 MB can be configured as cache memory; the
remaining 2 MB may be unused or configured as private memory.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
9
General Parameters
4
General Parameters
The following list provides a summary of the general parameters of the MPC7457:
Technology
Die size
Transistor count
Logic design
Packages
Core power supply
I/O power supply
5
0.13 µm CMOS, nine-layer metal
9.1 mm × 10.8 mm
58 million
Fully-static
MPC7447: Surface mount 360 ceramic ball grid array (CBGA)
MPC7457: Surface mount 483 ceramic ball grid array (CBGA)
1.3 V ±50 mV DC nominal
1.8 V ±5% DC, or
2.5 V ±5% DC, or
1.5 V ±5% DC (L3 interface only, not implemented on MPC7447)
Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7457.
5.1
DC Electrical Characteristics
The tables in this section describe the MPC7457 DC electrical characteristics.Table 2 provides the absolute
maximum ratings.
Table 2. Absolute Maximum Ratings 1
Characteristic
Symbol
Maximum Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.60
V
2
PLL supply voltage
AVDD
–0.3 to 1.60
V
2
BVSEL = 0
OVDD
–0.3 to 1.95
V
3, 4
BVSEL = HRESET or OVDD
OVDD
–0.3 to 2.7
V
3, 5
L3VSEL = ¬HRESET
GVDD
–0.3 to 1.65
V
3, 6
L3VSEL = 0
GVDD
–0.3 to 1.95
V
3, 7
L3VSEL = HRESET or GVDD
GVDD
–0.3 to 2.7
V
3, 8
Processor bus
Vin
–0.3 to OVDD + 0.3
V
9, 10
L3 bus
Vin
–0.3 to GVDD + 0.3
V
9, 10
JTAG signals
Vin
–0.3 to OVDD + 0.3
V
Processor bus supply voltage
L3 bus supply voltage
Input voltage
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Freescale Semiconductor
Electrical and Thermal Characteristics
Table 2. Absolute Maximum Ratings 1 (continued)
Characteristic
Storage temperature range
Symbol
Maximum Value
Unit
Tstg
–55 to 150
°C
Notes
Notes:
1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: VDD/AVDD must not exceed OV DD/GVDD by more than 1.0 V during normal operation; this limit may be exceeded
for a maximum of 20 ms during power-on reset and power-down sequences.
3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2.0 V during normal operation; this limit may be exceeded
for a maximum of 20 ms during power-on reset and power-down sequences.
4. BVSEL must be set to 0, such that the bus is in 1.8-V mode.
5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.
6. L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5-V mode.
7. L3VSEL must be set to 0, such that the bus is in 1.8-V mode.
8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode.
9. Caution: V in must not exceed OVDD or GVDD by more than 0.3 V at any time including during power-on reset.
10. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
Figure 2 shows the undershoot and overshoot voltage on the MPC7457.
OVDD/GVDD + 20%
OVDD/GVDD + 5%
OVDD /GVDD
VIH
VIL
GND
GND – 0.3 V
GND – 0.7 V
Not to exceed 10%
of tSYSCLK
Figure 2. Overshoot/Undershoot Voltage
The MPC7457 provides several I/O voltages to support both compatibility with existing systems and migration to
future systems. The MPC7457 core voltage must always be provided at nominal 1.3 V (see Table 4 for actual
recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are provided through separate sets
of supply pins and may be provided at the voltages shown in Table 3. The input voltage threshold for each bus is
selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage
will swing from GND to the maximum voltage applied to the OVDD or GVDD power pins.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
11
Electrical and Thermal Characteristics
Table 3. Input Threshold Voltage Setting
BVSEL Signal
Processor Bus Input Threshold
is Relative to:
L3VSEL Signal 1
L3 Bus Input Threshold is
Relative to:
Notes
0
1.8 V
0
1.8 V
2, 3
¬HRESET
Not Available
¬HRESET
1.5 V
2, 4
HRESET
2.5 V
HRESET
2.5 V
2
1
2.5 V
1
2.5 V
2
Notes:
1. Not implemented on MPC7447.
2. Caution: The input threshold selection must agree with the OVDD/GVDD voltages supplied. See notes in Table 2.
3. If used, pull-down resistors should be less than 250 Ω .
4. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.
Table 4 provides the recommended operating conditions for the MPC7457.
Table 4. Recommended Operating Conditions 1
Recommended Value
Characteristic
Symbol
Unit
Min
Core supply voltage
VDD
1.3 V ± 50 mV
V
PLL supply voltage
AVDD
1.3 V ± 50 mV
V
BVSEL = 0
OVDD
1.8 V ± 5%
V
BVSEL = HRESET or OVDD
OVDD
2.5 V ± 5%
V
L3VSEL = 0
GVDD
1.8 V ± 5%
V
L3VSEL = HRESET or GVDD
GVDD
2.5 V ± 5%
V
L3VSEL = ¬HRESET
GVDD
1.5 V ± 5%
V
Processor bus supply voltage
L3 bus supply voltage
Input voltage
Die-junction temperature
Notes
Max
Processor bus
Vin
GND
OVDD
V
L3 bus
Vin
GND
GVDD
V
JTAG signals
Vin
GND
OVDD
V
Tj
0
105
°C
2
3
Notes:
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not
guaranteed.
2. This voltage is the input to the filter discussed in Section 9.2, “PLL Power Supply Filtering,” and not necessarily the voltage
at the AVDD pin, which may be reduced from V DD by the filter.
3. ¬HRESET is the inverse of HRESET.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
12
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 5 provides the package thermal characteristics for the MPC7457.
Table 5. Package Thermal Characteristics 1
Value
Characteristic
Symbol
MPC7447
MPC7457
Unit
Notes
Junction-to-ambient thermal resistance, natural convection
RθJA
22
20
°C/W
2, 3
Junction-to-ambient thermal resistance, natural convection,
four-layer (2s2p) board
RθJMA
14
14
°C/W
2, 4
Junction-to-ambient thermal resistance, 200 ft/min airflow,
single-layer (1s) board
RθJMA
16
15
°C/W
2, 4
Junction-to-ambient thermal resistance, 200 ft/min airflow,
four-layer (2s2p) board
RθJMA
11
11
°C/W
2, 4
Junction-to-board thermal resistance
RθJB
6
6
°C/W
5
Junction-to-case thermal resistance
RθJC
<0.1
<0.1
°C/W
6
6.8
6.8
ppm/°C
Coefficient of thermal expansion
Notes:
1. Refer to Section 9.8, “Thermal Management Information,” for more details about thermal management.
2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
4. Per JEDEC JESD51-6 with the board horizontal.
5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
6. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1) with the calculated case temperature. The actual value of RθJC for the part is less than 0.1°C/W.
Table 6 provides the DC electrical characteristics for the MPC7457.
Table 6. DC Electrical Specifications
At recommended operating conditions. See Table 4.
Characteristic
Input high voltage
(all inputs including SYSCLK)
Input low voltage
(all inputs including SYSCLK)
Nominal
Bus
Voltage 1
Symbol
Min
Max
Unit
Notes
1.5
VIH
GVDD × 0.65
GVDD + 0.3
V
2
1.8
OVDD/GVDD × 0.65
OVDD/GVDD + 0.3
V
2.5
1.7
OVDD/GVDD + 0.3
V
–0.3
GVDD × 0.35
V
1.8
–0.3
OVDD/GVDD × 0.35
V
2.5
–0.3
0.7
V
1.5
VIL
2, 6
Input leakage current, Vin = GVDD/OVDD
—
Iin
—
30
µA
2, 3
High-impedance (off-state) leakage
current, Vin = GVDD/OVDD
—
ITSI
—
30
µA
2, 3, 4
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
13
Electrical and Thermal Characteristics
Table 6. DC Electrical Specifications (continued)
At recommended operating conditions. See Table 4.
Characteristic
Nominal
Bus
Voltage 1
Symbol
Min
Max
Unit
Notes
1.5
VOH
OVDD/GVDD – 0.45
—
V
6
1.8
OVDD/GVDD – 0.45
—
V
2.5
1.8
—
V
—
0.45
V
1.8
—
0.45
V
2.5
—
0.6
V
—
9.5
pF
—
8.0
Output high voltage, IOH = –5 mA
Output low voltage, IOL = 5 mA
Capacitance,
Vin = 0 V, f = 1 MHz
1.5
L3 interface
—
VOL
Cin
All other inputs
6
5
Notes:
1. Nominal voltages; see Table 4 for recommended operating conditions.
2. For processor bus signals, the reference is OV DD while GVDD is the reference for the L3 bus signals.
3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.
4. The leakage is measured for nominal OVDD/GVDD and VDD, or both OVDD/GVDD and VDD must vary in the same direction
(for example, both OVDD and VDD vary by either +5% or –5%).
5. Capacitance is periodically sampled rather than 100% tested.
6. Applicable to L3 bus interface only.
Table 7 provides the power consumption for the MPC7457.
Table 7. Power Consumption for MPC7457
Processor (CPU) Frequency
867 MHz
1000 MHz
1200 MHz
1267 MHz
Unit
Notes
Full-Power Mode
Typical
14.8
15.8
17.5
18.3
W
1, 2
Maximum
21.0
22.0
24.2
25.6
W
1, 3
5.2
5.2
W
1, 2
5.1
5.1
W
1, 2
Nap Mode
Typical
5.2
5.2
Sleep Mode
Typical
5.1
5.1
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Freescale Semiconductor
Electrical and Thermal Characteristics
Table 7. Power Consumption for MPC7457 (continued)
Processor (CPU) Frequency
867 MHz
1000 MHz
1200 MHz
Unit
Notes
W
1, 2
1267 MHz
Deep Sleep Mode (PLL Disabled)
Typical
5.0
5.0
5.0
5.0
Notes:
1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OVDD and
GV DD) or PLL supply power (AVDD). OVDD and GVDD power is system dependent, but is typically <5% of VDD power. Worst
case power consumption for AVDD < 3 mW.
2. Typical power is an average value measured at the nominal recommended VDD (see Table 4) and 65°C while running the
Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.
3. Maximum power is the average measured at nominal VDD and maximum operating junction temperature (see Table 4) while
running an entirely cache-resident, contrived sequence of instructions which keep all the execution units maximally busy.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode. As a
result, power consumption for this mode is not tested.
5.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC7457. After fabrication, functional parts are
sorted by maximum processor core frequency as shown in Section 1.5.2.1, “Clock AC Specifications,” and tested
for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus
(SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core
frequency; see Section 1.11, “Ordering Information.”
5.2.1
Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 6 and represents the tested operating
frequencies of the devices. The maximum system bus frequency, fSYSCLK, given in Table 8 is considered a practical
maximum in a typical single-processor system. The actual maximum SYSCLK frequency for any application of the
MPC7457 will be a function of the AC timings of the MPC7457, the AC timings for the system controller, bus
loading, printed-circuit board topology, trace lengths, and so forth, and may be less than the value given in Table 8.
For information regarding the use of spread spectrum clock generators, see Section 9.1.3, “System Bus Clock
(SYSCLK) and Spread Spectrum Sources.” PLL configuration and bus-to-core multiplier information is found in
Section 9.1.1, “Core Clocks and PLL Configuration.”
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See Table 4.
Maximum Processor Core Frequency
Characteristic
Symbol
867 MHz
1000 MHz
1200 MHz
1267 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Processor frequency
fcore
600
867
600
1000
600
1200
600
1267
MHz
1
VCO frequency
fVCO
1200
1733
1200
2000
1200
2400
1200
2534
MHz
1
fSYSCLK
33
167
33
167
33
167
33
167
MHz
1, 2
SYSCLK frequency
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
15
Electrical and Thermal Characteristics
Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions. See Table 4.
Maximum Processor Core Frequency
Characteristic
Symbol
867 MHz
1000 MHz
1200 MHz
1267 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
SYSCLK cycle time
tSYSCLK
6.0
30
6.0
30
6.0
30
6.0
30
ns
2
SYSCLK rise and fall time
tKR, tKF
—
1.0
—
1.0
—
1.0
—
1.0
ns
3
SYSCLK duty cycle measured
at OVDD/2
tKHKL/
tSYSCLK
40
60
40
60
40
60
40
60
%
4
SYSCLK cycle-to-cycle jitter
—
150
—
150
—
150
—
150
ps
5, 6
Internal PLL relock time
—
100
—
100
—
100
—
100
µs
7
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Configuration,” for valid PLL_CFG[0:4]
settings.
2. Assumes lightly-loaded, single-processor system; see Section 5.2.1, “Clock AC Specifications” for more information.
3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.
4. Timing is guaranteed by design and characterization.
5. Guaranteed by design.
6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at –3 dB.
7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for
PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies
when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Figure 3 provides the SYSCLK input timing diagram.
SYSCLK
VM
VM
VM
CVIH
CVIL
tKHKL
tKR
tKF
tSYSCLK
VM = Midpoint Voltage (OV DD/2)
Figure 3. SYSCLK Input Timing Diagram
5.2.2
Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7457 as defined in Figure 4 and Figure 5.
Timing specifications for the L3 bus are provided in Section 5.2.3, “L3 Clock AC Specifications.”
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Freescale Semiconductor
Electrical and Thermal Characteristics
Table 9. Processor Bus AC Timing Specifications 1
At recommended operating conditions. See Table 4.
Parameter
Symbol
2
All Revisions and
Speed Grades
Unit
Notes
Min
Max
tAVKH
tDVKH
tIVKH
1.8
1.8
1.8
—
—
—
tMVKH
1.8
—
tAXKH
tDXKH
tIXKH
0
0
0
—
—
—
tMXKH
0
—
tKHAV
tKHDV
tKHOV
—
—
—
2.0
2.0
2.0
tKHAX
tKHDX
tKHOX
0.5
0.5
0.5
—
—
—
SYSCLK to output enable
tKHOE
0.5
—
ns
SYSCLK to output high impedance (all except TS, ARTRY,
SHD0, SHD1)
tKHOZ
—
3.5
ns
SYSCLK to TS high impedance after precharge
tKHTSPZ
—
1
tSYSCLK
3, 4, 5
Maximum delay to ARTRY/SHD0/SHD1 precharge
tKHARP
—
1
tSYSCLK
3, 5
6, 7
Input setup times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,
PMON_IN, SHD[0:1], BMODE[0:1],
BMODE[0:1], BVSEL, L3VSEL
Input hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:3],
QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,
HD[0:1]
BMODE[0:1], BVSEL, L3VSEL
Output valid times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT,
PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], TS,
SHD[0:1], WT
Output hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3], GBL, HIT,
PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3], TS,
SHD[0:1], WT
ns
8
ns
8
ns
ns
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
17
Electrical and Thermal Characteristics
Table 9. Processor Bus AC Timing Specifications 1 (continued)
At recommended operating conditions. See Table 4.
Symbol 2
Parameter
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge
tKHARPZ
All Revisions and
Speed Grades
Min
Max
—
2
Unit
Notes
tSYSCLK
3, 5
6, 7
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal
in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input and output timings are measured at
the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and
t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V)
relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from
SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that
the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state
for inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).
3. tsysclk is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged high
before returning to high impedance as shown in Figure 6. The nominal precharge width for TS is 0.5 × tSYSCLK, that is, less
than the minimum tSYSCLK period, to ensure that another master asserting TS on the following clock will not contend with
the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for
precharge.The high-impedance behavior is guaranteed by design.
5. Guaranteed by design and not tested.
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following
AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it
low in the first clock following AACK will then go to high impedance for one clock before precharging it high during the second
cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; that is, it should be high
impedance as shown in Figure 6 before the first opportunity for another master to assert ARTRY. Output valid and output
hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.
7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS.
Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire
cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1
is 1.0 tSYSCLK. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations).
8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These parameters
represent the input setup and hold times for each sample. These values are guaranteed by design and not tested. These
inputs must remain stable after the second sample. See Figure 5 for sample timing.
Figure 4 provides the AC test load for the MPC7457.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 4. AC Test Load
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 5 provides the mode select input timing diagram for the MPC7457.
VM
VM
SYSCLK
HRESET
Mode Signals
2nd Sample
1st Sample
VM = Midpoint Voltage (OVDD/2)
Figure 5. Mode Input Timing Diagram
Figure 6 provides the input/output timing diagram for the MPC7457.
SYSCLK
VM
VM
VM
tAVKH
tIVKH
tMVKH
tAXKH
tIXKH
tMXKH
All Inputs
All Outputs
(Except TS,
ARTRY, SHD0, SHD1)
tKHAV
tKHAX
tKHDV
tKHDX
tKHOV
tKHOX
tKHOE
tKHOZ
All Outputs
(Except TS,
ARTRY, SHD0, SHD1)
tKHTSPZ
tKHTSV
tKHTSX
tKHTSV
TS
tKHARPZ
tKHARV
tKHARP
ARTRY,
SHD0,
SHD1
tKHARX
VM = Midpoint Voltage (OVDD/2)
Figure 6. Input/Output Timing Diagram
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
19
Electrical and Thermal Characteristics
5.2.3
L3 Clock AC Specifications
The L3_CLK frequency is programmed by the L3 configuration register core-to-L3 divisor ratio. See Table 18 for
example core and L3 frequencies at various divisors. Table 10 provides the potential range of L3_CLK output AC
timing specifications as defined in Figure 7.
The maximum L3_CLK frequency is the core frequency divided by two. Given the high core frequencies available
in the MPC7457, however, most SRAM designs will be not be able to operate in this mode using current technology
and, as a result, will select a greater core-to-L3 divisor to provide a longer L3_CLK period for read and write access
to the L3 SRAMs. Therefore, the typical L3_CLK frequency shown in Table 10 is considered to be the practical
maximum in a typical system. The maximum L3_CLK frequency for any application of the MPC7457 will be a
function of the AC timings of the MPC7457, the AC timings for the SRAM, bus loading, and printed-circuit board
trace length, and may be greater or less than the value given in Table 10. Note that SYSCLK input jitter and
L3_CLK[0:1] output jitter are already comprehended in the L3 bus AC timing specifications and do not need to be
separately accounted for in an L3 AC timing analysis. Clock skews, where applicable, do need to be accounted for
in an AC timing analysis.
Freescale is similarly limited by system constraints and cannot perform tests of the L3 interface on a socketed part
on a functional tester at the maximum frequencies of Table 10. Therefore, functional operation and AC timing
information are tested at core-to-L3 divisors which result in L3 frequencies at 250 MHz or lower.
Table 10. L3_CLK Output AC Timing Specifications
At recommended operating conditions. See Table 4.
Device Revision (L3 I/O Voltage) 6
Parameter
Symbol
Rev 1.1. (All I/O Modes)
Rev 1.2 (1.5-V I/O Mode)
Rev 1.2
(1.8-, 2.5-V I/O Modes)
Min
Typ
Max
Min
Typ
Max
Unit
Notes
L3 clock frequency
fL3_CLK
—
200
—
—
250
—
MHz
1
L3 clock cycle time
tL3_CLK
—
5.0
—
—
4.0
—
ns
1
L3 clock duty cycle
tCHCL/tL3_CLK
—
50
—
—
50
—
%
2
L3 clock output-to-output skew
(L3_CLK0 to L3_CLK1)
tL3CSKW1
—
—
100
—
—
100
ps
3
L3 clock output-to-output skew
(L3_CLK[0:1] to
L3_ECHO_CLK[1,3])
tL3CSKW2
—
—
100
—
—
100
ps
4
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
20
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 10. L3_CLK Output AC Timing Specifications (continued)
At recommended operating conditions. See Table 4.
Device Revision (L3 I/O Voltage) 6
Parameter
Symbol
Rev 1.1. (All I/O Modes)
Rev 1.2 (1.5-V I/O Mode)
Rev 1.2
(1.8-, 2.5-V I/O Modes)
Min
Typ
Max
Min
Typ
Max
—
—
± 75
—
—
± 75
L3 clock jitter
Unit
Notes
ps
5
Notes:
1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependent. See Section 5.2.3, “L3 Clock
AC Specifications,” for an explanation that this maximum frequency is not functionally tested at speed by Freescale. The
minimum L3 clock frequency and period are fSYSCLK and tSYSCLK, respectively.
2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control signals which
are common to both SRAM chips in the L3.
4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for PB2 or
Late Write SRAM. This parameter is critical to the read data signals because the processor uses the feedback loop to latch
data driven from the SRAM, each of which drives data based on L3_CLK0 or L3_CLK1.
5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address, data, and
control signals equally and, therefore, is already comprehended in the AC timing and does not have to be considered in the
L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period caused by supply voltage
noise or thermal effects. This is also comprehended in the AC timing specifications and need not be considered in the L3
timing analysis.
6. L3 I/O voltage mode must be configured by L3VSEL as described in Table 3, and voltage supplied at GVDD must match
mode selected as specified in Table 4. See Table 23 for revision level information and part marking.
The L3_CLK timing diagram is shown in Figure 7.
tL3_CLK
tCHCL
tL3CR
L3_CLK0
VM
VM
VM
L3_CLK1
VM
VM
VM
tL3CF
VM
tL3CSKW1
For PB2 or Late Write:
L3_ECHO_CLK1
VM
VM
VM
VM
tL3CSKW2
L3_ECHO_CLK3
VM
VM
VM
VM
tL3CSKW2
Figure 7. L3_CLK_OUT Output Timing Diagram
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
21
Electrical and Thermal Characteristics
5.2.4
L3 Bus AC Specifications
The MPC7457 L3 interface supports three different types of SRAM: source-synchronous, double data rate (DDR)
MSUG2 SRAM, Late Write SRAMs, and pipeline burst (PB2) SRAMs. Each requires a different protocol on the L3
interface and a different routing of the L3 clock signals. The type of SRAM is programmed in L3CR[22:23] and the
MPC7457 then follows the appropriate protocol for that type. The designer must connect and route the L3 signals
appropriately for each type of SRAM. Following are some observations about the L3 interface.
•
•
•
•
•
•
The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7], and
L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched.
For 1-Mbyte of SRAM, use L3_ADDR[16:0] (L3_ADDR[0] is LSB)
For 2-Mbyte of SRAM, use L3_ADDR[17:0] (L3_ADDR[0] is LSB)
For 4-Mbyte of SRAM, use L3_ADDR[18:0] (L3_ADDR[0] is LSB)
No pull-up resistors are required for the L3 interface
For high-speed operations, L3 interface address and control signals should be a ‘T’ with minimal stubs to
the two loads; data and clock signals should be point-to-point to their single load. Figure 8 shows the AC
test load for the L3 interface.
Output
Z0 = 50 Ω
RL = 50 Ω
GVDD/2
Figure 8. AC Test Load for the L3 Interface
In general, if routing is short, delay-matched, and designed for incident wave reception and minimal reflection, there
is a high probability that the AC timing of the MPC7457 L3 interface will meet the maximum frequency operation
of appropriately chosen SRAMs. This is despite the pessimistic, guard-banded AC specifications (see Table 12,
Table 13, and Table 14), the limitations of functional testers described in Section 5.2.3, “L3 Clock AC
Specifications,” and the uncertainty of clocks and signals which inevitably make worst-case critical path timing
analysis pessimistic.
More specifically, certain signals within groups should be delay-matched with others in the same group while
intergroup routing is less critical. Only the address and control signals are common to both SRAMs and additional
timing margin is available for these signals. The double-clocked data signals are grouped with individual clocks as
shown in Figure 9 or Figure 11, depending on the type of SRAM. For example, for the MSUG2 DDR SRAM (see
Figure 9); L3DATA[0:31], L3DP[0:3], and L3_CLK[0] form a closely coupled group of outputs from the MPC7457;
while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0] form a closely coupled group of inputs.
The MPC7450 RISC Microprocessor Family User’s Manual refers to logical settings called ‘sample points’ used in
the synchronization of reads from the receive FIFO. The computation of the correct value for this setting is
system-dependent and is described in the MPC7450 RISC Microprocessor Family User’s Manual. Three
specifications are used in this calculation and are given in Table 11. It is essential that all three specifications are
included in the calculations to determine the sample points, as incorrect settings can result in errors and
unpredictable behavior. For more information, see the MPC7450 RISC Microprocessor Family User’s Manual.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Electrical and Thermal Characteristics
Table 11. Sample Points Calculation Parameters
Parameter
Symbol
Max
Unit
Notes
Delay from processor clock to internal_L3_CLK
tAC
3/4
tL3_CLK
1
Delay from internal_L3_CLK to L3_CLK[n] output pins
tCO
3
ns
2
Delay from L3_ECHO_CLK[n] to receive latch
tECI
3
ns
3
Notes:
1. This specification describes a logical offset between the internal clock edge used to launch the L3 address and control
signals (this clock edge is phase-aligned with the processor clock edge) and the internal clock edge used to launch the
L3_CLK[n] signals. With proper board routing, this offset ensures that the L3_CLK[n] edge will arrive at the SRAM within a
valid address window and provide adequate setup and hold time. This offset is reflected in the L3 bus interface AC timing
specifications, but must also be separately accounted for in the calculation of sample points and, thus, is specified here.
2. This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding rising or falling
edge at the L3CLK[n] pins.
3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to data valid and ready to be sampled from
the FIFO.
5.2.4.1
Effects of L3OHCR Settings on L3 Bus AC Specifications
The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control Register (L3OCHR). Each
field controls the timing for a group of signals. The AC timing specifications presented herein represent the AC
timing when the register contains the default value of 0x0000_0000. Incrementing a field delays the associated
signals, increasing the output valid time and hold time of the affected signals. In the special case of delaying an
L3_CLK signal, the net effect is to decrease the output valid and output hold times of all signals being latched
relative to that clock signal. The amount of delay added is summarized in Table 12. Note that these settings affect
output timing parameters only and do not impact input timing parameters of the L3 bus in any way.
Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing
At recommended operating conditions. See Table 4.
Output Valid Time
Field
Name1
Affected Signals
Value
L3_ADDR[18:0],
L3_CNTL[0:1]
0b00
L3AOH
L3CLKn_OH
All signals latched by
SRAM connected to
L3_CLKn
Output Hold Time
Parameter
Parameter
Change 3
Change 3
Symbol 2
Symbol 2
tL3CHOV
0
tL3CHOX
0
0b01
+50
+50
0b10
+100
+100
0b11
+150
+150
0b000
0b001
tL3CHOV,
tL3CHDV,
tL3CLDV
0
– 50
tL3CHOX,
tL3CHDX,
tL3CLDX,
0
Unit
Notes
ps
4
ps
4
– 50
5
0b010
– 100
– 100
5
0b011
– 150
– 150
5
0b100
– 200
– 200
5
0b101
– 250
– 250
5
0b110
– 300
– 300
5
0b111
– 350
– 350
5
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Electrical and Thermal Characteristics
Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing (continued)
At recommended operating conditions. See Table 4.
Output Valid Time
Field Name
L3DOHn
1
Affected Signals
Value
L3_DATA[n:n+7],
L3_DP[n/8]
0b000
0b001
Output Hold Time
Parameter
Parameter
Change 3
Change 3
Symbol 2
Symbol 2
tL3CHDV,
tL3CLDV
0
+ 50
tL3CHDX,
tL3CLDX,
0
Unit
Notes
ps
4
+ 50
0b010
+ 100
+ 100
0b011
+ 150
+ 150
0b100
+ 200
+ 200
0b101
+ 250
+ 250
0b111
+ 300
+ 300
0b111
+ 350
+ 350
Notes:
1. See the MPC7450 RISC Microprocessor Family User’s Manual for specific information regarding L3OHCR.
2. See Table 13 and Table 14 for more information.
3. Approximate delay verified by simulation; not tested or characterized.
4. Default value.
5. Increasing values of L3CLKn_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold times
of all signals latched relative to that clock signal by the SRAM; see Figure 9 and Figure 11.
5.2.4.2
L3 Bus AC Specifications for DDR MSUG2 SRAMs
When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as shown in Figure 9. Outputs
from the MPC7457 are actually launched on the edges of an internal clock phase-aligned to SYSCLK (adjusted for
core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock output with 90° phase delay, so
outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid times are typically negative when
referenced to L3_CLKn because the data is launched one-quarter period before L3_CLKn to provide adequate setup
time at the SRAM after the delay-matched address, control, data, and L3_CLKn signals have propagated across the
printed-wiring board.
Inputs to the MPC7457 are source-synchronous with the CQ clock generated by the DDR MSUG2 SRAMs. These
CQ clocks are received on the L3_ECHO_CLKn inputs of the MPC7457. An internal circuit delays the incoming
L3_ECHO_CLKn signal such that it is positioned within the valid data window at the internal receiving latches. This
delayed clock is used to capture the data into these latches which comprise the receive FIFO. This clock is
asynchronous to all other processor clocks. This latched data is subsequently read out of the FIFO synchronously to
the processor clock. The time between writing and reading the data is set by the using the sample point settings
defined in the L3CR register.
Table 13 provides the L3 bus interface AC timing specifications for the configuration as shown in Figure 9,
assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Electrical and Thermal Characteristics
Table 13. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See Table 4.
Device Revision (L3 I/O Voltage) 9
Parameter
Symbol
Rev 1.1. (All I/O Modes)
Rev 1.2 (1.5-V I/O Mode)
Rev 1.2
(1.8-, 2.5-V I/O Modes)
Unit
Notes
Min
Max
Min
Max
tL3CR, tL3CF
—
0.75
—
0.75
ns
1
Setup times: Data and parity
tL3DVEH,
tL3DVEL
(– tL3CLK/4)
+ 0.90
—
(– tL3CLK/4)
+ 0.70
—
ns
2, 3, 4
Input hold times: Data and parity
tL3DXEH,
tL3DXEL
(tL3CLK/4)
+ 0.85
—
(tL3CLK/4)
+ 0.70
—
ns
2, 4
Valid times: Data and parity
tL3CHDV,
tL3CLDV
—
(– tL3CLK/4)
+ 0.60
—
(– tL3CLK/4)
+ 0.50
ns
5, 6,
7, 8
Valid times: All other outputs
tL3CHOV
—
(tL3CLK/4)
+ 0.65
—
(tL3CLK/4)
+ 0.65
ns
5, 7, 8
Output hold times: Data and parity
tL3CHDX,
tL3CLDX,
(tL3CLK/4)
– 0.60
—
(tL3CLK/4)
– 0.50
—
ns
5, 6,
7, 8
Output hold times: All other outputs
tL3CHOX
(tL3CLK/4)
– 0.50
—
(tL3CLK/4)
– 0.50
—
ns
5, 7, 8
L3_CLK to high impedance: Data
and parity
tL3CLDZ
—
(– tL3CLK/4)
+ 0.60
—
(– tL3CLK/4)
+ 0.60
ns
L3_CLK to high impedance: All
other outputs
tL3CHOZ
—
(tL3CLK/4)
+ 0.65
—
(tL3CLK/4)
+ 0.65
ns
L3_CLK rise and fall time
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the
rising or falling edge of the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10. For consistency with other
input setup time specifications, this will be treated as negative input setup time.
4. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the MPC7457 can latch an input signal that is
valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising)
edges of L3_ECHO_CLKn at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge
of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume
a purely resistive 50-Ω load (see Figure 8).
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10. For consistency with other output
valid time specifications, this will be treated as negative output valid time.
7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched
by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid and output hold
times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock
before the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.
8. Assumes default value of L3OHCR. See Section 5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC Specifications,” for
more information.
9. L3 I/O voltage mode must be configured by L3VSEL as described in Table 3, and voltage supplied at GVDD must match
mode selected as specified in Table 4. See Table 23 for revision level information and part marking.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Electrical and Thermal Characteristics
Figure 9 shows the typical connection diagram for the MPC7457 interfaced to MSUG2 DDR SRAMs.
L3ADDR[18:0]
MPC7457
L3_CNTL[0]
L3_CNTL[1]
Denotes
Receive (SRAM
to MPC7457)
Aligned Signals
L3_ECHO_CLK[0]
{L3DATA[0:15], L3DP[0:1]}
L3_CLK[0]
{L3DATA[16:31], L3DP[2:3]}
L3_ECHO_CLK[1]
Denotes
Transmit
(MPC7457 to
SRAM)
Aligned Signals
L3ECHO_CLK[2]
{L3_DATA[32:47], L3DP[4:5]}
L3_CLK[1]
{L3DATA[48:63], L3DP[6:7]}
L3_ECHO_CLK[3]
SRAM 0
SA[18:0]
B1
B3
GND
G
GND
LBO
GND
B2
CQ
CQ
NC
CK
CQ
NC
D[18:35]
CK
GVDD/2 1
D[0:17]
CQ
SRAM 1
SA[18:0]
B3
B1
G
B2
GND
CQ
GND
LBO
GND
D[0:17]
CQ
NC
CK
CQ
NC
D[18:35]
CK
GVDD/2 1
CQ
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
Figure 9. Typical Source Synchronous 4-Mbyte L3 Cache DDR Interface
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Electrical and Thermal Characteristics
Figure 10 shows the L3 bus timing diagrams for the MPC7457 interfaced to MSUG2 SRAMs.
Outputs
L3_CLK[0,1]
VM
VM
tL3CHOV
VM
VM
VM
tL3CHOZ
tL3CHOX
ADDR, L3CNTL
tL3CLDV
tL3CLDZ
tL3CHDV
L3DATA WRITE
tL3CHDX
tL3CLDX
Note: tL3CHDV and tL3CLDV as drawn here will be negative numbers, that is, output valid time will be
time before the clock edge.
Inputs
L3_ECHO_CLK[0,1,2,3]
VM
VM
VM
VM
tL3DVEL
VM
tL3DXEL
tL3DVEH
L3 Data and Data
Parity Inputs
tL3DXEH
Note: tL3DVEH and tL3DVEL as drawn here are negative numbers, that is, input setup time is
time after the clock edge.
VM = Midpoint Voltage (GVDD/2)
Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
5.2.4.3
L3 Bus AC Specifications for PB2 and Late Write SRAMs
When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as shown in Figure 11.
These SRAMs are synchronous to the MPC7457; one L3_CLKn signal is output to each SRAM to latch address,
control, and write data. Read data is launched by the SRAM synchronous to the delayed L3_CLKn signal it received.
The MPC7457 needs a copy of that delayed clock which launched the SRAM read data to know when the returning
data will be valid. Therefore, L3_ECHO_CLK1 and L3_ECHO_CLK3 must be routed halfway to the SRAMs and
returned to the MPC7457 inputs L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively. Thus, L3_ECHO_CLK0
and L3_ECHO_CLK2 are phase-aligned with the input clock received at the SRAMs. The MPC7457 will latch the
incoming data on the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.
Table 14 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11, assuming
the timing relationships of Figure 12 and the loading of Figure 8.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Electrical and Thermal Characteristics
Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
Parameter
Symbol
All Revisions and L3 I/O
Voltage Modes
Unit
Notes
Min
Max
tL3CR, tL3CF
—
0.75
ns
1, 2
Setup times: Data and parity
tL3DVEH
0.1
—
ns
2, 3
Input hold times: Data and parity
tL3DXEH
—
0.7
ns
2, 3
Valid times: Data and parity
tL3CHDV
—
2.5
ns
2, 4, 5
Valid times: All other outputs
tL3CHOV
—
1.8
ns
5
Output hold times: Data and parity
tL3CHDX
1.4
—
ns
2, 4, 5
Output hold times: All other outputs
tL3CHOX
1.0
—
ns
2, 5
L3_CLK to high impedance: Data and parity
tL3CHDZ
—
3.0
ns
2
L3_CLK to high impedance: All other outputs
tL3CHOZ
—
3.0
ns
2
L3_CLK rise and fall time
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. Timing behavior and characterization are currently being evaluated.
3. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.
4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Figure 10).
5. Assumes default value of L3OHCR. See Section 5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC Specifications,” for
more information.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 11 shows the typical connection diagram for the MPC7457 interfaced to PB2 SRAMs or Late Write SRAMs.
MPC7457
L3_ADDR[16:0]
L3_CNTL[0]
L3_CNTL[1]
Denotes
Receive (SRAM
to MPC7457)
Aligned Signals
L3_ECHO_CLK[0]
{L3_DATA[0:15], L3_DP[0:1]}
L3_CLK[0]
{L3_DATA[16:31], L3_DP[2:3]}
Denotes
Transmit
(MPC7457 to
SRAM)
Aligned Signals
SRAM 0
SA[16:0]
SS
SW
DQ[0:17]
ZZ
GND
K
G
GND
DQ[18:36]
K
GVDD/2 1
L3_ECHO_CLK[1]
SRAM 1
SA[16:0]
SS
L3_ECHO_CLK[2]
{L3_DATA[32:47], L3_DP[4:5]}
L3_CLK[1]
{L3_DATA[48:63], L3_DP[6:7]}
SW
ZZ
GND
K
G
GND
DQ[18:36]
K
GV DD/2 1
DQ[0:17]
L3_ECHO_CLK[3]
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
Figure 11. Typical Synchronous 1-MByte L3 Cache Late Write or PB2 Interface
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
29
Electrical and Thermal Characteristics
Figure 12 shows the L3 bus timing diagrams for the MPC7457 interfaced to PB2 or Late Write SRAMs.
Outputs
L3_CLK[0,1]
L3_ECHO_CLK[1,3]
VM
VM
tL3CHOX
tL3CHOV
ADDR, L3_CNTL
tL3CHOZ
tL3CHDV
tL3CHDX
L3DATA WRITE
tL3CHDZ
Inputs
L3_ECHO_CLK[0,2]
VM
tL3DVEH
tL3DXEH
Parity Inputs
L3 Data and Data
VM = Midpoint Voltage (GVDD/2)
Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs
5.2.5
IEEE 1149.1 AC Timing Specifications
Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14 through Figure 17.
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Unit
TCK frequency of operation
fTCLK
0
33.3
MHz
TCK cycle time
tTCLK
30
—
ns
TCK clock pulse width measured at 1.4 V
tJHJL
15
—
ns
tJR and tJF
0
2
ns
TRST assert time
tTRST
25
—
ns
2
Input setup times:
Boundary-scan data
TMS, TDI
ns
3
tDVJH
tIVJH
4
0
—
—
Input hold times:
Boundary-scan data
TMS, TDI
ns
3
tDXJH
tIXJH
20
25
—
—
Valid times:
Boundary-scan data
TDO
ns
4
tJLDV
tJLOV
4
4
20
25
TCK rise and fall times
Notes
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
30
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Output hold times:
Boundary-scan data
TDO
tJLDX
tJLOX
30
30
—
—
TCK to output high impedance:
Boundary-scan data
TDO
tJLDZ
tJLOZ
3
3
19
9
Unit
Notes
ns
4
ns
4, 5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 13).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Figure 13 provides the AC test load for TDO and the boundary-scan outputs of the MPC7457.
Z0 = 50 Ω
Output
RL = 50 Ω
OVDD/2
Figure 13. Alternate AC Test Load for the JTAG Interface
Figure 14 provides the JTAG clock input timing diagram.
TCLK
VM
VM
VM
tJHJL
tJR
tJF
tTCLK
VM = Midpoint Voltage (OVDD/2)
Figure 14. JTAG Clock Input Timing Diagram
Figure 15 provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 15. TRST Timing Diagram
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
31
Electrical and Thermal Characteristics
Figure 16 provides the boundary-scan timing diagram.
TCK
VM
VM
tDVJH
tDXJH
Boundary
Data Inputs
Input
Data Valid
tJLDV
tJLDX
Boundary
Data Outputs
Output Data Valid
tJLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 16. Boundary-Scan Timing Diagram
Figure 17 provides the test access port timing diagram.
TCK
VM
VM
tIVJH
tIXJH
Input
Data Valid
TDI, TMS
tJLOV
tJLOX
Output Data Valid
TDO
tJLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 17. Test Access Port Timing Diagram
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
32
Freescale Semiconductor
Pin Assignments
6
Pin Assignments
Figure 18 (Part A) shows the pinout of the MPC7447, 360 CBGA package as viewed from the top surface. Part B
shows the side profile of the CBGA package to indicate the direction of the top surface view.
Part A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Not to Scale
Part B
Substrate Assembly
Encapsulant
View
Die
Figure 18. Pinout of the MPC7447, 360 CBGA Package as Viewed from the Top Surface
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
33
Pin Assignments
Figure 19 (Part A) shows the pinout of the MPC7457, 483 CBGA package as viewed from the top surface. Part B
shows the side profile of the CBGA package to indicate the direction of the top surface view.
Part A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Not to Scale
Part B
Substrate Assembly
Encapsulant
View
Die
Figure 19. Pinout of the MPC7457, 483 CBGA Package as Viewed from the Top Surface
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
34
Freescale Semiconductor
Pinout Listings
7
Pinout Listings
Table 16 provides the pinout listing for the MPC7447, 360 CBGA package. Table 17 provides the pinout listing for
the MPC7457, 483 CBGA package.
NOTE
This pinout is not compatible with the MPC750, MPC7400, or MPC7410 360 BGA
package.
Table 16. Pinout Listing for the MPC7447, 360 CBGA Package
Pin Number
Active
I/O
I/F Select 1
Notes
A[0:35]
E11, H1, C11, G3, F10, L2, D11, D1, C10, G2, D12, L3,
G4, T2, F4, V1, J4, R2, K5, W2, J2, K4, N4, J3, M5, P5,
N3, T1, V2, U1, N5, W1, B12, C4, G10, B11
High
I/O
BVSEL
2
AACK
R1
Low
Input
BVSEL
AP[0:4]
C1, E3, H6, F5, G7
High
I/O
BVSEL
ARTRY
N2
Low
I/O
BVSEL
AV DD
A8
—
Input
N/A
BG
M1
Low
Input
BVSEL
BMODE0
G9
Low
Input
BVSEL
4
BMODE1
F8
Low
Input
BVSEL
5
BR
D2
Low
Output
BVSEL
BVSEL
B7
High
Input
BVSEL
1, 6
CI
J1
Low
Output
BVSEL
3
CKSTP_IN
A3
Low
Input
BVSEL
CKSTP_OUT
B1
Low
Output
BVSEL
CLK_OUT
H2
High
Output
BVSEL
D[0:63]
R15, W15, T14, V16, W16, T15, U15, P14, V13, W13,
T13, P13, U14, W14, R12, T12, W12, V12, N11, N10,
R11, U11, W11, T11, R10, N9, P10, U10, R9, W10, U9,
V9, W5, U6, T5, U5, W7, R6, P7, V6, P17, R19, V18,
R18, V19, T19, U19, W19, U18, W17, W18, T16, T18,
T17, W3, V17, U4, U8, U7, R7, P6, R8, W8, T8
High
I/O
BVSEL
DBG
M2
Low
Input
BVSEL
DP[0:7]
T3, W4, T4, W9, M6, V3, N8, W6
High
I/O
BVSEL
DRDY
R3
Low
Output
BVSEL
7
DTI[0:3]
G1, K1, P1, N1
High
Input
BVSEL
8
EXT_QUAL
A11
High
Input
BVSEL
9
GBL
E2
Low
I/O
BVSEL
Signal Name
3
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
35
Pinout Listings
Table 16. Pinout Listing for the MPC7447, 360 CBGA Package (continued)
Pin Number
Active
I/O
I/F Select 1
GND
B5, C3, D6, D13, E17, F3, G17, H4, H7, H9, H11, H13,
J6, J8, J10, J12, K7, K3, K9, K11, K13, L6, L8, L10, L12,
M4, M7, M9, M11, M13, N7, P3, P9, P12, R5, R14, R17,
T7, T10, U3, U13, U17, V5, V8, V11, V15
—
—
N/A
HIT
B2
Low
Output
BVSEL
HRESET
D8
Low
Input
BVSEL
INT
D4
Low
Input
BVSEL
L1_TSTCLK
G8
High
Input
BVSEL
9
L2_TSTCLK
B3
High
Input
BVSEL
10
No Connect
A6, A13, A14, A15, A16, A17, A18, A19, B13, B14, B15,
B16, B17, B18, B19, C13, C14, C15, C16, C17, C18,
C19, D14, D15, D16, D17, D18, D19, E12, E13, E14,
E15, E16, E19, F12, F13, F14, F15, F16, F17, F18, F19,
G11, G12, G13, G14, G15, G16, G19, H14, H15, H16,
H17, H18, H19, J14, J15, J16, J17, J18, J19, K15, K16,
K17, K18, K19, L14, L15, L16, L17, L18, L19, M14, M15,
M16, M17, M18, M19, N12, N13, N14, N15, N16, N17,
N18, N19, P15, P16, P18, P19
—
—
—
11
LSSD_MODE
E8
Low
Input
BVSEL
6, 12
MCP
C9
Low
Input
BVSEL
OV DD
B4, C2, C12, D5, E18, F2, G18, H3, J5, K2, L5, M3, N6,
P2, P8, P11, R4, R13, R16, T6, T9, U2, U12, U16, V4, V7,
V10, V14
—
—
N/A
PLL_CFG[0:4]
B8, C8, C7, D7, A7
High
Input
BVSEL
PMON_IN
D9
Low
Input
BVSEL
PMON_OUT
A9
Low
Output
BVSEL
QACK
G5
Low
Input
BVSEL
QREQ
P4
Low
Output
BVSEL
SHD[0:1]
E4, H5
Low
I/O
BVSEL
SMI
F9
Low
Input
BVSEL
SRESET
A2
Low
Input
BVSEL
SYSCLK
A10
—
Input
BVSEL
TA
K6
Low
Input
BVSEL
TBEN
E1
High
Input
BVSEL
TBST
F11
Low
Output
BVSEL
TCK
C6
High
Input
BVSEL
TDI
B9
High
Input
BVSEL
TDO
A4
High
Output
BVSEL
Signal Name
Notes
7
13
3
6
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
36
Freescale Semiconductor
Pinout Listings
Table 16. Pinout Listing for the MPC7447, 360 CBGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Select 1
Low
Input
BVSEL
Notes
TEA
L1
TEST[0:3]
A12, B6, B10, E10
—
Input
BVSEL
12
TEST[4]
D10
—
Input
BVSEL
9
TMS
F1
High
Input
BVSEL
6
TRST
A5
Low
Input
BVSEL
6, 14
TS
L4
Low
I/O
BVSEL
3
TSIZ[0:2]
G6, F7, E7
High
Output
BVSEL
TT[0:4]
E5, E6, F6, E9, C5
High
I/O
BVSEL
WT
D3
Low
Output
BVSEL
VDD
H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7,
L9, L11, L13, M8, M10, M12
—
—
N/A
3
Notes:
1. OV DD supplies power to the processor bus, JTAG, and all control signals; and VDD supplies power to the processor core
and the PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8 V) or
to HRESET (selects 2.5 V). If used, the pull-down resistor should be less than 250 Ω. For actual recommended value of Vin
or supply voltages see Table 4.
2. Unused address pins must be pulled down to GND.
3. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state after
they have been actively negated and released by the MPC7447 and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
5. This signal must be negated during reset, by pull up to OVDD or negation by ¬HRESET (inverse of HRESET), to ensure
proper operation.
6. Internal pull up on die.
7. Ignored in 60x bus mode.
8. These signals must be pulled down to GND if unused, or if the MPC7447 is in 60x bus mode.
9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10. This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.
11. These signals are for factory use only and must be left unconnected for normal machine operation.
12. These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
13. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
14. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package
Pin Number
Active
I/O
I/F Select 1
Notes
A[0:35]
E10, N4, E8, N5, C8, R2, A7, M2, A6, M1, A10, U2,
N2, P8, M8, W4, N6, U6, R5, Y4, P1, P4, R6, M7, N7,
AA3, U4, W2, W1, W3, V4, AA1, D10, J4, G10, D9
High
I/O
BVSEL
2
AACK
U1
Low
Input
BVSEL
AP[0:4]
L5, L6, J1, H2, G5
High
I/O
BVSEL
ARTRY
T2
Low
I/O
BVSEL
Signal Name
3
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
37
Pinout Listings
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Select 1
Notes
AV DD
B2
—
Input
N/A
BG
R3
Low
Input
BVSEL
BMODE0
C6
Low
Input
BVSEL
4
BMODE1
C4
Low
Input
BVSEL
5
BR
K1
Low
Output
BVSEL
BVSEL
G6
High
Input
N/A
6, 7
CI
R1
Low
Output
BVSEL
3
CKSTP_IN
F3
Low
Input
BVSEL
CKSTP_OUT
K6
Low
Output
BVSEL
CLK_OUT
N1
High
Output
BVSEL
D[0:63]
AB15, T14, R14, AB13, V14, U14, AB14, W16, AA11,
Y11, U12, W13, Y14, U13, T12, W12, AB12, R12,
AA13, AB11, Y12, V11, T11, R11, W10, T10, W11,
V10, R10, U10, AA10, U9, V7, T8, AB4, Y6, AB7,
AA6, Y8, AA7, W8, AB10, AA16, AB16, AB17, Y18,
AB18, Y16, AA18, W14, R13, W15, AA14, V16, W6,
AA12, V6, AB9, AB6, R7, R9, AA9, AB8, W9
High
I/O
BVSEL
DBG
V1
Low
Input
BVSEL
DP[0:7]
AA2, AB3, AB2, AA8, R8, W5, U8, AB5
High
I/O
BVSEL
DRDY
T6
Low
Output
BVSEL
8
DTI[0:3])
P2, T5, U3, P6
High
Input
BVSEL
9
EXT_QUAL
B9
High
Input
BVSEL
10
GBL
M4
Low
I/O
BVSEL
GND
A22, B1, B5, B12, B14, B16, B18, B20, C3, C9, C21,
D7, D13, D15, D17, D19, E2, E5, E21, F10, F12, F14,
F16, F19, G4, G7, G17, G21, H13, H15, H19, H5, J3,
J10, J12, J14, J17, J21, K5, K9, K11, K13, K15, K19,
L10, L12, L14, L17, L21, M3, M6, M9, M11, M13,
M19, N10, N12, N14, N17, N21, P3, P9, P11, P13,
P15, P19, R17, R21, T13, T15, T19, T4, T7, T9, U17,
U21, V2, V5, V8, V12, V15, V19, W7, W17, W21, Y3,
Y9, Y13, Y15, Y20, AA5, AA17, AB1, AB22
—
—
N/A
GV DD
B13, B15, B17, B19, B21, D12, D14, D16, D18, D21,
E19, F13, F15, F17, F21, G19, H12, H14, H17, H21,
J19, K17, K21, L19, M17, M21, N19, P17, P21, R15,
R19, T17, T21, U19, V17, V21, W19, Y21
—
—
N/A
11
HIT
K2
Low
Output
BVSEL
8
HRESET
A3
Low
Input
BVSEL
INT
J6
Low
Input
BVSEL
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
38
Freescale Semiconductor
Pinout Listings
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Select 1
Notes
L1_TSTCLK
H4
High
Input
BVSEL
10
L2_TSTCLK
J2
High
Input
BVSEL
12
L3VSEL
A4
High
Input
N/A
6, 7
L3ADDR[18:0]
H11, F20, J16, E22, H18, G20, F22, G22, H20, K16,
J18, H22, J20, J22, K18, K20, L16, K22, L18
High
Output
L3VSEL
L3_CLK[0:1]
V22, C17
High
Output
L3VSEL
L3_CNTL[0:1]
L20, L22
Low
Output
L3VSEL
L3DATA[0:63]
AA19, AB20, U16, W18, AA20, AB21, AA21, T16,
W20, U18, Y22, R16, V20, W22, T18, U20, N18, N20,
N16, N22, M16, M18, M20, M22, R18, T20, U22, T22,
R20, P18, R22, M15, G18, D22, E20, H16, C22, F18,
D20, B22, G16, A21, G15, E17, A20, C19, C18, A19,
A18, G14, E15, C16, A17, A16, C15, G13, C14, A14,
E13, C13, G12, A13, E12, C12
High
I/O
L3VSEL
L3DP[0:7]
AB19, AA22, P22, P16, C20, E16, A15, A12
High
I/O
L3VSEL
L3_ECHO_CLK[0,2]
V18, E18
High
Input
L3VSEL
L3_ECHO_CLK[1,3]
P20, E14
HIgh
I/O
L3VSEL
LSSD_MODE
F6
Low
Input
BVSEL
MCP
B8
Low
Input
BVSEL
No Connect
A8, A11, B6, B11, C11, D11, D3, D5, E11, E7, F2, F11,
G2, H9
—
—
N/A
OV DD
B3, C5, C7, C10, D2, E3, E9, F5, G3, G9, H7, J5, K3,
L7, M5, N3, P7, R4, T3, U5, U7, U11, U15, V3, V9,
V13, Y2, Y5, Y7, Y10, Y17, Y19, AA4, AA15
—
—
N/A
PLL_CFG[0:4]
A2, F7, C2, D4, H8
High
Input
BVSEL
PMON_IN
E6
Low
Input
BVSEL
PMON_OUT
B4
Low
Output
BVSEL
QACK
K7
Low
Input
BVSEL
QREQ
Y1
Low
Output
BVSEL
SHD[0:1]
L4, L8
Low
I/O
BVSEL
SMI
G8
Low
Input
BVSEL
SRESET
G1
Low
Input
BVSEL
SYSCLK
D6
—
Input
BVSEL
TA
N8
Low
Input
BVSEL
TBEN
L3
High
Input
BVSEL
TBST
B7
Low
Output
BVSEL
TCK
J7
High
Input
BVSEL
7, 13
14
15
3
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
39
Pinout Listings
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Select 1
Notes
7
TDI
E4
High
Input
BVSEL
TDO
H1
High
Output
BVSEL
TEA
T1
Low
Input
BVSEL
TEST[0:5]
B10, H6, H10, D8, F9, F8
—
Input
BVSEL
13
TEST[6]
A9
—
Input
BVSEL
10
TMS
K4
High
Input
BVSEL
7
TRST
C1
Low
Input
BVSEL
7, 16
TS
P5
Low
I/O
BVSEL
3
TSIZ[0:2]
L1,H3,D1
High
Output
BVSEL
TT[0:4]
F1, F4, K8, A5, E1
High
I/O
BVSEL
WT
L2
Low
Output
BVSEL
VDD
J9, J11, J13, J15, K10, K12, K14, L9, L11, L13, L15,
M10, M12, M14, N9, N11, N13, N15, P10, P12, P14
—
—
N/A
VDD_SENSE[0:1]
G11, J8
—
—
N/A
3
17
Notes:
1. OV DD supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls (L3CTL[0:1]); GVDD
supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3], and
L3_CLK[0:1]) and the L3 control signals L3_CNTL[0:1]; and VDD supplies power to the processor core and the PLL (after
filtering to become AVDD). For actual recommended value of Vin or supply voltages, see Table 4.
2. Unused address pins must be pulled down to GND.
3. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state after
they have been actively negated and released by the MPC7457 and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
5. This signal must be negated during reset, by pull up to OVDD or negation by ¬HRESET (inverse of HRESET), to ensure
proper operation.
6. See Table 3 for bus voltage configuration information. If used, pull-down resistors should be less than 250 Ω .
7. Internal pull up on die.
8. Ignored in 60x bus mode.
9. These signals must be pulled down to GND if unused or if the MPC7457 is in 60x bus mode.
10. These input signals for factory use only and must be pulled down to GND for normal machine operation.
11. Power must be supplied to GVDD, even when the L3 interface is disabled or unused.
12. This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.
13. These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
14. These signals are for factory use only and must be left unconnected for normal machine operation.
15. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
16. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
17. These pins are internally connected to VDD. They are intended to allow an external device to detect the core voltage level
present at the processor core. If unused, they must be connected directly to VDD or left unconnected.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
40
Freescale Semiconductor
Package Description
8
Package Description
The following sections provide the package parameters and mechanical dimensions for the CBGA package.
8.1
Package Parameters for the MPC7447, 360 CBGA
The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360-lead ceramic
ball grid array (CBGA).
Package outline
Interconnects
Pitch
Minimum module height
Maximum module height
Ball diameter
8.2
25 × 25 mm
360 (19 × 19 ball array – 1)
1.27 mm (50 mil)
2.72 mm
3.24 mm
0.89 mm (35 mil)
Mechanical Dimensions for the MPC7447, 360 CBGA
Figure 20 provides the mechanical dimensions and bottom surface nomenclature for the MPC7447, 360 CBGA
package.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
41
Package Description
2X
0.2
D
Capacitor Region
B
D1
D3
A1 CORNER
D2
A
1
0.15 A
E3
NOTES:
1. DIMENSIONING AND
TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN
MILLIMETERS.
3. TOP SIDE A1 CORNER
INDEX IS A METALIZED
FEATURE WITH VARIOUS
SHAPES. BOTTOM SIDE A1
CORNER IS DESIGNATED
WITH A BALL MISSING
FROM THE ARRAY.
E4
E
Millimeters
E2
E1
2X
0.2
D4
C
1 2 3 4 5 6 7 8 9 10 11 1213141516 171819
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
e
360X
b
0.3 A B C
0.15 A
DIM
MIN
MAX
A
2.72
3.20
A1
0.80
1.00
A2
1.10
1.30
A3
—
0.6
b
0.82
0.93
D
A3
A2
A1
A
0.35 A
25.00 BSC
D1
—
11.3
D2
8.0
—
D3
—
6.5
D4
10.9
11.1
e
1.27 BSC
E
25.00 BSC
E1
—
11.3
E2
8.0
—
E3
—
6.5
E4
9.55
9.75
Figure 20. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447,
360 CBGA Package
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
42
Freescale Semiconductor
Package Description
8.3
Substrate Capacitors for the MPC7447, 360 CBGA
Figure 21 shows the connectivity of the substrate capacitor pads for the MPC7447, 360 CBGA. All capacitors are
100 nF.
Pad Number
Capacitor
A1 CORNER
C1-1
C2-1 C3-1
C4-1
C5-1
C6-1
1
C8-2
C18-2 C17-2 C16-2 C15-2 C14-2 C13-2
C18-1 C17-1 C16-1 C15-1 C14-1 C13-1
C7-1
C6-2
C8-1
C5-2
C12-1 C11-1 C10-1 C9-1
C4-2
C7-2
C2-2 C3-2
C12-2 C11-2 C10-2 C9-2
C19-2 C20-2 C21-2 C22-2 C23-2 C24-2
C19-1 C20-1 C21-1 C22-1 C23-1 C24-1
C1-2
-1
-2
C1
GND
VDD
C2
GND
VDD
C3
GND
OVDD
C4
GND
VDD
C5
GND
VDD
C6
GND
VDD
C7
GND
VDD
C8
GND
VDD
C9
GND
OVDD
C10
GND
VDD
C11
GND
VDD
C12
GND
VDD
C13
GND
VDD
C14
GND
VDD
C15
GND
VDD
C16
GND
OVDD
C17
GND
VDD
C18
GND
OVDD
C19
GND
VDD
C20
GND
VDD
C21
GND
OVDD
C22
GND
VDD
C23
GND
VDD
C24
GND
VDD
Figure 21. Substrate Bypass Capacitors for the MPC7447, 360 CBGA
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
43
Package Description
8.4
Package Parameters for the MPC7457, 483 CBGA
The package parameters are as provided in the following list. The package type is 29 × 29 mm, 483-lead ceramic
ball grid array (CBGA).
Package outline
Interconnects
Pitch
Minimum module height
Maximum module height
Ball diameter
8.5
29 × 29 mm
483 (22 × 22 ball array – 1)
1.27 mm (50 mil)
—
3.22 mm
0.89 mm (35 mil)
Mechanical Dimensions for the MPC7457, 483 CBGA
Figure 22 provides the mechanical dimensions and bottom surface nomenclature for the MPC7457, 483 CBGA
package.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
44
Freescale Semiconductor
Package Description
2X
Capacitor Region
0.2
D
B
D1
D3
A1 CORNER
NOTES:
1. DIMENSIONING AND
TOLERANCING
A
PER ASME Y14.5M, 1994.
2. DIMENSIONS IN
MILLIMETERS.
3. TOP SIDE A1 CORNER
INDEX IS A METALIZED
FEATURE WITH VARIOUS
SHAPES. BOTTOM SIDE.
A1 CORNER IS
DESIGNATED WITH A BALL
MISSING FROM THE
ARRAY.
D2
1
0.15 A
E3
E
E4
E1
E2
Millimeters
2X
0.2
D4
C
DIM
MIN
MAX
A
2.72
3.20
A1
0.80
1.00
A2
1.10
1.30
A3
--
0.60
b
0.82
0.93
1 2 3 4 5 6 7 8 9 10 11 1213141516 171819 2021 22
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
e
483X
b
0.3 A B C
A3
A2
A1
A
0.35 A
D
29.00 BSC
D1
—
12.5
D2
8.5
—
D3
—
8.4
D4
10.9
11.1
e
1.27 BSC
E
29.00 BSC
E1
—
12.5
E2
8.5
—
E3
—
8.4
E4
9.55
9.75
0.15 A
Figure 22. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7457,
483 CBGA Package
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
45
Package Description
8.6
Substrate Capacitors for the MPC7457, 483 CBGA
Figure 23 shows the connectivity of the substrate capacitor pads for the MPC7457, 483 CBGA. All capacitors are
100 nF.
Pad Number
A1 CORNER
Capacitor
C1-1
C2-1
C3-1
C4-1
C5-1
C6-1
1
GND
GVDD
C4
GND
VDD
C5
GND
VDD
C6
GND
GVDD
GND
VDD
C8
GND
VDD
GND
GVDD
C10
GND
VDD
C11
GND
VDD
C12
GND
GVDD
C13
GND
VDD
C14
GND
VDD
C15
GND
VDD
C16
GND
OVDD
C17
GND
VDD
C18
GND
OVDD
C19
GND
VDD
C20
GND
VDD
C21
GND
OVDD
C22
GND
VDD
C23
GND
VDD
C24
GND
VDD
C9
C15-2 C14-2 C13-2
C18-1 C17-1 C16-1
C15-1 C14-1 C13-1
C12-1 C11-1 C10-1
C18-2 C17-2 C16-2
C7-1
C7
C7-2
C8-1
C3
C9-1
VDD
C8-2
GND
C9-2
C6-2
C2
C12-2 C11-2 C10-2
C5-2
OVDD
C22-2 C23-2 C24-2
C4-2
GND
C19-2 C20-2 C21-2
C3-2
C1
C22-1 C23-1 C24-1
C2-2
-2
C19-1 C20-1 C21-1
C1-2
-1
Figure 23. Substrate Bypass Capacitors for the MPC7457, 483 CBGA
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
46
Freescale Semiconductor
System Design Information
9
System Design Information
This section provides system and thermal design recommendations for successful application of the MPC7457.
9.1
Clocks
The following sections provide more detailed information regarding the clocking of the MPC7457.
9.1.1
Core Clocks and PLL Configuration
The MPC7457 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the PLL
configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the
MPC7457 is shown in Table 18 for a set of example frequencies. In this example, shaded cells represent settings
that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the 1-GHz
column in Table 8. Note that these configurations were different in some earlier MPC7450-family devices and care
should be taken when upgrading to the MPC7457 to verify the correct PLL settings for an application.
Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-toCore
Multiplier
Core-toVCO
Multiplier
01000
2x
2x
10000
3x
2x
10100
4x
2x
10110
5x
2x
667
(1333)
835
(1670)
10010
5.5x
2x
733
(1466)
919
(1837)
11010
6x
2x
600
(1200)
800
(1600)
1002
(2004)
01010
6.5x
2x
650
(1300)
866
(1730)
1086
(2171)
00100
7x
2x
700
(1400)
931
(1862)
1169
(2338)
00010
7.5x
2x
623
(1245)
750
(1500)
1000
(2000)
1253
(2505)
11000
8x
2x
600
(1200)
664
(1328)
800
(1600)
1064
(2128)
01100
8.5x
2x
638
(1276)
706
(1412)
850
(1700)
1131
(2261)
01111
9x
2x
675
(1350)
747
(1494)
900
(1800)
1197
(2394)
PLL_CFG[0:4]
Bus (SYSCLK) Frequency
33.3
MHz
50
MHz
66.6
MHz
75
MHz
83
MHz
100
MHz
133
MHz
167
MHz
667
(1333)
600
(1200)
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
47
System Design Information
Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (continued)
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-toCore
Multiplier
Core-toVCO
Multiplier
01110
9.5x
10101
PLL_CFG[0:4]
Bus (SYSCLK) Frequency
66.6
MHz
75
MHz
83
MHz
100
MHz
133
MHz
2x
633
(1266)
712
(1524)
789
(1578)
950
(1900)
1264
(2528)
10x
2x
667
(1333)
750
(1500)
830
(1660)
1000
(2000)
10001
10.5x
2x
700
(1400)
938
(1876)
872
(1744)
1050
(2100)
10011
11x
2x
733
(1466)
825
(1650)
913
(1826)
1100
(2200)
00000
11.5x
2x
766
(532)
863
(1726)
955
(1910)
1150
(2300)
10111
12x
2x
600
(1200)
800
(1600)
900
(1800)
996
(1992)
1200
(2400)
11111
12.5x
2x
600
(1200)
833
(1666)
938
(1876)
1038
(2076)
1250
(2500)
01011
13x
2x
650
(1300)
865
(1730)
975
(1950)
1079
(2158)
11100
13.5x
2x
675
(1350)
900
(1800)
1013
(2026)
1121
(2242)
11001
14x
2x
700
(1400)
933
(1866)
1050
(2100)
1162
(2324)
00011
15x
2x
750
(1500)
1000
(2000)
1125
(2250)
1245
(2490)
11011
16x
2x
800
(1600)
1066
(2132)
1200
(2400)
00001
17x
2x
850
(1900)
1132
(2264)
00101
18x
2x
600
(1200)
900
(1800)
1200
(2400)
00111
20x
2x
667
(1334)
1000
(2000)
01001
21x
2x
700
(1400)
1050
(2100)
01101
24x
2x
800
(1600)
1200
(2400)
11101
28x
2x
933
(1866)
00110
PLL bypass
33.3
MHz
50
MHz
167
MHz
PLL off, SYSCLK clocks core circuitry directly
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
48
Freescale Semiconductor
System Design Information
Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (continued)
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
PLL_CFG[0:4]
Bus-toCore
Multiplier
11110
Core-toVCO
Multiplier
Bus (SYSCLK) Frequency
33.3
MHz
50
MHz
PLL off
66.6
MHz
75
MHz
83
MHz
100
MHz
133
MHz
167
MHz
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:4] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or
VCO frequencies which are not useful, not supported, or not tested for by the MPC7455; see Section 5.2.1, “Clock AC
Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However,
the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at
one-half the frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold time tIXKH (see
Table 9). The result is that the processor bus frequency is one-half SYSCLK while the internal processor is clocked at
SYSCLK frequency. This mode is intended for factory use and emulator tool use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7455 regardless of the SYSCLK input.
9.1.2
L3 Clocks
The MPC7457 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock
frequency of the MPC7457. The core-to-L3 frequency divisor for the L3 PLL is selected through the L3_CLK bits
of the L3CR register. Generally, the divisor must be chosen according to the frequency supported by the external
RAMs, the frequency of the MPC7457 core, and timing analysis of the circuit board routing. Table 19 shows various
example L3 clock frequencies that can be obtained for a given set of core frequencies.
Table 19. Sample Core-to-L3 Frequencies 1
Core
Frequency
(MHz) 2
÷2
÷2.5
÷3
÷3.5
÷4
÷4.5
÷5
÷5.5
÷6
÷6.5
÷7
÷7.5
÷8
500
250
200
167
143
125
111
100
91
83
77
71
67
63
533
266
213
178
152
133
118
107
97
89
82
76
71
67
550
275
220
183
157
138
122
110
100
92
85
79
73
69
600
300
240
200
171
150
133
120
109
100
92
86
80
75
650
325
260
217
186
163
144
130
118
108
100
93
87
81
666
333
266
222
190
167
148
133
121
111
102
95
89
83
700
350
280
233
200
175
156
140
127
117
108
100
93
88
733
367
293
244
209
183
163
147
133
122
113
105
98
92
800
400
320
266
230
200
178
160
145
133
123
114
107
100
866
433
347
289
248
217
192
173
157
145
133
124
115
108
933
467
373
311
266
233
207
187
170
156
144
133
124
117
1000
500
400
333
285
250
222
200
182
166
154
143
133
125
1050
525
420
350
300
263
233
191
191
175
162
150
140
131
1100
550
440
367
314
275
244
200
200
183
169
157
147
138
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
49
System Design Information
Table 19. Sample Core-to-L3 Frequencies 1 (continued)
Core
Frequency
(MHz) 2
÷2
÷2.5
÷3
÷3.5
÷4
÷4.5
÷5
÷5.5
÷6
÷6.5
÷7
÷7.5
÷8
1150
575
460
383
329
288
256
209
209
192
177
164
153
144
1200
600
480
400
343
300
267
218
218
200
185
171
160
150
1250
638
500
417
357
313
278
227
227
208
192
179
167
156
1300
650
520
433
371
325
289
236
236
217
200
186
173
163
Notes:
1. The core and L3 frequencies are for reference only. Note that maximum L3 frequency is design dependent. Some examples
may represent core or L3 frequencies which are not useful, not supported, or not tested for the MPC7457; see Section 5.2.3,
“L3 Clock AC Specifications,” for valid L3_CLK frequencies and for more information regarding the maximum L3 frequency.
2. Not all core frequencies are supported by all speed grades; see Table 8 for minimum and maximum core frequency
specifications.
9.1.3
System Bus Clock (SYSCLK) and Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions
(EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet
industry and government requirements. These clock sources intentionally add long-term jitter in order to diffuse the
EMI spectral content. The jitter specification given in Table 8 considers short-term (cycle-to-cycle) jitter only and
the clock generator’s cycle-to-cycle output jitter should meet the MPC7457 input cycle-to-cycle jitter requirement.
Frequency modulation and spread are separate concerns, and the MPC7457 is compatible with spread spectrum
sources if the recommendations listed in Table 20 are observed.
Table 20. Spread Specturm Clock Source Recommendations
At recommended operating conditions. See Table 4.
Parameter
Min
Max
Unit
Notes
Frequency modulation
—
50
kHz
1
Frequency spread
—
1.0
%
1, 2
Notes:
1. Guaranteed by design.
2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO
frequencies, must meet the minimum and maximum specifications given in Table 8.
It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies must not
be exceeded regardless of the type of clock source. Therefore, systems in which the processor is operated at its
maximum rated core or bus frequency should avoid violating the stated limits by using down-spreading only.
9.2
PLL Power Supply Filtering
The AVDD power signal is provided on the MPC7457 to provide power to the clock generation PLL. To ensure
stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any noise in the
500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 24 using
surface mount capacitors with minimum effective series inductance (ESL) is recommended.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
50
Freescale Semiconductor
System Design Information
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby circuits.
It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360 CBGA
footprint and very close to the periphery of the 483 CBGA footprint, without the inductance of vias.
10 Ω
VDD
AVDD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 24. PLL Power Supply Filter Circuit
NOTE
Previous revisions of this document required a 400 Ω resistor for Rev. 1.1 (Rev. B)
devices instead of the 10 Ω resistor shown above. All production devices require a
10 Ω resistor. For more information, see the MPC7450 Family Chip Errata for the
MPC7457 and MPC7447.
9.3
Decoupling Recommendations
Due to the MPC7457 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC7457 can generate transient power surges and high frequency noise in its power supply,
especially while driving large capacitive loads. This noise must be prevented from reaching other components in the
MPC7457 system, and the MPC7457 itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, and GVDD pin
of the MPC7457. It is also recommended that these decoupling capacitors receive their power from separate V DD,
OVDD/GVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. If compromises
must be made due to board constraints, VDD pins should receive the highest priority for decoupling.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT) capacitors
should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along
the length of the part. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design:
A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling
Freescale microprocessors, multiple small capacitors of equal value are recommended over using multiple values of
capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the
VDD, GVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low equivalent series resistance (ESR) rating to ensure the quick response time necessary. They should
also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
9.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level.
Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to GND. All NC
(no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, GVDD, and GND pins in the MPC7457.
If the L3 interface is not used, GVDD should be connected to the OVDD power plane, and L3VSEL should be
connected to BVSEL; the remainder of the L3 interface may be left unterminated.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
51
System Design Information
9.5
Output Buffer DC Impedance
The MPC7457 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature. To
measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor
is varied until the pad voltage is OVDD/2 (see Figure 23).
The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When
data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals OV DD/2. RN
then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and
RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP
and RN are designed to be close to each other in value. Then, Z 0 = (RP + RN)/2.
OVDD
RN
SW2
Data
Pad
SW1
RP
OGND
Figure 25. Driver Impedance Measurement
Table 21 summarizes the signal impedance results. The impedance increases with junction temperature and is
relatively unaffected by bus voltage.
Table 21. Impedance Characteristics
VDD = 1.5 V, OVDD = 1.8 V ± 5%, Tj = 5°–85°C
Impedance
Z0
9.6
Processor Bus
L3 Bus
Unit
Typical
33–42
34–42
Ω
Maximum
31–51
32–44
Ω
Pull-Up/Pull-Down Resistor Requirements
The MPC7457 requires high-resistive (weak: 4.7-kΩ) pull-up resistors on several control pins of the bus interface to
maintain the control signals in the negated state after they have been actively negated and released by the MPC7457
or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pins designated as being for factory test must be pulled up to OVDD or down to GND to ensure proper device
operation. For the MPC7447, 360 BGA, the pins that must be pulled up to OV DD are: LSSD_MODE and TEST[0:3];
the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. For the MPC7457, 483 BGA, the pins
that must be pulled up to OVDD are: LSSD_MODE and TEST[0:5]; the pins that must be pulled down are:
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
52
Freescale Semiconductor
System Design Information
L1_TSTCLK and TEST[6]. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (weak or
stronger: 4.7–1 kΩ) to prevent erroneous assertions of this signal.
In addition, the MPC7457 has one open-drain style output that requires a pull-up resistor (weak or stronger:
4.7–1 kΩ) if it is used by the system. This pin is CKSTP_OUT.
If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be less than 250 Ω (see
Table 16). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and pull-down
resistors (1 kΩ or less) are recommended to configure these signals in order to protect against erroneous switching
due to ground bounce, power supply noise or noise coupling.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may,
therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7457 must
continually monitor these signals for snooping, this float condition may cause excessive power draw by the input
receivers on the MPC7457 or by other receivers in the system. These signals can be pulled up through weak (10-kΩ)
pull-up resistors by the system, address bus driven mode enabled (see the MPC7450 RISC Microprocessor Family
Users’ Manual for more information about this mode), or they may be otherwise driven by the system during
inactive periods of the bus to avoid this additional power draw. Preliminary studies have shown the additional power
draw by the MPC7457 input receivers to be negligible and, in any event, none of these measures are necessary for
proper device operation. The snooped address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT,
and GBL.
If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through weak pull-down
resistors. If the MPC7457 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak pull-down
resistors.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not
require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that
those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are:
D[0:63] and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the
input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left
unconnected by the system. If all parity generation is disabled through HID0, all parity checking should also be
disabled through HID0, and all parity pins may be left unconnected by the system.
The L3 interface does not normally require pull-up resistors. Unused L3_ADDR signals are driven low when the
SRAM is configured to be less than 1 M in size via L3CR. For example, L3_ADD[18] will be driven low if the
SRAM size is configured to be 2 M; likewise, L3_ADDR[18:17] will be driven low if the SRAM size is configured
to be 1 M.
9.7
JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE
1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible
to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset
performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is
also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not
practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware
and debugging software) to access and control the internal operations of the processor. The COP interface connects
primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
53
System Design Information
requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target
system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, the COP reset signals must be merged into these signals with logic.
The arrangement shown in Figure 26 allows the COP port to independently assert HRESET or TRST, while ensuring
that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be
tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is
asserted, ensuring that the JTAG scan chain is initialized during power-on. While Freescale recommends that the
COP header be designed into the system as shown in Figure 26, if this is not possible, the isolation resistor will allow
future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations.
The COP header shown in Figure 26 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and can be as
inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100"
centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector
key.
There is no standardized way to number the COP header shown in Figure 26; consequently, many different pin
numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while
others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with
an IC). Regardless of the numbering, the signal placement recommended in Figure 26 is common to all known
emulators.
The QACK signal shown in Figure 26 is usually connected to the PCI bridge chip in a system and is an input to the
MPC7457 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power
mode selection. In order for COP to work, the MPC7457 must see this signal asserted (pulled down). While shown
on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be
populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can
only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted
when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are
mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation,
QACK should be merged via logic so that it also can be driven by the PCI bridge.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
54
Freescale Semiconductor
System Design Information
From Target
Board Sources
(if any)
SRESET
SRESET
HRESET
HRESET
QACK
13
11
HRESET
10 kΩ
SRESET
10 kΩ
OVDD
OVDD
10 kΩ
OVDD
10 kΩ
OVDD
0Ω5
1
2
3
4
5
6
7
8
9
10
11
12
TRST
6
5
OVDD
OVDD
CHKSTP_OUT
CHKSTP_OUT
Key
14 2
10 kΩ
OVDD
OVDD
CHKSTP_IN
CHKSTP_IN
8
COP Header
COP Connector
Physical Pin Out
10 kΩ
2 kΩ
10 kΩ
KEY
16
VDD_SENSE
1
15
13 No Pin
15
TRST
4
TMS
9
1
3
TMS
TDO
TDO
TDI
TDI
TCK
7
2
10
12
6
TCK
QACK
QACK
NC
2 kΩ 3
10 kΩ 4
OVDD
16
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7457. Connect
pin 5 of the COP header to OVDD with a 10-kΩ pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-Ω isolation resistor.
6. Though defined as a No-Connect, it is a common and recommended practice to use pin 12 as an
additional GND pin for improved signal integrity.
Figure 26. JTAG Interface Connection
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
55
System Design Information
9.8
Thermal Management Information
This section provides thermal management information for the ceramic ball grid array (CBGA) package for
air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat
sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to
the package by several methods—spring clip to holes in the printed-circuit board or package, and mounting clip and
screw assembly (see Figure 25); however, due to the potential large mass of the heat sink, attachment through the
printed-circuit board is suggested. If a spring clip is used, the spring force should not exceed 10 pounds.
Heat Sink
CBGA Package
Heat Sink
Clip
Thermal
Interface Material
Printed-Circuit Board
Figure 27. Package Exploded Cross-Sectional View with Several Heat Sink Options
The board designer can choose between several types of heat sinks to place on the MPC7457. There are several
commercially available heat sinks for the MPC7457 provided by the following vendors:
Aavid Thermalloy
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
603-224-9988
Alpha Novatech
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
408-749-7601
International Electronic Research Corporation (IERC)
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
818-842-7277
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
800-522-6752
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
56
Freescale Semiconductor
System Design Information
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
603-635-5102
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at
a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
9.8.1
Internal Package Conduction Resistance
For the exposed-die packaging technology, shown in Table 3, the intrinsic conduction thermal resistance paths are
as follows:
•
•
The die junction-to-case (actually top-of-die since silicon die is exposed) thermal resistance
The die junction-to-ball thermal resistance
Figure 26 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit
board.
External Resistance
Radiation
Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Package/Leads
Internal Resistance
Printed-Circuit Board
External Resistance
Radiation
Convection
(Note the internal versus external package resistance.)
Figure 28. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Heat generated on the active side of the chip is conducted through the silicon, through the heat sink attach material
(or thermal interface material), and finally to the heat sink where it is removed by forced-air convection.
Because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon
may be neglected. Thus, the thermal interface material and the heat sink conduction/convective thermal resistances
are the dominant terms.
9.8.2
Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal
contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 27 shows
the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare
joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal
interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
57
System Design Information
interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater
than the thermal grease joint.
Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see
Figure 25). Therefore, the synthetic grease offers the best thermal performance, considering the low interface
pressure and is recommended due to the high power dissipation of the MPC7457. Of course, the selection of any
thermal interface material depends on many factors—thermal performance requirements, manufacturability, service
temperature, dielectric properties, cost, etc.
Silicone Sheet (0.006 in.)
Bare Joint
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
Specific Thermal Resistance (K-in.2/W)
2
1.5
1
0.5
0
0
10
20
30
40
50
60
70
80
Contact Pressure (psi)
Figure 29. Thermal Performance of Select Thermal Interface Material
The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be
selected based on high conductivity, yet adequate mechanical strength to meet equipment shock/vibration
requirements. There are several commercially available thermal interfaces and adhesive materials provided by the
following vendors:
The Bergquist Company
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
800-347-4572
Chomerics, Inc.
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
781-935-4850
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Freescale Semiconductor
System Design Information
Dow-Corning Corporation
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
Midland, MI 48686-0997
Internet: www.dow.com
800-248-2481
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
888-642-7674
Thermagon Inc.
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
888-246-9050
The following section provides a heat sink selection example using one of the commercially available heat sinks.
9.8.3
Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
Tj = TI + Tr + (RθJC + Rθint + Rθsa) × Pd
where:
Tj is the die-junction temperature
TI is the inlet cabinet ambient temperature
Tr is the air temperature rise within the computer cabinet
RθJC is the junction-to-case thermal resistance
Rθint is the adhesive or interface material thermal resistance
Rθsa is the heat sink base-to-ambient thermal resistance
Pd is the power dissipated by the device
During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in Table 4.
The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air
temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30°
to 40°C. The air temperature rise within a cabinet (Tr) may be in the range of 5° to 10°C. The thermal resistance of
the thermal interface material (Rθint) is typically about 1.5°C/W. For example, assuming a Ta of 30°C, a Tr of 5°C,
a CBGA package RθJC = 0.1, and a typical power consumption (Pd) of 18.7 W, the following expression for Tj is
obtained:
Die-junction temperature:
Tj = 30°C + 5°C + (0.1°C/W + 1.5°C/W + θsa) × 18.7 W
For this example, a Rθsavalue of 2.1°C/W or less is required to maintain the die junction temperature below the
maximum value of Table 4.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit
used for comparing the thermal performance of various microelectronic packaging technologies, one should
exercise caution when only using this metric in determining thermal management because no single parameter can
adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function
of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to
the component's power consumption, a number of factors affect the final operating die-junction
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
59
System Design Information
temperature—airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink
attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic
equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary
widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level
designs.
For system thermal modeling, the MPC7447 and MPC7457 thermal model is shown in Figure 28. Four volumes will
be used to represent this device. Two of the volumes, solder ball, and air and substrate, are modeled using the
package outline size of the package. The other two, die, and bump and underfill, have the same size as the die. The
silicon die should be modeled 9.64 × 11.0 × 0.74 mm with the heat source applied as a uniform source at the bottom
of the volume. The bump and underfill layer is modeled as 9.64 × 11.0 × 0.69 mm (or as a collapsed volume) with
orthotropic material properties: 0.6 W/(m • K) in the xy-plane and 2 W/(m • K) in the direction of the z-axis. The
substrate volume is 25 × 25 × 1.2 mm (MPC7447) or 29 × 29 × 1.2 mm (MPC7457), and this volume has
18 W/(m • K) isotropic conductivity. The solder ball and air layer is modeled with the same horizontal dimensions
as the substrate and is 0.9 mm thick. It can also be modeled as a collapsed volume using orthotropic material
properties: 0.034 W/(m • K) in the xy-plane direction and 3.8 W/(m • K) in the direction of the z-axis.
Die
Bump and Underfill
z
Conductivity
Value
Substrate
Unit
Solder and Air
Bump and Underfill
Side View of Model (Not to Scale)
kx
0.6
ky
0.6
kz
2
W/(m • K)
x
Substrate
k
Substrate
18
Solder Ball and Air
kx
0.034
ky
0.034
kz
3.8
Die
y
Top View of Model (Not to Scale)
Figure 30. Recommended Thermal Model of MPC7447 and MPC7457
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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Document Revision History
10 Document Revision History
Table 22 provides a revision history for this hardware specification.
Table 22. Document Revision History
Revision
Number
Date
5
09/09/2004
Substantive Change(s)
Updated document to new Freescale template.
Updated section numbering and changed reference from part number specifications to addendums.
Added Rev. 1.2 devices, including increased L3 clock max frequency to 250 MHz and improved L3
AC timing.
Table 5: Added CTE information.
Table 8: Modified jitter specifications to conform to JEDEC standards, changed jitter specification to
cycle-to-cycle jitter (instead of long- and short-term jitter); changed jitter bandwidth
recommendations.
Table 13: Deleted note 9 and renumbered.
Table 14: Deleted note 5 and renumbered.
Table 17: Revised note 6.
Added Section 9.1.3.
Section 9.2: Changed filter resistor recommendations. Recommend 10 Ω resistor for all production
devices, including production Rev. 1.1 devices. 400 Ω resistor needed only for early Rev. 1.1
devices.
Table 22: Reversed the order of revision numbers.
Added Tables 25 and 26.
4.1
Section 9.1.1: Corrected note regarding different PLL configurations for earlier devices; all
MPC7457 devices to date conform to this table.
Section 9.6: Added information about unused L3_ADDR signals.
Table 24: Changed title to include document order information for MPC74x7RXnnnnNx series part
number specification.
4
Table 9: Corrected pin lists for input and output AC timing to correctly show HIT as an output-only
signal
Added specifications for 1267 MHz devices; removed specs for 1300 MHz devices.
Section 5.2.3: Changed recommendations regarding use of L3 clock jitter in AC timing analysis. The
L3 jitter is now fully comprehended in the AC timing specs and does not need to be included in the
timing analysis.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
61
Document Revision History
Table 22. Document Revision History (continued)
Revision
Number
3
Date
Substantive Change(s)
Corrected numerous errors in lists of pins associated with tKHOV, tKHOX, tIVKH, and tIXKH in Table 9.
Added support for 1.5 V L3 interface voltage; issues fixed in Rev. 1.1.
Corrected typos in Table 12.
Added data to Table 2.
Clarified address bus pull-up resistor recommendations in Section 1.9.6.
Modified Table 9, Figure 5, and Figure 6 to more accurately show when the mode select inputs
(BMODE[0:1], L3VSEL, BVSEL) are sampled and AC timing requirements
Table 10: Added skew and jitter values.
Table 14: Added AC timing values.
Table 24: Updated to reflect past and current part numbers not fully covered by this document.
Table 6: Removed CVIH and CVIL; VIH and VIL for SYSCLK input is the same as for other input
signals, and is now noted accordingly in this table.
Table 7: Removed Doze mode power entry (but left footnote 4 for clarity); documentation change
only.
Nontechnical formatting
2
Added substrate capacitor information in Sections 1.8.3 and 1.8.6.
Increased minimum processor and VCO frequencies in Table 8 from 500 and 1000 MHz to 600 and
1200 MHz (respectively).
Corrected maximum processor frequency for 1300 MHz devices in Table 8 (changed from 1333 to
1300 MHz).
Added value for to tL3CSKW1 Table 10.
Added L3OHCR information in Section 1.5.2.4.1.
Added values for tCO and tECI to Table 11.
Added Note 8 to Table 13 and Note 6 to Table 14.
Changed resistor value in PLL filter in Figure 25 from 10 Ω to 400 Ω.
Added 867 MHz speed grade.
Corrected Product Code in Tables 22 and 23.
Added pull-up/pull-down recommendations for CKSTP_IN and PLL_CFG[0:4] to Section 1.9.6.
1.1
Nontechnical reformatting.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
62
Freescale Semiconductor
Part Numbering and Marking
Table 22. Document Revision History (continued)
Revision
Number
Date
1
Substantive Change(s)
Removed support for 1.5 V L3 interface voltage from Tables 3 and 4. 1.5 V I/O voltage is not
supported in current MPC7457 devices.
Added package thermal characteristics values to Table 5, made minor revisions to Section 1.9.8.
Added preliminary AC timing values to Tables 10 and 12.
Added footnotes to Table 17.
0
Initial release.
11 Part Numbering and Marking
Ordering information for the parts fully covered by this specification document is provided in Section 11.1, “Part
Numbers Fully Addressed by This Document.” Note that the individual part numbers correspond to a maximum
processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the
processor frequency, the part numbering scheme also includes an application modifier which may specify special
application conditions. Each part number also contains a revision level code which refers to the die mask revision
number. Section 11.2, “Part Numbers Not Fully Addressed by This Document,” lists the part numbers which do not
fully conform to the specifications of this document. These special part numbers require an additional document
called a referred to as a hardware specification addendum.
11.1 Part Numbers Fully Addressed by This Document
Table 23 provides the Freescale part numbering nomenclature for the MPC7457.
Table 23. Part Numbering Nomenclature
MC
74x7
RX
nnnn
L
x
Product
Code
Part
Identifier
Package
Processor
Frequency 1
Application
Modifier
Revision Level
PPC 2
MC
7457
7447
MC
7457
RX = CBGA
867
1000
1200
1267
867
1000
1200
1267
L: 1.3 V ± 50 mV
0° to 105°C
B: 1.1; PVR = 8002 0101
C: 1.2; PVR = 8002 0102
Notes:
1. Processor core frequencies supported by parts addressed by this specification only. Parts addressed by a
hardware specification addendum may support other maximum core frequencies.
2. The P prefix in a Freescale part number designates a “Pilot Production Prototype” as defined by Freescale SOP
3-13. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may
be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging
the qualification status and the fact that product changes may still occur while shipping pilot production prototypes.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
63
Part Numbering and Marking
11.2 Part Numbers Not Fully Addressed by This Document
Parts with application modifiers or revision levels not fully addressed are described in a separate addendum, which
supplement and supersede this hardware specification. As such parts are released, these specifications will be listed
in this section.
Table 24. Part Numbers Addressed by MPC74x7RXnnnnNx Series Hardware Specifications Addendum
(Document Order No. MPC7457ECS1AD)
MC
74x7
RX
nnnn
N
x
Product
Code
Part
Identifier
Package
Processor
Frequency
Application
Modifier
Revision Level
PPC
7457
MC
RX = CBGA
1000
867
733
600
N: 1.1 V ± 50 mV
0° to 105°C
B: 1.1; PVR = 8002 0101
7447
1000
867
7447
1000
867
733
600
B: 1.1; PVR = 8002 0101
7457
1000
867
733
600
C: 1.2; PVR = 8002 0102
Table 25. Part Numbers Addressed by MPC7457TRXnnnnLB Series Hardware Specifications Addendum
(Document Order No. MPC7457ECS2AD)
MC
7457
T
RX
nnnn
L
x
Product
Code
Part
Identifier
Specification
Modifier
Package
Processor
Frequency
Application
Modifier
Revision Level
MC
7457
T = Extended
Temperature
Device
RX = CBGA
1000
1267
L: 1.3 V ± 50 mV
–40° to 105°C
C: 1.2; PVR = 8002 0102
Table 26. Part Numbers Addressed by MPC7457TRXnnnnNx Series Hardware Specifications Addendum
(Document Order No. MPC7457ECS3AD)
MC
74x7
T
RX
nnnn
N
x
Product
Code
Part
Identifier
Specification
Modifier
Package
Processor
Frequency
Application
Modifier
Revision Level
MC
7447
T = Extended
Temperature
Device
7457
RX = CBGA
733
1000
N: 1.1 V ± 50 mV
–40° to 105°C
B: 1.1; PVR = 8002 0101
C: 1.2; PVR = 8002 0102
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
64
Freescale Semiconductor
Part Numbering and Marking
11.3 Part Marking
Parts are marked as the examples shown in Figure 32.
MC7447
RX1nnnLx
MMMMMM
ATWLYYWWA
Notes:
MC7457
RXnnnnLx
MMMMMM
ATWLYYWWA
7447
7457
BGA
BGA
MMMMMM is the 6-digit mask number.
ATWLYYWWA is the traceability code.
Figure 31. Part Marking for BGA Device
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
65
Part Numbering and Marking
THIS PAGE INTENTIONALLY LEFT BLANK
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Part Numbering and Marking
THIS PAGE INTENTIONALLY LEFT BLANK
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
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67
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Rev. 5
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