Renesas ISL9011IRMGZ Dual ldo with low noise, low iq and high psrr Datasheet

DATASHEET
ISL9011
FN9219
Rev.5.00
March 10, 2008
Dual LDO with Low Noise, Low IQ and High PSRR
ISL9011 is a high performance dual LDO capable of
sourcing 150mA current from Channel 1 and 300mA from
Channel 2. The device has a low standby current and
high-PSRR and is stable with output capacitance of 1µF to
10µF with ESR of up to 200m.
Features
A reference bypass pin allows an external capacitor for
adjusting a noise filter for low noise and high PSRR
applications.
• Excellent transient response to large current steps
The quiescent current is typically only 45µA with both LDO’s
enabled and active. Separate enable pins control each
individual LDO output. When both enable pins are low, the
device is in shutdown, typically drawing less than 0.1µA.
• High PSRR: 70dB @ 1kHz
Several combinations of voltage outputs are standard.
Output voltage options for each LDO range from 1.5V to
3.3V. Other output voltage options may be available upon
request.
• Low dropout voltage: typically 120mV @ 150mA
• Integrates two high performance LDOs
- VO1 - 150mA output
- VO2 - 300mA output
• Excellent load regulation: <1% voltage change across full
range of load current
• Wide input voltage capability: 2.3V to 6.5V
• Extremely low quiescent current: 45µA (both LDOs active)
• Low output noise: typically 30µVRMS @ 100µA (1.5V)
• Stable with 1µF to10µF ceramic capacitors
• Separate enable pins for each LDO
Pinout
• Soft-start to limit input current surge during enable
ISL9011
(10 LD 3X3 DFN)
TOP VIEW
• Current limit and overheat protection
• ±1.8% accuracy over all operating conditions
• Tiny 10 Ld 3mmx3mm DFN package
VIN
1
10 VO1
EN1
2
9
VO2
EN2
3
8
NC
• Pin compatible with Micrel MIC2211
CBYP
4
7
NC
• Pb-free (RoHS compliant)
NC
5
6
GND
• -40°C to +85°C operating temperature range
Applications
• PDAs, Cell Phones and Smart Phones
• Portable Instruments, MP3 Players
• Handheld Devices including Medical Handhelds
FN9219 Rev.5.00
March 10, 2008
Page 1 of 11
ISL9011
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
VO1 VOLTAGE
(V)
VO2 VOLTAGE
(V)
TEMP RANGE (°C)
PACKAGE
(Pb-free)
PKG. DWG. #
ISL9011IRNNZ
DAAM
3.3
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRNJZ
DTAA
3.3
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRNFZ
DVAA
3.3
2.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRNCZ
DAAN
3.3
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRMNZ
DAAP
3.0
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRMMZ
DANA
3.0
3.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRMGZ
DAAS
3.0
2.7
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRLLZ
DAMA
2.9
2.9
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRKNZ
DAAW
2.85
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRKKZ
DWAA
2.85
2.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRKJZ
DYAA
2.85
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRKFZ
DABA
2.85
2.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRKPZ
DDHA
2.85
1.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRKCZ
DAEA
2.85
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRJNZ
DAAY
2.8
3.3
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRJMZ
DALA
2.8
3.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRJRZ
DAKA
2.8
2.6
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRJCZ
DAJA
2.8
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRJBZ
DACA
2.8
1.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRGPZ
DDGA
2.7
1.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRGCZ
DAHA
2.7
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRFJZ
DADA
2.5
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRFDZ
DCRA
2.5
2.0
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRFCZ
DBMA
2.5
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRPLZ
DAGA
1.85
2.9
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRPPZ
DDDA
1.85
1.85
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRCJZ
DBVA
1.8
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRCCZ
DCSA
1.8
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRBLZ
DBBF
1.5
2.9
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRBJZ
DAFA
1.5
2.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRBCZ
DBBH
1.5
1.8
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9011IRBBZ
DDEA
1.5
1.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. For availability and lead time of devices with voltage combinations not listed in the table, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
FN9219 Rev.5.00
March 10, 2008
Page 2 of 11
ISL9011
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V
VO1, VO2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V
Thermal Resistance (Notes 4, 5)
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
JA (°C/W)
JC (°C/W)
10 Ld 3x3 DFN Package . . . . . . . . . . .
50
10
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
TA = -40°C to +85°C; VIN = (VO + 1.0V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
CBYP = 0.01µF:
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 7) TYP (Note 7)
UNITS
DC CHARACTERISTICS
Supply Voltage
VIN
Ground Current
2.3
6.5
V
Quiescent condition: IO1 = 0µA; IO2 = 0µA
IDD1
One LDO active
25
40
µA
IDD2
Both LDO active
45
60
µA
Shutdown Current
IDDS
@ +25°C
0.1
1.0
µA
UVLO Threshold
VUV+
1.9
2.1
2.3
V
VUV-
1.6
1.8
2.0
V
+1.8
%
0
0.2
%/V
0.1
0.7
%
1.0
%
Regulation Voltage Accuracy
Variation from nominal voltage output, VIN = VO + 0.5V to 5.5V,
TJ = -40°C to +125°C
-1.8
Line Regulation
VIN = (VOUT + 1.0V relative to highest output voltage) to 5.5V
-0.2
Load Regulation
IOUT = 100µA to 150mA (VO1 and VO2)
IOUT = 100µA to 300mA (VO2)
Maximum Output Current
Internal Current Limit
Dropout Voltage (Note 6)
Thermal Shutdown Temperature
IMAX
VO1: Continuous
150
mA
VO2: Continuous
300
mA
475
600
mA
VDO1
IO = 150mA; VO 2.1V (VO1)
350
125
200
mV
VDO2
IO = 300mA; VO < 2.5V (VO2)
300
500
mV
VDO3
IO = 300mA; 2.5V  VO  2.8V (VO2)
250
400
mV
VDO4
IO = 300mA; VO > 2.8V (VO2)
200
325
mV
ILIM
TSD+
145
°C
TSD-
110
°C
@ 1kHz
70
dB
@ 10kHz
55
dB
@ 100kHz
40
dB
IO = 100µA, VO = 1.5V, TA = +25°C, CBYP = 0.1µF
BW = 10Hz to 100kHz
30
µVRMS
AC CHARACTERISTICS
Ripple Rejection
Output Noise Voltage
FN9219 Rev.5.00
March 10, 2008
IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1µF
Page 3 of 11
ISL9011
Electrical Specifications
PARAMETER
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
TA = -40°C to +85°C; VIN = (VO + 1.0V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
CBYP = 0.01µF: (Continued)
MIN
MAX
(Note 7) TYP (Note 7)
UNITS
Time from assertion of the ENx pin to when the output voltage
reaches 95% of the VO(nom)
250
500
µs
Slope of linear portion of LDO output voltage ramp during
start-up
30
60
µs/V
SYMBOL
TEST CONDITIONS
DEVICE START-UP CHARACTERISTICS
Device Enable Time
LDO Soft-Start Ramp Rate
tEN
tSSR
EN1, EN2 PIN CHARACTERISTICS
Input Low Voltage
VIL
-0.3
0.5
V
Input High Voltage
VIH
1.4
VIN + 0.3
V
0.1
µA
Input Leakage Current
IIL, IIH
Pin Capacitance
CPIN
Informative
5
pF
NOTE:
6. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.
7. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
FN9219 Rev.5.00
March 10, 2008
Page 4 of 11
ISL9011
Typical Performance Curves
0.10
0.8
VO = 3.3V
ILOAD = 0mA
0.4
0.2
-40°C
0.0
+25°C
-0.2
+85°C
-0.4
VIN = 3.8V
VO = 3.3V
0.08
OUTPUT VOLTAGE CHANGE (%)
OUTPUT VOLTAGE, VO (%)
0.6
-0.6
0.06
0.04
-40°C
0.02
+25°C
0.00
-0.02
+85°C
-0.04
-0.06
-0.08
-0.8
3.4
3.8
4.6
4.2
5.0
5.4
5.8
6.2
-0.10
6.6
0
50
200
250
300
350
400
LOAD CURRENT - IO (mA)
FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V
OUTPUT)
FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
0.10
3.4
VIN = 3.8V
VO = 3.3V
ILOAD = 0mA
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
VO1 = 3.3V
IO = 0mA
3.3
OUTPUT VOLTAGE, VO (V)
OUTPUT VOLTAGE CHANGE (%)
150
100
INPUT VOLTAGE (V)
3.2
IO = 150mA
3.1
3.0
2.9
-0.08
2.8
-0.10
-40
-25
-10
5
20 35 50 65
TEMPERATURE (°C)
80
95
110 125
DROPOUT VOLTAGE, VDO (mV)
OUTPUT VOLTAGE, VO (V)
IO = 150mA
2.6
IO = 300mA
2.5
2.4
3.6
4.1
4.6
5.1
5.6
INPUT VOLTAGE (V)
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE
(VO2 = 2.8V)
FN9219 Rev.5.00
March 10, 2008
5.1
5.6
6.1
6.5
300
2.7
3.1
4.6
350
VO2 = 2.8V
2.8
2.6
4.1
FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE
(VO1 = 3.3V)
2.9
2.3
3.6
INPUT VOLTAGE (V)
FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
IO = 0mA
3.1
6.1
6.5
250
VO2 = 2.8V
200
150
100
VO1 = 3.3V
50
0
0
50
100
150
200
250
OUTPUT LOAD (mA)
300
350
FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT
Page 5 of 11
400
ISL9011
Typical Performance Curves
(Continued)
55
175
VO1 = 3.3V
50
GROUND CURRENT (µA)
DROPOUT VOLTAGE, VDO (mV)
150
125
+85°C
+25°C
100
-40°C
75
50
+125°C
+25°C
45
-40°C
40
35
VO1 = 3.3V
VO2 = 2.8V
30
25
IO (BOTH CHANNELS) = 0µA
0
0
25
50
75
100
125
150
175
25
200
3.0
4.0
3.5
OUTPUT LOAD (mA)
4.58
5.0
5.5
6.5
6.0
INPUT VOLTAGE (V)
FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE
55
200
180
50
GROUND CURRENT (µA)
GROUND CURRENT (µA)
160
140
+25°C
+85°C
120
-40°C
100
80
60
40
40
35
VIN = 3.8V
VO1 = 3.3V
VO2 = 2.8V
20
0
45
0
50
100
150
200
250
300
350
VIN = 3.8V
VO = 3.3V
ILOAD = 0µA
30
BOTH OUTPUTS ON
25
-40
400
-25
-10
5
LOAD CURRENT (mA)
VIN
VO1
VO1 (V)
3
VO2
2
1
1
0
0
5
0
1
2
3
4
5
TIME (s)
6
7
8
FIGURE 11. POWER-UP/POWER-DOWN
FN9219 Rev.5.00
March 10, 2008
110 125
VIN = 5.0V
VO1 = 3.3V
VO2 = 2.8V
IL1 = 150mA
IL2 = 300mA
CL-1, CL-2 = 1µF
CBYP = 0.01µF
3
VEN (V)
VOLTAGE (V)
IL2 = 300mA
2
95
VO2 (10mV/DIV)
VO1 = 3.3V
VO2 = 2.8V
IL1 = 150mA
4
80
FIGURE 10. GROUND CURRENT vs TEMPERATURE
FIGURE 9. GROUND CURRENT vs LOAD
5
20 35 50 65
TEMPERATURE (°C)
9
10
0
0
100
200
300
400
500
600
700
800
900 1000
TIME (µs)
FIGURE 12. TURN-ON/TURN-OFF RESPONSE
Page 6 of 11
ISL9011
Typical Performance Curves
(Continued)
VO1 = 3.3V
ILOAD = 150mA
VO2 = 2.8V
ILOAD = 300mA
CLOAD = 1µF
CBYP = 0.01µF
CLOAD = 1µF
CBYP = 0.01µF
4.3V
4.2V
3.6V
3.5V
10mV/DIV
10mV/DIV
400s/DIV
400µs/DIV
FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
100
VIN = 3.6V
VO = 1.8V
IO = 10mA
90
80
VO (25mV/DIV)
CBYP = 0.1µF
VO = 1.8V
VIN = 2.8V
300mA
PSRR (dB)
70
CLOAD = 1µF
60
50
40
30
ILOAD
20
100µA
10
0
0.1
100µs/DIV
FIGURE 15. LOAD TRANSIENT RESPONSE
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 16. PSRR vs FREQUENCY
SPECTRAL NOISE DENSITY (nV/Hz)
1000
100
10
1
VIN = 3.6V
VO = 1.8V
ILOAD = 10mA
CBYP = 0.1µF
CIN = 1µF
CLOAD = 1µF
0.1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY
FN9219 Rev.5.00
March 10, 2008
Page 7 of 11
ISL9011
Pin Description
PIN
NUMBER
PIN
NAME
TYPE
1
VIN
Analog I/O
2
EN1
Low Voltage Compatible
CMOS Input
LDO-1 Enable.
3
EN2
Low Voltage Compatible
CMOS Input
LDO-2 Enable.
4
CBYP
Analog I/O
5, 7, 8
NC
NC
6
GND
Ground
9
VO2
Analog I/O
LDO-2 Output:
Connect capacitor with a value of 1µF to 10µF to GND (1µF recommended).
10
VO1
Analog I/O
LDO-1 Output:
Connect capacitor with a value of 1µF to 10µF to GND (1µF recommended).
DESCRIPTION
Supply Voltage/LDO Input:
Connect a 1µF capacitor to GND.
Reference Bypass Capacitor Pin:
Optionally connect capacitor with a value of 0.01µF to 1µF between this pin and GND to tune
in the desired noise and PSRR performance.
No Connection
GND is the connection to system ground. Connect to PCB Ground plane.
Typical Application
ISL9011
VIN (2.3 TO 6.5V)
1
ON
2
ENABLE1
OFF ON
ENABLE2
OFF
3
4
5
C1
VIN
EN1
VO1
VO2
EN2
NC
CBYP
NC
NC
GND
10
VOUT 1
9
VOUT 2
8
7
6
C2
C3
C4
C1, C3, C4: 1µF X5R CERAMIC CAPACITOR
C2: 0.1µF X5R CERAMIC CAPACITOR
FN9219 Rev.5.00
March 10, 2008
Page 8 of 11
ISL9011
Block Diagram
VIN
IS1
1V
LDO
VREF
VO1
ERROR
TRIM
VO1
AMPLIFIER
QEN1
~1.0V
VO2
LDO-1
EN1
CONTROL
LOGIC
EN2
UVLO
GND
BANDGAP AND
TEMPERATURE
SENSOR
VOLTAGE
REFERENCE
GENERATOR
1.00V
CBYP
Functional Description
The ISL9011 contains all circuitry required to implement two
high performance LDO’s. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9011 adjusts its biasing to achieve the lowest standby
current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, staged turn-on and soft-start.
Smart Thermal shutdown protects the device against
overheating. Staged turn-on and soft-start minimize start-up
input current surges without causing excessive device
turn-on time.
Power Control
The ISL9011 has two separate enable pins (EN1 and EN2)
to individually control power to each of the LDO outputs.
When both EN1 and EN2 are low, the device is in shutdown
FN9219 Rev.5.00
March 10, 2008
QEN2
QEN1
IS2
IS1
LDO-2
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When one or both of the enable pins are asserted, the
device first polls the output of the UVLO detector to ensure
that VIN voltage is at least about 2.1V. Once verified, the
device initiates a start-up sequence. During the start-up
sequence, trim settings are first read and latched. Then,
sequentially, the bandgap, reference voltage and current
generation circuitry power-up. Once the references are
stable, a fast-start circuit quickly charges the external
reference bypass capacitor (connected to the CBYP pin) to
the proper operating voltage. After the bypass capacitor has
been charged, the LDO’s power-up.
If EN1 is brought high, and EN2 goes high before the VO1
output stabilizes, the ISL9011 delays the VO2 turn-on until
the VO1 output reaches its target level.
Page 9 of 11
ISL9011
If EN2 is brought high, and EN1 goes high before VO2 starts
its output ramp, then VO1 turns on first and the ISL9011
delays the VO2 turn-on until the VO1 output reaches its
target level.
If EN2 is brought high, and EN1 goes high after VO2 starts
its output ramp, then the ISL9011 immediately starts to ramp
up the VO1 output.
If both EN1 and EN2 are brought high at the same time, the
VO1 output has priority, and is always powered up first.
During operation, whenever the VIN voltage drops below
about 1.8V, the ISL9011 immediately disables both LDO
outputs. When VIN rises back above 2.1V, the device
re-initiates its start-up sequence and LDO operation will
resume automatically.
Reference Generation
The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter. The filter
includes the external capacitor connected to the CBYP pin.
A 0.01µF capacitor connected CBYP implements a 100Hz
lowpass filter, and is recommended for most high
performance applications. For the lowest noise application, a
0.1µF or greater CBYP capacitor should be used. This filters
the reference noise to below the 10Hz to 1kHz frequency
band, which is crucial in many noise-sensitive applications.
The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider
provides the regulation reference and other voltage
references required for current generation and
over-temperature detection.
The current generator outputs references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9011 provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200m. The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9011 provides short-circuit protection by limiting the
output current to about 475mA.
Each LDO uses an independently trimmed 1V reference. An
internal resistor divider drops the LDO output voltage down
to 1V. This is compared to the 1V reference for regulation.
The resistor division ratio is programmed in the factory.
Overheat Detection
The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +145°C, one or both of the
LDO’s momentarily shut down until the die cools sufficiently.
In the overheat condition, only the LDO sourcing more than
50mA will be shut off. This does not affect the operation of
the other LDO. If both LDOs source more than 50mA and an
overheat condition occurs, both LDO outputs are disabled.
Once the die temperature falls back below about +110°C,
the disabled LDO(s) are re-enabled and soft-start
automatically takes place.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9219 Rev.5.00
March 10, 2008
Page 10 of 11
ISL9011
Dual Flat No-Lead Plastic Package (DFN)
L10.3x3C
2X
0.10 C A
A
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
E
NOMINAL
MAX
NOTES
A
0.85
0.90
0.95
-
A1
-
-
0.05
-
b
B
D2
//
A
C
SEATING
PLANE
0.10 C
D2
0.08 C
7
8
D2/2
1
0.20
0.25
0.30
5, 8
3.00 BSC
2.33
E
E2
A3
SIDE VIEW
(DATUM B)
0.20 REF
D
TOP VIEW
2.38
2.43
7, 8
1.69
7, 8
3.00 BSC
1.59
e
1.64
-
0.50 BSC
-
k
0.20
-
-
-
L
0.35
0.40
0.45
8
N
10
2
Nd
5
3
Rev. 1 4/06
2
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k
2. N is the number of terminals.
(DATUM A)
3. Nd refers to the number of terminals on D.
E2
E2/2
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
NX L
N
8
MIN
A3
6
INDEX
AREA
6
INDEX
AREA
SYMBOL
N-1
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
0.10 M C A B
(A1)
9 L
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
CL
NX (b)
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FN9219 Rev.5.00
March 10, 2008
Page 11 of 11