19-2641; Rev 0; 10/02 KIT ATION EVALU LE B A IL A AV PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets The MAX8500–MAX8504 PWM DC-to-DC buck converters are optimized with integrated bypass FET (0.25Ω typ) to provide power to the PA in N-CDMA and W-CDMA cell phones. The devices have a low on-resistance FET to bypass the external inductor for low dropout of only 150mV at 600mA load, regardless of inductor series resistance. The supply voltage range is from 2.6V to 5.5V and the guaranteed converter output current is 600mA. The 1MHz PWM switching frequency allows for small external components. The MAX8500–MAX8503 are dynamically controlled to provide varying output voltages from 0.4V to VBATT. The LDO regulation point is slightly lower than the PWM converter such that the transition into and out of dropout is smooth, regardless of the inductor resistance. The MAX8504 is programmed for fixed 1.25V to 2.5V output with external resistors. It features a high-power bypass mode that connects the output directly to the battery. All devices are designed to achieve an output settling time of less than 30µs for a full-scale change in output voltage and load current. Features ♦ Integrated Bypass PFET ♦ 150mV Dropout at 600mA Load (Regardless of External Inductor) ♦ Dynamically Adjustable Output from 0.4V to VBATT ♦ Externally Fixed Output from 1.25V to 2.5V with Digitally Controlled High-Power Bypass Mode (MAX8504) ♦ 1MHz Fixed-Frequency PWM Switching ♦ 600mA Guaranteed Output Current ♦ 10% to 100% Duty-Cycle Operation ♦ Low Quiescent Current 280µA (typ) in Normal Mode 3.3mA (typ) in PWM Mode 0.1µA (typ) in Shutdown Mode ♦ 12-Pin Thin QFN (4mm x 4mm, 0.8mm max Height) The MAX8500–MAX8504 are available in a 12-lead 4mm x 4mm thin QFN package (0.8mm max height). Applications N-CDMA/W-CDMA Cellular Phones Wireless PDAs and Modems Typical Operating Circuit Ordering Information PART TEMP RANGE PINPACKAGE TOP MARK MAX8500ETC -40°C to +85°C 12 Thin QFN AABQ MAX8501ETC* -40°C to +85°C 12 Thin QFN — MAX8502ETC* -40°C to +85°C 12 Thin QFN — MAX8503ETC -40°C to +85°C 12 Thin QFN AABU MAX8504ETC -40°C to +85°C 12 Thin QFN AABS *Future product—contact factory for availability. 4.7µH INPUT 2.6V TO 5.5V OUTPUT 0.4V TO VBATT 10µF Pin Configuration 4.7µF BATT LX OUT SKIP SHDN REF LDO PWM REFIN 1MHz OSC gm COMP PGND RC 8.2kΩ CC 1000pF MAX8500MAX8503 GND SHDN SKIP OUT 12 11 10 DAC GND 1 REF 2 REFIN (FB) 3 MAX8500– MAX8504 4 5 6 COMP BATT (HP) PGND 9 BATT 8 BATTP 7 LX Thin QFN 4mm x 4mm ( ) MAX8504 ONLY ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8500–MAX8504 General Description MAX8500–MAX8504 PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets ABSOLUTE MAXIMUM RATINGS BATTP, BATT, OUT, SHDN, SKIP, HP, REFIN, FB to GND ....................................................-0.3V to +6V PGND to GND .......................................................-0.3V to +0.3V REF, COMP to GND ................................-0.3V to (VBATT + 0.3V) LX Current (Note 1) .............................................................2.25A Output Short-Circuit Duration ........................................Indefinite Continuous Power Dissipation (TA = +70°C) 12-Lead Thin QFN (derate 16.9mW/°C above +70°C) .1349mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 1: LX has internal clamp diodes to PGND and BATTP. Applications that forward bias these diodes should take care not to exceed the IC’s package power dissipation limits. ELECTRICAL CHARACTERISTICS (VBATT = VBATTP = 3.6V, SHDN = SKIP = BATT, VREFIN = 1.932V (MAX8500, MAX8502), VREFIN = 1.70V (MAX8501, MAX8503), CREF = 0.22µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER Input BATT Voltage Undervoltage Lockout Threshold Quiescent Current SYMBOL VBATT VUVLO IQ Quiescent Current in Dropout Shutdown Supply Current ISHDN OUT Voltage Accuracy (MAX8500, MAX8502) VOUT OUT Voltage Accuracy (MAX8501, MAX8503) VOUT CONDITIONS VBATT rising, 1% hysteresis MIN 2.6 TYP MAX 5.5 UNITS V 2.15 2.35 2.50 V SKIP = GND 280 450 SKIP = BATT, no switching 450 2200 µA SKIP = BATT, switching 3300 VREFIN = 2.2V (MAX8500, MAX8503), HP = BATT (MAX8504) 400 700 µA SHDN = GND, VBATT = VBATTP = 5.5V 0.1 5 µA VREFIN = 1.932V, load = 0 to 600mA 3.33 3.40 3.47 VREFIN = 0.227V 0.35 0.40 0.45 VREFIN = 1.700V, load = 0 to 600mA 3.33 3.40 3.47 VREFIN = 0.200V 0.35 0.40 0.45 V V OUT Voltage-Load Regulation -0.05 %/A OUT Voltage-Line Regulation 0.007 %/V OUT Input Resistance REFIN Input Current MAX8500, MAX8503 IREF REFIN to OUT Gain (MAX8500, MAX8502) AV REFIN to OUT Gain (MAX8501, MAX8503) AV Reference Voltage LDO linear regulator 1.68 PWM buck VFB FB Input Current (MAX8504) IFB PRDS kΩ +1 LDO linear regulator V/V 1.909 1.225 1.25 µA V/V 2 10µA < IREF < 100 µA FB Voltage Accuracy (MAX8504) 2 0.1 1.76 Reference UVLO P-Channel On-Resistance 245 -1 PWM buck VREF Reference Load Regulation 100 1.275 V 6.25 mV V 0.86 0.96 1.10 1.225 1.250 1.275 V 10 150 nA ILX = 180mA, VBATT = 3.6V 0.35 0.70 ILX = 180mA, VBATT = 2.6V 0.45 VFB = 1.3V _______________________________________________________________________________________ Ω PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets (VBATT = VBATTP = 3.6V, SHDN = SKIP = BATT, VREFIN = 1.932V (MAX8500, MAX8502), VREFIN = 1.70V (MAX8501, MAX8503), CREF = 0.22µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER N-Channel On-Resistance SYMBOL NRDS LDO/Bypass P-Channel On-Resistance P-Channel Current-Limit Threshold ILIMP N-Channel Current-Limit Threshold ILIMN P-Channel Pulse-Skipping Current Threshold ISKIP TYP MAX ILX = 180mA, VBATT = 3.6V CONDITIONS MIN 0.26 0.60 ILX = 180mA, VBATT = 2.6V 0.33 IOUT = 180mA, VBATT = 3.6V 0.25 IOUT = 180mA, VBATT = 2.6V 0.3 0.60 Ω Ω 1.30 1.45 1.60 A SKIP = BATT -0.80 -0.60 -0.40 A SKIP = GND 30 47 65 mA SKIP = GND 118 148 178 mA 0.70 1.00 1.55 A 1.5 A +20 µA LDO/Bypass P-Channel Current-Limit Threshold LX RMS Current (Note 3) LX Leakage Current VBATT = VBATTP = 5.5V, VLX = 0 to 5.5V Maximum Duty Cycle -20 +0.1 100 % SKIP = GND Minimum Duty Cycle UNITS 0 SKIP = BATT 10 13 % COMP Clamp Low Voltage 0.7 1.0 1.1 V COMP Clamp High Voltage 2.0 2.3 2.4 V MAX8500, MAX8501 85 142 200 MAX8502, MAX8503 75 125 175 MAX8504 150 250 350 Transconductance gm Current-Sense Transresistance RCS Internal Oscillator Frequency fOSC 0.8 0.38 Logic Input High VIH 1.6 Logic Input Low VIL 1.0 µS V/A 1.2 MHz 0.4 V 1.0 µA LOGIC INPUTS (SHDN, HP, SKIP) Logic Input Current V 0.1 THERMAL SHUTDOWN Thermal-Shutdown Temperature 160 °C Thermal-Shutdown Hysteresis 15 °C Note 2: Specifications to -40°C are guaranteed by design and not subject to production test. Note 3: Guaranteed by design, not production tested. _______________________________________________________________________________________ 3 MAX8500–MAX8504 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VBATT = 3.6V, TA = +25°C, unless otherwise noted.) EFFICIENCY vs. OUTPUT VOLTAGE IN PWM MODE 90 RLOAD = 15Ω 70 60 RLOAD = 5Ω 80 RLOAD = 15Ω 70 1.0 1.5 2.0 2.5 3.5 3.0 1.5 2.0 2.5 3.0 2.5 3.5 3.5 4.0 4.5 5.5 5.0 MAX8500/MAX8503 DROPOUT VOLTAGE vs. LOAD CURRENT MAX8504 DROPOUT VOLTAGE vs. LOAD CURRENT VOUT = 1.5V; PWM 70 60 VOUT = 3.4V 150 100 VOUT = 2.5V 10 100 0.10 VOUT = 3.5V HP = BATT 0 0 50 0.15 0.05 50 VOUT = 2.5V; PWM 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 1000 MAX8500 toc06 0.20 DROPOUT VOLTAGE (V) 250 200 0.25 MAX8500 toc05 300 MAX8500 toc04 VOUT = 2.5V; NORMAL MODE 1 3.0 EFFICIENCY vs. LOAD CURRENT DROPOUT VOLTAGE (mV) LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA) MAX8500/MAX8503 ENTERING REGULATOR DROPOUT REGION MAX8500/MAX8503 ENTERING REGULATOR DROPOUT REGION MAX8500/MAX8503 ENTERING REGULATOR DROPOUT REGION RLOAD = 15Ω 3.40 VBATT 3.35 RLOAD = 10Ω 3.30 RLOAD = 7.6Ω RLOAD = 5Ω 3.45 3.35 RLOAD = 15Ω RLOAD = 10Ω 3.30 3.25 3.20 L = SUMIDA CDRH3D16-4R7M 3.15 VBATT 3.40 3.15 RLOAD = 7.6Ω 3.45 OUTPUT VOLTAGE (V) 3.45 3.50 OUTPUT VOLTAGE (V) 3.50 3.50 MAX8500 toc09 3.55 MAX8500 toc07 3.55 MAX8500 toc08 EFFICIENCY (%) 1.0 INPUT VOLTAGE (V) VOUT = 1.5V; NORMAL MODE 4 0.5 OUTPUT VOLTAGE (V) 80 3.20 50 0 OUTPUT VOLTAGE (V) 100 90 VOUT = 0.4V SKIP = GND RLOAD = 10Ω 50 0.5 70 SKIP = BATT 50 0 VOUT = 3.4V VOUT = 1.5V 80 60 60 SKIP = GND 3.25 90 EFFICIENCY (%) RLOAD = 5Ω 80 RLOAD = 10Ω EFFICIENCY (%) EFFICIENCY (%) 90 100 MAX8500 toc02 RLOAD = 10Ω EFFICIENCY vs. INPUT VOLTAGE 100 MAX8500 toc01 100 MAX8500 toc03 EFFICIENCY vs. OUTPUT VOLTAGE IN NORMAL MODE OUTPUT VOLTAGE (V) MAX8500–MAX8504 PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets 3.40 3.35 3.30 3.25 VOUT = 3.4V; SKIP = BATT RLOAD = 5Ω L = TOKO D312F-4R7M 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 VBATT (V) VBATT (V) 3.20 0 300 600 900 LOAD CURRENT (mA) _______________________________________________________________________________________ 1200 1500 PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets SUPPLY CURRENT vs. SUPPLY VOLTAGE IN PWM MODE SUPPLY CURRENT vs. SUPPLY VOLTAGE IN NORMAL MODE 4 VOUT = 1.5V 3 2 MAX8500 toc11 700 600 VOUT = 3.4V 500 VIN = 3.6V, VOUT = 3.3V LOAD = 10Ω 300 VOUT = 0.4V 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 400ns/div SUPPLY VOLTAGE (V) LIGHT-LOAD SWITCHING WAVEFORM IN PWM MODE MEDIUM-LOAD SWITCHING WAVEFORM MAX8500 toc13 VIN = 3.6V, VOUT = 1.5V LOAD = 10Ω VOUT AC-COUPLED 2mV/div VOUT = 1.5V SKIP = BATT 0 VLX 2V/div 800 400 VOUT = 0.4V 1 SKIP = GND 900 SUPPLY CURRENT (µA) SUPPLY CURRENT (mA) 5 HEAVY-LOAD SWITCHING WAVEFORM MAX8500 toc12 1000 MAX8500 toc10 6 LIGHT-LOAD SWITCHING WAVEFORM IN SKIP MODE MAX8500 toc14 MAX8500 toc15 VLX 2V/div VLX 2V/div VOUT AC-COUPLED 5mV/div VOUT AC-COUPLED 5mV/div VLX 2V/div VIN = 3.6V, VOUT = 0.4V LOAD = 10Ω VOUT AC-COUPLED 20mV/div VIN = 3.6V, VOUT = 0.4V LOAD = 10Ω 400ns/div 400ns/div 2µs/div _______________________________________________________________________________________ 5 MAX8500–MAX8504 Typical Operating Characteristics (continued) (VBATT = 3.6V, TA = +25°C, unless otherwise noted.) MAX8500–MAX8504 PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets Typical Operating Characteristics (continued) (VBATT = 3.6V, TA = +25°C, unless otherwise noted.) EXITING AND ENTERING SHUTDOWN REFIN TRANSIENT RESPONSE MAX8500 toc16 MAX8500 toc17 REFIN 1V/div SHDN 2V/div VOUT 1V/div SKIP = BATT VOUT 2V/div VIN = 3.6V, VOUT = 3.4V LOAD = 10Ω SKIP = GND VIN = 3.6V, LOAD = 10Ω, REFIN = 0.455 TO 1.932V 100µs/div 20µs/div HP TRANSIENT RESPONSE LINE-TRANSIENT RESPONSE MAX8500 toc18 MAX8500 toc19 VOUT AC-COUPLED 10mV/div HP 1V/div VIN = 3.5V TO 4.5V, VOUT = 1.5V LOAD = 10Ω, VIN = 3.6V, LOAD = 10Ω, HP = 0 TO 1.8V SKIP = GND VOUT 1V/div VIN 500mV/div SKIP = BATT 20µs/div 100µs/div ENTERING AND EXITING DROPOUT MAX8500 toc20 VOUT AC-COUPLED 200mV/div VIN = 3.8V TO 3.4V TO 3.8V, VOUT = 3.4V, LOAD = 600mA VIN 200mV/div 100µs/div 6 _______________________________________________________________________________________ PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets PIN NAME FUNCTION MAX8500– MAX8503 MAX8504 1 1 GND Ground 2 2 REF Reference Bypass Pin. Connect a 0.22µF ceramic capacitor from this pin to GND. 3 — REFIN — 3 FB Output Feedback Sense Input. To set the output voltage, connect FB to the center of an external resistive voltage-divider between OUT and GND. FB voltage regulates to 1.25V when HP is logic 0. 4 4 COMP Compensation. Connect a series resistor and capacitor from this pin to GND to stabilize the regulator (see the Compensation, Stability, and Output Capacitor section). 5, 9 9 BATT IC Supply Voltage Input. Connect to BATTP. — 5 HP 6 6 PGND 7 7 LX Inductor Connection to the Drains of the Internal Power MOSFETs. High impedance in shutdown mode. 8 8 BATTP Power-Supply Voltage Input. Connect to a 2.6V to 5.5V source. Bypass with a low-ESR 10µF capacitor. 10 10 OUT Regulator Output. Connect OUT directly to the output voltage. 11 11 SKIP Skip Control Input. Connect to GND or logic 0 for normal mode. Connect to BATT or logic 1 for forced-PWM mode. 12 12 SHDN Shutdown Control Input. Connect to GND or logic 0 for shutdown mode. Connect to BATT or logic 1 for normal operation. External Reference Input. Connect REFIN to the output of a DA converter for dynamic adjustment of the output voltage. High-Power Bypass Mode. Connect to GND or logic 0 for OUT to regulate to the voltage set by the external resistors on FB. Drive with logic 1 for OUT to be connected to BATT through the internal bypass PFET. Power Ground Detailed Description The MAX8500–MAX8504 PWM step-down DC-to-DC converters with integrated bypass PFET are optimized for low-voltage, battery-powered applications where high efficiency and small size are priorities (such as linear PA applications). An analog control signal dynamically adjusts the MAX8500–MAX8503s’ output voltage from 0.4V to VBATT with a settling time <30µs (Figure 1). The MAX8504 uses external feedback resistors to set the output voltage from 1.25V to 2.5V. The MAX8500–MAX8504 operate at a high 1MHz switching frequency that reduces external component size. Each device includes an internal synchronous rectifier that provides for high efficiency and eliminates the need for an external Schottky diode. The normal operating mode uses constant-frequency PWM switching at medium and heavy loads, and automatically pulse skips at light loads to reduce supply current and extend battery life. An additional forced-PWM mode switches at a constant frequency, regardless of load, to provide a well-controlled spectrum in noise-sensitive applications. Battery life is maximized by low-dropout operation at 100% duty cycle and a 0.1µA (typ) logic-controlled shutdown mode. _______________________________________________________________________________________ 7 MAX8500–MAX8504 Pin Description MAX8500–MAX8504 PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets 4.7µH INPUT 2.6V TO 5.5V OUTPUT 0.4V TO VBATT 10µF 4.7µF BATT LX OUT SKIP SHDN REF LDO PWM REFIN DAC 1MHz OSC gm COMP PGND MAX8500MAX8503 GND RC 8.2kΩ CC 1000pF Figure 1. MAX8500–MAX8503 Functional Diagram and Typical Operating Circuit PWM Control Normal Mode Operation The MAX8500–MAX8504 use a fixed-frequency, currentmode, PWM controller capable of achieving 100% duty cycle. Current-mode feedback provides cycle-by-cycle current limiting, superior load and line response, as well as overcurrent protection for the internal MOSFET and rectifier. A comparator at the P-channel MOSFET switch detects overcurrent at 1.5A. During PWM operation, the MAX8500–MAX8504 regulate output voltage by switching at a constant frequency and then modulating the duty cycle with PWM control. The error-amp output, the main switch current-sense signal, and the slope compensation ramp are all summed using a PWM comparator. The comparator modulates the output power by adjusting the peak inductor current during the first half of each cycle based on the output error voltage. The MAX8500–MAX8504 have relatively low AC loop gain coupled with a high gain integrator to enable the use of a small, low-valued output filter capacitor. The resulting load regulation is 0.03% at 0 to 600mA. Connecting SKIP to GND enables normal operation. This allows automatic PWM control at medium and heavy loads and skip mode at light loads to improve efficiency and reduce quiescent current to 280µA. Operating in normal mode also allows the MAX8500–MAX8504 to pulse skip when the peak inductor current drops below 148mA, corresponding to a load current of approximately 75mA. During skip operation, the MAX8500–MAX8504 switch only as needed to service the load, reducing the switching frequency and associated losses in the internal switch and synchronous rectifier. There are three steady-state operating conditions for the MAX8500–MAX8504 in normal mode. The device performs in continuous conduction for heavy loads in a manner identical to forced-PWM mode. The inductor current becomes discontinuous at medium loads, requiring the synchronous rectifier to be turned off before the end of a cycle as the inductor current reaches zero. The device enters into skip mode when the converter output voltage exceeds its regulation limit before the inductor current reaches its skip threshold level. During skip mode, a switching cycle initiates when the output voltage has dropped out of regulation. The P-channel MOSFET switch turns on and conducts cur- 8 _______________________________________________________________________________________ PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets Dropout voltage at 100% duty cycle is the output current multiplied by the sum of the internal PMOS on-resistance (0.35Ω typ) and the inductor resistance. Once the output voltage drops by 5%, the PFET bypass LDO (MAX8500–MAX8503) turns on and reduces the dropout voltage. The dropout in the bypass PFET equals the load current multiplied by the on-resistance (0.25Ω typ) in parallel with the buck converter and inductor dropout resistance. Forced-PWM Operation Connect SKIP to BATT for forced-PWM operation. Forced-PWM operation is desirable in sensitive RF and data-acquisition applications to ensure that switching harmonics do not interfere with sensitive IF and datasampling frequencies. A minimum load is not required during forced-PWM operation since the synchronous rectifier passes reverse-inductor current as needed to allow constant-frequency operation with no load. ForcedPWM operation uses higher supply current with no load (3.3mA typ) compared to skip mode (280µA typ). Undervoltage Lockout (UVLO) The MAX8500–MAX8504 do not operate with battery voltages below the UVLO threshold of 2.35V (typ). The output remains off until the supply voltage exceeds the UVLO threshold. This guarantees the integrity of the output voltage regulation. Synchronous Rectification An N-channel, synchronous rectifier operates during the second half of each switching cycle (off-time). When the inductor current falls below the N-channel current comparator threshold or when the PWM reaches the end of the oscillator period, the synchronous rectifier turns off. This prevents reverse current from the output to the input in pulse-skipping mode. During PWM operation, the ILIMN threshold adjusts to permit reverse current during light loads. This allows regulation with a constant switching frequency and eliminates minimum load requirements for fixed-frequency operation. 100% Duty-Cycle Operation and Dropout The maximum on-time can exceed one internal oscillator cycle, which permits operation at 100% duty cycle. Near dropout, cycles may be skipped, reducing switching frequency. However, voltage ripple remains small because the current ripple is still low. As the input voltage drops even further, the duty cycle increases until the internal P-channel MOSFET stays on continuously. OUTPUT 1.25V TO 2.5V OR VBATT 4.7µH INPUT 2.6V TO 5.5V 10µF 4.7µF LX BATT OUT OVERCURRENT PROTECTION SKIP SHDN REF PWM 1MHz OSC FB gm HP COMP PGND 1.25V GND RC 9.1kΩ CC 560pF Figure 2. MAX8504 Functional Diagram and Typical Operating Circuit _______________________________________________________________________________________ 9 MAX8500–MAX8504 rent to the output filter capacitor and load until the inductor current reaches the skip peak current limit. Then the main switch turns off, and the magnetic field in the inductor collapses, while current flows through the synchronous rectifier to the output filter capacitor and the load. The synchronous rectifier is turned off when the inductor current reaches zero. The MAX8500–MAX8504 wait until the skip comparator senses a low output voltage again. High-Power Bypass Mode (MAX8504) A high-power bypass mode is available on the MAX8504 for use when a PA transmits at high power. This mode connects OUT to BATT through the bypass PFET. Additionally, the PWM buck converter is forced into 100% duty cycle to further reduce dropout. Shutdown Mode Driving SHDN to GND places the MAX8500–MAX8504 in shutdown mode. In shutdown, the reference, control circuitry, internal switching MOSFET, and synchronous rectifier turn off and the output becomes high impedance. Input current falls to 0.1µA (typ) during shutdown mode. Drive SHDN high for normal operation. Current-Sense Comparators The MAX8500–MAX8504 use several internal currentsense comparators. In PWM operation, the PWM comparator terminates the cycle-by-cycle on-time and provides improved load and line response. A second current-sense comparator used across the P-channel switch controls entry into skip mode. A third currentsense comparator monitors current through the internal N-channel MOSFET to prevent excessive reverse currents and determine when to turn off the synchronous rectifier. A fourth comparator used at the P-channel MOSFET detects overcurrent. A fifth comparator used at the bypass/LDO P-channel MOSFET detects overcurrent in the HP mode or at dropout. This protects the system, external components, and internal MOSFETs under overload conditions. 3.4 WCDMA PA SUPPLY VOLTAGE (V) MAX8500–MAX8504 PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets 3.0 1.0 0.4 0 0 30 300 600 W-CDMA PA SUPPLY CURRENT (mA) Figure 3. Typical W-CDMA Power Amplifier Load Profile LX MAX8504 R1 FB R2 50kΩ Applications Information Setting the Output Voltage Using a DAC (MAX8500–MAX8503) The MAX8500–MAX8503 are optimized for highest system efficiency when applying power to a linear PA in CDMA handsets. When transmitting at less than full power, the supply voltage to the PA is lowered from VBATT to as low as 0.4V to greatly reduce battery current. Figure 3 shows the typical CDMA PA load profile. The use of DC-to-DC converters such as the MAX8500– MAX8503 dramatically extends talk time in these applications. The MAX8500–MAX8503s’ output voltage is dynamically adjustable from 0.4V to VBATT by the use of the REFIN input. The gain from VREFIN to VOUT is internally set to 1.76X (MAX8500 and MAX8502) or 2X (MAX8501 and MAX8503). VOUT can be adjusted during operation by 10 Figure 4. Setting the Adjustable Output Voltage driving REFIN with an external DAC. The MAX8500– MAX8503 output responds to full-scale change in voltage and current in <30µs. Using External Divider (MAX8504) The MAX8504 is intended for two-step VCC control applications where high efficiency is a priority. Select an output voltage between 1.25V and VBATT by connecting FB to a resistive divider between the output and GND (Figure 4). Select feedback resistor R2 in the 5kΩ to 50kΩ range. R1 is then given by: V R1 = R2 × OUT - 1 VFB where VFB = 1.25V. ______________________________________________________________________________________ PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets The input filter capacitor reduces peak currents and noise at the input voltage source. Connect a low-ESR bulk capacitor (≥10µF typ) to the input. Select this bulk capacitor to meet the input ripple requirements and voltage rating rather than capacitance value. Use the following equation to calculate the maximum RMS input current: I IRMS = OUT × VIN VOUT × ( VIN - VOUT ) Compensation, Stability, and Output Capacitor The MAX8500–MAX8504 are externally compensated by placing a resistor and a capacitor (see Figures 1 and 2, RC and CC) in series from COMP to GND. An additional capacitor (Cf) may be required from COMP to GND if high-ESR output capacitors are used. The capacitor integrates the current from the transconductance amplifier, averaging output capacitor ripple. This sets the device speed for transient response and allows the use of small ceramic output capacitors because the phase-shifted capacitor ripple does not disturb the current-regulation loop. The resistor sets the proportional gain of the output error voltage by a factor gm ✕ RC. Increasing this resistor also increases the sensitivity of the control loop to output ripple. The resistor and capacitor set a compensation zero that defines the system’s transient response. The load creates a dynamic pole, shifting in frequency with changes in load. As the load decreases, the pole frequency shifts to the left. System stability requires that the compensation zero must be placed to ensure adequate phase margin (at least 30° at unity gain). See Figures 1 and 2 for RC and CC recommended values. Inductor Selection A 4µH to 6µH inductor is recommended for most applications. For best efficiency, the inductor’s DC resistance should be <400mΩ. Saturation current (ISAT) should be greater than the maximum DC load at the PA’s supply plus half the inductor current ripple. Twostep V CC applications typically require very small inductors with ISAT in the 200mA to 300mA region. See Table 1 and Table 2 for recommended inductors and manufacturers. PC Board Layout and Routing High switching frequencies and large peak currents make PC board layout a very important part of design. Good design minimizes EMI, noise on the feedback paths, and voltage gradients in the ground plane, all of which can result in instability or regulation errors. Connect the inductor, input filter capacitor, and output filter capacitor as close together as possible and keep their traces short, direct, and wide. Connect their ground pins at a single common node in a star ground configuration. The external voltage-feedback network should be very close to the FB pin, within 0.2in (5mm). Keep noisy traces, such as those from the LX pin, away from the voltage-feedback network. Position the bypass capacitors as close as possible to their respective pins to minimize noise coupling. For optimum performance, place input and output capacitors as close to the device as possible. Connect GND and PGND directly under the IC to the exposed paddle. The MAX8504 evaluation kit manual illustrates an example PC board layout and routing scheme. Chip Information TRANSISTOR COUNT: 2530 PROCESS: BiCMOS ______________________________________________________________________________________ 11 MAX8500–MAX8504 Input Capacitor Selection Capacitor ESR is a major contributor to input ripple in high-frequency DC-to-DC converters. Ordinary aluminum electrolytic capacitors have high ESR and should be avoided. Low-ESR tantalum capacitors or polymer capacitors are better and provide a compact solution for space-constrained surface-mount designs. Ceramic capacitors have the lowest ESR overall. MAX8500–MAX8504 PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets Table 1. Suggested Inductors MANUFACTURER Murata Sumida Taiyo Yuden Toko PART NO. INDUCTANCE (µH) ESR (mΩ) SATURATION CURRENT (A) DIMENSIONS (mm) LQH3C CDRH2D18 LBLQ2016 D312F 4.7 4.7 4.7 4.7 200 63 250 320 0.45 0.63 0.21 0.83 2.5 x 3.2 x 2 3.2 x 3.2 x 2 1.6 x 2 x 1.6 3.6 x 3.6 x 1.2 Table 2. Manufacturers of Suggested Components MANUFACTURER PHONE WEBSITE Murata 770-436-1300 www.murata.com Sumida 847-956-0666 (USA) 81-3-3607-5111 (Japan) www.sumida.com Taiyo Yuden 408-573-4150 www.t-yuden.com Toko 847-297-0070 www.tokoam.com 12 ______________________________________________________________________________________ PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets 24L QFN THIN.EPS PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 A ______________________________________________________________________________________ 13 MAX8500–MAX8504 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX8500–MAX8504 PWM Buck Converters with Bypass FET for N-CDMA/W-CDMA Handsets Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 A Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.