LSI/CSI UL ® LS7183N LS7184N LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 April 2009 QUADRATURE CLOCK CONVERTER VDD (Pin 2) Supply Voltage positive terminal. VSS (Pin 3) Supply Voltage negative terminal. A, B (Pin 4, Pin 5) Quadrature Clock inputs A and B. Directional output pulses are generated from the A and B clocks according to Fig. 2. A and B inputs have built-in immunity for noise signals less than 50ns duration (Validation delay, TVD). The A and B inputs are inhibited during the occurrence of a directional output clock (UPCK or DNCK), so that spurious clocks resulting from encoder dither are rejected. MODE (Pin 6) MODE is a 3-state input to select resolution x1, x2 or x4. The input quadrature clock rate is multiplied by factors of 1, 2 and 4 in x1, x2 and x4 mode, respectively, in producing the output UP/DN clocks (See Fig. 2). x1, x2 and x4 modes selected by the MODE input logic levels are as follows: Mode = 0 : x1 selected Mode = 1 : x2 selected Mode = Float : x4 selected 7183N/84N-042709-1 8 UPCK 7 DNCK 6 MODE V DD (+V ) 2 V SS (-V ) 3 A 4 5 B RBIAS 1 8 CLK V DD (+V ) 2 V SS (-V ) 3 A 4 LS7184N INPUT/OUTPUT DESCRIPTION: RBIAS (Pin 1) Input for external component connection. A resistor connected between this input and VSS adjusts the output clock pulse width (Tow). 1 LSI DESCRIPTION: The LS7183N and LS7184N are CMOS quadrature clock converters. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B inputs of the LS7183N / LS7184N, are converted to strings of Up Clocks and Down Clocks (LS7183N) or to a Clock and an Up/Down direction control (LS7184N). These outputs can be interfaced directly with standard Up/Down counters for direction and position sensing of the encoder. RBIAS LS7183N Applications: • Interface incremental encoders to Up / Down Counters (See Figure 6A and Figure 6B) • Interface rotary encoders to Digital Potentiometers (See Figure 7) PIN ASSIGNMENT - TOP VIEW LSI FEATURES: • x1, x2 and x4 resolution • Programmable output pulse width (200ns to 140µs) • Excellent regulation of output pulse width • TTL and low voltage CMOS compatible I/Os • +3V to +12V operation (VDD - VSS) • LS7183N, LS7184N (DIP); LS7183N-S, LS7184N-S (SOIC) - See Figure 1 7 UP/DN 6 MODE 5 B FIGURE 1 LS7183N - DNCK (Pin 7) In LS7183N, this is the DOWN Clock Output. This output consists of low-going pulses generated when A input lags the B input. LS7184N - UP/DN (Pin 7) In LS7184N, this is the count direction indication output. When A input leads the B input, the UP/DN output goes high indicating that the count direction is UP. When A input lags the B input, UP/DN output goes low, indicating that the count direction is DOWN. LS7183N - UPCK (Pin 8) In LS7183N, this is the UP Clock output. This output consists of low-going pulses generated when A input leads the B input. LS7184N - CLK (Pin 8) In LS7184N, this is the combined UP Clock and DOWN Clock output. The count direction at any instant is indicated by the UP/DN output (Pin 7). NOTE: For the LS7184N, the timing of CLK and UP/DN requires that the counter interfacing with LS7184N counts on the rising edge of the CLK pulses. ABSOLUTE MAXIMUM RATINGS: PARAMETER DC Supply Voltage Voltage at any input Operating temperature Storage temperature SYMBOL VDD - VSS VIN TA TSTG VALUE 16.0 VSS - 0.3 to VDD + 0.3 -20 to +85 -55 to +150 UNITS V V °C °C DC ELECTRICAL CHARACTERISTICS: (Unless otherwise specified VDD = 3V to 12V and TA = -20°C to +85°C) PARAMETER Supply Voltage Supply current SYMBOL VDD IDD MIN 3.0 - TYP 185 MAX 12 200 UNITS V µA Logic 0 Logic 1 Logic float Vml Vmh Vmf VDD - 0.5 (VDD /2) - 0.5 - VDD /2 0.5 (VDD /2) + 0.5 V V V - Logic 0 input current Iml Iml Iml Imh Imh Imh - 2.2 3.5 8.3 -2.0 -3.4 -8.2 4.2 6.9 16.2 -9.8 -6.6 -16 µA µA uA µA µA µA VDD = 3V VDD = 5V VDD =12V VDD = 3V VDD = 5V VDD = 12V VABl VABh IABlk 0.7VDD - 0 0.25VDD 10 V V nA - RB 2k - 10M Ohm - Iol Iol Iol Ioh Ioh Ioh - -3.4 -4.8 -7.2 1.7 2.2 3.1 - mA mA mA mA mA mA SYMBOL TOW MIN 190 TYPE - MAX - UNITS ns TVD TVD TVD - 50 25 11 100 50 21 ns ns ns VDD = 3V VDD = 5V VDD = 12V Phase Delay TPS TVD + TOW - Infinite s - Pulse Width TPW 2TPS - Infinite s - Frequency fA, B - - 1/(2TPW) Hz - Inupt to Output Delay TDS TDS TDS - 213 133 78 270 150 63 ns ns ns VDD = 3V VDD = 5V VDD = 12V MODE input: Logic 1 input current A, B inputs: Logic 0 Logic 1 Input current RBIAS input: External resistor CONDITON VDD = 12V, All input frequencies = 0Hz and RBIAS = 2M All outputs: Sink current Source current Vo = 0.5V, VDD = 3V Vo = 0.5V, VDD = 5V Vo = 0.5V, VDD = 12V Vo = 2.5V, VDD = 3V Vo = 4.5V, VDD = 5V Vo = 11.5V, VDD = 12V TRANSIENT CHARACTERISTICS (TA = -20°C to +85°C) PARAMETER Output Clock Pulse Width A, B inputs: Validation Delay 7183N/84N-040609-2 CONDITON See Fig. 2 FORWARD A REVERSE T PW T PS B T PS T DS UPCLK (7183N) 4 1 4 2 T OW DNCLK (7183N) CLK (7184N) 2 4 1 4 2 2 4 1 4 2 2 4 1 4 2 UP/DN (7184N) NOTE: Output clocks labeled 1, 2 and 4 have the following interpretations. 1: Generated in x1, x2 and x4 modes 2: Generated in x2 and x4 modes only 4: Generated in x4 mode only FIGURE 2. LS7183N, LS7184N INPUT/OUTPUT TIMING A DIRECTION FILTER 4 INHIBIT LOGIC B FILTER 5 RBIAS MUX AND BUFFER 8 7 1 CURRENT MIRROR UPCK or CLK DNCK or UP/DN PULSE V DD 1M MODE MODE DECODE 6 1M V DD 2 V SS 3 FIGURE 3. LS7183N, LS7184N BLOCK DIAGRAM The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7183N/84N-121508-3 300 25 V DD = 3V T OW , us 20 15 V DD = 5V 10 V DD = 9V V DD = 12V 5 0 V DD = 3V 250 200 V DD = 5V 150 V DD = 9V V DD = 12V 100 50 0 200 400 600 0 800 0 5 Figure 5. TOW vs RBIAS (R in M ) Figure 4. TOW vs RBIAS (R in k ) A CLOCK 4 ENCODER B CLOCK 5 1 A B RBIAS +V V DD V DD UPCK LS7183N DNCK 8 5 7 4 6 40193 ENCODER CK-DN A CLOCK 4 B CLOCK 5 1 Vss 3 8 CLK A B LS7184N UP/DN V DD 8 15 7 10 CK UP/DN 4516 RBIAS Vss Vss 3 RB FIGURE 6A. TYPICAL APPLICATION FOR LS7183N in x4 MODE 16 2 V DD MODE CK-UP Vss RB +V 16 2 MODE SPDT (On - Off - On) +V +V 6 10 8 FIGURE 6B*. TYPICAL APPLICATION FOR LS7184N WITH MODE SELECTION *See NOTE at bottom right of Page 1 +5V A1 10k 10k 100k 2 B ROTARY ENCODER 1 RBIAS 3 A GND 10k 10k V DD U/D V SS MODE 4 A B 7183N/84N-042709-4 8 1 7 2 6 3 A1 B1 5 4 GND W1 5 CLK V DD U/D CS LS7184N 0.01uF Part Number: RE11CT-V1Y12-EF2CS CLK DIGITAL POTENTIOMETER 0.01uF FIGURE 7. Rotary Encoder Control of Digital Potentiometer AD5220 8 7 6 B1 W1