PRELIMINARY CYW89035 Automotive Grade Bluetooth Low Energy System on a Chip The Cypress CYW89035 is an AECQ100 Automotive Grade, Bluetooth 4.2-compliant, stand-alone baseband processor with an integrated 2.4 GHz transceiver. Manufactured in ISO/TS16949 Automotive Qualified Facilities using the industry's most advanced 40 nm CMOS low-power process, the CYW89035 employs the highest level of integration to eliminate all critical external components, thereby minimizing the device footprint and the automotive qualification costs associated with implementing Bluetooth solutions. The CYW89035 is the optimal solution for automotive connectivity and body control applications including keyless entry, wireless seat and lighting controls, tire pressure monitoring, and other sensor connections. Built-in firmware adheres to the Bluetooth Low Energy (BLE) profile and the BLE Human Interface Device (HID) profile. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table 1. Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number Cypress Part Number BCM89035 CYW89035 BCM89035CWMLG CYW89035CWMLG Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. Acronyms and abbreviations in this document are also defined in Acronyms and Abbreviations on page 42. For a comprehensive list of acronyms and other terms used in Cypress documents, go to http://www.cypress.com/glossary. Applications Key entry and remote start ■ Tire pressure monitoring ■ Environmental controls ■ Seat and lighting controls ■ ■ ■ ■ Sensors and actuators Passenger wearables Lighting controls Features ■ Complies with Bluetooth Core Specification version 4.2 including Basic Rate (BR) BR/BLE ■ Programmable key scan matrix interface, up to 8 × 20 keyscanning matrix ■ Supports Cypress proprietary LE data rate up to 2 Mbps ■ Three-axis quadrature signal decoder ■ BLE HID profile version 1.00 compliant ■ Infrared modulator ■ Bluetooth Device ID profile version 1.3 compliant ■ IR learning ■ Supports Generic Access Profile (GAP) ■ Auxiliary ADC with up to 28 analog channels ■ Supports Adaptive Frequency Hopping (AFH) ■ ■ Excellent receiver sensitivity On-chip support for serial peripheral interface (SPI) (master and slave modes) ■ Programmable output power control ■ Broadcom Serial Communications (BSC) interface (compatible with NXP I2C slaves) ■ Integrated ARM Cortex-M4 microprocessor core floating point unit (FPU) ■ LE package extension ■ On-chip power-on reset (POR) ■ Timed wakeup ■ Support for serial flash interfaces ■ Wireless charging interface ■ Integrated buck and low dropout (LDO) regulators ■ ■ On-chip software controlled power management unit Automotive grade package: ❐ 60-pin wettable flanks quad flat no-lead (QFN) ❐ RoHS compliant Cypress Semiconductor Corporation Document Number: 002-14957 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 14, 2016 PRELIMINARY CYW89035 Figure 1. Functional Block Diagram RF MODEM I2C Master JTAP SPIFFY Dual SPI Quad SPI SW Debug I2C Slave SPIFFY Random Number UART UART PCM (I2S) PKA MIPI DBI-C AES TX/RX DDT SHA JTAG Master ARM SMDMAC ARM CM4/FPU SPI Slave AHB Master Debug UART PTU Main PCM2 (I2S) RX TX CRC CRC Filter CSMACA Decoder BLE RX/TX BlueRF BT RF Scheduler Security Engine BIST Symbol Counter PTU Aux LCU MAC154_TOP GCI BPL AHB Bus Matrix (12/24/48/96 MHz) Patch Control ROM 2MB MTU BT Audio AHB2APB Patch RAM 64KB RAM 320KB OTP 2KB CLB_UPI_MISC CLB_UPI_PMU PWM MIA_KQD Programmable Wait States TRIAC KYS IR IRL MIF (Quad) ADC Control Timer Thick Oxide Retention RAM Analog PMU 16KB Bermuda PDS Cap Touch 3D Glass AVS SPM Watch Dog GPIO Power Domain Digital PMU Sleep Timer DWP Programmable Wait States for LHL LPO Timer VDDC Pause LPO Calibration VDDCG Level Shifter Level Shifter OTP AHB Master VBAT Legend Panama Power Switch HID OFF Timer Wakeup KYS/QUAD/GPIO/Timer HP-LPO 128KHz XTALOSC 32KHz LHL_LSP_PAD GPIO * 40 + IR Power/Ground LP-LPO 16/32/128KHz AUX ADC LHL_TOP RSTN JTAG_SEL LHL_PAD IoT Resources Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website (http://community.cypress.com/). Document Number: 002-14957 Rev. *B Page 2 of 45 PRELIMINARY CYW89035 Contents 1. Functional Description ................................................. 4 1.1 Bluetooth Baseband Core ..................................... 4 1.2 Microprocessor Unit .............................................. 6 1.3 Power Management Unit ....................................... 7 1.4 Integrated Radio Transceiver ................................ 7 1.5 Peripheral Transport Unit ...................................... 8 1.6 UART Interface ...................................................... 9 1.7 Peripheral UART Interface .................................... 9 1.8 Clock Frequencies ............................................... 10 1.9 GPIO Ports .......................................................... 11 1.10 Keyboard Scanner ............................................. 12 1.11 Mouse Quadrature Signal Decoder ................... 13 1.12 PWM .................................................................. 14 1.13 Triac Control ...................................................... 14 1.14 Serial Peripheral Interface ................................. 14 1.15 Infrared Modulator ............................................. 15 1.16 Infrared Learning ............................................... 15 Document Number: 002-14957 Rev. *B 1.17 Security Engine ................................................. 15 1.18 Power Management Unit ................................... 16 2. Pin Assignments and GPIOs ..................................... 17 2.1 Pin Assignments .................................................. 17 2.2 GPIO Pin Descriptions ........................................ 19 2.3 Ball Map .............................................................. 26 3. Specifications ............................................................. 27 3.1 Electrical Characteristics ..................................... 27 3.2 RF Specifications ................................................ 33 3.3 Timing and AC Characteristics ............................ 35 4. Mechanical Information ............................................. 39 4.1 Package Diagram ................................................ 39 4.2 Tray Packaging Specification .............................. 40 5. Ordering Information .................................................. 41 A. Appendix: Acronyms and Abbreviations ................ 42 Document History ........................................................... 44 Sales, Solutions, and Legal Information ...................... 45 Page 3 of 45 PRELIMINARY CYW89035 1. Functional Description 1.1 Bluetooth Baseband Core The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL and TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/ RX data before sending over the air: ■ Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening in the receiver. ■ Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the transmitter. 1.1.1 Bluetooth 4.2 Features The CYW89035 supports the following Bluetooth v4.2 features: ■ LE data packet length extension ■ LE secure connections ■ Link layer privacy 1.1.2 Bluetooth 4.1 Features The CYW89035 supports the following Bluetooth v4.1 features: ■ Secure connections for BR ■ Fast advertising interval ■ Piconet clock adjust ■ Connectionless broadcast ■ LE privacy v1.1 ■ Low duty cycle directed advertising ■ LE dual mode topology 1.1.3 Bluetooth 4.0 Features The BBC supports all Bluetooth 4.0 features, with the following benefits: ■ Dual-mode Bluetooth low energy (BT and BLE operation) ■ Extended inquiry response (EIR): Shortens the time to retrieve the device name, specific profile, and operating mode. ■ Encryption pause resume (EPR): Enables the use of Bluetooth technology in a much more secure environment. ■ Sniff subrating (SSR): Optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery life. ■ Secure simple pairing (SSP): Reduces the number of steps for connecting two devices, with minimal or no user interaction required. ■ Link supervision time out (LSTO): Additional commands added to HCI and Link Management Protocol (LMP) for improved link timeout supervision. ■ Quality of service (QoS) enhancements: Changes to data traffic control, which results in better link performance. Audio, human interface device (HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet boundary flag (PBF) enhancements. Document Number: 002-14957 Rev. *B Page 4 of 45 PRELIMINARY CYW89035 1.1.4 Link Control Layer The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer consists of the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks. Each task is performed in a different state or substate in the Bluetooth Link Controller. ■ BLE states: ❐ Advertising ❐ Scanning ❐ Connection ■ Major states: ❐ Standby ❐ Connection ■ Substates: ❐ Page ❐ Page Scan ❐ Inquiry ❐ Inquiry Scan ❐ Sniff 1.1.5 Test Mode Support The CYW89035 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence. In addition to the standard Bluetooth Test Mode, the CYW89035 also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing. These features include: ■ Fixed frequency carrier wave (unmodulated) transmission ❐ Simplifies some type-approval measurements (Japan) ❐ Aids in transmitter performance analysis ■ Fixed frequency constant receiver mode ❐ Receiver output directed to I/O pin ❐ Allows for direct BER measurements using standard RF test equipment ❐ Facilitates spurious emissions testing for receive mode ■ Fixed frequency constant transmission ❐ 8-bit fixed pattern or PRBS-9 ❐ Enables modulated signal measurements with standard RF test equipment 1.1.6 Frequency Hopping Generator The frequency hopping sequence generator selects the correct hopping channel number based on the link controller state, Bluetooth clock, and device address. Document Number: 002-14957 Rev. *B Page 5 of 45 PRELIMINARY CYW89035 1.2 Microprocessor Unit The CYW89035 microprocessor unit runs software from the link control (LC) layer up to the host controller interface (HCI). The microprocessor is a Cortex-M4 32-bit RISC processor with embedded ICE-RT debug and serial wire debug (SWD) interface units. The microprocessor also includes 2 MB of ROM memory for program storage and 384 KB of RAM for data scratch-pad. The internal ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. At powerup, the lower-layer protocol stack is executed from internal ROM. External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions.The device also supports the integration of user applications and profiles. 1.2.1 Floating Point Unit CYW89035 includes the CM4 single precision IEEE-754 compliant floating point unit. For details see the Cortex-M4 manual. 1.2.2 OTP Memory The CYW89035 includes 2 KB of one-time programmable memory that can be used by the factory to store product-specific information. Note: Use of OTP requires that a 3V supply to be present at all times. 1.2.3 NVRAM Configuration Data and Storage NVRAM contains configuration information about the customer application, including the following: ■ Fractional-N information ■ BD_ADDR ■ UART baud rate ■ SDP service record ■ File system information used for code, code patches, or data. The CYW89035 uses SPI flash for NVRAM storage. 1.2.4 External Reset An external active-low reset signal, RESET_N, can be used to put the CYW89035 in the reset state. An external voltage detector reset IC with 50 ms delay is needed on the RESET_N. The RESET_N should be released only after the VDDO supply voltage level has been stabilized for 50 ms. Figure 2. Reset Timing RESET_N (External) VDDIO ~190 us (*1) VDDC ~2 LPO cycles VDDIO POR 8 LPO cycles VDDC Reset (Internal) XTAL_PU ~2 LPO cycles ~30 LPO cycles XTAL_BUF_PU *1: The latency depends on the value of DEFAULT_STRAP. If DEFAULT_STRAP is high, it’s ~190 us. If DEFAULT_STRAP is low, it’s ~250 us. Document Number: 002-14957 Rev. *B Page 6 of 45 PRELIMINARY CYW89035 1.3 Power Management Unit Figure 3 shows the CYW89035 power management unit (PMU) block diagram. The CYW89035 includes an integrated buck regulator, a capless LDO, PALDO and an additional 1.2V LDO for RF. Figure 3. Power Management Unit PMU CBUCK SR_VDDBAT3V 50 mA SR_VLX SR_VBF DIGLDO DIGLDO_VDDIN1P5 RFLDO_VDDIN1P5 (Capless, with bypass mode) 30 mA RFLDO 20 mA DIGLDO_VDDOUT o_vddout_digldo RFLDO_VDDOUT PMU_AVSS PALDO PALDO_VDDIN_5V NOTE: PALDO_VDDOUT3V = Bump/Ball 1.4 Integrated Radio Transceiver The CYW89035 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. The CYW89035 is fully compliant with the Bluetooth Radio Specification and meets or exceeds the requirements to provide the highest communication link quality of service. 1.4.1 Transmit Path The CYW89035 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band. Digital Modulator The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal. Power Amplifier The CYW89035 has an integrated power amplifier (PA) that can transmit up to +10 dBm for class 1 operations. 1.4.2 Receiver Path The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, with built-in out-of-band attenuation, enables the CYW89035 to be used in most applications with minimal off-chip filtering. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer takes the low-IF received signal and performs an optimal frequency tracking and bitsynchronization algorithm. Receiver Signal Strength Indicator The radio portion of the CYW89035 provides a receiver signal strength indicator (RSSI) signal to the baseband, so that the controller can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. 1.4.3 Local Oscillator A local oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The CYW89035 uses an internal loop filter. Document Number: 002-14957 Rev. *B Page 7 of 45 PRELIMINARY CYW89035 1.4.4 Calibration The CYW89035 radio transceiver features a self-contained automated calibration scheme. No user interaction is required during normal operation or during manufacturing to provide optimal performance. Calibration compensates for filter, matching network, and amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. Calibration takes process and temperature variations into account, and it occurs transparently during normal operation and hop setting times. 1.5 Peripheral Transport Unit 1.5.1 Broadcom Serial Communications Interface The CYW89035 provides a 2-pin master BSC to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse devices. The BSC interface is compatible with I2C slave devices. BSC does not support multimaster capability or flexible wait-state insertion by either master or slave devices. The following transfer clock rates are supported by BSC: ■ 100 kHz ■ 400 kHz ■ 800 kHz (Not a standard I2C-compatible speed.) ■ 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.) The following transfer types are supported by BSC: ■ Read (Up to 8 bytes can be read.) ■ Write (Up to 8 bytes can be written.) ■ Read-then-Write (Up to 8 bytes can be read and up to 8 bytes can be written.) ■ Write-then-Read (Up to 8 bytes can be written and up to 8 bytes can be read.) Hardware controls the transfers, requiring minimal firmware setup and supervision. The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW89035 are required on both the SCL and SDA pins for proper operation. Document Number: 002-14957 Rev. *B Page 8 of 45 PRELIMINARY CYW89035 1.6 UART Interface The CYW89035 includes a UART interface for factory programming and when operating as a BT HCI device in a system with an external host.The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 57600 bps to 6 Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendorspecific UART HCI command. The CYW89035 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud. The UART clock default setting is 24 MHz, and can be configured to run as high as 48 MHz to support up to 6 Mbps. The baud rate of the CYW89035 UART is controlled by two values. The first is a UART clock divisor (set in the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rate adjustment (set in the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can be inserted into the end of each bit time. Table 2 contains example values to generate common baud rates with a 24 MHz UART clock. Table 2. Common Baud Rate Examples, 24 MHz Clock Baud Rate (bps) Baud Rate Adjustment High Nibble Low Nibble Mode Error (%) 3M 0xFF 0xF8 High rate 0.00 2M 0XFF 0XF4 High rate 0.00 1M 0X44 0XFF Normal 0.00 921600 0x05 0x05 Normal 0.16 460800 0x02 0x02 Normal 0.16 230400 0x04 0x04 Normal 0.16 115200 0x00 0x00 Normal 0.16 57600 0x00 0x00 Normal 0.16 Table 3 contains example values to generate common baud rates with a 48 MHz UART clock. Table 3. Common Baud Rate Examples, 48 MHz Clock Baud Rate (bps) High Rate Low Rate Mode Error (%) 6M 0xFF 0xF8 High rate 0 4M 0xFF 0xF4 High rate 0 3M 0x0 0xFF Normal 0 2M 0x44 0xFF Normal 0 1.5M 0x0 0xFE Normal 0 1M 0x0 0xFD Normal 0 921600 0x22 0xFD Normal 0.16 230400 0x0 0xF3 Normal 0.16 115200 0x1 0xE6 Normal –0.08 57600 0x1 0xCC Normal 0.04 Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYW89035 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%. 1.7 Peripheral UART Interface The CYW89035 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed through the optional I/O ports, which can be configured individually and separately for each functional pin. The CYW89035 can map the peripheral UART to any LHL GPIO. The peripheral UART clock is fixed at 24 MHz. Both TX and RX have a 256-byte FIFO (see Table 2 on page 9). Document Number: 002-14957 Rev. *B Page 9 of 45 PRELIMINARY CYW89035 1.8 Clock Frequencies The CYW89035 uses a 24 MHz crystal oscillator (XTAL). 1.8.1 Crystal Oscillator The XTAL must have an accuracy of ±20 ppm as defined by the Bluetooth specification. Two external load capacitors in the range of 5 pF to 30 pF are required to work with the crystal oscillator. The selection of the load capacitors is XTAL-dependent (see Figure 4). Figure 4. Recommended Oscillator Configuration—12 pF Load Crystal 22 pF XIN Crystal XOUT 20 pF Table 4 shows the recommended crystal specifications. Table 4. Reference Crystal Electrical Specifications Parameter Conditions Minimum Nominal frequency – – Oscillation mode – Frequency tolerance Typical Maximum Unit 24.000 – MHz Fundamental – @25°C – ±10 – ppm Tolerance stability over temp @0°C to +70°C – ±10 – ppm Equivalent series resistance – – – 60 Ω Load capacitance – – 10 – pF Operating temperature range – 0 – +70 °C Storage temperature range – –40 – +125 °C Drive level – – – 200 μW Aging – – ±3 ±10 ppm/year Shunt capacitance – – – 2 pF HID Peripheral Block The peripheral blocks of the CYW89035 all run from a single 128 kHz low-power RC oscillator. The oscillator can be turned on at the request of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock request line. The keyboard scanner is a special case, in that it may drop its clock request line even when enabled, and then reassert the clock request line if a keypress is detected. Document Number: 002-14957 Rev. *B Page 10 of 45 PRELIMINARY CYW89035 32 kHz Crystal Oscillator Figure 5 shows the 32 kHz XTAL oscillator with external components and Table 5 on page 11 lists the oscillator’s characteristics. It is a standard Pierce oscillator using a comparator with hysteresis on the output to create a singleended digital output. The hysteresis was added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mV. This circuit can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar frequency. The default component values are: R1 = 10 MΩ and C1 = C2 = ~10 pF. The values of C1 and C2 are used to fine-tune the oscillator. Figure 5. 32 kHz Oscillator Block Diagram C2 32.768 kHz XTAL R1 C1 Table 5. XTAL Oscillator Characteristics Parameter Output frequency Frequency tolerance Symbol Conditions Minimum Typical Maximum Unit Foscout – – 32.768 – kHz – 100 – ppm – Crystal-dependent – – 500 ms Pdrv For crystal selection 0.5 – – μW XTAL series resistance Rseries For crystal selection – – 70 kΩ XTAL shunt capacitance Cshunt For crystal selection – – 1.3 pF Start-up time XTAL drive level Tstartup – 1.9 GPIO Ports 1.9.1 60-Pin QFN Package The 60-pin QFN package GPIO ports are shown in Table 7 on page 19. Document Number: 002-14957 Rev. *B Page 11 of 45 PRELIMINARY CYW89035 1.10 Keyboard Scanner The keyboard scanner is designed to autonomously sample keys and store them into buffer registers without the need for the host microcontroller to intervene. The scanner has the following features: ■ Ability to turn off its clock if no keys are pressed. ■ Sequential scanning of up to 160 keys in an 8 × 20 matrix. ■ Programmable number of columns from 1 to 20. ■ Programmable number of rows from 1 to 8. ■ 16-byte key-code buffer (can be augmented by firmware). ■ 128 kHz clock that allows scanning of full 160-key matrix in about 1.2 ms. ■ N-key rollover with selective 2-key lockout if ghost is detected. ■ Keys are buffered until host microcontroller has a chance to read it, or until overflow occurs. ■ Hardware debouncing and noise/glitch filtering. ■ Low-power consumption. Single-digit µA-level sleep current. 1.10.1 Theory of Operation The key scan block is controlled by a state machine with the following states: Idle The state machine begins in the idle state. In this state, all column outputs are driven high. If any key is pressed, a transition occurs on one of the row inputs. This transition causes the 128 kHz clock to be enabled (if it is not already enabled by another peripheral) and the state machine to enter the scan state. Also in this state, an 8-bit row-hit register and an 8-bit key-index counter is reset to 0. Scan In the scan state, a row counter counts from 0 up to a programmable number of rows minus 1. After the last row is reached, the row counter is reset and the column counter is incremented. This cycle repeats until the row and column counters are both at their respective terminal count values. At that point, the state machine moves into the Scan-End state. As the keys are being scanned, the key-index counter is incremented. This counter value is compared to the modifier key codes stored in RAM, or in the key-code buffer if the key is not a modifier key. It can be used by the microprocessor as an index into a lookup table of usage codes. Also, as the nth row is scanned, the row-hit register is ORed with the current 8-bit row input values if the current column contains two or more row hits. During the scan of any column, if a key is detected at the current row, and the row-hit register indicates that a hit was detected in that same row on a previous column, then a ghost condition may have occurred, and a bit in the status register is set to indicate this. Scan End This state determines whether any keys were detected while in the scan state. If yes, the state machine returns to the scan state. If no, the state machine returns to the idle state, and the 128 kHz clock request signal is made inactive. Note: The microcontroller can poll the key status register. Document Number: 002-14957 Rev. *B Page 12 of 45 PRELIMINARY CYW89035 1.11 Mouse Quadrature Signal Decoder The mouse signal decoder is designed to autonomously sample two quadrature signals commonly generated by an optomechanical mouse. The decoder has the following features: ■ Three pairs of inputs for X, Y, and Z (typical scroll wheel) axis signals. Each axis has two options: ❐ For the X axis, choose P2 or P32 as X0 and P3 or P33 as X1. ❐ For the Y axis, choose P4 or P34 as Y0 and P5 or P35 as Y1. ❐ For the Z axis, choose P6 or P36 as Z0 and P7 or P37 as Z1. ■ Control of up to four external high-current GPIOs to power external optoelectronics: ❐ Turn-on and turn-off time can be staggered for each HC-GPIO to avoid simultaneous switching of high currents and having multiple high-current devices on at the same time. ❐ Sample time can be staggered for each axis. ❐ Sense of the control signal can be active high or active low. ❐ Control signal can be tristated for off condition or driven high or low, as appropriate. 1.11.1 Theory of Operation The mouse decoder block has four 10-bit PWMs for controlling external quadrature devices and sampling the quadrature inputs at its core. The GPIO signals may be used to control such items as LEDs, external ICs that may emulate quadrature signals, photodiodes, and photodetectors. Document Number: 002-14957 Rev. *B Page 13 of 45 PRELIMINARY CYW89035 1.12 PWM The CYW89035 has six internal PWMs. The PWM module consists of the following: ■ PWM0–5. Each of the six PWM channels contains the following registers: ❐ 16-bit initial value register (read/write) ❐ 16-bit toggle register (read/write) ❐ 16-bit PWM counter value register (read) PWM configuration register shared among PWM0–5 (read/write). This 18-bit register is used: ❐ To configure each PWM channel ❐ To select the clock of each PWM channel ❐ To change the phase of each PWM channel Figure 6 shows the structure of one PWM. ■ Figure 6. PWM Block Diagram pwm#_init_val_adr register enable o_flip clk_sel pwm_cfg_adr register pwm#_togg_val_adr register 16 16 pwm#_cntr_adr 16 cntr value is ARM readable pwm_out Example: PWM cntr w/ pwm#_init_val = 0 (dashed line) PWM cntr w/ pwm#_init_val = x (solid line) 16'HFFFF pwm_togg_val_adr 16'Hx 16'H000 pwm_out 1.13 Triac Control The CYW89035 includes hardware support for zero-crossing detection and trigger control for up to four triacs. The CYW89035 detects zero-crossing on the AC zero detection line and uses that to provide a pulse that is offset from the zero crossing. This allows the CYW89035 to be used in dimmer applications, as well as any other applications that require a control signal that is offset from an input event. The zero-crossing hardware includes an option to suppress glitches. 1.14 Serial Peripheral Interface The CYW89035 has two independent SPI interfaces, Both of which support single, dual, and quad mode SPI operations. Either interface can be a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user applications, the CYW89035 has optional I/O ports that can be configured individually and separately for each functional pin. The CYW89035 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW89035 can also act as an SPI slave device that supports a 1.8V or 3.3V SPI master. Note: SPI voltage depends on VDDO/VDDM; therefore, it defines the type of devices that can be supported. Document Number: 002-14957 Rev. *B Page 14 of 45 PRELIMINARY CYW89035 1.15 Infrared Modulator The CYW89035 includes hardware support for infrared TX. The hardware can transmit both modulated and unmodulated waveforms. For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced from firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter. If descriptors are used, they include IR on/off state and the duration between 1–32767 µsec. The CYW89035 IR TX firmware driver inserts this information in a hardware FIFO and makes sure that all descriptors are played out without a glitch due to underrun (see Figure 7). Figure 7. Infrared TX VCC R1 62 D1 INFRARED‐LD CYW89035 R2 Q1 MMBTA42 IR TX 2.4k 1.16 Infrared Learning The CYW89035 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals. For modulated signals, the CYW89035 can detect carrier frequencies between 10 kHz and 500 kHz, and the duration that the signal is present or absent. The CYW89035 firmware driver supports further analysis and compression of the learned signal. The learned signal can then be played back through the CYW89035 IR TX subsystem (see Figure 8). Figure 8. Infrared RX VCC CYW89035 D1 PHOTODIODE IR RX 1.17 Security Engine The CYW89035 includes a hardware security accelerator that greatly decreases the time required to perform typical security operations. These functions include: ■ Public key acceleration (PKA) cryptography ■ AES-CTR/CBC-MAC/CCM acceleration ■ SHA2 message hash and HMAC acceleration ■ RSA encryption and decryption of modulus sizes up to 2048 bits ■ Elliptic curve Diffie-Hellman in prime field GF(p) ■ Generic modular math functions Document Number: 002-14957 Rev. *B Page 15 of 45 PRELIMINARY CYW89035 1.18 Power Management Unit The Power Management Unit (PMU) provides power management features that can be invoked by software through power management registers or packet-handling in the baseband core. 1.18.1 RF Power Management The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz transceiver, which then processes the power-down functions accordingly. 1.18.2 Host Controller Power Management Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the disabling of the on-chip regulator when in HIDOFF (deep sleep) mode. 1.18.3 BBC Power Management There are several low-power operations for the BBC: ■ Physical layer packet handling turns RF on and off dynamically within packet TX and RX. ■ Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYW89035 runs on the Low Power Oscillator and wakes up after a predefined time period. The CYW89035 automatically adjusts its power dissipation based on user activity. The following power modes are supported: ■ Active mode ■ Idle mode ■ Sleep mode ■ HIDOFF (deep sleep) mode The CYW89035 transitions to the next lower state after a programmable period of user inactivity. When user activity resumes, the CYW89035 immediately enters Active mode. In HIDOFF mode, the CYW89035 baseband and core are powered off by disabling power to VDDC_OUT and PAVDD. The VDDO domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power consumption and is used for longer periods of inactivity. Document Number: 002-14957 Rev. *B Page 16 of 45 PRELIMINARY CYW89035 2. Pin Assignments and GPIOs 2.1 Pin Assignments Table 6. Pin Assignments Pin Name QFN Pin I/O Power Domain Description MIC_AVDD 48 I MIC_AVDD Microphone supply MICBIAS 45 I MIC_AVDD Microphone bias supply MICN 47 I MIC_AVDD Microphone negative input MICP 46 I MIC_AVDD Microphone positive input Microphone Baseband Supply BT_VDDO 36 I VDDO I/O pad power supply BT_VDDC 37 I VDDC Baseband core power supply LHL_VDDO 60 I VDDO LHL PAD power supply: can be tied to BT_VDDO RF Power Supply BT_PAVDD2P5 26 I PAVDD2P5 PA supply BT_PLLVDD1P2 31 I PLLVDD1P2 RFPLL and crystal oscillator supply BT_VCOVDD1P2 29 I VCOVDD1P2 VCO supply BT_IFVDD1P2 28 I IFVDD1P2 IFPLL power supply Onboard LDOs DIGLDO_VDDIN1P5 25 I – Internal digital LDO input and feedback pin of switching regulator (CBUCK). RFLDO_VDDIN1P5 24 I – RF LDO input RFLDO_VDDOUT 23 O – RF LDO output PALDO_VDDIN_5V 19 I – PA LDO input PALDO_VDDOUT3V 20 O – PA LDO output SR_VDDBAT3V 22 I – Core buck input SR_VLX 21 O – Core buck output HS-VSS H I Ground Pins VSS Digital ground UART UART_CTS_N 44 I, PU VDDO CTS for HCI UART interface: NC if unused. UART_RTS_N 43 O, PU VDDO RTS for HCI UART interface. NC if unused. UART_RXD 41 I VDDO UART serial input. Serial data input for the HCI UART interface. UART_TXD 42 O, PU VDDO UART serial input. Serial data input for the HCI UART interface. Serial Peripheral Interface SPI_MISO 40 I VDDO SPI Master In Slave Out SPI_MOSI 39 O VDDO SPI Master Out Slave In SPI_CSN 38 O VDDO SPI Chip Select SPI_CLK 35 O VDDO SPI Clock Document Number: 002-14957 Rev. *B Page 17 of 45 PRELIMINARY CYW89035 Table 6. Pin Assignments (Cont.) Pin Name QFN Pin I/O Power Domain Description Crystal BT_XTALI 32 I PLLVDD1P2 Crystal oscillator input: see “Crystal Oscillator” on page 10 for options BT_XTALO 33 O PLLVDD1P2 Crystal oscillator output XTALI_32K 50 I VDDO Low-power oscillator input XTALO_32K 49 O VDDO Low-power oscillator output DEFAULT_STRAP 18 I Others VDDO Connect to VDDO Host wake-up. This is a signal from the Bluetooth device to the host indicating that the Bluetooth device requires attention. BT_HOST_WAKE 34 O VDDO ■ Asserted: Host device must wake up or remain awake. ■ Deasserted: Host device may sleep when sleep criteria is met. The polarity of this signal is software configurable and can be asserted high or low. BT_RF 27 I/O PAVDD2P5 JTAG_SEL 17 – – RST_N 16 I VDDO NC 30 Document Number: 002-14957 Rev. *B RF antenna port ARM JTAG debug mode control: connect to GND for all applications Active-low system reset with open-drain output and internal pull-up resistor Leave floating Page 18 of 45 PRELIMINARY CYW89035 2.2 GPIO Pin Descriptions Table 7. GPIO Pin Descriptionsab Pin Number 8 Pin Name Default Direction P0 Input POR State Floating Power Domain VDDO Default Alternate Function Description ■ GPIO: P0 ■ Keyboard scan input (row): KSI0 ■ A/D converter input 29 ■ Peripheral UART: puart_tx ■ SPI_1: MOSI (master and slave) ■ IR_RX ■ 60Hz_main Note: Not available during TM1 = 1. 9 52 53 P1 P2 P3 Document Number: 002-14957 Rev. *B Input Input Input Floating Floating Floating VDDO VDDO VDDO ■ GPIO: P1 ■ Keyboard scan input (row): KSI1 ■ A/D converter input 28 ■ Peripheral UART: puart_rts ■ SPI_1: MISO (master and slave) ■ IR_TX ■ GPIO: P2 ■ Keyboard scan input (row): KSI2 ■ Quadrature: QDX0 ■ Peripheral UART: puart_rx ■ SPI_1: SPI_CS (slave only) ■ SPI_1: MOSI (master only) ■ GPIO: P3 ■ Keyboard scan input (row): KSI3 ■ Quadrature: QDX1 ■ Peripheral UART: puart_cts ■ SPI_1: SPI_CLK (master and slave) Page 19 of 45 PRELIMINARY CYW89035 Table 7. GPIO Pin Descriptionsab (Cont.) Pin Number 54 55 56 57 Pin Name Default Direction P4 P5 P6 P7 Document Number: 002-14957 Rev. *B Input Input Input Input POR State Floating Floating Floating Floating Power Domain VDDO VDDO VDDO VDDO Default Alternate Function Description ■ GPIO: P4 ■ Keyboard scan input (row): KSI4 ■ Quadrature: QDY0 ■ Peripheral UART: puart_rx ■ SPI_1: MOSI (master and slave) ■ IR_TX ■ GPIO: P5 ■ Keyboard scan input (row): KSI5 ■ Quadrature: QDY1 ■ Peripheral UART: puart_tx ■ SPI_1: MISO (master and slave) ■ BSC: SDA ■ GPIO: P6 ■ Keyboard scan input (row): KSI6 ■ Quadrature: QDZ0 ■ Peripheral UART: puart_rts ■ SPI_1: SPI_CS (slave only) ■ 60Hz_main ■ GPIO: P7 ■ Keyboard scan input (row): KSI7 ■ Quadrature: QDZ1 ■ Peripheral UART: puart_cts ■ SPI_1: SPI_CLK (master and slave) ■ BSC: SCL Page 20 of 45 PRELIMINARY CYW89035 Table 7. GPIO Pin Descriptionsab (Cont.) Pin Number 58 1 2 3 4 5 Pin Name Default Direction P8 P9 P10 P11 P12 P13 Document Number: 002-14957 Rev. *B Input Input Input Input Input Input POR State Floating Floating Floating Floating Floating Floating Power Domain VDDO VDDO VDDO VDDO VDDO VDDO Default Alternate Function Description ■ GPIO: P8 ■ Keyboard scan output (column): KSO0 ■ A/D converter input 27 ■ External T/R switch control: ~tx_pd ■ GPIO: P9 ■ Keyboard scan output (column): KSO1 ■ A/D converter input 26 ■ External T/R switch control: tx_pd ■ GPIO: P10 ■ Keyboard scan output (column): KSO2 ■ A/D converter input 25 ■ External PA ramp control: ~PA_Ramp ■ GPIO: P11 ■ Keyboard scan output (column): KSO3 ■ A/D converter input 24 ■ GPIO: P12 ■ Keyboard scan output (column): KSO4 ■ A/D converter input 23 ■ GPIO: P13 ■ Keyboard scan output (column): KSO5 ■ A/D converter input 22 ■ PWM3 ■ Triac control 3 Page 21 of 45 PRELIMINARY CYW89035 Table 7. GPIO Pin Descriptionsab (Cont.) Pin Number 59 50 51 13 Pin Name Default Direction P14 P15 P16 P26 PWM0 Input Input Input Input POR State Floating Floating Floating Floating Power Domain VDDO VDDO VDDO VDDO Default Alternate Function Description ■ GPIO: P14 ■ Keyboard scan output (column): KSO6 ■ A/D converter input 21 ■ PWM2 ■ Triac control 4 ■ GPIO: P15 ■ Keyboard scan output (column): KSO7 ■ A/D converter input 20 ■ IR_RX ■ 60Hz_main ■ GPIO: P16 ■ Keyboard scan output (column): KSO8 ■ A/D converter input 19 ■ GPIO: P26 ■ Keyboard scan output (column): KSO18 ■ SPI_1: SPI_CS (slave only) ■ Optical control output: QOC0 ■ Triac control 1 Current: 16 mA sink 14 P27 PWM1 Input Floating VDDO ■ GPIO: P27 ■ Keyboard scan output (column): KSO19 ■ SPI_1: MOSI (master and slave) ■ Optical control output: QOC1 ■ Triac control 2 Current: 16 mA sink Document Number: 002-14957 Rev. *B Page 22 of 45 PRELIMINARY CYW89035 Table 7. GPIO Pin Descriptionsab (Cont.) Pin Number 6 Pin Name Default Direction P28 PWM2 Input POR State Floating Power Domain VDDO Default Alternate Function Description ■ GPIO: P28 ■ Optical control output: QOC2 ■ A/D converter input 11 ■ LED1 Current: 16 mA sink 7 P29 PWM3 Input Floating VDDO ■ GPIO: P29 ■ Optical control output: QOC3 ■ A/D converter input 10 ■ LED2 Current: 16 mA sink 15 10 11 P32 P34 P38 Document Number: 002-14957 Rev. *B Input Input Input Floating Floating Floating VDDO VDDO VDDO ■ GPIO: P32 ■ A/D converter input 7 ■ Quadrature: QDX0 ■ SPI_1: SPI_CS (slave only) ■ Auxiliary clock output: ACLK0 ■ Peripheral UART: puart_tx ■ GPIO: P34 ■ A/D converter input 5 ■ Quadrature: QDY0 ■ Peripheral UART: puart_rx ■ External T/R switch control: tx_pd ■ GPIO: P38 ■ A/D converter input 1 ■ SPI_1: MOSI (master and slave) ■ IR_TX Page 23 of 45 PRELIMINARY CYW89035 Table 7. GPIO Pin Descriptionsab (Cont.) Pin Number 12 Pin Name Default Direction P39 Input POR State Floating Power Domain VDDO Default Alternate Function Description ■ GPIO: P39 ■ SPI_1: SPI_CS (slave only) ■ External PA ramp control: PA_Ramp ■ 60Hz_main a. All GPIOs are supermux. All GPIOs can be programmed for any alternative functions. For example, key scan, SPI, I2C, IR_TX, quadrature, peripheral UART, ADC, etc. b. During power-on reset, all inputs are disabled. Document Number: 002-14957 Rev. *B Page 24 of 45 PRELIMINARY CYW89035 Table 8. GPIO Supermux Input/Output Function List Function Function Function Function SPI_1: CLK SPI_1: CS SPI_1: MOSI SPI_1: MISO SPI_1: INT SPI_2: CLK SPI_2: CS SPI_2: MOSI SPI_2: MISO SPI_2: INT SPI_3: CLK SPI_3: CS SPI_3: MOSI SPI_3: MISO SPI_3: INT UART_RX UART_CTS UART_TX UART_RTS PUART_RX PUART_CTS PUART_TX PUART_RTS SCL SDA SCL2 SDA2 PCM_IN PCM_OUT PCM_CLK PCM_SYNC I2S_DO I2S_DI I2S_WS I2S_CLK IR_TX kso0 kso1 kso2 kso3 kso4 kso5 kso6 kso7 kso8 kso9 kso10 kso11 kso12 kso13 kso14 kso15 kso16 kso17 kso18 kso19 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 aclk0 aclk1 pa_ramp tx_pd ~tx_pd – Document Number: 002-14957 Rev. *B Page 25 of 45 PRELIMINARY CYW89035 2.3 Ball Map The 60-pin QFN package is shown in Figure 9. Figure 9. CYW89035 60-Pin QFN Package MICP MICN MIC_AVDD XTALO_32K P15/XTALI_32K P2 P16 P3 P4 P7 P6 P5 P8 P9 P10 P11 P12 P13 P28 P29 P0 P1 P34 P38 P39 P26 P27 P32 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 H MICBIAS UART_CTS_N UART_RTS_N UART_TXD UART_RXD SPI_MISO SPI_MOSI SPI_CSN BT_VDDC BT_VDDO SPI_CLK BT_HOST_WAKE BT_XTALO BT_XTALI BT_PLLVDD1P2 ͲͲͲ BT_VCOVDD1P2 BT_IFVDD1P2 BT_RF BT_PAVDD2P5 RFLDO_VDDIN1P5 DIGLDO_VDDIN1P5 SR_VDDBAT3V RFLDO_VDDOUT DEFAULT_STRAP PALDO_VDDIN_5V PALDO_VDDOUT3V SR_VLX RST_N HSͲVSS JTAG_SEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P14 LHL_VDDO 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Note: Pin H is a ground pin that is used for the signal name HS-VSS. Document Number: 002-14957 Rev. *B Page 26 of 45 PRELIMINARY CYW89035 3. Specifications 3.1 Electrical Characteristics Table 9 shows the maximum electrical rating for voltages referenced to VDD pin. Table 9. Absolute Maximum Voltages Requirement Parameter Ambient Temperature of Operation Specification Min. Nom. – 25 Max. Unit °C Storage temperature –40 – 150 °C ESD Tolerance HBM –2000 – 2000 V ESD Tolerance MM –100 – 100 V ESD Tolerance CDM –500 – 500 V Latch-up – 200 – mA VDD IO 1.62 3.3 3.6 V VDD RF 1.14 1.2 1.26 V VDDBAT3V 1.62 3.0 3.63 V DIGLDO_VDDIN1P5 1.2 1.35 1.5 V RFLDO_VDDIN1P5 1.3 1.35 1.5 V PALDO_VDDIN_5V 2.5 3.0 3.63 V Document Number: 002-14957 Rev. *B Page 27 of 45 PRELIMINARY CYW89035 3.1.1 Core Buck Regulator Table 10. Core Buck Regulator Parameter Input supply voltage DC, VBAT Conditions DC voltage range CBUCK output current – Min. Typ. Max. Unit 1.62 3.0 3.63 V – – 65 mA 1.2 1.35 1.5 V –4 –2 – +4 +2 % % Output voltage range Programmable, 30mV/step default = 1.35V (bits = 0000) Output voltage DC accuracy Includes load and line regulation: Before trimming After trimming LPOM ripple voltage, static Measured with 20 MHz bandwidth limit, static load. Max ripple based on VBAT = 3V, Vout = 1.35V Inductor: 0806 inch-size, Tmax = 1 mm, 2.2 μH ±25%, DCR = 114 mΩ ±20%, ACR<1Ω (for frequency <1 MHz) Capacitor: 1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor + board total-ESR < 20 mΩ – – 30 mVpp Efficiency (high load) 10–50 mA load current, Vout = 1.35V, Vbat = 3V @25°C Inductor: 0806 inch-size, Tmax = 1 mm, 2.2 μH ±25%, DCR = 114 mΩ ±20%, ACR<1Ω (for frequency<1 MHz) Capacitor: 1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor +board total-ESR < 20 mΩ – 85 – % Efficiency (low load) 1–5 mA load current, Vout = 1.35V, Vbat = 3V @25°C Inductor: 0806 inch-size, Tmax = 1 mm, 2.2 μH ±25%, DCR = 114 mΩ ±20%, ACR<1Ω (for frequency<1 MHz) Capacitor: 1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor +board total-ESR < 20 mΩ – 80 – % Startup time See Table 11 on page 29. – – – – External inductor L 2.2 μH ±25%, DCR = 114 mΩ ±20%, ACR<1Ω (for frequency<1 MHz) – 2.2 – μH External output capacitor, Cout 1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor +board total-ESR < 20 mΩ 0.7 1 1.1 μF External input capacitor, Cin For SR_VDDBAT 3V pin Ceramic, X5R, 0402, ESR<30 mΩ at 4 MHz, +/-20%, 6.3V, 4.7 μF 0.7 4.7 5.64 μF Input supply voltage ramp-up time 0 to 3.3V 40 – – μs ■ Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging. ■ Maximum capacitor value refers to the total capacitance seen at a node where the capacitor is connected. This also includes any decoupling capacitors connected at the load side, if any. Document Number: 002-14957 Rev. *B Page 28 of 45 PRELIMINARY CYW89035 3.1.2 Digital LDO Table 11. Digital LDO Parameter Conditions Min. Typ. Max. Unit Input supply voltage, Vin Minimum Vin = Vo + 0.12V requirement must be met under maximum load. 1.2 1.35 1.6 V Nominal output voltage,Vo Internal default bit setting – 1.1 – V Output voltage programmability Range Step size Accuracy at any step (including line/load regulation) before trimming Accuracy at any step (including line/load regulation) after trimming 0.9 – –4 – 10 – 1.25 – +4 V mV % –2 – +2 % – – 120 mV 0.2a – 40 mA Dropout voltage At maximum load Output current DC load Output loading capacitor Internal, including the decoupling capacitor to be placed next to the load and the equivalent loading capacitor by the core. 4 – 10 nF Quiescent current At no load, excluding main bandgap Iq – 90 120 μA Line regulation Vin from (Vo+0.12V) to 1.5V; 40 mA load – – 5 mV/V Load regulation Load from 1 mA to 25 mA; Vin (Vo+0.12V) – 0.025 0.045 mV/mA Leakage current In full power-down mode or bypass mode: Junction temperature: 25°C Junction temperature: 125°C – – 0.05 1.1 0.2 5.0 μA μA PSRR @1 kHz, Vin, Vo+0.12V Output cap of 4 nF~10 nF 40 – – dB LDO turn-on time LDO turn-on time when balance of chip is up – – 22 μs External input capacitor Only use an external input capacitor at VDD_DIGLDO1P5 pin if it is not supplied from CBUCK output. – 1 2.2 μF a. By default, an internal loading of ~0.2 mA resides inside the LDO. This is to ensure the LDO is stable with zero loading from the core. After the core is up, digital logic can disable this internal loading by setting i_ldo_cntl<8:7> to 00. Document Number: 002-14957 Rev. *B Page 29 of 45 PRELIMINARY CYW89035 3.1.3 PA LDO Table 12. PA LDO Specification Notes Input supply voltage Min = 3.0 + 0.1V = 3.1V Dropout voltage requirement must be met under max load for performance specs Output current Junction temperature 125°C Min. Typ. Max. Units 2.5 3.3 3.63 V – – 50 mA Output voltage (Vo) Default = 3.0V 2.4 3.0 3.4 V Dropout voltage At max. load – – 100 mV Output voltage DC accuracy Include line/load regulation –5 +5 % Quiescent current No load – – μA Line regulation Vin from (Vo + 0.1V) to 4.8V, max load Load regulation Load from 1 mA to 50 mA Leakage current In Power-Down mode at 25°C junction temp PSRR 8 +0.2 %Vo/V 0.02 0.05 %Vo/mA – 0.3 – μA Vbat 3.6V, Vo = 2.5V, Co = l µF, max load, 100 Hz to 100 kHz 20 – LDO turn-on time LDO turn-on time when the rest of the chip is up – – 100 μs In-rush current during turn-on From its output cap in the fully-discharged state – – 70 mA External output capacitor (Co) Ceramic, X5R, 0402, (ESR: 30m–200 mΩ), ±10%, 6.3V 0.44 1 – μF External input capacitor For PALDO_VDDIN_5V pin Ceramic, X5R, 0402, (ESR: 30m-200 mΩ), ±10%, 6.3V – 1 – μF Operating temperature Junction temperature –40 50 125 °C Document Number: 002-14957 Rev. *B –0.2 dB Page 30 of 45 PRELIMINARY CYW89035 3.1.4 RF LDO Table 13. RF LDO Parameter Conditions Min. Typ. Max. Unit Input supply voltage, Vin Min Vin = Vo + 0.15V = 1.35V (for Vo = 1.2V) Dropout voltage requirement must be met under maximum load. 1.2 1.35 1.5 V Nominal output voltage,Vo Internal default bit setting 000 – 1.2 – V 1.1 – 1.275 V Step size – 25 – mV Accuracy at any step (including line/load regulation) –4 – +4 % Accuracy at any step (including line/load regulation) after trimming –2 – +2 % Dropout voltage At maximum load – – 150 mV Output current TBD Range Output voltage programmability 0.1 – 25 mA No load – 44 – μA Maximum load – 200 – μA Vin from (Vo+0.15V) to 1.5V; 25 mA load – – 5.5 mV/V Load regulation Load from 1 mA to 25 mA; Vin≥ (Vo+0.15V) – 0.025 0.045 mV/mA Load step error Load step from 1 mA–25 mA in 1 μs and 25 mA–1 mA in 1μs; Vin(Vo+0.15V); Co = 2.2 μF – – 35 mV Leakage current Power-down junction temperature: 85°C – – 10 μA @30 kHz, 25 mA load, Co = 2.2 μF – – 60 nV/√Hz Quiescent current Line regulation Output noise @100 kHz, 25 mA load, Co = 2.2 μF – – 35 nV/√Hz PSRR @1kHz, Input > 1.35V, Co = 2.2 μF, Vo = 1.2V 20 – – dB LDO turn-on time LDO turn-on time when balance of chip is up – 140 180 μs In-rush current Vin = Vo+0.15V to 1.5V, Co = 2.2 μF, no load – – 100 mA 0.5 2.2 4.7 μF – 1 2.2 μF External output capacitor, Co Total ESR (trace/cap): 5 m–240 mΩ External input capacitor Only use an external input capacitor at RFLDO_VDDIN1P5 pin if it is not supplied from CBUCK output. Note: Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging. Document Number: 002-14957 Rev. *B Page 31 of 45 PRELIMINARY CYW89035 3.1.5 Digital I/O Characteristics Table 14. Digital I/O Characteristics Characteristics Symbol Minimum Typical Maximum Unit Input low voltage (VDDO = 3.3V) VIL – – 0.8 V Input high voltage (VDDO = 3.3V) VIH 2.0 – – V Input low voltage (VDDO = 1.8V) VIL – – 0.6 V Input high voltage (VDDO = 1.8V) VIH 1.1 – – V Output low voltage VOL – – 0.4 V Output high voltage VOH VDDO – 0.4V – – V Input low current IIL – – 1.0 μA Input high current IIH – – 1.0 μA Output low current (VDDO = 3.3V, VOL = 0.4V) IOL – – 2.0 mA Output high current (VDDO = 3.3V, VOH = 2.9V) IOH – – 4.0 mA Output high current (VDDO = 1.8V, VOH = 1.4V) IOH – – 2.0 mA Input capacitance CIN – – 0.4 pF 3.1.6 Current Consumption In Table 15, current consumption measurements are taken at VBAT with the assumption that VBAT is connected to VDDIO and LDOIN. Table 15. BLE Current Consumption Operational Mode Conditions Typical Max. Unit Receiving Receiver and baseband are both operating, 100% ON. 8 – mA Transmitting Transmitter and baseband are both operating, 100% ON. 18 – mA Advertising 1.28s direct advertising in low power idle mode 30 – µA Connecting 1-second connection interval in low power idle mode 25 – μA 1 – μA HIDOFF (Deep Sleep) Document Number: 002-14957 Rev. *B – Page 32 of 45 PRELIMINARY CYW89035 3.2 RF Specifications Note: ■ Table 16 and Table 17 on page 34 apply to single-ended industrial temperatures. Unused inputs are left open. Table 16. Receiver RF Specifications Parameter Minimum Typical a Maximum Unit – 2402 – 2480 MHz – – –91.5 – – GFSK, 1 Mbps – – –20 dBm Conditions General Frequency range RX sensitivity b Maximum input Interference Performance TBD Out-of-Band Blocking Performance (CW)c 30 MHz–2000 MHz 0.1% BER – –10.0 – dBm 2000–2399 MHz 0.1% BER – –27 – dBm 2498–3000 MHz 0.1% BER – –27 – dBm 3000 MHz–12.75 GHz 0.1% BER – –10.0 – dBm –39.0 – – dBm – – –62 dBm d Intermodulation Performance BT, Df = 4 MHz – e Spurious Emissions 30 MHz to 1 GHz – 1 GHz to 12.75 GHz – – – –47 dBm 65 MHz to 108 MHz FM RX – –147 – dBm/Hz 746 MHz to 764 MHz CDMA – –147 – dBm/Hz 851–894 MHz CDMA – –147 – dBm/Hz 925–960 MHz EDGE/GSM – –147 – dBm/Hz 1805–1880 MHz EDGE/GSM – –147 – dBm/Hz 1930–1990 MHz PCS – –147 – dBm/Hz 2110–2170 MHz WCDMA – –147 – dBm/Hz a. b. c. d. Typical operating conditions are 1.22V operating voltage and 25°C ambient temperature. The receiver sensitivity is measured at BER of 0.1% on the device interface. Meets this specification using front-end band pass filter. f0 = –64 dBm Bluetooth-modulated signal, f1 = –39 dBm sine wave, f2 = –39 dBm Bluetooth-modulated signal, f0 = 2f1 – f2, and |f2 – f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4. e. Includes baseband radiated emissions. Document Number: 002-14957 Rev. *B Page 33 of 45 PRELIMINARY CYW89035 Table 17. Transmitter RF Specifications (TBD) Parameter Conditions Minimum Typical Maximum Unit General Frequency range – 2402 – 2480 MHz Class 1: GFSK TX power – – 10 – dBm – 2 4 8 dB – –36.0a Power control step Out-of-Band Spurious Emissions 30 MHz to 1 GHz – – –30.0 dBm a, b dBm 1 GHz to 12.75 GHz – – – 1.8 GHz to 1.9 GHz – – – –47.0 dBm 5.15 GHz to 5.3 GHz – – – –47.0 dBm Conditions Minimum Typical Maximum Unit N/A 2402 – 2480 MHz GFSK, 0.1% BER, 1 Mbps – –94.5 – dBm N/A – 9 – dBm a. Maximum value is the value required for Bluetooth qualification. b. Meets this spec using a front-end band-pass filter. Table 18. BLE RF Specifications Parameter Frequency range RX sensea TX power b Mod Char: Delta F1 average N/A 225 255 275 kHz Mod Char: Delta F2 maxc N/A 99.9 – – % Mod Char: Ratio N/A 0.8 0.95 – % a. Dirty TX is Off. b. The BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc. The output is capped at 12 dBm out. The BLE TX power at the antenna port cannot exceed the 10 dBm EIRP specification limit. c. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. Document Number: 002-14957 Rev. *B Page 34 of 45 PRELIMINARY CYW89035 3.3 Timing and AC Characteristics In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams. 3.3.1 UART Timing Table 19. UART Timing Specifications Reference Min. Max. Unit 1 Delay time, UART_CTS_N low to UART_TXD valid Characteristics – 24 Baud out cycles 2 Setup time, UART_CTS_N high before midpoint of stop bit – 10 ns 3 Delay time, midpoint of stop bit to UART_RTS_N high – 2 Baud out cycles Figure 10. UART Timing Document Number: 002-14957 Rev. *B Page 35 of 45 PRELIMINARY CYW89035 3.3.2 SPI Timing The SPI interface can be clocked up to 12 MHz. Table 20 and Figure 11 show the timing requirements when operating in SPI Mode 0 and 2. Table 20. SPI Mode 0 and 2 Reference 1 Characteristics Min. Max. Unit Time from master assert SPI_CSN to first clock edge 45 – ns 2 Hold time for MOSI data lines 12 ½ SCK ns 3 Time from last sample on MOSI/MISO to slave deassert SPI_INT 0 100 ns 4 Time from slave deassert SPI_INT to master deassert SPI_CSN 0 – ns 5 Idle time between subsequent SPI transactions 1 SCK – ns Figure 11. SPI Timing, Mode 0 and 2 5 SPI_CSN SPI_INT (DirectWrite) 3 4 SPI_INT (DirectRead) 1 SPI_CLK (Mode 0) SPI_CLK (Mode 2) 2 First Bit SPI_MOSI SPI_MISO Not Driven First Bit Document Number: 002-14957 Rev. *B Second Bit Last bit Second Bit Last bit Not Driven Page 36 of 45 PRELIMINARY CYW89035 Table 21 and Figure 12 show the timing requirements when operating in SPI Mode 1 and 3. Table 21. SPI Mode 1 and 3 Reference Characteristics Min. Max. Unit 1 Time from master assert SPI_CSN to first clock edge 45 – ns 2 Hold time for MOSI data lines 12 ½ SCK ns 3 Time from last sample on MOSI/MISO to slave deassert SPI_INT 0 100 ns 4 Time from slave deassert SPI_INT to master deassert SPI_CSN 0 – ns 5 Idle time between subsequent SPI transactions 1 SCK – ns Figure 12. SPI Timing, Mode 1 and 3 SPI_CSN 5 SPI_INT (DirectWrite) 3 4 SPI_INT (DirectRead) SPI_CLK (Mode 1) 1 SPI_CLK (Mode 3) 2 SPI_MOSI SPI_MISO Not Driven Invalid bit First bit Last bit Invalid bit First bit Last bit Document Number: 002-14957 Rev. *B Not Driven Page 37 of 45 PRELIMINARY CYW89035 3.3.3 BSC Interface Timing The specifications in Table 22 references Figure 13. Table 22. BSC Interface Timing Specifications (up to 1 MHz) Reference Characteristics Minimum Maximum Unit 100 1 Clock frequency 400 – kHz 800 1000 2 START condition setup time 650 – ns 3 START condition hold time 280 – ns 4 Clock low time 650 – ns 5 Clock high time 280 – ns a 6 Data input hold time 0 – ns 7 Data input setup time 100 – ns 8 STOP condition setup time 280 – ns 9 Output valid from clock – 400 ns 650 – ns b 10 Bus free time a. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. b. Time that the CBUS must be free before a new transaction can start. Figure 13. BSC Interface Timing Diagram 1 5 SCL 2 4 8 6 3 7 SDA IN 10 9 SDA OUT Document Number: 002-14957 Rev. *B Page 38 of 45 PRELIMINARY CYW89035 4. Mechanical Information 4.1 Package Diagram Figure 14. CYW89035 7 mm × 7 mm 60-Pin QFN Package Document Number: 002-14957 Rev. *B Page 39 of 45 PRELIMINARY CYW89035 4.2 Tray Packaging Specification The CYW89035 QFN package and tray dimensions are annotated in Figure 15 and defined in Table 23 and Table 24 on page 40. Figure 15. QFN Package and Tray Dimensions Table 23. QFN Package Dimensions and Tolerances Parameter Description Nom. Min. Max. ± Tol. Unit P1 Package size 7 6.9 7.1 0.1 mm P2 Top hat width 0 0 0 – mm P3 Top hat height 0 0 0 – mm P4 Substrate thickness 0.85 0.8 0.9 0.05 mm P7 Total thickness (P3 + P4) 0.85 0.8 0.9 0.05 mm Nom. Min. Max. ± Tol. Unit Table 24. QFN Tray Dimensions and Tolerances Parameter Description T1 Top pocket size 7.25 7.17 7.33 0.08 mm T3 Top pocket depth 1.75 1.5 2 0.25 mm T5 Stacking height 2 1.87 2.13 0.13 mm T6 Bottom pocket size 7.25 7.17 7.33 0.08 mm T8 Bottom pocket depth 1.650 1.52 1.78 0.13 mm a2 Bottom pocket relief wall draft angle 5 5 5 0 Degrees 0.2 0.07 0.33 0.13 mm T10 Packing value between two stacking trays Document Number: 002-14957 Rev. *B Page 40 of 45 PRELIMINARY CYW89035 5. Ordering Information Table 25. Ordering Information Part Number CYW89035CWMLG Document Number: 002-14957 Rev. *B Package Ambient Operating Temperature 60-pin QFN –40°C to 105°C Page 41 of 45 PRELIMINARY CYW89035 A. Appendix: Acronyms and Abbreviations The following list of acronyms and abbreviations may appear in this document. Term Description ADC analog-to-digital converter AFH adaptive frequency hopping AHB advanced high-performance bus APB advanced peripheral bus APU audio processing unit ™ ARM7TDMI-S Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable BSC Broadcom Serial Control BTC Bluetooth controller COEX coexistence DFU device firmware update DMA direct memory access EBI external bus interface HCI Host Control Interface HV high voltage IDC initial digital calibration IF intermediate frequency IRQ interrupt request JTAG Joint Test Action Group LCU link control unit LDO low drop-out LHL lean high land LPO low power oscillator LV LogicVision™ MIA multiple interface agent PDM pulse density modulation PLL phase locked loop PMU power management unit POR power-on reset PWM pulse width modulation QD quadrature decoder RAM random access memory RC oscillator A resistor-capacitor oscillator is a circuit composed of an amplifier, which provides the output signal, and a resistor-capacitor network, which controls the frequency of the signal. RF radio frequency ROM read-only memory RX/TX receive, transmit SPI serial peripheral interface SW software Document Number: 002-14957 Rev. *B Page 42 of 45 PRELIMINARY Term CYW89035 Description SWD serial wire debug UART universal asynchronous receiver/transmitter UPI µ-processor interface WD watchdog Document Number: 002-14957 Rev. *B Page 43 of 45 PRELIMINARY CYW89035 Document History Document Title: CYW89035 Automotive Grade Bluetooth Low Energy System on a Chip Document Number: 002-14957 Revision ECN Orig. of Change Submission Date ** – – 04/22/2015 89035-DS100-R: Initial release *A – – 11/06/2015 89035-DS101-R: Updated: • Table 15 on page 32 *B 5474879 UTSV 10/14/2016 Updated to Cypress template Document Number: 002-14957 Rev. *B Description of Change Page 44 of 45 CYW89035 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Lighting & Power Control Memory cypress.com/iot cypress.com/powerpsoc cypress.com/memory PSoC Cypress Developer Community Forums | WICED IoT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers Wireless/RF PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP cypress.com/usb cypress.com/wireless 45 © Cypress Semiconductor Corporation, 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). 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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-14957 Rev. *B Revised October 14, 2016 Page 45 of 45