High Performance, ISM Band, FSK/ASK Transceiver IC ADF7020 Data Sheet FEATURES On-chip VCO and fractional-N PLL On-chip 7-bit ADC and temperature sensor Fully automatic frequency control loop (AFC) compensates for ±25 ppm crystal at 862 MHz to 956 MHz or±50 ppm at 431 MHz to 478 MHz Digital RSSI Integrated Tx/Rx switch Leakage current of <1 µA in power-down mode Low power, low IF transceiver Frequency bands 431 MHz to 478 MHz 862 MHz to 956 MHz Data rates supported 0.15 kbps to 200 kbps, FSK 0.15 kbps to 64 kbps, ASK 2.3 V to 3.6 V power supply Programmable output power −16 dBm to +13 dBm in 0.3 dBm steps Receiver sensitivity −119 dBm at 1 kbps, FSK −112 dBm at 9.6 kbps, FSK −106.5 dBm at 9.6 kbps, ASK Low power consumption 19 mA in receive mode 26.8 mA in transmit mode (10 dBm output) −3 dBm IIP3 in high linearity mode APPLICATIONS Low cost wireless data transfer Remote control/security systems Wireless metering Keyless entry Home automation Process and building control Wireless voice FUNCTIONAL BLOCK DIAGRAM RSET RLNA CREG[1:4] LDO(1:4) ADCIN MUXOUT TEMP SENSOR OFFSET CORRECTION ADF7020 TEST MUX LNA RFIN MUX RSSI IF FILTER RFINB FSK/ASK DEMODULATOR 7-BIT ADC DATA SYNCHRONIZER GAIN OFFSET CORRECTION CE AGC CONTROL FSK MOD CONTROL RFOUT DIVIDERS/ MUXING Σ-Δ MODULATOR GAUSSIAN FILTER DIV P DATA CLK Tx/Rx CONTROL AFC CONTROL DATA I/O INT/LOCK N/N + 1 SLE SERIAL PORT VCO SREAD SCLK PFD DIV R VCOIN CPOUT OSC OSC1 OSC2 CLK DIV CLKOUT 05351-001 CP SDATA Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved. ADF7020 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Image Rejection Calibration ..................................................... 26 Applications ....................................................................................... 1 Transmit Protocol and Coding Considerations ..................... 27 Functional Block Diagram .............................................................. 1 Device Programming after Initial Power-Up ......................... 27 Revision History ............................................................................... 3 Interfacing to Microcontroller/DSP ........................................ 27 General Description ......................................................................... 4 Power Consumption and battery lifetime calculations ......... 28 Specifications..................................................................................... 5 Serial Interface ................................................................................ 31 Timing Characteristics ..................................................................... 8 Readback Format........................................................................ 31 Timing Diagrams.......................................................................... 8 Registers ........................................................................................... 32 Absolute Maximum Ratings .......................................................... 10 Register 0—N Register............................................................... 32 ESD Caution ................................................................................ 10 Register 1—Oscillator/Filter Register ...................................... 33 Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ........................................... 13 Register 2—Transmit Modulation Register (ASK/OOK Mode) ........................................................................................... 34 Frequency Synthesizer ................................................................... 15 Register 2—Transmit Modulation Register (FSK Mode) ..... 35 Reference Input ........................................................................... 15 Register 2—Transmit Modulation Register (GFSK/GOOK Mode) ........................................................................................... 36 Choosing Channels for Best System Performance ................. 17 Transmitter ...................................................................................... 18 RF Output Stage .......................................................................... 18 Modulation Schemes.................................................................. 18 Receiver ............................................................................................ 20 RF Front End ............................................................................... 20 RSSI/AGC .................................................................................... 21 FSK Demodulators on the ADF7020 ....................................... 21 FSK Correlator/Demodulator ................................................... 21 Linear FSK Demodulator .......................................................... 23 AFC .............................................................................................. 23 Automatic Sync Word Recognition ......................................... 24 Applications Information .............................................................. 25 LNA/PA Matching ...................................................................... 25 Register 3—Receiver Clock Register ....................................... 37 Register 4—Demodulator Setup Register ............................... 38 Register 5—Sync Byte Register ................................................. 39 Register 6—Correlator/Demodulator Register ...................... 40 Register 7—Readback Setup Register ...................................... 41 Register 8—Power-Down Test Register .................................. 42 Register 9—AGC Register ......................................................... 43 Register 10—AGC 2 Register.................................................... 44 Register 11—AFC Register ....................................................... 44 Register 12—Test Register......................................................... 45 Register 13—Offset Removal and Signal Gain Register ....... 46 Outline Dimensions ....................................................................... 47 Ordering Guide .......................................................................... 47 Rev. D | Page 2 of 48 Data Sheet ADF7020 REVISION HISTORY 8/12—Rev. C to Rev. D Added EPAD Notation ...................................................................11 Changed CP-48-3 Package to CP-48-5 Package ..........................47 Updated Outline Dimensions ........................................................47 Changes to Ordering Guide ...........................................................47 5/11—Rev. B to Rev. C Added Exposed Pad Notation to Outline Dimensions ..............47 Changes to Ordering Guide ...........................................................47 8/07—Rev. A to Rev. B Changes to Features .......................................................................... 1 Changes to General Description ..................................................... 4 Changes to Table 1 ............................................................................ 5 Changes to Table 2 ............................................................................ 8 Changes to Reference Input Section .............................................15 Changes to N Counter Section ......................................................16 Changes to Choosing Channels for Best Performance Section 17 Changes to Table 5 ..........................................................................20 Changes to FSK Correlator Register Settings Section ................22 Added Image Rejection Calibration Section ...............................26 Added Figure 41 ..............................................................................30 Changes to Readback Format Section ..........................................31 Changes to Register 9—AGC Register Comments Section .......43 Added Register 12—Test Register Comments Section ..............45 4/06—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Changes to Table 1 ............................................................................ 5 Changes to Figure 24 ...................................................................... 17 Changes to the Setting Up the ADF7020 for GFSK Section ..... 19 Changes to Table 6 .......................................................................... 21 Changes to Table 9 .......................................................................... 23 Changes to External AFC Section................................................. 23 Deleted Maximum AFC Range Section ....................................... 23 Added AFC Performance Section ................................................. 24 Changes to Internal Rx/Tx Switch Section .................................. 25 Changes to Figure 32 ...................................................................... 25 Changes to Transmit Protocol and Coding Considerations Section .............................................................................................. 26 Added Text Relating to Figure 37 ................................................. 27 Changes to Figure 41 ...................................................................... 31 Changes to Register 1—Oscillator/Filter Register Comments ........................................................................................ 31 Changes to Figure 42 ...................................................................... 32 Changes to Register 2—Transmit Modulation Register (FSK Mode) Comments ................................................................. 33 Changes to Figure 44 ...................................................................... 34 Changes to Register 2—Transmit Modulation Register (GFSK/GOOK Mode) Comments ................................................ 34 Changes to Register 4—Demodulator Setup Register Comments ........................................................................................ 36 Changes to Figure 51 ...................................................................... 41 Changes to Figure 53 ...................................................................... 42 Changes to Ordering Guide ........................................................... 45 6/05—Revision 0: Initial Version Rev. D | Page 3 of 48 ADF7020 Data Sheet GENERAL DESCRIPTION The ADF7020 is a low power, highly integrated FSK/ASK/OOK transceiver designed for operation in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz, as well as the proposed Japanese RFID band at 950 MHz. A Gaussian data filter option is available to allow either GFSK or G-ASK modulation, which provides a more spectrally efficient modulation. In addition to these modulation options, the ADF7020 can also be used to perform both MSK and GMSK modulation, where MSK is a special case of FSK with a modulation index of 0.5. The modulation index is calculated as twice the deviation divided by the data rate. MSK is spectrally equivalent to O-QPSK modulation with half-sinusoidal Tx baseband shaping, so the ADF7020 can also support this modulation option by setting up the device in MSK mode. This device is suitable for circuit applications that meet the European ETSI-300-220, the North American FCC (Part 15), or the Chinese Short Range Device regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7020 very suitable for price-sensitive and area-sensitive applications. The transmitter block on the ADF7020 contains a VCO and low noise fractional-N PLL with an output resolution of <1 ppm. This frequency agile PLL allows the ADF7020 to be used in frequency-hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency-pulling problems. The transmitter output power is programmable in 0.3 dB steps from −16 dBm to +13 dBm. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use. A low IF architecture is used in the receiver (200 kHz), minimizing power consumption and the external component count and avoiding interference problems at low frequencies. The ADF7020 supports a wide variety of programmable features, including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop, allowing the PLL to track out the frequency error in the incoming signal. An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, or the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ±10°C over the full operating temperature range of −40°C to +85°C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory. Rev. D | Page 4 of 48 Data Sheet ADF7020 SPECIFICATIONS VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C. All measurements are performed using the EVAL-ADF7020DBZx using the PN9 data sequence, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS Frequency Ranges (Direct Output) Frequency Ranges (Divide-by-2 Mode) Phase Frequency Detector Frequency TRANSMISSION PARAMETERS Data Rate FSK/GFSK OOK/ASK OOK/ASK Frequency Shift Keying GFSK/FSK Frequency Deviation 2, 3 Deviation Frequency Resolution Gaussian Filter BT Amplitude Shift Keying ASK Modulation Depth PA Off Feedthrough in OOK Mode Transmit Power 4 Transmit Power Variation vs. Temperature Transmit Power Variation vs. VDD Transmit Power Flatness Programmable Step Size −20 dBm to +13 dBm Integer Boundary Reference Harmonics Second Harmonic Third Harmonic All Other Harmonics VCO Frequency Pulling, OOK Mode Optimum PA Load Impedance 5 Min Typ Max Unit Test Conditions 862 902 928 431 440 RF/256 870 928 956 440 478 24 MHz MHz MHz MHz MHz MHz VCO adjust = 0, VCO bias = 10 VCO adjust = 3, VCO bias = 10 VCO adjust = 3, VCO bias = 12, VDD = 2.7 V to 3.6 V VCO adjust = 0, VCO bias = 10 VCO adjust = 3, VCO bias = 12 0.15 0.15 0.3 200 64 1 100 kbps kbps kbaud Using Manchester encoding 1 4.88 100 110 620 kHz kHz Hz PFD = 3.625 MHz PFD = 20 MHz PFD = 3.625 MHz 30 ±1 dB dBm dBm dB VDD = 3.0 V, TA = 25°C From −40°C to +85°C ±1 ±1 dB dB From 2.3 V to 3.6 V at 915 MHz, TA = 25°C From 902 MHz to 928 MHz, 3 V, TA = 25°C 0.3125 −55 −65 dB dBc dBc 50 kHz loop BW −27 −21 −35 30 39 + j61 48 + j54 54 + j94 dBc dBc dBc kHz rms Ω Ω Ω 0.5 −50 −20 +13 RECEIVER PARAMETERS FSK/GFSK Input Sensitivity Sensitivity at 1 kbps Sensitivity at 9.6 kbps Sensitivity at 200 kbps OOK Input Sensitivity Sensitivity at 1 kbps Sensitivity at 9.6 kbps −119.2 −112.8 −100 dBm dBm dBm −116 −106.5 dBm dBm Rev. D | Page 5 of 48 Unfiltered conductive DR = 9.6 kbps FRF = 915 MHz FRF = 868 MHz FRF = 433 MHz At BER = 1E − 3, FRF = 915 MHz, LNA and PA matched separately 6 FDEV = 5 kHz, high sensitivity mode 7 FDEV = 10 kHz, high sensitivity mode FDEV = 50 kHz, high sensitivity mode At BER = 1E − 3, FRF = 915 MHz High sensitivity mode High sensitivity mode ADF7020 Parameter LNA and Mixer, Input IP37 Enhanced Linearity Mode Low Current Mode High Sensitivity Mode Rx Spurious Emissions 8 AFC Pull-In Range at 868 MHz/915 MHz Pull-In Range at 433 MHz Response Time Accuracy CHANNEL FILTERING Data Sheet Min Typ Max Unit Test Conditions −57 −47 dBm dBm dBm dBm dBm Pin = −20 dBm, 2 CW interferers FRF = 915 MHz, F1 = FRF + 3 MHz F2 = FRF + 6 MHz, maximum gain <1 GHz at antenna input >1 GHz at antenna input kHz kHz Bits kHz IF_BW = 200 kHz IF_BW = 200 kHz Modulation index = 0.875 −3 −5 −24 ±50 ±25 48 1 27 dB Desired signal 3 dB above the input sensitivity level, CW interferer power level increased until BER = 10−3, image channel excluded IF filter BW settings = 100 kHz, 150 kHz, 200 kHz 50 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz 55 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz 30 dB Image at FRF = 400 kHz 50 −2 70 dB dB dB Image at FRF = 400 kHz 60 68 65 72 12 24 − j60 26 − j63 71 − j128 dB dB dB dB dBm Ω Ω Ω −110 to −24 ±2 ±3 150 dBm dB dB µs 65 MHz/V Phase Noise (In-Band) 130 65 −89 MHz/V MHz/V dBc/Hz Phase Noise (Out-of-Band) Residual FM PLL Settling −110 128 40 dBc/Hz Hz µs Adjacent Channel Rejection (Offset = ±1 × IF Filter BW Setting) Second Adjacent Channel Rejection (Offset = ±2 × IF Filter BW Setting) Third Adjacent Channel Rejection (Offset = ±3 × IF Filter BW Setting) Image Channel Rejection (Uncalibrated) Image Channel Rejection (Calibrated) CO-CHANNEL REJECTION Wideband Interference Rejection BLOCKING ±1 MHz ±5 MHz ±10 MHz ±10 MHz (High Linearity Mode) Saturation (Maximum Input Level) LNA Input Impedance RSSI Range at Input Linearity Absolute Accuracy Response Time PHASE-LOCKED LOOP VCO Gain Rev. D | Page 6 of 48 Swept from 100 MHz to 2 GHz, measured as channel rejection Desired signal 3 dB above the input sensitivity level, CW interferer power level increased until BER = 10−2 FSK mode, BER = 10−3 FRF = 915 MHz, RFIN to GND FRF = 868 MHz FRF = 433 MHz See the RSSI/AGC section 902 MHz to 928 MHz band, VCO adjust = 0, VCO_BIAS_SETTING = 10 860 MHz to 870 MHz band, VCO adjust = 0 433 MHz, VCO adjust = 0 PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz, FRF = 915 MHz, VCO_BIAS_SETTING = 10 1 MHz offset From 200 Hz to 20 kHz, FRF = 868 MHz Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, LBW = 50 kHz Data Sheet Parameter REFERENCE INPUT Crystal Reference External Oscillator Load Capacitance Crystal Start-Up Time ADF7020 Min Max Unit Test Conditions 24 24 MHz MHz pF ms ms CMOS levels See crystal manufacturer’s specification sheet 11.0592 MHz crystal, using 33 pF load capacitors Using 16 pF load capacitors See the Reference Input section ±1 ±1 LSB LSB From 2.3 V to 3.6 V, TA = 25°C From 2.3 V to 3.6 V, TA = 25°C 10 3.0 150 µs + (5 × TBIT) µs ms CREG = 100 nF See Table 11 for more details Time to synchronized data out, includes AGC settling; see the AGC Information and Timing section 3.625 3.625 33 2.1 1.0 Input Level ADC PARAMETERS INL DNL TIMING INFORMATION Chip Enabled to Regulator Ready Chip Enabled to RSSI Ready Tx to Rx Turnaround Time LOGIC INPUTS Input High Voltage, VINH Typ 0.7 × VDD V Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN Control Clock Input LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL CLKOUT Rise/Fall CLKOUT Load TEMPERATURE RANGE, TA POWER SUPPLIES Voltage Supply VDD Transmit Current Consumption −20 dBm −10 dBm 0 dBm 10 dBm 10 dBm Receive Current Consumption Low Current Mode High Sensitivity Mode Power-Down Mode Low Power Sleep Mode 0.2 × VDD ±1 10 50 DVDD − 0.4 V µA pF MHz V IOH = 500 µA V ns pF °C IOL = 500 µA −40 0.4 5 10 +85 2.3 3.6 V All VDD pins must be tied together FRF = 915 MHz, VDD = 3.0 V, PA is matched to 50 Ω Combined PA and LNA matching network as on EVAL-ADF7020DBZx boards VCO_BIAS_SETTING = 12 14.8 15.9 19.1 28.5 26.8 mA mA mA mA mA 19 21 mA mA 0.1 1 PA matched separately with external antenna switch, VCO_BIAS_SETTING = 12 µA 1 Higher data rates are achievable, depending on local regulations. For the definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section. For the definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section. 4 Measured as maximum unmodulated power. Output power varies with both supply and temperature. 5 For matching details, see the LNA/PA Matching section and the AN-764 Application Note. 6 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks. 7 See Table 5 for a description of different receiver modes. 8 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications. 2 3 Rev. D | Page 7 of 48 ADF7020 Data Sheet TIMING CHARACTERISTICS VDD = 3 V ± 10%, VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design, not production tested. Table 2. Parameter t1 t2 t3 t4 t5 t6 t8 t9 t10 Limit at TMIN to TMAX >10 >10 >25 >25 >10 >20 <25 <25 >10 Unit ns ns ns ns ns ns ns ns ns Test Conditions/Comments SDATA to SCLK setup time SDATA to SCLK hold time SCLK high duration SCLK low duration SCLK to SLE setup time SLE pulse width SCLK to SREAD data valid, readback SREAD hold time after SCLK, readback SCLK to SLE disable time, readback TIMING DIAGRAMS t3 t4 SCLK t1 SDATA DB31 (MSB) t2 DB30 DB1 (CONTROL BIT C2) DB2 DB0 (LSB) (CONTROL BIT C1) t6 05351-002 SLE t5 Figure 2. Serial Interface Timing Diagram t1 t2 SCLK SDATA R7_DB0 (CONTROL BIT C1) SLE t3 t10 t8 RV16 RV15 RV2 RV1 05351-003 X SREAD t9 Figure 3. Readback Timing Diagram Rev. D | Page 8 of 48 Data Sheet ADF7020 ±1 × DATA RATE/32 1/DATA RATE RxCLK RxDATA 05351-004 DATA Figure 4. RxData/RxCLK Timing Diagram 1/DATA RATE TxCLK TxDATA DATA SAMPLE 05351-005 FETCH NOTES 1. TxCLK ONLY AVAILABLE IN GFSK MODE. Figure 5. TxData/TxCLK Timing Diagram Rev. D | Page 9 of 48 ADF7020 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND 1 Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature MLF θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +5 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 26°C/W 260°C 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION GND = GND1 = RFGND = GND4 = VCO GND = 0 V. Rev. D | Page 10 of 48 Data Sheet ADF7020 48 47 46 45 44 43 42 41 40 39 38 37 CVCO GND1 GND VCO GND GND VDD CPOUT CREG3 VDD3 OSC1 OSC2 MUXOUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 ADF7020 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 CLKOUT DATA CLK DATA I/O INT/LOCK VDD2 CREG2 ADCIN GND2 SCLK SREAD SDATA SLE NOTES 1. EXPOSED PAD MUST BE CONNECTED TO GROUND. 05351-006 MIX_I MIX_I MIX_Q MIX_Q FILT_I FILT_I GND4 FILT_Q FILT_Q GND4 TEST_A CE 13 14 15 16 17 18 19 20 21 22 23 24 VCOIN CREG1 VDD1 RFOUT RFGND RFIN RFINB RLNA VDD4 RSET CREG4 GND4 Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic VCOIN 2 CREG1 3 VDD1 4 RFOUT 5 6 RFGND RFIN 7 8 9 10 RFINB RLNA VDD4 RSET 11 CREG4 12 13 to 18 24 GND4 MIX_I, MIX_I, MIX_Q, MIX_Q, FILT_I, FILT_I GND4 FILT_Q, FILT_Q, TEST_A CE 25 SLE 26 SDATA 19, 22 20, 21, 23 Description The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 10 pF should be placed as close as possible to this pin. All VDD pins should be tied together. The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The output should be impedance matched to the desired load using suitable components. See the Transmitter section. Ground for Output Stage of Transmitter. All GND pins should be tied together. LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. See the LNA/PA Matching section. Complementary LNA Input. See the LNA/PA Matching section. External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance. Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor. External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance. Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for regulator stability and noise rejection. Ground for LNA/MIXER Block. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Ground for LNA/MIXER Block. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed once CE is brought high. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the fourteen latches. A latch is selected using the control bits. Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high impedance CMOS input. Rev. D | Page 11 of 48 ADF7020 Pin No. 27 Mnemonic SREAD 28 SCLK 29 30 GND2 ADCIN 31 CREG2 32 VDD2 33 INT/LOCK 34 35 DATA I/O DATA CLK 36 CLKOUT 37 MUXOUT 38 OSC2 39 40 OSC1 VDD3 41 CREG3 42 CPOUT 43 44 to 47 VDD GND, GND1, VCO GND CVCO EP 48 Data Sheet Description Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input. Ground for Digital Section. Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is made using the SREAD pin. Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin. Bidirectional Pin. In output mode (interrupt mode), the ADF7020 asserts the INT/ LOCK pin when it has found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked, NRZ data can be reliably received. In this mode, a demodulation lock can be asserted with minimum delay. Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply. In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. See the Gaussian Frequency Shift Keying (GFSK) section. A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 markspace ratio. This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked to the correct frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface regulator. The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the crystal oscillator. The reference crystal should be connected between this pin and OSC2. Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 0.01 µF capacitor. Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 µF capacitor. Grounds for VCO Block. A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise. Exposed Pad. The exposed pad must be connected to ground. Rev. D | Page 12 of 48 Data Sheet ADF7020 TYPICAL PERFORMANCE CHARACTERISTICS CARRIER POWER –0.28dBm REF –70.00dBc/Hz 10.00 dB/DIV ATTEN 0.00dB MKR1 10.0000kHz –87.80dBc/Hz 1 MKR4 3.482GHz SWEEP 16.52ms (601pts) ATTEN 20dB REF 10dBm PEAK log 10dB/DIV 1 3 4 FREQUENCY OFFSET 10MHz START 100MHz RES BW 3MHz REF 15dBm FSK 40 LgAv W1 S2 S3 FC AA £(f): FTun Swp 50 60 70 913.28 913.30 913.32 913.36 FREQUENCY (MHz) 913.38 05351-008 GFSK 1 START 800MHz #RES BW 30kHz Figure 8. Output Spectrum in FSK and GFSK Modulation VBW 30kHz STOP 5.000GHz SWEEP 5.627s (601pts) 05351-011 SIGNAL LEVEL (dBm) MARKER Δ 1.834000000GHz –62.57dB 30 Figure 11. Harmonic Response, Murata Dielectric Filter 0 –5 Δ Mkr1 1.834GHz –62.57dB ATTEN 30dB NORM 1R log 10dB/DIV PRBS PN9 DR = 7.1kbps FDEV = 4.88kHz RBW = 300kHz 20 STOP 10.000GHz SWEEP 16.52ms (601pts) Figure 10. Harmonic Response, RFOUT Matched to 50 Ω, No Filter Figure 7. Phase Noise Response at 868.3 MHz, VDD = 3.0 V, ICP = 1.5 mA 10 VBW 3MHz 05351-010 1kHz 05351-007 REF LEVEL 10.00dBm 10 200kHz FILTER BW –10 0 SIGNAL LEVEL (dBm) –20 –25 –30 –35 –40 –50 –55 150kHz FILTER BW 100kHz FILTER BW –10 ASK –20 OOK –30 –40 –60 –65 –70 –400 –300 –200 –100 0 100 200 300 400 500 600 –350 –250 –150 –50 50 150 250 350 450 550 IF FREQ (kHz) Figure 9. IF Filter Response –50 899.60 GOOK 899.80 900.00 900.20 900.40 FREQUENCY (MHz) 900.60 900.80 05351-012 –45 05351-009 ATTENUATION LEVEL (dB) –15 Figure 12. Output Spectrum in ASK, OOK, and GOOK Modes, DR = 10 kbps Rev. D | Page 13 of 48 ADF7020 Data Sheet 20 0 15 –1 11µA 10 –2 5 –3 5µA 2.4V, +85°C 0 7µA BER –5 –4 3.6V, –40°C –5 –10 –6 –15 RF INPUT LEVEL (dBm) Figure 13. PA Output Power vs. Setting Figure 16. BER vs. VDD and Temperature 80 0 70 –1 200.8k DATA RATE 60 –2 50 –3 1.002k DATA RATE BER 40 30 9.760k DATA RATE –4 05351-017 1100 05351-014 1050 950 FREQUENCY OF INTERFERER (MHz) 1000 900 850 800 750 700 650 600 550 500 –8 450 –10 400 –7 350 0 300 –6 250 10 –122 –121 –120 –119 –118 –117 –116 –115 –114 –113 –112 –111 –110 –109 –108 –107 –106 –105 –104 –103 –102 –101 –100 –99 –98 –97 –96 –95 –94 –93 –92 –91 –90 –5 20 200 LEVEL OF REJECTION (dB) 05351-016 –106 –107 –108 –109 –110 –111 –112 –113 –114 –115 –116 –117 –118 –8 –119 13 17 21 25 29 33 37 41 45 49 53 57 61 PA SETTING –120 9 –121 5 –122 1 05351-013 –25 –123 –7 –20 –124 PA OUTPUT POWER DATA RATE = 1kbps FSK IF BW = 100kHz DEMOD BW = 0.77kHz 3.0V, +25°C 9µA RF INPUT LEVEL (dBm) Figure 14. Wideband Interference Rejection; Wanted Signal (880 MHz) at 3 dB above Sensitivity Point Interferer = FM Jammer (9.76 kbps, 10 kHz Deviation) Figure 17. BER vs. Data Rate (Combined Matching Network) Separate LNA and PA Matching Paths Typically Improve Performance by 2 dB –60 20 –65 0 –70 ACTUAL INPUT LEVEL SENSITIVITY (dBm) –40 RSSI READBACK LEVEL –60 –80 –85 CORRELATOR AFC ON –90 –95 –80 CORRELATOR AFC OFF LINEAR AFC ON –100 –100 –80 –60 –40 RF INPUT (dB) –20 0 20 FREQUENCY ERROR (kHz) Figure 15. Digital RSSI Readback Linearity Figure 18. Sensitivity vs. Frequency Error with AFC On/Off Rev. D | Page 14 of 48 05351-018 –110 –100 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 –120 –120 –105 05351-015 RSSI LEVEL (dB) LINEAR AFC OFF –75 –20 Data Sheet ADF7020 FREQUENCY SYNTHESIZER R Counter REFERENCE INPUT The on-board crystal oscillator circuitry (see Figure 19) can use an inexpensive quartz crystal as the PLL reference. The oscillator circuit is enabled by setting R1_DB12 high. It is enabled by default on power-up and is disabled by bringing CE low. Errors in the crystal can be corrected using the automatic frequency control (see the AFC section) feature or by adjusting the fractional-N value (see the N Counter section). A single-ended reference (TCXO, CXO) can also be used. The CMOS levels should be applied to OSC2 with R1_DB12 set low. The 3-bit R counter divides the reference input frequency by an integer ranging from 1 to 7. The divided-down signal is presented as the reference clock to the phase frequency detector (PFD). The divide ratio is set in Register 1. Maximizing the PFD frequency reduces the N value. Every doubling of the PFD gives a 3 dB benefit in phase noise, as well as reducing occurrences of spurious components. The R register defaults to R = 1 on power-up. PFD [Hz] = XTAL/R MUXOUT and Lock Detect The MUXOUT pin allows the user to access various digital points in the ADF7020. The state of MUXOUT is controlled by Bits R0_DB[29:31]. CP1 Regulator Ready Figure 19. Oscillator Circuit on the ADF7020 Two parallel resonant capacitors are required for oscillation at the correct frequency; their values are dependent on the crystal specification. They should be chosen so that the series value of capacitance added to the PCB track capacitance adds up to the load capacitance of the crystal, usually 20 pF. PCB track capacitance values might vary from 2 pF to 5 pF, depending on board layout. Thus, CP1 and CP2 can be calculated using: CL = 1 1 1 + CP1 CP2 DVDD + CPCB Where possible, choose capacitors that have a low temperature coefficient to ensure stable frequency operation over all conditions. CLKOUT Divider and Buffer DVDD ANALOG LOCK DETECT MUX R COUNTER OUTPUT MUXOUT CONTROL CLKOUT 05351-020 ÷2 PLL TEST MODES Σ-Δ TEST MODES DGND Figure 21. MUXOUT Circuit Digital Lock Detect Digital lock detect is active high. The lock detect circuit is located at the PFD. When the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. Lock detect remains high until 25 ns phase error is detected at the PFD. Because no external components are needed for digital lock detect, it is more widely used than analog lock detect. CLKOUT ENABLE BIT DIVIDER 1 TO 15 REGULATOR READY DIGITAL LOCK DETECT N COUNTER OUTPUT The CLKOUT circuit takes the reference clock signal from the oscillator section, shown in Figure 19, and supplies a divideddown 50:50 mark-space signal to the CLKOUT pin. An even divide from 2 to 30 is available. This divide number is set in R1_DB[8:11]. On power-up, the CLKOUT defaults to divide-by-8. OSC1 Regulator ready is the default setting on MUXOUT after the transceiver has been powered up. The power-up time of the regulator is typically 50 µs. Because the serial interface is powered from the regulator, the regulator must be at its nominal voltage before the ADF7020 can be programmed. The status of the regulator can be monitored at MUXOUT. When the regulator ready signal on MUXOUT is high, programming of the ADF7020 can begin. 05351-021 CP2 05351-019 OSC2 OSC1 Figure 20. CLKOUT Stage To disable CLKOUT, set the divide number to 0. The output buffer can drive up to a 20 pF load with a 10% rise time at 4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A small series resistor (50 Ω) can be used to slow the clock edges to reduce these spurs at fCLK. Analog Lock Detect This N-channel open-drain lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When a lock has been detected, this output is high with narrow low going pulses. Rev. D | Page 15 of 48 ADF7020 Data Sheet Voltage Regulators N Counter The ADF7020 contains four regulators to supply stable voltages to the part. The nominal regulator voltage is 2.3 V. Each regulator should have a 100 nF capacitor connected between CREGx and GND. When CE is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 mA. Bringing the chip-enable pin low disables the regulators, reduces the supply current to less than 1 μA, and erases all values held in the registers. The serial interface operates off a regulator supply; therefore, to write to the part, the user must have CE high and the regulator voltage must be stabilized. Regulator status (CREG4) can be monitored using the regulator ready signal from MUXOUT. The feedback divider in the ADF7020 PLL consists of an 8-bit integer counter and a 15-bit Σ-Δ fractional-N divider. The integer counter is the standard pulse-swallow type common in PLLs. This sets the minimum integer divide value to 31. The fractional divide value gives very fine resolution at the output, where the output frequency of the PLL is calculated as Fractional _ N fOUT PFD Integer _ N 215 REFERENCE IN 4÷R PFD/ CHARGE PUMP VCO Loop Filter 4÷N The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. A typical loop filter design is shown in Figure 22. FRACTIONAL-N INTEGER-N 05351-023 THIRD-ORDER Σ-∆ MODULATOR Figure 23. Fractional-N PLL VCO The maximum N divide value is the combination of the Integer_N (maximum = 255) and the Fractional_N (maximum = 32767/32768) and puts a lower limit on the minimum usable PFD. 05351-022 CHARGE PUMP OUT Figure 22. Typical Loop Filter Configuration In FSK, the loop should be designed so that the loop bandwidth (LBW) is approximately one and a half times the data rate. Widening the LBW excessively reduces the time spent jumping between frequencies, but it can cause insufficient spurious attenuation. For ASK systems, a wider LBW is recommended. The sudden large transition between two power levels can result in VCO pulling and can cause a wider output spectrum than is desired. By widening the LBW to more than 10 times the data rate, the amount of VCO pulling is reduced, because the loop settles quickly back to the correct frequency. The wider LBW can restrict the output power and data rate of ASK-based systems compared with FSK-based systems. Narrow-loop bandwidths can result in the loop taking long periods of time to attain lock. Careful design of the loop filter is critical to obtaining accurate FSK/GFSK modulation. For GFSK, it is recommended that an LBW of 1.0 to 1.5 times the data rate be used to ensure that sufficient samples are taken of the input data while filtering system noise. The free design tool ADI SRD Design Studio™ can be used to design loop filters for the ADF7020. It can also be used to view the effect of loop filter bandwidth on the spectrum of the transmitted signal for different combinations of modulation type, data rates, and modulation indices. PFDMIN [Hz] = Maximum Required Output Frequency/(255 + 1) For example, when operating in the European 868 MHz to 870 MHz band, PFDMIN equals 3.4 MHz. In the majority of cases, it is advisable to use as high a value of PFD as possible to obtain best phase noise performance. Voltage Controlled Oscillator (VCO) To minimize spurious emissions, the on-chip VCO operates from 1724 MHz to 1912 MHz. The VCO signal is then divided by 2 to give the required frequency for the transmitter and the required LO frequency for the receiver. The VCO should be recentered, depending on the required frequency of operation, by programming the VCO Adjust Bits R1_DB[20:21]. The VCO is enabled as part of the PLL by the PLL Enable bit, R0_DB28. A further frequency divide-by-2 block is included to allow operation in the lower 433 MHz and 460 MHz bands. To enable operation in these bands, R1_DB13 should be set to 1. The VCO needs an external 22 nF between the VCO and the regulator to reduce internal noise. Rev. D | Page 16 of 48 Data Sheet ADF7020 VCO Bias Current CHOOSING CHANNELS FOR BEST SYSTEM PERFORMANCE VCO bias current can be adjusted using Bit R1_DB19 to Bit R1_DB16. To ensure VCO oscillation, the minimum bias current setting under all conditions is 0xA. VCO BIAS R1_DB[16:19] LOOP FILTER The fractional-N PLL allows the selection of any channel within 868 MHz to 956 MHz (and 433 MHz using divide-by-2) to a resolution of <300 Hz. This also facilitates frequency-hopping systems. TO N DIVIDER VCO MUX ÷2 TO PA ÷2 220µF VCO SELECT BIT Figure 24. Voltage-Controlled Oscillator (VCO) 05351-024 CVCO PIN Careful selection of the XTAL frequency is important to achieve best spurious and blocking performance. The architecture of fractional-N causes some level of the nearest integer channel to couple directly to the RF output. This phenomenon is often referred to as integer boundary spurious. If the desired RF channel and the nearest integer channel are separated by a frequency of less than the PLL loop bandwidth (LBW), the integer boundary spurs are not attenuated by the loop. Integer boundary spurs can be significantly reduced in amplitude by choosing XTAL values that place the wanted RF channel away from integer multiples of the PFD. Rev. D | Page 17 of 48 ADF7020 Data Sheet TRANSMITTER RF OUTPUT STAGE The PA of the ADF7020 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dBm into a 50 Ω load at a maximum frequency of 956 MHz. The PA is equipped with overvoltage protection, which makes it robust in severe mismatch conditions. Depending on the application, one can design a matching network for the PA to exhibit optimum efficiency at the desired radiated output power level for a wide range of different antennas, such as loop or monopole antennas. See the LNA/PA Matching section for details. The PA output current and, consequently, the output power are programmable over a wide range. The PA configurations in FSK/GFSK and ASK/OOK modulation modes are shown in Figure 25 and Figure 26, respectively. In FSK/GFSK modulation mode, the output power is independent of the state of the DATA I/O pin. In ASK/OOK modulation mode, it is dependent on the state of the DATA I/O pin and Bit R2_DB29, which selects the polarity of the TxData input. For each transmission mode, the output power can be adjusted as follows: PA Bias Currents MODULATION SCHEMES Frequency shift keying is implemented by setting the N value for the center frequency and then toggling this with the TxData line. The deviation from the center frequency is set using Bits R2_DB[15:23]. The deviation from the center frequency in Hz is FSK DEVIATION [Hz] PFD Modulation Number 214 where Modulation Number is a number from 1 to 511 (R2_DB[15:23]). R2_DB[30:31] 2 IDAC Frequency Shift Keying (FSK) Select FSK using Bits R2_DB[6:8]. 6 R2_DB[9:14] RFOUT R2_DB4 + R2_DB5 RFGND FROM VCO 4R 05351-025 DIGITAL LOCK DETECT PFD/ CHARGE PUMP PA STAGE VCO FSK DEVIATION FREQUENCY ÷N Figure 25. PA Configuration in FSK/GFSK Mode –fDEV DATA I/O +fDEV ASK/OOK MODE R2_DB29 THIRD-ORDER Σ-∆ MODULATOR TxDATA FRACTIONAL-N R2_DB[30:31] 6 IDAC 6 6 R2_DB[9:14] R2_DB[15:23] 0 RFOUT R2_DB4 R2_DB5 DIGITAL LOCK DETECT RFGND FROM VCO 05351-026 + INTEGER-N Figure 27. FSK Implementation Figure 26. PA Configuration in ASK/OOK Mode Rev. D | Page 18 of 48 05351-027 FSK/GFSK The output power is set using Bits R2_DB[9:14]. ASK The output power for the inactive state of the TxData input is set by Bits R2_DB[15:20]. The output power for the active state of the TxData input is set by Bits R2_DB[9:14]. OOK The output power for the active state of the TxData input is set by Bits R2_DB[9:14]. The PA is muted when the TxData input is inactive. Control Bits R2_DB[30:31] facilitate an adjustment of the PA bias current to further extend the output power control range, if necessary. If this feature is not required, the default value of 7 μA is recommended. The output stage is powered down by resetting Bit R2_DB4. To reduce the level of undesired spurious emissions, the PA can be muted during the PLL lock phase by toggling this bit. Data Sheet ADF7020 Gaussian Frequency Shift Keying (GFSK) Amplitude Shift Keying (ASK) Gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the TxData. A TxCLK output line is provided from the ADF7020 for synchronization of TxData from the microcontroller. The TxCLK line can be connected to the clock input of a shift register that clocks data to the transmitter at the exact data rate. Amplitude shift keying is implemented by switching the output stage between two discrete power levels. This is accomplished by toggling the DAC, which controls the output level between two 6-bit values set up in Register 2. A 0 TxData bit sends Bits R2_DB[15:20] to the DAC. A high TxData bit sends Bits R2_DB[9:14] to the DAC. A maximum modulation depth of 30 dB is possible. Setting Up the ADF7020 for GFSK To set up the frequency deviation, set the PFD and the modulation control bits. GFSK DEVIATION [Hz] = PFD × 2m 212 where m is GFSK_Mod_Control, set using R2_DB[24:26]. On-Off Keying (OOK) On-off keying is implemented by switching the output stage to a certain power level for a high TxData bit and switching the output stage off for a zero. For OOK, the transmitted power for a high input is programmed using Bits R2_DB[9:14]. Gaussian On-Off Keying (GOOK) To set up the GFSK data rate, PFD DR [bps] = DIVIDER _ FACTOR × INDEX _ COUNTER The INDEX_COUNTER variable controls the number of intermediate frequency steps between the low and high frequency. It is usually possible to achieve a given data rate with various combinations of DIVIDER_FACTOR and INDEX_COUNTER. Choosing a higher INDEX_COUNTER can help in improving the spectral performance. Gaussian on-off keying represents a prefiltered form of OOK modulation. The usually sharp symbol transitions are replaced with smooth Gaussian filtered transitions, the result being a reduction in frequency pulling of the VCO. Frequency pulling of the VCO in OOK mode can lead to a wider than desired BW, especially if it is not possible to increase the loop filter BW > 300 kHz. The GOOK sampling clock samples data at the data rate (see the Setting Up the ADF7020 for GFSK section). Rev. D | Page 19 of 48 ADF7020 Data Sheet RECEIVER RF FRONT END The ADF7020 is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from power lineinduced interference problems. Figure 28 shows the structure of the receiver front end. The many programming options allow users to trade off sensitivity, linearity, and current consumption against each other in the way best suitable for their applications. To achieve a high level of resilience against spurious reception, the LNA features a differential input. Switch SW2 shorts the LNA input when transmit mode is selected (R0_DB27 = 0). This feature facilitates the design of a combined LNA/PA matching network, avoiding the need for an external Rx/Tx switch. See the LNA/PA Matching section for details on the design of the matching network. I (TO FILTER) RFIN Tx/Rx SELECT (R0_DB27) SW2 LNA LO RFINB Q (TO FILTER) LNA MODE (R6_DB15) MIXER LINEARITY (R6_DB18) LNA CURRENT (R6_DB[16:17]) 05351-028 LNA GAIN (R9_DB[20:21]) LNA/MIXER ENABLE (R8_DB6) Figure 28. ADF7020 RF Front End The LNA is followed by a quadrature down conversion mixer, that converts the RF signal to the IF frequency of 200 kHz. It is important to consider that the output frequency of the synthesizer must be programmed to a value 200 kHz below the center frequency of the received channel. The LNA has two basic operating modes: high gain/low noise mode and low gain/low power mode. To switch between these two modes, use the LNA_Mode bit, R6_DB15. The mixer is also configurable between a low current and an enhanced linearity mode using the mixer_linearity bit, R6_DB18. Based on the specific sensitivity and linearity requirements of the application, it is recommended to adjust control bits LNA_Mode (R6_DB15) and Mixer_Linearity (R6_DB18), as outlined in Table 5. The gain of the LNA is configured by the LNA_Gain field, R9_DB[20:21], and can be set by either the user or the automatic gain control (AGC) logic. IF Filter Settings/Calibration Out-of-band interference is rejected by means of a fourth-order Butterworth polyphase IF filter centered around a frequency of 200 kHz. The bandwidth of the IF filter can be programmed between 100 kHz and 200 kHz by using Control Bits R1_DB[22:23] and should be chosen as a compromise between interference rejection, attenuation of the desired signal, and the AFC pull-in range. To compensate for manufacturing tolerances, the IF filter should be calibrated once after power-up. The IF filter calibration logic requires that the IF filter divider in Bits R6_DB[20:28] be set as dependent on the crystal frequency. Once initiated by setting Bit R6_DB19, the calibration is performed automatically without any user intervention. The calibration time is 200 μs, during which the ADF7020 should not be accessed. It is important not to initiate the calibration cycle before the crystal oscillator has fully settled. If the AGC loop is disabled, the gain of IF filter can be set to three levels using the Filter_Gain field, R9_DB[20:21]. The filter gain is adjusted automatically, if the AGC loop is enabled. Table 5. LNA/Mixer Modes Receiver Mode High Sensitivity Mode (Default) RxMode2 Low Current Mode Enhanced Linearity Mode RxMode5 RxMode6 LNA Mode (R6_DB15) 0 1 1 1 1 0 LNA Gain Value (R9_DB[20:21]) 30 10 3 3 10 30 Mixer Linearity (R6_DB18) 0 0 0 1 1 1 Rev. D | Page 20 of 48 Sensitivity (DR = 9.6 kbps, fDEV = 10 kHz) −110.5 −104 −94 −88 −98 −107 Rx Current Consumption (mA) 21 20 19 19 20 21 Input IP3 (dBm) −24 −13.5 −5 −3 −10 −20 Data Sheet ADF7020 RSSI/AGC The RSSI is implemented as a successive compression log amp following the baseband channel filtering. The log amp achieves ±3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. The RSSI itself is used for amplitude shift keying (ASK) demodulation. In ASK mode, extra digital filtering is performed on the RSSI value. Offset correction is achieved using a switched capacitor integrator in feedback around the log amp. This uses the baseband offset clock divide. The RSSI level is converted for user readback and digitally controlled AGC by an 80-level (7-bit) flash ADC. This level can be converted to input power in dBm. OFFSET CORRECTION FWR A FWR A FWR LATCH FWR FSK DEMOD CLK RSSI ASK DEMOD ADC R AGC _ Wait _ Time = AGC _ DELAY × SEQ _ CLK XTAL AGC Settling = AGC_Wait_Time × Number of Gain Changes Thus, in the worst case, if the AGC loop has to go through all 5 gain changes, AGC_Delay =10, SEQ_CLK = 200 kHz, AGC Settling = 10 × 5 µs × 5 = 250 µs. Minimum AGC_Wait_Time needs to be at least 25 µs. RSSI Formula (Converting to dBm) Input_Power [dBm] = −120 dBm + (Readback_Code + Gain_Mode_Correction) × 0.5 where: Readback_Code is given by Bit RV7 to Bit RV1 in the readback register (see the Readback Format section). Gain_Mode_Correction is given by the values in Table 6. 05351-029 A 1 This wait time can be adjusted to speed up this settling by adjusting the appropriate parameters. NOTES 1. FWR = FULL WAVE RECTIFIER LNA gain and filter gain (LG2/LG1, FG2/FG1) are also obtained from the readback register. Table 6. Gain Mode Correction Figure 29. RSSI Block Diagram RSSI Thresholds When the RSSI is above AGC_HIGH_THRESHOLD, the gain is reduced. When the RSSI is below AGC_LOW_THRESHOLD, the gain is increased. A delay (AGC_DELAY) is programmed to allow for settling of the loop. The user programs the two threshold values (recommended defaults of 30 and 70) and the delay (default of 10). The default AGC setup values should be adequate for most applications. The threshold values must be chosen to be more than 30 apart for the AGC to operate correctly. LNA Gain (LG2, LG1) H (1,1) M (1,0) M (1,0) M (1,0) L (0,1) EL (0,0) Filter Gain (FG2, FG1) H (1,0) H (1,0) M (0,1) L (0,0) L (0,0) L (0,0) Gain Mode Correction 0 24 45 63 90 105 An additional factor should be introduced to account for losses in the front-end matching network/antenna. Offset Correction Clock FSK DEMODULATORS ON THE ADF7020 In Register 3, the user should set the BB offset clock divide bits R3_DB[4:5] to give an offset clock between 1 MHz and 2 MHz. The two FSK demodulators on the ADF7020 are BBOS_CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE) • FSK correlator/demodulator • Linear demodulator where BBOS_CLK_DIVIDE can be set to 4, 8, or 16. Select these using the demodulator select bits, R4_DB[4:5]. AGC Information and Timing FSK CORRELATOR/DEMODULATOR AGC is selected by default, and operates by selecting the appropriate LNA and filter gain settings for the measured RSSI level. It is possible to disable AGC by writing to Register 9 if entering one of the modes listed in Table 5 is desired, for example. The time for the AGC circuit to settle and, therefore, the time to take an accurate RSSI measurement is typically 150 µs, although this depends on how many gain settings the AGC circuit has to cycle through. After each gain change, the AGC loop waits for a programmed time to allow transients to settle. The quadrature outputs of the IF filter are first limited and then fed to a pair of digital frequency correlators that perform bandpass filtering of the binary FSK frequencies at (IF + fDEV) and (IF − fDEV). Data is recovered by comparing the output levels from each of the two correlators. The performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of additive white Gaussian noise (AWGN). Rev. D | Page 21 of 48 ADF7020 Data Sheet SLICER I LIMITERS Q IF – fDEV IF + fDEV POST DEMOD FILTER IF DATA SYNCHRONIZER FREQUENCY CORRELATOR Discriminator _ BW RxCLK 05351-030 0 R6_DB[4:13] R6_DB[14] The discriminator BW is controlled in Register 6 by Bit R6_DB[4:13] and is defined as RxDATA R3_DB[8:15] Figure 30. FSK Correlator/Demodulator Block Diagram Postdemodulator Filter A second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. The bandwidth of this postdemodulator filter is programmable and must be optimized for the user’s data rate. If the bandwidth is set too narrow, performance is degraded due to intersymbol interference (ISI). If the bandwidth is set too wide, excess noise degrades the receiver’s performance. Typically, the 3 dB bandwidth of this filter is set at approximately 0.75 times the user’s data rate, using Bits R4_DB[6:15]. where: DEMOD_CLK is as defined in the Register 3—Receiver Clock Register section, second comment. K = Round(200 × 103/FSK Deviation) To optimize the coefficients of the FSK correlator, two additional bits, R6_DB14 and R6_DB29, must be assigned. The value of these bits depends on whether K (as defined above) is odd or even. These bits are assigned according to Table 7 and Table 8. Table 7. When K Is Even K Even Even K/2 Even Odd Bit Slicer Table 8. When K Is Odd The received data is recovered by the threshold detecting the output of the postdemodulator low-pass filter. In the correlator/ demodulator, the binary output signal levels of the frequency discriminator are always centered on 0. Therefore, the slicer threshold level can be fixed at 0, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. This results in robust data recovery, which does not suffer from the classic baseline wander problems that exist in the more traditional FSK demodulators. K Odd Odd Frequency errors are removed by an internal AFC loop that measures the average IF frequency at the limiter output and applies a frequency correction value to the fractional-N synthesizer. This loop should be activated when the frequency errors are greater than approximately 40% of the transmit frequency deviation (see the AFC section). (K + 1)/2 Even Odd R6_DB14 0 0 R6_DB29 0 1 R6_DB14 1 1 R6_DB29 0 1 Postdemodulator Bandwidth Register Settings The 3 dB bandwidth of the postdemodulator filter is controlled by Bits R4_DB[6:15] and is given by Postdemod_BW_Setting 210 2π fCUTOFF DEMOD _ CLK where fCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter. This should typically be set to 0.75 times the data rate (DR). Some sample settings for the FSK correlator/demodulator are DEMOD_CLK = 5 MHz DR = 9.6 kbps fDEV = 20 kHz Data Synchronizer An oversampled digital PLL is used to resynchronize the received bit stream to a local clock. The oversampled clock rate of the PLL (CDR_CLK) must be set at 32 times the data rate. See the Register 3—Receiver Clock Register Comments section for a definition of how to program. The clock recovery PLL can accommodate frequency errors of up to ±2%. DEMOD _ CLK K 800 103 Therefore, fCUTOFF = 0.75 × 9.6 × 103 Hz Postdemod_BW_Setting = 211 π 7.2 × 103 Hz/(5 MHz) Postdemod_BW_Setting = Round(9.26) = 9 and FSK Correlator Register Settings To enable the FSK correlator/demodulator, Bits R4_DB[5:4] should be set to 01. To achieve best performance, the bandwidth of the FSK correlator must be optimized for the specific deviation frequency that is used by the FSK transmitter. Rev. D | Page 22 of 48 K = Round(200 kHz)/20 kHz) = 10 Discriminator_BW = (5 MHz × 10)/(800 × 103) = 62.5 = 63 (rounded to the nearest integer) Data Sheet ADF7020 ASK/OOK Operation Table 9. Register Settings1 Setting Name Postdemod_BW_Setting Discriminator_BW Dot_Product RxData_Invert 1 Register Address R4_DB[6:15] R6_DB[4:13] R6_DB14 R6_DB29 Value 0x09 0x3F 0 1 The latest version of the ADF7020 configuration software can aid in calculating register settings. LINEAR FSK DEMODULATOR Figure 31 shows a block diagram of the linear FSK demodulator. MUX 1 ADC RSSI OUTPUT Digital filtering and envelope detecting the digitized RSSI input via MUX 1, as shown in Figure 31, performs ASK/OOK demodulation. The bandwidth of the digital filter must be optimized to remove any excess noise without causing ISI in the received ASK/OOK signal. The 3 dB bandwidth of this filter is typically set at approximately 0.75 times the user data rate and is assigned by R4 _DB[6:15] as SLICER Postdemod _ BW _ Setting 7 LEVEL LIMITER Q FREQUENCY LINEAR DISCRIMINATOR FREQUENCY READBACK AND AFC LOOP R4_DB[6:15] Figure 31. Block Diagram of Frequency Measurement System and ASK/OOK/Linear FSK Demodulator This method of frequency demodulation is useful when very short preamble length is required, and the system protocol cannot support the overhead of the settling time of the internal feedback AFC loop settling. A digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. The discriminator output is then filtered and averaged using a combined averaging filter and envelope detector. The demodulated FSK data is recovered by threshold-detecting the output of the averaging filter, (see Figure 31). In this mode, the slicer output shown in Figure 31 is routed to the data synchronizer PLL for clock synchronization. To enable the linear FSK demodulator, set Bits R4_DB[4:5] to 00. The 3 dB bandwidth of the postdemodulation filter is set in the same way as the FSK correlator/demodulator, which is set in R4_DB[6:15] and is defined as Postdemod _ BW _ Setting 210 2 fCUTOFF DEMOD _ CLK where fCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter. It is also recommended to adjust the peak response factor to 6 in Register 10 for robust operation over the full input range. This improves the receiver’s AM immunity performance. 05351-031 IF ENVELOPE DETECTOR RxDATA AVERAGING FILTER I ASK/OOK demodulation is activated by setting Bits R4_DB[4:5] to 10. 210 2 fCUTOFF DEMOD _ CLK AFC The ADF7020 supports a real-time AFC loop, which is used to remove frequency errors that can arise due to mismatches between the transmit and receive crystals. This uses the frequency discriminator block, as described in the Linear FSK Demodulator section (see Figure 31). The discriminator output is filtered and averaged to remove the FSK frequency modulation, using a combined averaging filter and envelope detector. In FSK mode, the output of the envelope detector provides an estimate of the average IF frequency. Two methods of AFC, external and internal, are supported on the ADF7020 (in FSK mode only). External AFC The user reads back the frequency information through the ADF7020 serial port and applies a frequency correction value to the fractional-N synthesizer’s N divider. The frequency information is obtained by reading the 16-bit signed AFC_READBACK, as described in the Readback Format section, and applying the following formula: FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215 where fCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter. DEMOD_CLK is as defined in the Register 3—Receiver Clock Register section, second comment. Note that while the AFC_READBACK value is a signed number, under normal operating conditions, it is positive. The frequency error can be calculated from FREQ_Error [Hz] = FREQ_RB (Hz) − 200 kHz Thus, in the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 200 kHz. Rev. D | Page 23 of 48 ADF7020 Data Sheet Internal AFC AUTOMATIC SYNC WORD RECOGNITION The ADF7020 supports a real-time internal automatic frequency control loop. In this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer N divider using an internal PI control loop. The ADF7020 also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7020. In receive mode, this preprogrammed word is compared to the received bit stream and, when a valid match is identified, the external pin INT/LOCK is asserted by the ADF7020. The internal AFC control loop parameters are controlled in Register 11. The internal AFC loop is activated by setting R11_DB20 to 1. A scaling coefficient must also be entered, based on the crystal frequency in use. This is set up in Bits R11_DB[4:19] and should be calculated using This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption. The INT/LOCK is automatically deasserted again after nine data clock cycles. AFC_Scaling_Coefficient = (500 × 224)/XTAL Therefore, using a 10 MHz XTAL yields an AFC scaling coefficient of 839. AFC Performance The improved sensitivity performance of the Rx when AFC is enabled and in the presence of frequency errors is shown in Figure 18. The maximum AFC frequency range is ±50 kHz, which corresponds to ±58 ppm at 868 MHz. This is the total error tolerance allowed in the link. For example, in a point-topoint system, AFC can compensate for two ±29 ppm crystals or one ±50 ppm crystal and one ±8 ppm TCXO. AFC settling typically takes 48 bits to settle within ±1 kHz. This can be improved by increasing the postdemodulator bandwidth in Register 4 at the expense of Rx sensitivity. The automatic sync/ID word detection feature is enabled by selecting Demodulator Mode 2 or Demodulator Mode 3 in the demodulator setup register. Do this by setting Bits R4_DB[25:23] = 010 or 011. Bits R5_DB[4:5] are used to set the length of the sync/ID word, which can be 12, 16, 20, or 24 bits long. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware. For systems using forward error correction (FEC), an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. The error tolerance value is assigned in Bits R5_DB[6:7]. When AFC errors have been removed using either the internal or external AFC, further improvement in the receiver’s sensitivity can be obtained by reducing the IF filter bandwidth using Bits R1_DB[22:23]. Rev. D | Page 24 of 48 Data Sheet ADF7020 APPLICATIONS INFORMATION LNA/PA MATCHING The ADF7020 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its RF input and output ports are properly matched to the antenna impedance. For cost-sensitive applications, the ADF7020 is equipped with an internal Rx/Tx switch that facilitates the use of a simple combined passive PA/LNA matching network. Alternatively, an external Rx/Tx switch, such as the Analog Devices ADG919, can be used. It yields a slightly improved receiver sensitivity and lower transmitter power consumption. External Rx/Tx Switch Figure 32 shows a configuration using an external Rx/Tx switch. This configuration allows an independent optimization of the matching and filter network in the transmit and receive path and is, therefore, more flexible and less difficult to design than the configuration using the internal Rx/Tx switch. The PA is biased through Inductor L1, while C1 blocks dc current. Both elements, L1 and C1, also form the matching network, which transforms the source impedance into the optimum PA load impedance, ZOPT_PA. VBAT C1 L1 PA_OUT PA ANTENNA ZOPT_PA RFIN ADG919 Rx/Tx – SELECT LNA RFINB ZIN_RFIN CB ADF7020 05351-032 LA The immunity of the ADF7020 to strong out-of-band interference can be improved by adding a band-pass filter in the Rx path. Apart from discrete designs, SAW or dielectric filter components, such as the SAFCH869MAM0T00 or SAFCH915MAL0N00, both by Murata, are well suited for this purpose. Alternatively, the ADF7020 blocking performance can be improved by selecting the high linearity mode, as described in Table 5. Internal Rx/Tx Switch ZIN_RFIN OPTIONAL CA BPF (SAW) Depending on the antenna configuration, the user may need a harmonic filter at the PA output to satisfy the spurious emission requirement of the applicable government regulations. The harmonic filter can be implemented in various ways, such as a discrete LC pi or T-stage filter. Dielectric low-pass filter components, such as the LFL18924MTC1A052 (for operation in the 915 MHz and 868 MHz band) by Murata Manufacturing, Co., Ltd., represent an attractive alternative to discrete designs. AN-917 describes how to replace the Murata dielectric filter with an LC filter if desired. Figure 32. ADF7020 with External Rx/Tx Switch ZOPT_PA depends on various factors, such as the required output power, the frequency range, the supply voltage range, and the temperature range. Selecting an appropriate ZOPT_PA helps to minimize the Tx current consumption in the application. Application Note AN-767 contains a number of ZOPT_PA values for representative conditions. Under certain conditions, however, it is recommended that a suitable ZOPT_PA value be obtained by means of a load-pull measurement. Figure 33 shows the ADF7020 in a configuration where the internal Rx/Tx switch is used with a combined LNA/PA matching network. This is the configuration used in the ADF7020-XDBX evaluation boards. For most applications, the slight performance degradation of 1 dB to 2 dB caused by the internal Rx/Tx switch is acceptable, allowing the user to take advantage of the cost saving potential of this solution. The design of the combined matching network must compensate for the reactance presented by the networks in the Tx and the Rx paths, taking the state of the Rx/Tx switch into consideration. VBAT C1 L1 PA_OUT PA ANTENNA Due to the differential LNA input, the LNA matching network must be designed to provide both a single-ended-to-differential conversion and a complex conjugate impedance match. The network with the lowest component count that can satisfy these requirements is the configuration shown in Figure 32, which consists of two capacitors and one inductor. ZOPT_PA OPTIONAL BPF OR LPF ZIN_RFIN CA RFIN LA LNA RFINB ZIN_RFIN CB ADF7020 Figure 33. ADF7020 with Internal Rx/Tx Switch Rev. D | Page 25 of 48 05351-033 OPTIONAL LPF A first-order implementation of the matching network can be obtained by understanding the arrangement as two L type matching networks in a back-to-back configuration. Due to the asymmetry of the network with respect to ground, a compromise between the input reflection coefficient and the maximum differential signal swing at the LNA input must be established. The use of appropriate CAD software is strongly recommended for this optimization. ADF7020 Data Sheet Calibration Procedure and Setup The procedure typically requires several iterations until an acceptable compromise is reached. The successful implementation of a combined LNA/PA matching network for the ADF7020 is critically dependent on the availability of an accurate electrical model for the PC board. In this context, the use of a suitable CAD package is strongly recommended. To avoid this effort, however, a small form-factor reference design for the ADF7020 is provided, including matching and harmonic filter components. Gerber files and schematics are available at www.analog.com. The image rejection calibration works by connecting an external RF signal to the RF input port. The external RF signal should be set at the image frequency and the filter rejection measured by monitoring the digital RSSI readback. As the image rejection is improved by adjusting the I/Q Gain and phase, the RSSI reading reduces. The magnitude of the phase adjust is set by using the IR_PHASE_ ADJUST bits (R10_DB[24:27]). This correction can be applied to either the I channel or Q channel, by toggling bit (R10_DB28). IMAGE REJECTION CALIBRATION The image channel in the ADF7020 is 400 kHz below the desired signal. The polyphase filter rejects this image with an asymmetric frequency response. The image rejection performance of the receiver is dependent on how well matched the I and Q signals are in amplitude, and how well matched the quadrature is between them (that is, how close to 90º apart they are.) The uncalibrated image rejection performance is approximately 30 dB. However, it is possible to improve this performance by as much as 20 dB by finding the optimum I/Q gain and phase adjust settings. The magnitude of the I/Q gain is adjusted by the IR_GAIN_ ADJUST bits (R10_DB[16:20]). This correction can be applied to either the I or Q channel using bit (R10_DB22), while the GAIN/ATTENUATE bit (R10_DB21) sets whether the gain adjustment defines a gain or attenuation adjust. The calibration results are valid over changes in the ADF7020 supply voltage. However, there is some variation with temperature. A typical plot of variation in image rejection over temperature after initial calibrations at +25°C, −40°C, and +85°C is shown in Figure 35. The internal temperature sensor on the ADF7020 can be used to determine if a new IR calibration is required. ADF7020 MATCHING RFINB LNA GAIN ADJUST EXTERNAL SIGNAL SOURCE RFIN POLYPHASE IF FILTER RSSI/ LOG AMP 7-BIT ADC PHASE ADJUSTMENT I Q FROM LO SERIAL INTERFACE 4 PHASE ADJUST REGISTER 10 4 RSSI READBACK GAIN ADJUST REGISTER 10 I/Q GAIN/PHASE ADJUST AND RSSI MEASUREMENT ALGORITHM Figure 34. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller Rev. D | Page 26 of 48 05351-059 MICROCONTROLLER Data Sheet ADF7020 DEVICE PROGRAMMING AFTER INITIAL POWER-UP 60 CAL AT +25°C CAL AT –40°C 30 VDD = 3.0V IF BW = 25kHz 20 10 WANTED SIGNAL: RF FREQ = 430MHz MODULATION = 2FSK DATA RATE = 9.6kbps, PRBS9 fDEV = 4kHz LEVEL= –100dBm 0 –60 –40 –20 INTERFERER SIGNAL: RF FREQ = 429.8MHz MODULATION = 2FSK DATA RATE = 9.6kbps, PRBS11 fDEV = 4kHz 0 20 40 60 Table 10. Minimum Register Writes Required for Tx/Rx Setup 80 100 TEMPERATURE (°C) Mode Tx Rx (OOK) Rx (G/FSK) Tx ↔Rx Figure 35. Image Rejection Variation with Temperature after Initial Calibrations at +25°C, −40°C, and +85°C TRANSMIT PROTOCOL AND CODING CONSIDERATIONS SYNC WORD ID FIELD DATA FIELD Reg. 1 Reg. 1 Reg. 1 Reg. 2 Reg. 3 Reg. 3 Reg. 4 Reg. 4 Reg. 6 Reg. 6 Figure 39 and Figure 40 show the recommended programming sequence and associated timing for power-up from standby mode. 05351-034 PREAMBLE Register Reg. 0 Reg. 0 Reg. 0 Reg. 0 CRC Figure 36. Typical Format of a Transmit Protocol A dc-free preamble pattern is recommended for FSK/GFSK/ ASK/OOK demodulation. The recommended preamble pattern is a dc-balanced pattern such as a 10101010… sequence. Preamble patterns with longer run-length constraints such as 11001100… can also be used. However, this results in a longer synchronization time of the received bit stream in the receiver. INTERFACING TO MICROCONTROLLER/DSP Low level device drivers are available for interfacing the ADF7020 to the Analog Devices ADuC84x analog microcontrollers, or the Blackfin® ADSP-BF53x DSPs, using the hardware connections shown in Figure 37 and Figure 38. The remaining fields that follow the preamble header do not have to use dc-free coding. For these fields, the ADF7020 can accommodate coding schemes with a run-length of up to several bytes without any performance degradation, for example several bytes of 0x00 or 0xFF. To help minimize bit errors when receiving these long runs of continuous 0s or 1s, it is important to choose a data rate and XTAL combination that minimizes the error between the actual data rate and the on-board CDR_CLK/32. For example, if a 9.6 kbps data rate is desired, then using an 11.0592 MHz XTAL gives a 0% nominal error between the desired data rate and CDR_CLK/32. AN-915 gives more details on supporting long run lengths on the ADF7020. The ADF7020 can also support Manchester-encoded data for the entire protocol. Manchester decoding needs to be done on the companion microcontroller, however. In this case, the ADF7020 should be set up at the Manchester chip or baud rate, which is twice the effective data rate. Rev. D | Page 27 of 48 ADF7020 ADuC84x MISO DATA I/O MOSI SCLOCK DATA CLK SS P3.7 P3.2/INT0 GPIO CE INT/LOCK P2.4 SREAD P2.5 SLE P2.6 SDATA P2.7 SCLK 05351-035 CAL AT +85°C Figure 37. ADuC84x to ADF7020 Connection Diagram ADF7020 ADSP-BF533 SCK MOSI MISO PF5 RSCLK1 DT1PRI SCLK SDATA SREAD SLE DATA CLK DATA I/O DR1PRI RFS1 PF6 INT/LOCK CE VDDEXT VDD GND GND Figure 38. ADSP-BF533 to ADF7020 Connection Diagram 05351-036 40 Table 10 lists the minimum number of writes needed to set up the ADF7020 in either Tx or Rx mode after CE is brought high. Additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling AFC. When going from Tx to Rx or vice versa, the user needs to write only to the N Register to alter the LO by 200 kHz and to toggle the Tx/Rx bit. 05351-058 IMAGE REJECTION (dB) 50 ADF7020 Data Sheet Using a sequenced power-on routine like that illustrated in Figure 39 can reduce the IAVG_ON current and, hence, reduce the overall power consumption. When used in conjunction with a large duty-cycle or large tOFF, this can result in significantly increased battery life. Analog Devices, Inc.’s free design tool, ADI SRD Design Studio, can assist in these calculations. POWER CONSUMPTION AND BATTERY LIFETIME CALCULATIONS Average Power Consumption can be calculated using ADF7020 I DD Average Power Consumption = (tON × IAVG_ON + tOFF × IPowerDown)/(tON + tOFF) 19mA TO 22mA 14mA XTAL t0 3.65mA 2.0mA AFC t10 t1 WR0 WR1 t2 t3 VCO t4 AGC/ RSSI WR3 WR4 WR6 t5 t6 t7 t8 CDR t9 TIME RxDATA t11 tON tOFF 05351-037 REG. READY Figure 39. Rx Programming Sequence and Timing Diagram Table 11. Power-Up Sequence Description Parameter t0 Value 2 ms t1 10 μs t2, t3, t5, t6, t7 t4 32 × 1/SPI_CLK t8 150 μs t9 5 × Bit_Period t10 48 × Bit_Period t11 Packet Length 1 ms Description Crystal starts power-up after CE is brought high. This typically depends on the crystal type and the load capacitance specified. Time for regulator to power up. The serial interface can be written to after this time. Time to write to a single register. Maximum SPI_CLK is 25 MHz. Signal to Monitor CLKOUT pin The VCO can power-up in parallel with the crystal. This depends on the CVCO capacitance value used. A value of 22 nF is recommended as a trade-off between phase noise performance and power-up time. This depends on the number of gain changes the AGC loop needs to cycle through and AGC settings programmed. This is described in more detail in the AGC Information and Timing section. This is the time for the clock and data recovery circuit to settle. This typically requires 5-bit transitions to acquire sync and is usually covered by the preamble. This is the time for the automatic frequency control circuit to settle. This typically requires 48-bit transitions to acquire lock and is usually covered by an appropriate length preamble. Number of bits in payload by the bit period. CVCO pin Rev. D | Page 28 of 48 MUXOUT pin Analog RSSI on TEST_A pin (Available by writing 0x3800 000C) ADF7020 ADF7020 I DD Data Sheet 15mA TO 30mA 14mA 3.65mA 2.0mA t1 WR0 WR1 t2 t3 XTAL + VCO t4 WR2 TIME TxDATA t5 t12 tON Figure 40. Tx Programming Sequence and Timing Diagram Rev. D | Page 29 of 48 tOFF 05351-038 REG. READY ADF7020 Data Sheet LOOP FILTER XTAL REFERENCE VDD ADF7020 TOP VIEW (Not to Scale) RSET RESISTOR Figure 41. Application Circuit Rev. D | Page 30 of 48 VDD CHIP ENABLE TO MICROCONTROLLER RLNA RESISTOR DATA I/O INT/LOCK VDD2 CREG2 ADCIN GND2 SCLK SREAD SDATA SLE 36 35 34 33 32 31 30 29 28 27 26 25 TO MICROCONTROLLER CONFIGURATION INTERFACE VDD 3 4 5 6 7 8 9 10 11 12 CLKOUT DATA CLK 05351-056 VDD T-STAGE LC FILTER PIN 1 INDICATOR 13 14 15 16 17 18 19 20 21 22 23 24 ANTENNA CONNECTION VCOIN CREG1 VDD1 RFOUT RFGND RFIN RFINB RLNA VDD4 RSET CREG4 GND4 TO MICROCONTROLLER Tx/Rx SIGNAL INTERFACE 1 2 MATCHING MIX_I MIX_I MIX_Q MIX_Q FILT_I FILT_I GND4 FILT_Q FILT_Q GND4 TEST_A CE VDD CVCO GND1 GND VCO GND GND VDD CPOUT CREG3 VDD3 OSC1 OSC2 MUXOUT 48 47 46 45 44 43 42 41 40 39 38 37 CVCO CAP Data Sheet ADF7020 SERIAL INTERFACE RSSI Readback The serial interface allows the user to program the fourteen 32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). Signals should be CMOS compatible. The serial interface is powered by the regulator and, therefore, is inactive when CE is low. Data is clocked into the register, MSB first, on the rising edge of each clock (SCLK). Data is transferred to one of fourteen latches on the rising edge of SLE. The destination latch is determined by the value of the four control bits (C4 to C1). These are the bottom four LSBs, DB3 to DB0, as shown in the timing diagram in Figure 3. The RSSI readback operation yields valid results in Rx mode with ASK or FSK signals. The format of the readback word is shown in Figure 42. It comprises the RSSI level information (Bit RV1 to Bit RV7), the current filter gain (FG1, FG2), and the current LNA gain (LG1, LG2) setting. The filter and LNA gain are coded in accordance with the definitions in Register 9. With the reception of ASK modulated signals, averaging of the measured RSSI values improves accuracy. The input power can be calculated from the RSSI readback value as outlined in the RSSI/AGC section. READBACK FORMAT Battery Voltage/ADCIN/Temperature Sensor Readback The readback operation is initiated by writing a valid control word to the readback register and setting the readback enable bit (R7_DB8 = 1). The readback can begin after the control word has been latched with the SLE signal. SLE must be kept high while the data is being read out. Each active edge at the SCLK pin clocks the readback word out successively at the SREAD pin (see Figure 42), starting with the MSB first. The data appearing at the first clock cycle following the latch operation must be ignored. The last (eighteenth) SCLK edge puts the SREAD pin back in three-state. These three ADC readback values are valid by just enabling the ADC in Register 8 without writing to the other registers. The battery voltage is measured at Pin VDD4. The readback information is contained in Bit RV1 to Bit RV7. This also applies for the readback of the voltage at the ADCIN pin and the temperature sensor. From the readback information, the battery, ADCIN voltage or temperature can be obtained using VBATTERY = (Battery_Voltage_Readback)/21.1 VADCIN = (ADCIN_Voltage_Readback)/42.1 Temperature = −40°C + (68.4 − Temperature_Sensor_Readback) × 9.32 AFC Readback The AFC readback is valid only during the reception of FSK signals with either the linear or correlator demodulator active. The AFC readback value is formatted as a signed 16-bit integer comprising Bit RV1 to Bit RV16 and is scaled according to the following formula: Silicon Revision Readback The silicon revision word is coded with four quartets in BCD format. The product code (PC) is coded with three quartets extending from Bit RV5 to Bit RV16. The revision code (RV) is coded with one quartet extending from Bit RV1 to Bit RV4. The product code for the ADF7020 should read back as PC = 0x200. The current revision code should read as RV = 0x8. FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215 In the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 200 kHz. Note that, for the AFC readback to yield a valid result, the down-converted input signal must not fall outside the bandwidth of the analog IF filter. At low input signal levels, the variation in the readback value can be improved by averaging. Filter Calibration Readback The filter calibration readback word is contained in Bit RV1 to Bit RV8 and is for diagnostic purposes only. Using the automatic filter calibration function, accessible through Register 6, is recommended. Before filter calibration is initiated, decimal 32 should be read back as the default value. READBACK VALUE DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AFC READBACK RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 RSSI READBACK X X X X X LG2 LG1 FG2 FG1 RV7 RV6 RV5 RV4 RV3 RV2 RV1 BATTERY VOLTAGE/ADCIN/ TEMP. SENSOR READBACK X X X X X X X X X RV7 RV6 RV5 RV4 RV3 RV2 RV1 SILICON REVISION RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 FILTER CAL READBACK 0 0 0 0 0 0 0 0 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 Figure 42. Readback Value Table Rev. D | Page 31 of 48 05351-039 READBACK MODE ADF7020 Data Sheet REGISTERS DB2 DB1 DB0 C2(0) C1(0) DB3 C4(0) C3(0) DB4 M15 M14 M13 . M3 M2 M1 FRACTIONAL DIVIDE RATIO 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 . . . . . . . . . . 0 0 0 . . . 1 1 1 1 0 0 1 . . . 0 0 1 1 0 1 0 . . . 0 1 0 1 0 1 2 . . . 32,764 32,765 32,766 32,767 N8 N7 N6 N5 N4 N3 N2 N1 N COUNTER DIVIDE RATIO 0 0 . . . 1 0 0 . . . 1 0 1 . . . 1 1 0 . . . 1 1 0 . . . 1 1 0 . . . 1 1 0 . . . 0 1 0 . . . 1 31 32 . . . 253 1 1 1 1 1 1 1 0 254 1 1 1 1 1 1 1 1 255 05351-040 DB12 M9 M1 DB13 M10 DB5 DB14 DB6 DB15 M12 M11 M2 DB16 M13 REGULATOR READY (DEFAULT) R DIVIDER OUTPUT N DIVIDER OUTPUT DIGITAL LOCK DETECT ANALOG LOCK DETECT THREE-STATE PLL TEST MODES Σ-Δ TEST MODES M3 DB17 MUXOUT 0 1 0 1 0 1 0 1 DB7 DB18 M15 M14 M1 0 0 1 1 0 0 1 1 M4 DB19 N1 M2 0 0 0 0 1 1 1 1 DB8 DB20 N2 M3 DB9 DB21 N3 PLL OFF PLL ON M5 DB22 N4 0 1 M6 DB23 N5 PLE1 PLL ENABLE DB10 DB24 N6 TRANSMIT RECEIVE M7 DB25 0 1 DB11 DB26 N8 N7 TRANSMIT/ RECEIVE M8 Tx/Rx TR1 ADDRESS BITS 15-BIT FRACTIONAL-N DB27 DB29 M1 8-BIT INTEGER-N TR1 DB30 M2 PLE1 DB28 DB31 M3 MUXOUT PLL ENABLE REGISTER 0—N REGISTER Figure 43. Register 0—N Register Register 0—N Register Comments • • • The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and controls the state of the internal Tx/Rx switch. fOUT = XTAL Fractional _ N × (Integer _ N + ) R 215 If operating in 433 MHz band, with the VCO Band bit set, the desired frequency, fOUT, should be programmed to be twice the desired operating frequency, due to removal of the divide-by-2 stage in the feedback path. Rev. D | Page 32 of 48 Data Sheet ADF7020 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 XTAL DOUBLER XOSC ENABLE DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CL1 D1 R3 R2 R1 C4(0) C3(0) C2(0) C1(1) DB13 V1 DB9 DB14 CP1 DB10 DB15 CP2 CL2 DB16 VB1 CL3 DB17 VB2 DB11 DB18 VB3 VB4 VB3 VB2 VB1 0 0 0 . 1 0 0 0 . 1 0 0 1 . 1 0 1 0 . 1 FILTER BANDWIDTH 100kHz 150kHz 200kHz NOT USED CL4 DB19 VB4 VCO BAND DB20 VA1 X1 XTAL OSC 0 OFF 1 ON V1 VCO BIAS CURRENT 0 1 ADDRESS BITS R COUNTER DB12 DB21 FREQUENCY OF OPERATION 850 TO 920 860 TO 930 870 TO 940 880 TO 950 CLOCKOUT DIVIDE X1 CP CURRENT VCO ADJUST VA1 VA2 DB22 VA2 VCO BIAS R3 0 0 . . . 1 VCO Band (MHz) 862 TO 956 431 TO 478 0.125mA 0.375mA 0.625mA D1 0 1 R2 0 1 . . . 1 R1 1 0 . . . 1 RF R COUNTER DIVIDE RATIO 1 2 . . . 7 XTAL DOUBLER DISABLE ENABLED 3.875mA CP2 CP1 ICP (mA) 0 0 1 1 0 1 0 1 0.3 0.9 1.5 2.1 CL4 0 0 0 . . . 1 CL3 0 0 0 . . . 1 CL2 0 0 1 . . . 1 CL1 0 1 0 . . . 1 CLKOUT DIVIDE RATIO OFF 2 4 . . . 30 05351-041 IR2 IR1 IR1 IR2 DB23 IF FILTER BW REGISTER 1—OSCILLATOR/FILTER REGISTER Figure 44. Register 1—Oscillator/Filter Register Register 1—Oscillator/Filter Register Comments • • The VCO Adjust Bits R1_DB[20:21] should be set to 0 for operation in the 862 MHz to 870 MHz band and set to 3 for operation in the 902 MHz to 928 MHz band. The VCO bias setting should be 0xA for operation in the 862 MHz to 870 MHz and 902 MHz to 928 MHz bands. All VCO gain numbers are specified for these VCO Adjust and Bias settings. Rev. D | Page 33 of 48 ADF7020 Data Sheet DB12 DB11 DB10 DB9 DB8 DB7 P4 P3 P2 P1 S3 S2 DB0 DB13 P5 C1(0) DB14 P6 DB1 DB15 D1 MUTE PA UNTIL LOCK PA ENABLE PE1 POWER AMPLIFIER 0 1 OFF ON MUTE PA UNTIL MP1 LOCK DETECT HIGH DI1 TxDATA TxDATA 0 1 OFF ON PA2 PA1 PA BIAS S3 S2 S1 MODULATION SCHEME 0 0 1 1 0 1 0 1 5µA 7µA 9µA 11µA 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 FSK GFSK ASK OOK GOOK POWER AMPLIFIER OUTPUT LOW LEVEL D1 D6 D5 . D2 X 0 0 0 0 . . 1 X X 0 0 . . . 1 . . . . . . . . X X 0 0 1 . . 1 X X 0 1 0 . . 1 OOK MODE PA OFF –16.0dBm –16 + 0.45dBm –16 + 0.90dBm . . 13dBm POWER AMPLIFIER OUTPUT HIGH LEVEL P6 . . P2 P1 0 0 0 0 . . 1 . . . . . . 1 . . . . . . . X 0 0 1 . . 1 X 0 1 0 . . 1 PA OFF –16.0dBm –16 + 0.45dBm –16 + 0.90dBm . . 13dBm Figure 45. Register 2—Transmit Modulation Register (ASK/OOK Mode) Register 2—Transmit Modulation Register (ASK/OOK Mode) Comments • • • See the Transmitter section for a description of how the PA bias affects the power amplifier level. The default level is 9 µA. If maximum power is needed, program this value to 11 µA. See Figure 13. D7, D8, and D9 are don’t care bits. Rev. D | Page 34 of 48 05351-042 0 1 C2(1) DB16 D2 X DB2 DB17 D3 X DB3 DB18 D4 X C3(0) DB19 D5 X C4(0) DB20 D6 X DB4 DB21 D7 IC2 IC1 MC3 MC2 MC1 ADDRESS BITS PE1 DB22 D8 DB5 DB23 D9 DB6 DB24 MC1 S1 DB25 MP1 DB26 MC3 MC2 DB28 IC2 MODULATION SCHEME POWER AMPLIFIER MODULATION PARAMETER DB27 DB29 DI1 GFSK MOD CONTROL IC1 DB30 PA1 TxDATA INVERT DB31 PA2 PA BIAS INDEX COUNTER REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE) Data Sheet ADF7020 X X DI1 0 1 TxDATA TxDATA PA2 PA1 PA BIAS 0 0 1 1 0 1 0 1 5µA 7µA 9µA 11µA X DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 P6 P5 P4 P3 P2 P1 S3 S2 S1 MP1 DB0 DB15 D1 C1(0) DB16 D2 DB1 DB17 D3 DB2 DB18 D4 C2(1) DB19 D5 C3(0) DB20 D6 DB3 DB21 F DEVIATION 0 0 0 0 . 1 0 1 0 1 . 1 PLL MODE 1 × fSTEP 2 × fSTEP 3 × fSTEP . 511 × fSTEP 0 0 1 1 . 1 DB4 DB22 D8 D7 D1 0 0 0 0 . 1 PE1 POWER AMPLIFIER 0 1 OFF ON MUTE PA UNTIL MP1 LOCK DETECT HIGH FOR FSK MODE, D9 . D3 D2 . . . . . . PE1 DB23 D9 X ADDRESS BITS C4(0) DB25 DB24 IC2 IC1 MC3 MC2 MC1 X MUTE PA UNTIL LOCK PA ENABLE MODULATION SCHEME POWER AMPLIFIER MC1 DB26 MC3 MODULATION PARAMETER MC2 DB28 DB27 IC1 DB29 DI1 GFSK MOD CONTROL IC2 DB30 PA1 TxDATA INVERT DB31 PA2 PA BIAS INDEX COUNTER REGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE) 0 1 OFF ON S3 S2 S1 MODULATION SCHEME 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 FSK GFSK ASK OOK GOOK 0 0 0 0 . . 1 . . . . . . 1 . . . . . . . Figure 46. Register 2—Transmit Modulation Register (FSK Mode) Register 2—Transmit Modulation Register (FSK Mode) Comments • • • fSTEP = PFD/214. When operating in the 431 MHz to 478 MHz band, fSTEP = PFD/215. PA bias default = 9 µA. Rev. D | Page 35 of 48 X 0 0 1 . . 1 X 0 1 0 . . 1 PA OFF –16.0dBm –16 + 0.45dBm –16 + 0.90dBm . . 13dBm 05351-043 POWER AMPLIFIER OUTPUT LEVEL P6 . . P2 P1 ADF7020 Data Sheet PA1 PA BIAS 0 0 1 1 0 1 0 1 5µA 7µA 9µA 11µA MUTE PA UNTIL LOCK PA ENABLE 0 1 D9 0 0 1 1 IC2 IC1 INDEX_COUNTER 0 0 1 1 0 1 0 1 16 32 64 128 D8 0 1 0 1 GAUSSIAN – OOK MODE NORMAL MODE OUTPUT BUFFER ON BLEED CURRENT ON BLEED/BUFFER ON 0 1 . 1 DB2 DB1 DB0 C2(1) C1(0) S2 S1 MODULATION SCHEME 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 FSK GFSK ASK OOK GOOK 0 0 0 0 . . 1 0 1 . 7 . . . . . . 1 . . . . . . . X 0 0 1 . . 1 X 0 1 0 . . 1 Figure 47. Register 2—Transmit Modulation Register (GFSK/GOOK Mode) Register 2—Transmit Modulation Register (GFSK/GOOK Mode) Comments • • • • DB3 S3 PA OFF –16.0dBm –16 + 0.45dBm –16 + 0.90dBm . . 13dBm 05351-044 0 0 . 1 OFF ON POWER AMPLIFIER OUTPUT LEVEL P6 . . P2 P1 MC3 MC2 MC1 GFSK_MOD_CONTROL 0 0 . 1 MUTE PA UNTIL MP1 LOCK DETECT HIGH TxDATA TxDATA PA2 C3(0) DB7 S2 OFF ON C4(0) DB8 S3 POWER AMPLIFIER 0 1 DB4 DB9 P1 PE1 INVALID 1 2 3 . 127 PE1 DB10 P2 DIVIDER_FACTOR 0 1 0 1 . 1 DB5 DB11 P3 D1 0 0 1 1 . 1 DB6 DB12 P4 D2 0 0 0 0 . 1 S1 DB13 P5 D3 . . . . . . MP1 DB14 DB15 P6 . 0 0 0 0 . 1 D1 DB16 DB21 D7 D7 D2 DB22 D8 DB17 DB23 D9 DB18 DB24 MC1 D3 DB25 MC2 D4 DB26 MC3 DB19 DB27 IC1 D5 DB28 IC2 0 1 ADDRESS BITS DB20 DB29 DI1 DI1 MODULATION SCHEME POWER AMPLIFIER D6 DB30 PA1 MODULATION PARAMETER DB31 TxDATA INVERT GFSK MOD CONTROL PA2 PA BIAS INDEX COUNTER REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE) GFSK_DEVIATION = (2GFSK_MOD_CONTROL × PFD)/212. When operating in the 431 MHz to 478 MHz band, GFSK_DEVIATION = (2GFSK_MOD_CONTROL × PFD)/213. Data Rate = PFD/(INDEX_COUNTER × DIVIDER_FACTOR). PA Bias default = 9 µA. Rev. D | Page 36 of 48 Data Sheet ADF7020 SK7 0 0 . 1 1 0 0 . 1 1 DB0 DB5 BK2 C1(1) DB6 OK1 DB1 DB7 OK2 C2(1) DB8 FS1 DB2 DB9 FS2 DB3 DB10 FS3 C3(0) DB11 FS4 ADDRESS BITS C4(0) DB12 FS5 BB OFFSET CLOCK DIVIDE DB13 FS6 DB4 DB14 FS7 BK1 DB15 FS8 DB16 SK1 DB18 SK3 DB17 DB19 SK2 DB20 SK4 . . . . . . CDR CLOCK DIVIDE SK3 SK2 SK1 SEQ_CLK_DIVIDE BK2 BK1 BBOS_CLK_DIVIDE 0 0 . 1 1 0 1 . 1 1 1 0 . 0 1 1 2 . 254 255 0 0 1 0 1 x 4 8 16 OK2 OK1 DEMOD_CLK_DIVIDE 0 0 1 1 0 1 0 1 4 1 2 3 FS8 FS7 . FS3 FS2 FS1 CDR_CLK_DIVIDE 0 0 . 1 1 0 0 . 1 1 . . . . . 0 0 . 1 1 0 1 . 1 1 1 0 . 0 1 1 2 . 254 255 05351-045 SK8 SK5 DB21 DB22 SK7 SK6 DB23 SK8 SEQUENCER CLOCK DIVIDE DEMOD CLOCK DIVIDE REGISTER 3—RECEIVER CLOCK REGISTER Figure 48. Register 3—Receiver Clock Register Register 3—Receiver Clock Register Comments • Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where BBOS _ CLK = • XTAL BBOS _ CLK _ DIVIDE The demodulator clock (DEMOD_CLK) must be <12 MHz for FSK and <6 MHz for ASK, where DEMOD _ CLK = • Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where CDR _ CLK = • XTAL DEMOD _ CLK _ DIVIDE DEMOD _ CLK CDR _ CLK _ DIVIDE Note that this can affect your choice of XTAL, depending on the desired data rate. The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to 40 kHz for ASK. SEQ _ CLK = XTAL SEQ _ CLK _ DIVIDE Rev. D | Page 37 of 48 ADF7020 Data Sheet 0 0 0 0 1 1 0 0 1 1 0 1 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DW3 DW2 DW1 DS2 DS1 C4(0) C3(1) C2(0) C1(0) DB16 DL1 – – OUTPUT OUTPUT INPUT – DB9 DB17 DL2 INT/LOCK PIN SERIAL PORT CONTROL – FREE RUNNING SERIAL PORT CONTROL – LOCK THRESHOLD SYNC WORD DETECT – FREE RUNNING SYNC WORD DETECT – LOCK THRESHOLD INTERRUPT/LOCK PIN LOCKS THRESHOLD DEMOD LOCKED AFTER DL8–DL1 BITS DW4 DB18 DL3 DEMOD LOCK/SYNC WORD MATCH DW5 DB10 DB19 DL4 DW6 DB11 DB20 DL5 DW7 DB12 DB21 DL6 DW8 DB13 DB22 DL7 DW9 DB14 DB23 DL8 DW10 DB15 DB24 LM1 0 1 0 1 X DL8 ADDRESS BITS POSTDEMODULATOR BW DB25 DEMODULATOR LOCK SETTING LM2 DEMOD MODE LM2 LM1 DL8 0 1 2 3 4 5 DEMOD SELECT DEMOD LOCK/ SYNC WORD MATCH REGISTER 4—DEMODULATOR SETUP REGISTER DS2 DS1 DEMODULATOR TYPE 0 0 1 1 0 1 0 1 LINEAR DEMODULATOR CORRELATOR/DEMODULATOR ASK/OOK INVALID DL8 DL7 0 0 0 . 1 1 0 0 0 . 1 1 . . . . . . DL3 DL2 DL1 LOCK_THRESHOLD_TIMEOUT 0 0 0 . 1 1 0 0 1 . 1 1 0 1 0 . 0 1 0 1 2 . 254 255 05351-046 MODE5 ONLY Figure 49. Register 4—Demodulator Setup Register Register 4—Demodulator Setup Register Comments • • • Demodulator Mode 1, Demodulator Mode 3, Demodulator Mode 4, and Demodulator Mode 5 are modes that can be activated to allow the ADF7020 to demodulate data-encoding schemes that have run-length constraints greater than 7, when using the linear demodulator. 211 × π × fCUTOFF Postdemod_BW = DEMOD_CLK where the cutoff frequency (fCUTOFF) of the postdemodulator filter should typically be 0.75 times the data rate. For Mode 5, Timeout Delay to Lock Threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK where SEQ_CLK is defined in the Register 3—Receiver Clock Register section. Rev. D | Page 38 of 48 Data Sheet ADF7020 DB4 DB3 DB2 DB1 DB0 C4(0) C3(1) C2(0) C1(1) DB5 CONTROL BITS PL1 DB6 MT1 PL2 DB7 DB8 MT2 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DB19 DB18 DB20 DB21 DB22 DB23 DB24 DB25 DB26 DB27 DB28 DB29 DB30 DB31 SYNC BYTE SEQUENCE SYNC BYTE LENGTH MATCHING TOLERANCE REGISTER 5—SYNC BYTE REGISTER PL2 PL1 SYNC BYTE LENGTH 0 0 1 1 0 1 0 1 12 BITS 16 BITS 20 BITS 24 BITS 0 0 1 1 0 1 0 1 0 ERRORS 1 ERROR 2 ERRORS 3 ERRORS 05351-047 MATCHING MT2 MT1 TOLERANCE Figure 50. Register 5—Sync Byte Register Register 5—Sync Byte Register Comments • • • • Sync byte detect is enabled by programming Bits R4_DB[25:23] to 010 or 011. This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, then the INT/LOCK pin goes high when the sync byte is detected in Rx mode. Once the sync word detect signal goes high, it goes low again after nine data bits. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware. Choose a sync byte pattern that has good autocorrelation properties, for example, 0x123456. Rev. D | Page 39 of 48 ADF7020 Data Sheet LI2 LI1 LNA BIAS 0 0 800µA (DEFAULT) FC9 . FC6 FC5 FC4 FC3 FC2 FC1 FILTER CLOCK DIVIDE RATIO 0 0 . . . . 1 . . . . . . . 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 0 1 . . . . 1 1 0 . . . . 1 1 2 . . . . 511 DB2 DB1 DB0 C2(1) C1(0) DB5 TD2 C3(1) DB6 TD3 0 1 DEFAULT HIGH DB3 DB7 TD4 LG1 LNA MODE 0 1 DB4 DB8 TD5 ML1 MIXER LINEARITY TD1 DB9 CROSS PRODUCT DOT PRODUCT C4(0) DB10 TD6 DB14 DP1 TD7 DB15 LG1 DOT PRODUCT 0 1 DEFAULT REDUCED GAIN 05351-048 NORMAL OPPERATION CDR RESET DB11 DB16 LI1 DB24 FC5 RxRESET 0 1 TD8 DB17 LI2 DB25 FC6 NORMAL OPPERATION DEMOD RESET DB12 DB18 ML1 DP1 0 1 RxRESET 0 1 TD9 DOT PRODUCT DB19 CA1 CA1 FILTER CAL NO CAL CALIBRATE ADDRESS BITS DISCRIMINATOR BW TD10 DB13 LNA MODE DB20 FC1 DB26 FC7 RxDATA RxDATA LNA CURRENT DB21 FC2 IF FILTER CAL MIXER LINEARITY DB22 FC3 DB27 FC8 0 1 DB23 DB28 FC9 RI1 RxDATA INVERT FC4 DB29 DB30 IF FILTER DIVIDER RI1 DB31 Rx RESET RxDATA INVERT REGISTER 6—CORRELATOR/DEMODULATOR REGISTER Figure 51. Register 6—Correlator/Demodulator Register Register 6—Correlator/Demodulator Register Comments • • • • • • See the FSK Correlator/Demodulator section for an example of how to determine register settings. Nonadherence to correlator programming guidelines results in poorer sensitivity. The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The formula is XTAL/FILTER_CLOCK_DIVIDE. The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is set high. Discriminator_BW = (DEMOD_CLK × K)/(800 × 103). See the FSK Correlator/Demodulator section. Maximum value = 600. When LNA Mode = 1 (reduced gain mode), the Rx is prevented from selecting the highest LNA gain setting. This can be used when linearity is a concern. See Table 5 for details of the different Rx modes. Rev. D | Page 40 of 48 Data Sheet ADF7020 REGISTER 7—READBACK SETUP REGISTER CONTROL BITS ADC MODE DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RB3 RB2 RB1 AD2 AD1 C4(0) C3(1) C2(1) C1(1) RB3 READBACK AD2 AD1 ADC MODE 0 1 0 0 1 1 DISABLED ENABLED RB2 RB1 READBACK MODE 0 0 1 1 0 1 0 1 0 1 0 1 AFC WORD ADC OUTPUT FILTER CAL SILICON REV MEASURE RSSI BATTERY VOLTAGE TEMP SENSOR TO EXTERNAL PIN 05351-049 READBACK SELECT Figure 52. Register 7—Readback Setup Register Register 7—Readback Setup Register Comments • • • Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or the voltage at the external pin in Rx mode, AGC function in Register 9 must be disabled. To read back these parameters in Tx mode, the ADC must first be powered up using Register 8 because this is off by default in Tx mode to save power. This is the recommended method of using the battery readback function because most configurations typically require AGC. Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active. See the Readback Format section for more information. Rev. D | Page 41 of 48 ADF7020 Data Sheet PA (Rx MODE) 0 1 PA OFF PA ON INTERNAL Tx/Rx SWITCH ENABLE DEMOD ENABLE ADC ENABLE FILTER ENABLE LNA/MIXER ENABLE VCO ENABLE SYNTH ENABLE DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PD7 SW1 LR2 LR1 PD6 PD5 PD4 PD3 PD2 PD1 C4(1) C3(0) C2(0) C1(0) LOG AMP/ RSSI SW1 Tx/Rx SWITCH 0 1 DEFAULT (ON) OFF CONTROL BITS PLE1 (FROM REG 0) PD2 PD1 LOOP CONDITION 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X VCO/PLL OFF PLL ON VCO ON PLL/VCO ON PLL/VCO ON LR2 LR1 RSSI MODE PD3 LNA/MIXER ENABLE X X 0 1 RSSI OFF RSSI ON 0 1 LNA/MIXER OFF LNA/MIXER ON PD6 DEMOD ENABLE PD4 FILTER ENABLE 0 1 DEMOD OFF DEMOD ON 0 1 FILTER OFF FILTER ON PD5 ADC ENABLE 0 1 ADC OFF ADC ON 05351-050 PD7 PA ENABLE Rx MODE REGISTER 8—POWER-DOWN TEST REGISTER Figure 53. Register 8—Power-Down Test Register Register 8—Power-Down Test Register Comments • • For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition. It is not necessary to write to this register under normal operating conditions. Rev. D | Page 42 of 48 Data Sheet ADF7020 0 1 8 24 72 INVALID DB6 DB5 DB4 DB3 DB2 DB1 DB0 GL3 GL2 GL1 C4(1) C3(0) C2(0) C1(1) DB7 DB8 DB9 GL6 GL4 DB10 GL5 DB11 DB13 GH3 GC1 GAIN CONTROL 0 0 1 1 0 1 0 1 AGC LOW GL7 GL6 GL5 GL4 GL3 GL2 GL1 THRESHOLD AUTO AGC HOLD SETTING FG2 FG1 FILTER GAIN GL7 DB14 GH4 0 1 GH1 DB15 GH5 GS1 AGC SEARCH LOW HIGH DB12 DB16 GH6 FILTER CURRENT 0 1 GH2 DB17 DB19 GC1 FI1 ADDRESS BITS AGC LOW THRESHOLD AGC HIGH THRESHOLD GH7 DB20 LG1 DB18 DB21 LG2 GS1 DB22 FG1 GAIN CONTROL AGC SEARCH DB23 FG2 LNA GAIN DB24 DB25 FILTER GAIN FI1 DB26 DIGITAL TEST IQ FILTER CURRENT REGISTER 9—AGC REGISTER 0 0 0 0 . . . 1 1 1 AUTO USER 0 0 0 0 . . . 0 0 0 0 0 0 0 . . . 0 0 1 0 0 0 0 . . . 1 1 0 0 1 1 0 . . . 1 1 0 0 0 0 1 . . . 1 1 0 1 0 1 0 . . . 0 1 0 1 2 3 4 . . . 78 79 80 LG2 LG1 LNA GAIN 0 0 1 1 0 1 0 1 <1 3 10 30 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 0 0 0 0 0 0 0 . . . 0 0 1 0 0 0 0 . . . 1 1 0 0 0 0 1 . . . 1 1 0 0 1 1 0 . . . 1 1 0 1 0 1 0 . . . 0 1 0 1 2 3 4 . . . 78 79 80 Figure 54. Register 9—AGC Register Register 9—AGC Register Comments • This register does not need to be programmed in normal operation. Default AGC_Low_Threshold = 30, default AGC_High_Threshold = 70. See the RSSI/AGC section for details. Default register setting = 0xB2 31E9. • AGC high and low settings must be more than 30 apart to ensure correct operation. • LNA gain of 30 is available only if LNA mode, R6_DB15, is set to 0. Rev. D | Page 43 of 48 05351-051 AGC HIGH GH7 GH6 GH5 GH4 GH3 GH2 GH1 THRESHOLD ADF7020 Data Sheet DB2 DB1 DB0 C3(0) C2(1) C1(0) DB4 PR1 DB3 DB5 PR2 C4(1) DB6 DB7 PR4 PR3 DB8 DB12 DH1 DB9 DB13 DH2 GL4 DB14 DH3 DEFAULT = 0xA DEFAULT = 0xA DEFAULT = 0x2 05351-052 0 1 PHASE TO I CHANNEL PHASE TO Q CHANNEL GL5 DB15 DH4 0 1 DB10 DB16 GC1 SIQ2 SELECT IQ GL6 DB17 GC2 SIQ2 SELECT IQ DB11 DB18 GC3 IF DB21 = 0, THEN GAIN IS SELECTED. IF DB21 = 1, THEN ATTENUATE IS SELECTED ADDRESS BITS PEAK RESPONSE GL7 DB19 GC4 SELECT I/Q GAIN/ATTENUATE DB20 DB23 R1 LEAK FACTOR DB21 DB24 PH1 AGC DELAY UD1 DB25 PH2 I/Q GAIN ADJUST GC5 DB26 SIQ1 DB22 RESERVED DB27 PH3 I/Q PHASE ADJUST PH4 SIQ2 DB28 SELECT I/Q REGISTER 10—AGC 2 REGISTER GAIN TO I CHANNEL GAIN TO Q CHANNEL Figure 55. Register 10—AGC 2 Register Register 10—AGC 2 Register Comments • • This register is not used under normal operating conditions. For ASK/OOK modulation, the recommended settings for operation over the full input range are peak response = 2, leak factor = 10 (default), and AGC delay =10 (default). Bit DB31 to Bit DB16 should be cleared. For bit-rates below 4kbps the AGC_Wait_time can be increased by setting the AGC_Delay to 15. The SEQ_CLK should also be set at a minimum. DB20 AFC ENABLE DB19 DB18 DB17 DB16 DB15 AE1 M16 M15 M14 M13 M12 REGISTER 11—AFC REGISTER CONTROL BITS DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C4(1) C3(0) C2(1) C1(1) AFC SCALING COEFFICIENT 0 1 05351-053 INTERNAL AE1 AFC OFF ON Figure 56. Register 11—AFC Register Register 11—AFC Register Comments • • See the Internal AFC section to program the AFC scaling coefficient bits. The AFC scaling coefficient bits can be programmed using the following formula: AFC_Scaling_Coefficient = Round((500 × 224)/XTAL) Rev. D | Page 44 of 48 Data Sheet ADF7020 PRESCALER 0 1 4/5 (DEFAULT) 8/9 CAL SOURCE 0 1 INTERNAL SERIAL IF BW CAL DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 T7 T6 T5 T4 T3 T2 T1 C4(1) C3(1) C2(0) C1(0) COUNTER RESET T8 DB18 SF1 DB12 DB19 SF2 T9 DB20 SF3 DB17 DB21 SF4 DB13 DB22 SF5 CS1 ADDRESS BITS PLL TEST MODES CR1 DB23 SF6 DB14 SOURCE DB24 CS1 DB15 OSC TEST DB25 QT1 DEFAULT = 32. INCREASE NUMBER TO INCREASE BW IF USER CAL ON Σ-Δ TEST MODES CR1 COUNTER RESET 0 1 DEFAULT RESET 05351-054 P DIGITAL TEST MODES MANUAL FILTER CAL DB16 FORCE LD HIGH DB26 DB27 DB28 DB29 DB30 ANALOG TEST MUX PRE DB31 PRESCALER REGISTER 12—TEST REGISTER Figure 57. Register 12—Test Register Register 12—Test Register Comments This register does not need to be written to in normal operation. The default test mode is 0x0000 000C, which puts the part in normal operation. Using the Test DAC on the ADF7020 to Implement Analog FM Demodulation and Measuring of SNR The test DAC allows the output of the postdemodulator filter for both the linear and correlator/demodulators (see Figure 30 and Figure 31) to be viewed externally. It takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order Σ-Δ converter. The output can be viewed on the CLKOUT pin. This signal, when filtered appropriately, can then be used to • • Monitor the signals at the FSK/ASK postdemodulator filter output. This allows the demodulator output SNR to be measured. Eye diagrams can also be constructed of the received bit stream to measure the received signal quality. Provide analog FM demodulation. While the correlators and filters are clocked by DEMOD_CLK, CDR_CLK clocks the test DAC. Note that although the test DAC functions in a regular user mode, the best performance is achieved when the CDR_CLK is increased up to or above the frequency of DEMOD_CLK. The CDR block does not function when this condition exists. Programming the test register, Register 12, enables the test DAC. In correlator mode, this can be done by writing to Digital Test Mode 7 or 0x0001C00C. To view the test DAC output when using the linear demodulator, the user must remove a fixed offset term from the signal using Register 13. This offset is nominally equal to the IF frequency. The user can determine the value to program by using the frequency error readback to determine the actual IF and then programming half this value into the offset removal field. It also has a signal gain term to allow the usage of the maximum dynamic range of the DAC. Setting Up the Test DAC • Digital test modes = 7: enables the test DAC, with no offset removal (0x0001 C00C). • Digital test modes = 10: enables the test DAC, with offset removal (needed for linear demodulation only, 0x02 800C). The output of the active demodulator drives the DAC, that is, if the FSK correlator/demodulator is selected, the correlator filter output drives the DAC. The evaluation boards for the ADF7020 contain land patterns for placement of an RC filter on the CLKOUT line. This is typically designed so that the cut-off frequency of the filter is above the demodulated data rate. Rev. D | Page 45 of 48 ADF7020 Data Sheet REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER PE2 PE1 PULSE EXTENSION 0 0 0 . . . 1 0 0 1 . . . 1 0 1 0 . . . 1 NORMAL PULSE WIDTH 2 × PULSE WIDTH 3 × PULSE WIDTH . . . 16 × PULSE WIDTH DB3 DB2 DB1 DB0 C4(1) C3(1) C2(0) C1(1) DB4 DB6 KP DEFAULT = 2 05351-055 PE3 0 0 0 . . . 1 DB7 DB8 DB12 PE1 KI DEFAULT = 3 PE4 CONTROL BITS KP DB9 DB13 PE2 DB10 DB14 PE3 DB11 DB15 PE4 DB16 DB17 DB18 DB19 DB20 DB21 DB22 DB23 DB24 DB25 KI DB5 PULSE EXTENSION TEST DAC OFFSET REMOVAL DB26 DB27 DB28 DB29 DB30 DB31 TEST DAC GAIN Figure 58. Register 13—Offset Removal and Signal Gain Register Register 13—Offset Removal and Signal Gain Register Comments • • Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined with a relatively low signal. The offset can be removed, up to a maximum of 1.0, and gained to use the full dynamic range of the DAC: DAC_Input = (2Test_DAC_Gain) × (Signal − Test_DAC_Offset_Removal/4096) Ki (default) = 3. Kp (default) = 2. Rev. D | Page 46 of 48 Data Sheet ADF7020 OUTLINE DIMENSIONS 0.30 0.23 0.18 PIN 1 INDICATOR 48 37 36 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.45 0.40 0.35 4.25 4.10 SQ 3.95 EXPOSED PAD 12 25 24 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. 08-16-2010-B 7.00 BSC SQ Figure 59. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 7 mm × 7 mm Body, Very Very Thin Quad (CP-48-5) Dimensions shown in millimeters ORDERING GUIDE Model1 ADF7020BCPZ ADF7020BCPZ-RL EVAL-ADF70xxMBZ EVAL-ADF70xxMBZ2 EVAL-ADF7020DBZ1 EVAL-ADF7020DBZ2 EVAL-ADF7020DBZ3 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Control Mother Board Evaluation Platform 902 MHz to 928 MHz Daughter Board 860 MHz to 870 MHz Daughter Board 430 MHz to 445 MHz Daughter Board Z = RoHS Compliant Part. Formerly CP-48-3 package. Rev. D | Page 47 of 48 Package Option2 CP-48-5 CP-48-5 ADF7020 Data Sheet NOTES ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05351-0-8/12(D) Rev. D | Page 48 of 48