IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: IDT74SSTV16859 DESCRIPTION: • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs Differential CLK input RESET control compatible with LVCMOS levels Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) • Available in 56 pin VFQFPN and 64 pin TSSOP packages The SSTV16859 is a 13-bit to 26-bit registered buffer designed for 2.3V2.7V VDD and supports low standby operation. All data inputs and outputs are SSTL_2 level compatible with JEDEC standard for SSTL_2. RESET is an LVCMOS input since it must operate predictably during the power-up phase. RESET, which can be operated independent of CLK and CLK, must be held in the low state during power-up in order to ensure predictable outputs (low state) before a stable clock has been applied. RESET, when in the low state, will disable all input receivers, reset all registers, and force all outputs to a low state, before a stable clock has been applied. With inputs held low and a stable clock applied, outputs will remain low during the Low-to-High transition of RESET. APPLICATIONS: • Ideally suited for DIMM DDR registered applications FUNCTIONAL BLOCK DIAGRAM RESET CLK CLK VREF D1 51 48 49 45 35 16 1D Q1A C1 R 32 Q1B TO 12 OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE MARCH 2002 1 c 2003 Integrated Device Technology, Inc. DSC-5947/8 IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE VDDQ Q13A 1 64 VDDQ Q12A 2 63 GND Q11A 3 62 D13 Q10A 4 61 D12 43 D11 VDD D12 D13 GND Q13A VDDQ Q12A Q11A Q10A Q9A VDDQ 56 Q8A PIN CONFIGURATIONS Q9A 5 60 VDD VDDQ 6 59 VDDQ GND 7 58 GND Q8A 8 57 D11 Q7A 9 56 D10 Q6A 10 55 D9 Q5A 11 54 GND CLK Q4A 12 53 D8 CLK Q3A 13 52 D7 VDDQ VDDQ Q2A 14 51 RESET Q12B VDD GND 15 50 GND Q11B VREF 16 49 CLK Q10B D6 Q1A D5 Q13B 17 48 CLK 29 D4 VDDQ 18 47 VDDQ Q12B 19 46 VDD Q11B 20 45 VREF Q10B 21 44 D6 Q9B 22 43 GND Q8B 23 42 D5 Q7B 24 41 D4 Q6B 25 40 D3 Q7A 1 42 D10 Q6A D9 Q5A D8 D7 Q4A Q3A RESET Q2A GND Q1A GND Q13B Q9B D3 28 VDDQ VDD D2 D1 VDDQ Q1B Q2B Q3B Q4B Q5B VDDQ Q6B Q7B 15 Q8B 14 VFQFPN TOP VIEW GND 26 39 GND VDDQ 27 38 VDDQ Q5B 28 37 VDD Q4B 29 36 D2 Q3B 30 35 D1 Q2B 31 34 GND Q1B 32 33 VDDQ ABSOLUTE MAXIMUM RATINGS (1) Symbol VDD or VDDQ Description Supply Voltage Range Max. Unit –0.5 to 3.6 V VI(2) Input Voltage Range –0.5 to VDD +0.5 V VO(3) Output Voltage Range –0.5 to VDDQ +0.5 V IIK Input Clamp Current, VI < 0 –50 mA IOK Output Clamp Current, ±50 mA ±50 mA ±100 mA –65 to +150 °C TSSOP TOP VIEW VO < 0 or VO > VDDQ IO Continuous Output Current, FUNCTION TABLE (1) VO = 0 to VDDQ VDD Continuous Current through each Input VDD, VDDQ or GND TSTG Storage Temperature Range NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 3. The output current will flow if the following conditions are observed: a) Output in HIGH state b) VO = VDDQ RESET CLK CLK D Q Outputs H ↑ ↓ L L H ↑ ↓ H H H L or H L or H X Qo(2) L X X X L NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW 2. Qo = Output level before the indicated steady-state conditions were established. 2 IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Names Q1 - Q13 Description Data Output GND Ground VDDQ Output-stage drain power voltage VDD Logic power voltage Asynchronous reset input - resets registers and disables data and clock differential input recievers Input reference voltage Positive master clock input Negative master clock input Data Input - clocked in on the crossing of the rising edge of CLK and the falling edge of CLK Ground (MLF package only) RESET VREF CLK CLK D1 - D13 Center PAD DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C, VDD = 2.5V ±0.2V, VDDQ = 2.5V ±0.2V Symbol VIK Parameter Test Conditions Control Inputs VDD = 2.3V, II= −18mA VOH VDD = 2.3V to 2.7V, IOH = -100μA VDD = 2.3V, IOH = -16mA VOL II IDD Min. Typ. Max. Unit — — –1.2 V V VDD – 0.2 — — 1.95 — — VDD = 2.3V to 2.7V, IOL = 100μA — — 0.2 VDD = 2.3V, IOL = 16mA — — 0.35 All Inputs VDD = 2.7V,VI = VDD or GND — — ±5 μA Static Standby IO = 0, VDD = 2.7V, RESET = GND — — 0.01 mA Static Operating IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC) — — 20 Dynamic Operating (Clock Only) IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC), — 6 — μA/Clock Dynamic Operating IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC), — 43 — μA/Clock (Per Each Data Input)(1) CLK and CLK Switching 50% Duty Cycle. One Data Input CLK and CLK Switching 50% Duty Cycle. IDDD V MHz MHz/Data Switching at Half Clock Frequency, 50% Duty Cycle. Input rOH Output HIGH VDD = 2.3V to 2.7V, IOH = -20mA 7 — 20 Ω rOL Output LOW VDD = 2.3V to 2.7V, IOH = 20mA 7 — 20 Ω Ω rO(Δ) CI | rOH- rOL| each separate bit VDD = 2.5V, TA = 25°C, IOH = -20mA — — 4 Data Inputs VDD = 2.5V, VI = VREF ± 310mV 2 — 3 CLK and CLK VICR = 1.25V, VI (PP) = 360mV 2 — 3 RESET VI = VDD or GND 2 — 3 NOTE: 1. Power dissipation levels will allow operation at DDR333 speeds without excessive die temperature. 3 pF IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, TA = 25ºC (1) Symbol Typ.(1) Parameter Min. VDDQ — 2.7 V 2.3 2.5 2.7 V VDD Supply Voltage VDDQ Output Supply Voltage VREF Reference Voltage (VREF= VDDQ/2) V TT Termination Voltage VI Input Voltage VIH AC High-Level Input Voltage Data Inputs Max. Unit 1.15 1.25 1.35 V VREF– 40mV VREF VREF+ 40mV V 0 — VDD V VREF+ 310mV — — V VIL AC Low-Level Input Voltage Data Inputs — — VREF– 310mV V VIH DC High-Level Input Voltage Data Inputs VREF+ 150mV — — V VIL DC Low-Level Input Voltage Data Inputs — — VREF– 150mV V VIH High-Level Input Voltage RESET 1.7 — — V VIL Low-Level Input Voltage RESET — — 0.7 V VICR Common-Mode Input Range CLK, CLK 0.97 — 1.53 V VI (PP) Peak-to-Peak Input Voltage CLK, CLK 360 — — mV IOH High-Level Output Current — — – 20 mA IOL Low-Level Output Current TA Operating Free-Air Temperature — — 20 – 40 — +85 °C NOTE: 1. The RESET input of the device must be held at VDD or GND to ensure proper device operation. TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE VDD = 2.5V ± 0.2V Symbol Min. Max. Unit Clock Frequency — 200 MHz Pulse Duration, CLK, CLK HIGH or LOW 2.5 — ns tACT Differential Inputs Active Time — 22 ns tINACT Differential Inputs Inactive Time(2) — 22 ns 0.75 — ns 0.9 — ns 0.75 — ns 0.9 — ns CLOCK tw tSU Parameter (1) Setup Time, Fast Slew Rate (3, 5) Data Before CLK↑, CLK↓ Setup Time, Slow Slew Rate(4, 5) tN Hold Time, Fast Slew Rate (3,5) Data Before CLK↑, CLK ↓ Hold Time, Slow Slew Rate(2,5) NOTES: 1. Data inputs must be low a minimum time of tACT max., after RESET is taken HIGH. 2. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max., after RESET is taken LOW. 3. For data signal input slew rate is ≥1V/ns. 4. For data signal input slew rate is ≥0.5V/ns and <1V/ns. 5. CLK, CLK signal input slew rates are ≥1V/ns. SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) VDD = 2.5V ± 0.2V Symbol fMAX tPD tPHL Parameter Min 200 1.1 — CLK and CLK to Q RESET to Q 4 Max. — 2.8 5 Unit MHz ns ns IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 2.5V ± 0.2V) VTT RL = 50Ω From Output Under Test Test Point CL = 30 pF (see note 1) Load Circuit LVCMOS RESET Input VDD VDD/2 VDD/2 tINACT Timing Input 0V tACT VICR VICR tPLH VI(PP) tPHL VOH IDD 90% 10% Output VTT VTT VOL (see note 2) Voltage and Current Waveforms Inputs Active and Inactive Times Voltage Waveforms - Propagation Delay Times LVCMOS RESET Input VIH VDD/2 VIL tPHL tW VOH VIH Input VREF VREF Output Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Pulse Duration Timing Input VICR tSU VTT VIL VI(PP) tN VIH Input VREF VREF VIL Voltage Waveforms - Setup and Hold Times NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA. 3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDDQ/2 6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. tPLH and tPHL are the same as tPD. 5 VOL IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX XX SSTV Family Temp. Range XXX XX Device Type Package PA NL Thin Shrink Small Outline Package Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package 859 13-Bit to 26-Bit Registered Buffer with SSTL I/O 16 Double-Density 74 –40°C to +85°C CORPORATE HEADQUARTERS San Jose, CA 95138 6 for SALES: fax: 408-284-2775 www.idt.com