Low Phase Noise,1-to-4, 3.3V, 2.5V LVPECL Output Fanout Buffer IDT8SLVP1104I DATASHEET General Description Features The IDT8SLVP1104I is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVP1104I is characterized to operate from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVP1104I ideal for those clock distribution applications demanding well-defined performance and repeatability.Four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise. • • Four low skew, low additive jitter LVPECL differential output pairs • Differential PCLKx pairs can also accept single-ended LVCMOS levels. See the Applications section Writing the Differential Input Levels to Accept Single-ended Levels (Figures 1 and 2) • • • • • Maximum input clock frequency: 2GHz • • • • Maximum device current consumption (IEE): 60mA (maximum) Output skew: 5ps (typical) Propagation delay: 320ps (maximum) Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: 40fs (maximum) Full 3.3V or 2.5V supply voltage Lead-free (RoHS 6) packaging -40°C to 85°C ambient operating temperature 8 VREF 7 nPCLK Q3 15 6 PCLK nQ3 16 1 5 VCC 2 Q2 nQ2 3 4 nc Q1 nQ1 nc fREF 9 nQ2 14 VEE Pullup/Pulldown Q0 nQ1 12 11 10 Q2 13 Q0 nQ0 nc Pulldown nQ0 Pin Assignment VCC PCLK nPCLK LVCMOS interface levels for the control input (input select) Q1 Block Diagram Differential LVPECL input pair can accept the following differential input levels: LVDS, LVPECL, CML IDT8SLVP1104I Q3 nQ3 16 lead VFQFN 3.0mm x 3.0mm x 0.925mm package body 1.7mm x 1.7mm Epad Size NL Package VREF Top View Voltage Reference IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 1 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1 VEE Power 2 nc Unused Do not connect. 3 nc Unused Do not connect. 4 nc Unused Do not connect. 5 VCC Power 6 PCLK Input Pulldown Non-inverting differential LVPECL clock/data input. 7 nPCLK Input Pullup/ Pulldown Inverting differential LVPECL clock/data input. VCC/2 default when left floating. 8 VREF Output Bias voltage reference for the PCLK inputs. 9, 10 Q0, nQ0 Output Differential output pair 0. LVPECL interface levels. 11, 12 Q1, nQ1 Output Differential output pair 1. LVPECL interface levels. 13, 14 Q2, nQ2 Output Differential output pair 2. LVPECL interface levels. 15, 16 Q3, nQ3 Output Differential output pair 3. LVPECL interface levels. Negative supply pin. Power supply pin. NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 2 pF RPULLDOWN Input Pulldown Resistor 51 k RPULLUP Input Pullup Resistor 51 k IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 Test Conditions 2 Minimum Typical Maximum Units ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Input Sink/Source, IREF ±2mA Maximum Junction Temperature, TJ,MAX 125°C Storage Temperature, TSTG -65C to 150C ESD - Human Body Model, NOTE 1 2000V ESD - Charged Device Model, NOTE 1 1500V NOTE 1: According to JEDEC/JESD 22-A114/22-C101. DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current ICC Power Supply Current Minimum Typical Maximum Units 3.135 3.3V 3.465 V 53 60 mA 170 204 mA Q0 to Q3 terminated 50 to VCC – 2V Table 3B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current ICC Power Supply Current Minimum Typical Maximum Units 2.375 2.5V 2.625 V 49 55 mA 170 199 mA Typical Maximum Units 150 µA Q0 to Q3 terminated 50 to VCC – 2V Table 3C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum IIH Input High Current PCLK, nPCLK VCC = VIN = 3.465V Input Low Current PCLK VCC = 3.465V, VIN = 0V -10 µA IIL nPCLK VCC = 3.465V, VIN = 0V -150 µA VREF Reference Voltage for Input Bias IREF = ±1mA VCC – 1.6 VCC – 1.3 VCC – 1.1 V VOH Output High Voltage; NOTE 1 VCC – 1.1 VCC – 0.9 VCC – 0.7 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.65 VCC – 1.5 V NOTE 1: Outputs terminated with 50 to VCC – 2V. IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 3 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Table 3D. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current PCLK, nPCLK VCC = VIN = 2.625V 150 µA Input Low Current PCLK VCC = 2.625V, VIN = 0V -10 µA IIL nPCLK VCC = 2.625V, VIN = 0V -150 µA VREF Reference Voltage for Input Bias IREF = ±1mA VCC – 1.6 VCC – 1.3 VCC – 1.1 V VOH Output High Voltage; NOTE 1 VCC – 1.1 VCC – 0.9 VCC – 0.7 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.6 VCC – 1.5 V NOTE 1: Outputs terminated with 50 to VCC – 2V. IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 4 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER AC Electrical Characteristics Table 4. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fREF Input Frequency PCLK, nPCLK V/t Input Edge Rate PCLK, nPCLK tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tsk(p) Pulse Skew tsk(pp) Part-to-Part Skew; NOTE 3, 4 tJIT tR / tF Test Conditions Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Peak-to-Peak Input Voltage; NOTE 5, 6 VCMR Common Mode Input Voltage; NOTE 5, 6, 7 VO(pp) Output Voltage Swing, Peak-to-Peak VDIFF_OUT Differential Output Voltage Swing, Peak-to-Peak Typical Maximum Units 2 GHz 1.5 PCK, nPCLK to any Q[0:3], nQ[0:3] for VPP = 0.1V or 0.3V 120 fREF = 100MHz V/ns 200 320 ps 5 25 ps 5 20 ps 100 200 ps fREF = 122.88MHz Sine Wave, VPP = 1V, Integration Range: 1kHz – 40MHz 170 fs fREF = 122.88MHz Sine Wave, VPP = 1V, Integration Range: 10kHz – 20MHz 114 fs fREF = 122.88MHz Sine Wave, VPP = 1V, Integration Range: 12kHz – 20MHz 114 fs fREF = 156.25MHz Square Wave, VPP = 1V, Integration Range: 1kHz – 40MHz 42 51 fs fREF = 156.25MHz Square Wave, VPP = 1V, Integration Range: 10kHz – 20MHz 32 40 fs fREF = 156.25MHz Square Wave, VPP = 1V, Integration Range: 12kHz – 20MHz 32 40 fs fREF = 156.25MHz Square Wave, VPP = 0.5V, Integration Range: 1kHz – 40MHz 51 71 fs fREF = 156.25MHz Square Wave, VPP = 0.5V, Integration Range: 10kHz – 20MHz 38 52 fs fREF = 156.25MHz Square Wave, VPP = 0.5V, Integration Range: 12kHz – 20MHz 38 52 fs Output Rise/ Fall Time VPP Minimum 20% to 80% 35 180 ps fREF < 1.5 GHz 0.1 1.5 V fREF > 1.5 GHz 0.2 1.5 V 1.0 VCC – 0.6 V VCC = 3.3V, fREF 2GHz 0.45 0.75 1.0 V VCC = 2.5V, fREF 2GHz 0.4 0.65 1.0 V VCC = 3.3V, fREF 2GHz 0.9 1.5 2.0 V VCC = 2.5V, fREF 2GHz 0.8 1.3 2.0 V NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTES continued on next page. IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 5 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: For single-ended LVCMOS input applications, refer to the Applications section Writing the Differential Input Levels to Accept Single-ended Levels (Figures 1 and 2). NOTE 6: VIL should not be less than -0.3V. NOTE 7: Common mode input voltage is defined as the crosspoint. IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 6 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise dBc/Hz fREF = 156.25MHz, VPP = 1V, Integration Range 12kHz – 20MHz: 40fs (maximum) Offset from Carrier Frequency (Hz) Measured using a Wenzel 156.25MHz Oscillator as the input source. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 7 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Parameter Measurement Information 2V 2V VCC Qx SCOPE VCC Qx nQx SCOPE nQx VEE VEE -0.5V±0.125V -1.3V±0.165V 2.5V LVPECL Output Load Test Circuit 3.3V LVPECL Output Load Test Circuit VCC nQx Qx nPCLK nQy PCLK Qy VEE Output Skew Differential Input Level nPCLK Par t 1 nQx PCLK nQy nQy Qx Par t 2 Qy t PLH Qy tsk(pp) tsk(p) = |t PHL - t PLH| Pulse Skew Part-to-Part Skew IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 t PHL 8 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Parameter Measurement Information, continued nPCLK nQ[0:3] PCLK PCLK Q[0:3] Q[0:3] tPD Propagation Delay IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 Output Rise/Fall Time 9 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Applications Information Wiring the Differential Input to Accept Single-Ended Levels The IDT8SLVP1104I inputs can be interfaced to LVPECL, LVDS, CML or LVCMOS drivers. Figure 1A illustrates how to dc couple a single LVCMOS input to the IDT8SLVP1104I. The value of the series resistance RS is calculated as the difference between the transmission line impedance and the driver output impedance. This resistor should be placed close to the LVCMOS driver. To avoid cross-coupling of single-ended LVCMOS signals, apply the LVCMOS signals to no more than one PCLK input. VIH Vth VIL RS A practical method to implement Vth is shown in Figure 1B below. The reference voltage Vth = V1 = VCC/2, is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. LVCMOS The ratio of R1 and R2 might need to be adjusted to position the V1 in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below apply when both the single-ended swing and VCC are at the same voltage. Vth = VIH + VIL 2 Figure 1A. DC-Coupling a Single LVCMOS Input to the IDT8SLVP1104I When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced, particularly if both input references are LVCMOS to minimize cross talk. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. load. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. R3 and R4 in parallel should equal the transmission line impedance; for most 50 applications, R3 and R4 will be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. Though some of the recommended components of Figure 1B might not be used, the pads should be placed in the layout so that they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1B shows a way to attenuate the PCLK input level by a factor of two as well as matching the transmission line between the LVCMOS driver and the IDT8SLVP1104I at both the source and the VCC VCC VCC VCC R3 100 Ro RS R1 1K Zo = 50 Ohm + Driver V1 Ro + Rs = Zo R4 100 Receiv er - C1 0.1uF R2 1K Figure 1B. Alternative DC Coupling a Single LVCMOS Input to the IDT8SLVP1104I IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 10 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER 3.3V LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, LVDS, CML and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the PCLK/ nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V 3.3V Zo = 50Ω 3.3V PCLK PCLK R1 100Ω nPCLK Zo = 50Ω nPCLK LVPECL Input CML LVPECL CML Built-In Pullup Input Figure 2B. PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver Figure 2A. PCLK/nPCLK Input Driven by a CML Driver 3.3V 3.3V 3.3V R3 125Ω R4 125Ω Zo = 50Ω PCLK Zo = 50Ω nPCLK LVPECL Input LVPECL R1 84Ω R2 84Ω Figure 2D. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple Figure 2C. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V Zo = 50 PCLK R1 100 Zo = 50 LVDS nPCLK LVPECL Input Figure 2E. PCLK/nPCLK Input Driven by a 3.3V LVDS Driver IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 11 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER 2.5V LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, LVDS, CML and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the PCLK/ nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V 2.5V 2.5V PCLK PCLK nPCLK nPCLK CML LVPECL CML Built-In Pullup LVPECL Input Input Figure 3B. PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver Figure 3A. PCLK/nPCLK Input Driven by a CML Driver 2.5V 2.5V 2.5V PCLK nPCLK LVPECL Input LVPECL Figure 3D. PCLK/nPCLK Input Driven by a 2.5V LVPECL Driver with AC Couple Figure 3C. PCLK/nPCLK Input Driven by a 2.5V LVPECL Driver PCLK nPCLK Figure 3E. PCLK/nPCLK Input Driven by a 2.5V LVDS Driver IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 12 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Recommendations for Unused Output Pins Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 13 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are a low impedance follower output that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ LVPECL Input Zo = 50 R1 84 Figure 5A. 3.3V LVPECL Output Termination IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 R2 84 Figure 5B. 3.3V LVPECL Output Termination 14 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Termination for 2.5V LVPECL Outputs level. The R3 in Figure 6B can be eliminated and the termination is shown in Figure 6C. Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250Ω 50Ω R3 250Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50Ω 2.5V LVPECL Driver R2 62.5Ω R2 50Ω R4 62.5Ω R3 18Ω Figure 6A. 2.5V LVPECL Driver Termination Example Figure 6B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50Ω R2 50Ω Figure 6C. 2.5V LVPECL Driver Termination Example IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 15 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the IDT8SLVP1104I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the IDT8SLVP1104I is the sum of the core power plus the power dissipated due to loading. The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading. The maximum current at 85° is as follows: IEE_MAX = 60mA • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 60mA = 207.9mW • Power (outputs)MAX = 33.2mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 33.2mW = 132.8mW Total Power_MAX (3.465V, with all outputs switching) = 207.9mW + 132.8mW = 340.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 74.7°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.341W * 74.7°C/W = 110.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 5. Thermal Resistance JA for 16-Lead VFQFN, Forced Convection JA by Velocity Meters per Second 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 74.7°C/W 65.3°C/W 58.5°C/W IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 16 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 7. VCC Q1 VOUT RL VCC - 2V Figure 7. LVPECL Driver Circuit and Termination To calculate power dissipation due to loading, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V. These are typical calculations. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.7V (VCC_MAX – VOH_MAX) = 0.7V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.5V (VCC_MAX – VOL_MAX) = 1.5V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.7V)/50] * 0.7V = 18.2mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.5V)/50] * 1.5V = 15mW Total Power Dissipation per output pair = Pd_H + Pd_L = 33.2mW IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 17 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Reliability Information Table 6. JA vs. Air Flow Table for a 16-Lead VFQFN JA at 0 Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 74.7°C/W 65.3°C/W 58.5°C/W Transistor Count The transistor count for the IDT8SLVP1104I is: 258 IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 18 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER 16-Lead VFQFN Package Outline and Package Dimensions IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 19 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Ordering Information Table 7. Ordering Information Part/Order Number 8SLVP1104ANLGI 8SLVP1104ANLGI8 Marking 104AI 104AI IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 Package “Lead-Free” 16-Lead VFQFN “Lead-Free” 16-Lead VFQFN 20 Shipping Packaging Tube Tape & Reel Temperature -40C to 85C -40C to 85C ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER Revision History Sheet Rev Table Page A T7 20 Description of Change Date Ordering Info: Changed Tray to Tube. IDT8SLVP1104ANLGI REVISION A FEBRUARY 25, 2014 21 2/25/2014 ©2014 Integrated Device Technology, Inc. IDT8SLVP1104I Data Sheet LOW PHASE NOISE, 1:4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support Sales [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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