Order this document by MC145166/D SEMICONDUCTOR TECHNICAL DATA CMOS These devices are dual phase–locked loop (PLL) frequency synthesizers in– tended for use primarily in 46/49 MHz cordless phones with up to 10 channels. These parts contain two mask–programmable counter ROMs for receive and transmit loops with two independent phase detect circuits. A common reference oscillator and reference divider are shared by the receive and transmit circuits. Frequency selection is accomplished via a 4–bit parallel input for the MC145166. The MC145167 utilizes a serial interface. Other features include a lock detect circuit for the transmit loop, illegal code default, and a 5 kHz tone output. • • • • • • • • • Synthesizes Up to Ten Channel Pairs Maximum Operating Frequency: 60 MHz @ Vin = 200 mV p–p Operating Temperature Range: – 40 to + 75°C Operating Voltage Range: 2.5 to 5.5 V On–Chip Oscillator Circuit Supports External Crystal Lock Detect Signal Operating Power Consumption: 3.0 mA @ 3.0 V Standby Mode for Power Savings: 1.5 mA @ 3.0 V Also See MC145162 P SUFFIX PLASTIC DIP CASE 648 16 1 DW SUFFIX SOG PACKAGE CASE 751G 16 1 ORDERING INFORMATION MC145166P Plastic DIP MC145166DW SOG Package MC145167P Plastic DIP MC145167DW SOG Package PIN ASSIGNMENTS MC145166P MC145166DW OSCout 1 16 OSCin MODE 2 15 VDD SB 3 14 fin1 5k 4 13 PD1 D0 5 12 VSS D1 6 11 PD2 D2 7 10 LD D3 8 9 fin2 MC145167P MC145167DW OSCout 1 16 OSCin MODE 2 15 VDD SB 3 14 fin1 5k 4 13 PD1 DATA 5 12 VSS CLK 6 11 PD2 NC 7 10 LD ENB 8 9 fin2 NC = NO CONNECTION REV 2 1/98 TN98011400 Motorola, Inc. 1998 MOTOROLA MC145166•MC145167 1 BLOCK DIAGRAM fv = 5 kHz PHASE DET 1 13–BIT DIVIDE–BY–N RECEIVE COUNTER fin1 PD1 fr 13 VDD RECEIVE ROM LOCK DET TRANSMIT ROM SB LD * 14 14–BIT DIVIDE–BY–N TRANSMIT COUNTER fin2 PHASE DET 2 fv PD2 OSCin MODE * REFERENCE COUNTER DIVIDE–BY–2048 OSCout 5 kHz fr * D0 D1 MC145166 ONLY * DECODE LOGIC D2 * D3 5k 4–BIT LATCH ENB VSS CLK 4–BIT S/R * On–chip pull–down. DATA MC145167 ONLY MC145166•MC145167 2 MOTOROLA MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Vin Iin, Iout IDD, ISS Tstg Rating Value Unit – 0.5 to + 6.0 V – 0.5 to VDD + 0.5 V DC Current Drain Per Pin 10 mA DC Current Drain VDD or VSS Pins 30 mA – 65 to + 150 °C DC Supply Voltage Input Voltage, All Inputs Storage Temperature Range This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA = 25°C) Guaranteed Limit S b l Symbol Ch Characteristic i i VDD Power Supply Voltage Range VOL Output Voltage (Iout = 0) VDD Min Max U i Unit — 2.5 5.5 V 0 Level 2.5 5.5 — — 0.05 0.05 V 1 Level 2.5 5.5 2.45 5.45 — — 0 Level 2.5 5.5 — — 0.75 1.65 1 Level 2.5 5.5 1.75 3.85 — — (Vout = 2.2 V) (Vout = 5.0 V) Source 2.5 5.5 – 0.18 – 0.55 — — (Vout = 0.3 V) (Vout = 0.5 V) Sink 2.5 5.5 0.18 0.55 — — OSCin, fin1, fin2 2.5 5.5 — — – 30 – 66 DATA, SB, Mode 2.5 5.5 — — – 0.05 – 0.11 OSCin, fin1, fin2 2.5 5.5 — — 30 66 DATA, SB, Mode 2.5 5.5 — — 50 121 Input Capacitance — — 14.0 pF Cout Output Capacitance — — 8.0 pF IDD Standby Current, SB = VSS or Open 2.5 5.5 — — 1.4 3.6 mA Idd Operating Current (200 mV p–p input at fin1 and fin2, SB = VDD) 2.5 5.5 — — 2.8 6.2 mA IOZ Three–State Leakage Current (Vout = 0 or 5.5 V) 5.5 — ± 1.0 µA VOH VIL (Vin = VDD or 0) Input Voltage (Vout = 0.5 V or VDD – 0.5 V) VIH IOH Output Current IOL IIL IIH Cin MOTOROLA Input Current (Vin = 0) (Vin = VDD – 0.5) V mA µA µA MC145166•MC145167 3 SWITCHING CHARACTERISTICS (TA = 25°C, CL = 50 pF) S b l Symbol Figure No. Ch Characteristic i i Guaranteed Limit VDD Min Max U i Unit tTLH Output Rise Time 1, 5 3.0 5.0 — — 200 100 ns tTHL Output Fall Time 1, 5 3.0 5.0 — — 200 100 ns tr, tf Input Rise and Fall Time, OSCin 2 3.0 5.0 — — 5.0 4.0 µs fmax Input Frequency Input = Sine Wave 200 mV p–p 3.0 – 5.0 3.0 – 5.0 3.0 – 5.0 — — — 12 60 60 MHz 3.0 5.0 100 50 — — ns 3.0 5.0 200 100 — — tsu Setup Time (MC145167) OSCin fin1 fin2 DATA to CLK 3 ENB to CLK th trec tw Hold Time (MC145167), CLK to DATA 3 3.0 5.0 80 40 — — ns Recovery Time (MC145167), ENB to CLK 3 3.0 5.0 80 40 — — ns Input Pulse Width (MC145167), CLK and ENB 4 3.0 5.0 80 60 — — ns MC145166•MC145167 4 MOTOROLA SWITCHING WAVEFORMS tr tTHL tTLH ANY OUTPUT 90% OSCin, fin 10% tf 90% 10% Figure 1. DATA D3 D2 D1 D0 th tsu CLK Figure 2. 50% FIRST CLK FIRST CLK LAST CLK tsu trec 50% ENB Figure 3. PREVIOUS DATA LATCHED tw ENB, CLK 50% Figure 4. MOTOROLA MC145166•MC145167 5 PIN DESCRIPTIONS INPUT PINS OSCin/OSCout Reference Oscillator Input/Output (Pins 1,16) These pins form a reference oscillator when connected to an external parallel–resonant crystal. For a 46/49 MHz cordless phone application, a 10.24 MHz crystal is needed. OSC in may also serve as input for an externally generated reference signal. This signal is typically ac coupled to OSC in, but for larger amplitude signals (standard CMOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required for OSC out . CLK, DATA Clock, Data (MC145167 — Pins 5, 6) These pins provide the BCD input by using serial channel programming instead of parallel. Logical high represents a 1. Each low–to–high transition of the clock shifts one bit of data into the on–chip shift register. ENB Enable (MC145167 — Pin 8) The enable pin controls the data transfer from the shift register to the 4–bit latch. A positive pulse latches the data. OUTPUT PINS MODE Mode Select (Pin 2) 5k 5 kHz Tone Signals (Pin 4) Mode is for determining whether the part is to be used in the base or handset of a cordless phone. Internally, this pin is used in the decoding logic for selecting the ROM address. When high, the device is set in the base mode, and when low, it is set in the handset mode. This input has an internal pull–down device. The 5 kHz tone signals are N–channel, open–drain outputs derived from the reference oscillator. SB Standby Input (Pin 3) The standby pin is used to save power when not transmitting. When high, both the transmit and receive loops are in operation. When low, the transmit loop is disabled, thereby reducing power consumption. This input has an internal pull– down device. D0 – D3 Data Inputs (MC145166 — Pins 5 – 8) These inputs provide the BCD code for selecting the one of ten channels to be locked in both the transmit and receive loop. When address data other than 1 – 10 are input, the decoding logic defaults to channel 10. The frequency assignments with reference to Mode and D0 – D3 are shown in Table 1. These inputs have internal pull–down devices. fin1, fin2 Frequency Inputs (Pins 14, 9) fin1 and fin2 are inputs to the divide–by–N receive and transmit counters, respectively. These signals are typically derived from the loop VCO and are ac coupled. For larger amplitude signals (standard CMOS logic levels), dc coupling may be used. The minimum input level is 200 mV p–p. MC145166•MC145167 6 LD Lock Detect Signal (Pin 10) The lock detect signal is associated with the transmit loop. The lock output goes high to indicate an out–of–lock condition. This is a P–channel open–drain output. PD1, PD2 Phase Detector Outputs (Pins 13, 11) These are three–state outputs of the transmit and receive phase detectors for use as loop error signals. Phase detector gain is VDD/4 π volts per radian. Frequency fv > fr or fv leading: Output = Negative pulses Frequency fv < fr or fv lagging: Output = Positive pulses Frequency fv = fr and phase coincidence: Output = High– impedance state POWER SUPPLY VSS Negative Power Supply (Pin 12) This pin is the negative supply potential and is usually ground. VDD Positive Power Supply (Pin 15) This pin is the positive supply potential and may range from + 2.5 to + 5.5 V with respect to VSS. MOTOROLA Table 1. MC145166/67 Divide Ratios and VCO Frequencies Handset (Mode = 0) Channels Transmit D3 D2 D1 D0 CH# fin2 (MHz) 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970 Base (Mode = 1) Receive N 9934 9969 9972 9954 9975 9966 9978 9986 9998 9994 fin1 (MHz) 35.915 35.935 35.975 36.015 36.035 36.075 36.135 36.175 36.235 36.275 Transmit N 7183 7187 7195 7203 7207 7215 7227 7235 7247 7255 fin2 (MHz) 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970 Receive N 9322 9326 9334 9342 9346 9354 9366 9374 9386 9394 fin1 (MHz) 38.975 39.150 39.165 39.075 39.180 39.135 39.195 39.235 39.295 39.275 N 7795 7830 7833 7815 7836 7827 7839 7847 7859 7855 NOTES: 1. Other input combinations will be defaulted to channel 10. 2. 0 = logic low, 1 = logic high. MOTOROLA MC145166•MC145167 7 VCC (3.6 V) 1.2 kΩ 0.01 µF 1 kΩ 10 µF 12 pF 0.01 µF TO 1ST MIXER 68 kΩ 39 kΩ 27 pF MPS9426C 100 kΩ 2.7 kΩ 68 pF 47 pF 8 pF 3.3 kΩ 33 pF 47 kΩ 1N5462A 1 µF MPS9426C 10 pF 10.24 MHz 3 pF 1 TO 2ND MIXER OSCout V+ 15 6 7 8 12 fin1 PD1 VDD D0 D1 OSCin MC145166 PD2 LD D2 16 14 13 11 10 9 fin2 D3 VSS V+ LOCK DETECT (LD) 10 pF 1 kΩ ENABLE 1 kΩ 0.01 µF 0.01 µF 39 kΩ 10 µF 2.7 kΩ 10 pF TO PIN 1 OF MC2831A 100 kΩ 27 pF RF Tx AMP 33 pF 100 kΩ 47 pF 47 kW 8 pF 3.3 kΩ MPS9426C 1 µF 33 pF MPS9426C 1N5462A Figure 5. MC145166 Circuit Example MC145166•MC145167 8 MOTOROLA Figure 6. DPLL Application in 46/49 MHz Cordless Phone MOTOROLA MC145166•MC145167 9 FILTER RF 46.610 MHz Rx Tx FILTER DC VCO 46.610 MHz 49.670 MHz OSC in AMP f in –T 1ST MIX DIALING MIC 10.24 MHz OSC out f in–R 38.975 MHz VCO BUF RF 2ND MIX AMP OSC AMP 10.24 MHz 10.695 MHz MODE D3 D2 D1 D0 ROM PROG B PRESCALER 14 BITS PROG A PRESCALER REF COUNTER 11 BITS 0.455 MHz VSS 5 kHz 5 kHz 5 kHz MC145166 V DD LOCK DET PHASE DET B PHASE DET A LD PD–T 5 kHz PD–R LP FILTER LP FILTER PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP CASE 648–08 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 DW SUFFIX SOG PACKAGE CASE 751G–02 –A– 16 9 –B– 8X P 0.010 (0.25) 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. M B M 8 16X J D 0.010 (0.25) M T A S B S F R X 45 _ C –T– 14X G MC145166•MC145167 10 K SEATING PLANE M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 MOTOROLA Motorola reserves the right to make changes without further notice to any products herein. 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