Features • High-performance, Low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller • Non-volatile Program and Data Memories • • • • • – 16K - 128KBytes of In-System Self-Programmable Flash – 4K - 8KBytes Boot Code Section with Independent Lock Bits – 1K - 2KBytes EEPROM – 2K - 8KBytes Internal SRAM Peripheral Features – Four-channel DMA Controller – Eight-channel Event System – Five 16-bit Timer/Counters Three Timer/Counters with 4 Output Compare or Input Capture channels Two Timer/Counters with 2 Output Compare or Input Capture channels High-Resolution Extensions on all Timer/Counters Advanced Waveform Extension on one Timer/Counter – One USB device Interface USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant 32 Endpoints with full configuration flexibility – Five USARTs with IrDA support for one USART – Two Two-Wire Interfaces with dual address match (I2C and SMBus compatible) – Two Serial Peripheral Interfaces (SPIs) – AES and DES Crypto Engine – CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) Generator – 16-bit Real Time Counter with Separate Oscillator – One Twelve-channel, 12-bit, 2MSPS Analog to Digital Converter – One Two-channel, 12-bit, 1MSPS Digital to Analog Converter – Two Analog Comparators with Window compare function, and current source feature – External Interrupts on all General Purpose I/O pins – Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator – QTouch® library support Capacitive touch buttons, sliders and wheels Up to 64 sense channels Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal and External Clock Options with PLL and Prescaler – Programmable Multi-level Interrupt Controller – Five Sleep Modes – Programming and Debug Interfaces PDI (Program and Debug Interface) I/O and Packages – 34 Programmable I/O Pins – 44 - lead TQFP – 44 - pad VQFN/QFN – 49 - ball VFBGA Operating Voltage – 1.6 – 3.6V Operating Frequency – 0 – 12MHz from 1.6V – 0 – 32MHz from 2.7V 8/16-bit Atmel XMEGA A4U Microcontroller ATxmega128A4U ATxmega64A4U ATxmega32A4U ATxmega16A4U Preliminary Typical Applications • • • • • Industrial control Factory automation Building control Board control White Goods • • • • • Climate control RF and ZigBee USB Connectivity Sensor control Optical • • • • • Low power battery applications Power tools HVAC Utility Metering Medical Applications 8387A–AVR–07/11 XMEGA A4U 1. Ordering Information Ordering Code Flash (Bytes) EEPROM (Bytes) SRAM (Bytes) ATxmega128A4U-AU 128K + 8K 2K 8K ATxmega64A4U-AU 64K + 4K 2K 4K ATxmega32A4U-AU 32K + 4K 1K 4K ATxmega16A4U-AU 16K + 4K 1K 2K ATxmega128A4U-MH 128K + 8K 2K 8K ATxmega64A4U-MH 64K + 4K 2K 4K ATxmega32A4U-MH 32K + 4K 1K 4K ATxmega16A4U-MH 16K + 4K 1K 2K ATxmega128A4U-CU 128K + 8K 2K 8K ATxmega64A4U-CU 64K + 4K 2K 4K ATxmega32A4U-CU 32K + 4K 1K 4K ATxmega16A4U-CU 16K + 4K 1K 2K Notes: Speed (MHz) Power Supply Package(1)(2)(3) Temp 44A 32 1.6 - 3.6V 44M1 -40°C - 85°C 49C2 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For packaging information see ”Packaging information” on page 61. Package Type 44A 44-Lead, 10 x 10mm Body Size, 1.0mm Body Thickness, 0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 44M1 44-Pad, 7x7x1mm Body, Lead Pitch 0.50mm, 5.20mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad No Lead Package (VQFN) 49C2 49-Ball (7 x 7 Array), 0.65mm Pitch, 5.0 x 5.0 x 1.0mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) 2 8387A–AVR–07/11 XMEGA A4U 2. Pinout/Block Diagram Block Diagram and QFN/TQFP pinout PR1 PR0 RESET/PDI PDI 37 36 35 34 AVCC 39 GND PA0 40 38 PA1 41 General Purpose I/O PA2 Analog function 42 External clock / Crystal pins PA3 Digital function 43 Programming, debug, test PA4 Power / Ground 44 Figure 2-1. Port R PA6 2 PA7 3 PB0 4 PB1 5 PB2 6 PB3 7 DATA BUS Port A 1 OSC/CLK Control Watchdog Crypto / CRC Power Supervision Real Time Counter Watchdog Timer Reset Controller Sleep Controller Event System Controller Interrupt Controller OCD Prog/Debug Interface AREF ADC AC0:1 Port B PA5 BUS matrix TEMPREF AREF DAC DMA Controller CPU VREF FLASH GND EEPROM 33 PE3 32 PE2 31 VCC 30 GND 29 PE1 28 PE0 27 PD7 26 PD6 25 PD5 24 PD4 23 PD3 SRAM 8 DATA BUS Note: TWI TC0 USART0 USB SPI USART0:1 13 14 15 16 17 18 19 20 21 22 PC3 PC4 PC5 PC6 PC7 GND VDD PD0 PD1 PD2 Port E 12 Port D PC2 Port C TC0:1 11 TWI PC1 SPI 10 TC0:1 PC0 EVENT ROUTING NETWORK USART0:1 9 IRCOM VCC For full details on pinout and pin functions refer to ”Pinout and Pin Functions” on page 51. 3 8387A–AVR–07/11 XMEGA A4U Figure 2-2. BGA pinout Top view 1 Table 2-1. 2 3 4 5 Bottom view 6 7 7 6 5 4 3 2 1 A A B B C C D D E E F F G G BGA pinout 1 2 3 4 5 6 PA3 AVCC GND PR1 PR0 PDI_DATA PE3 PA4 PA1 PA0 GND RESET/ PDI_CLK PE2 VCC C PA5 PA2 PA6 PA7 GND PE1 GND D PB1 PB2 PB3 PB0 GND PD7 PE0 E GND GND PC3 GND PD4 PD5 PD6 F VCC PC0 PC4 PC6 PD0 PD1 PD3 G PC1 PC2 PC5 PC7 GND VCC PD2 A B 4 8387A–AVR–07/11 XMEGA A4U 3. Overview The Atmel® AVR® XMEGA® is a family of low power, high performance and peripheral rich 8/16bit microcontrollers based on the AVR® enhanced RISC architecture. By executing instructions in a single clock cycle, AVR achieves throughputs CPU approaching 1Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed. Atmel AVR CPU combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The XMEGA A4U devices provide the following features: In-System Programmable Flash with Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller, eight-channel Event System, Programmable Multi-level Interrupt Controller, 34 general purpose I/Opins, 16-bit Real Time Counter, five flexible 16-bit Timer/Counters with compare and PWM channels, one USB 2.0 full speed (12Mbps) Device Interface, five USARTs, two Two Wire Serial Interfaces (TWIs), two Serial Peripheral Interfaces (SPIs), AES and DES crypto engine, one Twelve-channel, 12-bit ADC with optional differential input with programmable gain, one Twochannel 12-bit DAC, two analog comparators with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate internal oscillators with PLL and prescaler and programmable Brown-Out Detection. The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging, is available. All XMEGA devices have five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and all peripherals to continue functioning. The Power-down mode saves the SRAM and register contents but stops the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is sleeping. This allows very fast start-up from external crystal combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in Active mode and Idle sleep mode. Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The device is manufactured using Atmel's high-density nonvolatile memory technology. The program Flash memory can be reprogrammed in-system through the PDI. A Bootloader running in the device can use any interface to download the application program to the Flash memory. The Bootloader software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A4U is a powerful microcontroller family that provides a highly flexible and cost effective solution for embedded applications. 5 8387A–AVR–07/11 XMEGA A4U The Atmel® AVR® XMEGA® devices are supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. 3.1 Block Diagram Figure 3-1. XMEGA A4U Block Diagram PR[0..1] Digital function Programming, debug, test Analog function Oscillator/Crystal/Clock XTAL1/ TOSC1 General Purpose I/O XTAL2/ TOSC2 Oscillator Circuits/ Clock Generation PORT R (2) Real Time Counter DATA BUS PA[0..7] PORT A (8) Watchdog Timer Event System Controller Oscillator Control SRAM ACA DMA Controller ADCA AREFA Watchdog Oscillator Sleep Controller Prog/Debug Controller BUS Matrix Power Supervision POR/BOD & RESET PDI VCC GND RESET/ PDI_CLK PDI_DATA Int. Refs. AES Tempref OCD AREFB DES PORT B (8) CRC Interrupt Controller CPU PB[0..7] DACB NVM Controller Flash IRCOM EEPROM DATA BUS PORT D (8) TWIE TCE0 USARTE0 USB SPID TCD0:1 USARTD0:1 SPIC PORT C (8) TWIC TCC0:1 USARTC0:1 EVENT ROUTING NETWORK PORT E (4) TOSC1 (optional) TOSC2 (optional) PC[0..7] PD[0..7] PE[0..3] 6 8387A–AVR–07/11 XMEGA A4U 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading • XMEGA® AU Manual • XMEGA Application Notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA AU Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals. All documentations are available from www.atmel.com/avr. 5. Capacitive touch sensing The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR® microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS™) technology for unambiguous detection of key events. The QTouch Library includes support for the QTouch and QMatrix® acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website. 7 8387A–AVR–07/11 XMEGA A4U 6. AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 142 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in SRAM • Stack Pointer accessible in I/O memory space • Direct addressing of up to 16Mbytes of program and 16Mbytes of data memory • True 16/24-bit access to 16/24-bit I/O registers • Support for 8-, 16- and 32-bit Arithmetic • Configuration Change Protection of system critical features 6.2 Overview The Atmel® AVR® XMEGA® devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program from the FLASH memory. Interrupt handling is described in a separate section, refer to ”Interrupts and Programmable Multi-level Interrupt Controller” on page 26. Figure 6-1 on page 8 shows the CPU block diagram of the AVR CPU architecture. Figure 6-1. Block Diagram of the AVR CPU architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruc- 8 8387A–AVR–07/11 XMEGA A4U tion is pre-fetched from the Program Memory. This enables instructions to be executed in every clock cycle. The program memory is In-System Self-Programmable Flash memory. 6.3 ALU - Arithmetic Logic Unit The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed. The ALU operates in direct connection with all the 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored back in the Register File. After an arithmetic or logic operation, the Status Register is updated to reflect information about the result of the operation. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format. 6.4 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to be fetched. After a reset, the PC is set to location ‘0’. Program flow is provided by conditional and unconditional jump and call instructions, capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number uses a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack is allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU. 6.5 Register File The Register File consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The Register File supports the following input/output schemes: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing - enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash program memory. 9 8387A–AVR–07/11 XMEGA A4U 7. Memories 7.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section for application code or bootloader code – Separate read/write protection lock bits for all sections – CRC Generator support for CRC check of a selectable flash program memory section • Data Memory – One linear address space – Single cycle access from CPU – SRAM – EEPROM Byte and page accessible Optional memory mapping for direct load and store – I/O Memory Configuration and Status registers for all peripherals and modules 16bit-accessible General Purpose Register for global variables or flags – Bus arbitration Safe and deterministic handling of priority between CPU, DMA Controller, and other bus masters – Separate buses for SRAM, EEPROM, and I/O Memory Simultaneous bus access for CPU and DMA Controller • Production Signature Row Memory for factory programmed data – ID for each microcontroller device type – Serial number for each device – Calibration bytes for factory calibrated peripherals • User Signature Row – One flash page in size – Can be read and written from software – Content is kept after chip erase 7.2 Overview The Atmel® AVR® architecture has two main memory spaces, the Program Memory and the Data Memory. Executable code can only reside in the Program Memory, while data can be stored both in the Program Memory and the Data Memory. The Data Memory includes both SRAM, and EEPROM Memory for nonvolatile data storage. All memory spaces are linear and require no memory bank switching. The available memory size configurations are shown in ”Ordering Information” on page 2. In addition each device has a Flash memory signature row for calibration data, device identification, serial number etc. Non Volatile Memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software. 10 8387A–AVR–07/11 XMEGA A4U 7.3 Flash Program Memory The Atmel® AVR® XMEGA® devices contain On-chip In-System Reprogrammable Flash memory for program storage. The Flash memory can be accessed for read and write both from an external programmer through the PDI, or from application software running in the device. All AVR instructions are 16- or 32-bit wide, each Flash address location is 16-bit. The Flash memory is organized in two main sections, the Application Section and the Boot Loader section. The size of the different sections are fixed, but device dependent. These two sections have separate lock bits and can have different levels of protection. The Store Program Memory (SPM) instruction, used to write to the Flash from the application software, will only operate when executed from the Boot Loader Section. The Application Section contains an Application Table Section with separate lock settings. This enables safe storage of Non-volatile data in the Program Memory. Figure 7-1. Flash Program Memory (Hexadecimal address) Word Address 0 Application Section (Bytes) (128K/64K/32K/16K) ... EFFF / 77FF / 37FF / 17FF F000 / 7800 / 3800 / 1800 FFFF / 7FFF / 3FFF / 1FFF 10000 / 8000 / 4000 / 2000 10FFF / 87FF / 47FF / 27FF Application Table Section (Bytes) (4K/4K/4K/4K) Boot Section (Bytes) (8K/4K/4K/4K) The Application Table Section and Boot Section can also be used for general application software. 7.4 Data Memory The Data memory contains the I/O Memory, internal SRAM, optionally memory mapped EEPROM, and external memory if available. The data memory is organized as one continuous memory section, see Figure 7-2 on page 12. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all XMEGA devices. 11 8387A–AVR–07/11 XMEGA A4U Figure 7-2. Data Memory Map (Hexadecimal address) Byte Address 0 FFF ATxmega64A4U I/O Registers (4 KB) 1000 EEPROM (2K) 17FF Byte Address 0 FFF 1000 13FF RESERVED 2000 2FFF Internal SRAM (4K) ATxmega32A4U I/O Registers (4 KB) EEPROM (1K) Byte Address 0 FFF 1000 13FF RESERVED 2000 2FFF Internal SRAM (4K) ATxmega16A4U I/O Registers (4 KB) EEPROM (1K) RESERVED 2000 27FF Byte Address 0 FFF 1000 17FF Internal SRAM (2K) ATxmega128A4U I/O Registers (4 KB) EEPROM (2K) RESERVED 2000 3FFF 7.4.1 Internal SRAM (8K) I/O Memory The Status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which is used to transfer data between the 32 registers in the Register File and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. In the address range 0x00 - 0x1F, single- cycle instructions for manipulation and checking of individual bits are available. The I/O memory address for all peripherals and modules in XMEGA A4U is shown in the ”Peripheral Module Address Map” on page 56. 7.4.2 SRAM Data Memory The devices have internal SRAM memory for data storage. 7.4.3 EEPROM Data Memory The devices have internal EEPROM memory for non-volatile data storage. It is addressable either in a separate data space or it can be memory mapped into the normal data memory space. The EEPROM memory supports both byte and page access. 7.5 Production Signature Row The Production Signature Row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. 12 8387A–AVR–07/11 XMEGA A4U The production signature row also contains an ID that identifies each microcontroller device type, and a serial number that is unique for each manufactured device. The device ID for the devices is shown in Table 7-1 on page 13. The serial number consists of the production LOT number, wafer number, and wafer coordinates for the device. The production signature row can not be written or erased, but it can be read from both application software and external programming. Table 7-1. Device ID bytes for XMEGA A4U devices. Device 7.6 Device ID bytes Byte 2 Byte 1 Byte 0 ATxmega16A4U 41 94 1E ATxmega32A4U 41 95 1E ATxmega64A4U 46 96 1E ATxmega128A4U 46 97 1E User Signature Row The User Signature Row is a separate memory section that is fully accessible (read and write) from application software and external programming. It is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial numbers or identification numbers, random number seeds etc. This section is not erased by Chip Erase commands that erase the Flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase session and on-chip debug sessions. 13 8387A–AVR–07/11 XMEGA A4U 7.7 Flash and EEPROM Page Size The Flash Program Memory and EEPROM data memory are organized in pages. The pages are word accessible for the Flash and byte accessible for the EEPROM. Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address bits (FWORD) give the word in the page. Table 7-2. Devices Flash Page Size Size (words) Number of words and Pages in the Flash. FWORD FPAGE Application Size Boot No of Pages Size No of Pages ATxmega16A4U 16K + 4K 128 Z[6:0] Z[13:7] 16K 64 4K 16 ATxmega32A4U 32K + 4K 128 Z[6:0] Z[14:7] 32K 128 4K 16 ATxmega64A4U 64K + 4K 128 Z[6:0] Z[15:7] 64K 256 4K 16 ATxmega128A4U 128K + 8K 128 Z[8:0] Z[16:7] 128K 512 8K 32 Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA A4U devices. EEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Table 7-3. Devices Number of Bytes and Pages in the EEPROM. EEPROM Page Size Size (Bytes) E2BYTE E2PAGE No of Pages ATxmega16A4U 1K ATxmega32A4U 1K 32 ADDR[4:0] ADDR[10:5] 32 32 ADDR[4:0] ADDR[10:5] 32 ATxmega64A4U ATxmega128A4U 2K 32 ADDR[4:0] ADDR[10:5] 64 2K 32 ADDR[4:0] ADDR[10:5] 64 14 8387A–AVR–07/11 XMEGA A4U 8. DMAC - Direct Memory Access Controller 8.1 Features • The DMA Controller allows data transfers with minimal CPU intervention • • • • • • • 8.2 – from data memory to data memory – from data memory to peripheral – from peripheral to data memory – from peripheral to peripheral Four DMA Channels with separate – transfer triggers – interrupt vectors – addressing modes Programmable channel priority From 1byte to 16Mbytes of data in a single transaction Multiple addressing modes – Static – Increment – Decrement Optional reload of source and destination address at the end of each – Burst – Block – Transaction Optional Interrupt on end of transaction Optional connection to CRC Generator module for CRC on DMA data Overview The 4-channel Direct Memory Access (DMA) Controller can transfer data between memories and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. The 4 DMA channels enable up to four independent and parallel transfers. The DMA Controller can move data between SRAM and peripherals, between SRAM locations and between peripheral registers directly. With access to all peripherals the DMA Controller can handle automatic transfer of data to/from communication modules, as well as data retrieval from ADC conversions, or data transfer to or from port pins. The DMA Controller can also read from memory mapped EEPROM. Data transfers are done in continues bursts of 1, 2, 4 or 8bytes. They build block transfers of configurable size from 1 to 64Kbytes. A repeat counter can be used to repeat each block transfer for single transactions up to 16Mbytes. Source and destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination address can be done after each burst, block transfer, or when transaction is complete. Application software, peripherals and events can trigger DMA transfers. The four DMA channels have individual configuration and control settings. This include source, destination, transfer triggers and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated both when a transaction is complete or if the DMA Controller detects an error on a DMA channel. To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished and vice versa. 15 8387A–AVR–07/11 XMEGA A4U 9. Event System 9.1 Features • System for direct peripheral to peripheral communication and signaling • Peripherals can directly send, receive and react to peripheral events • • • • 9.2 – CPU and DMA controller independent operation – 100% predictable signal timing – Short and guaranteed response time 8 Event Channels for up to 8 different and parallel signal routines and configurations Events can be sent and/or used by most peripherals, clock system and software Additional functions include – Quadrature Decoders – Digital Filtering of I/O pin change Works in Active mode and Idle sleep mode Overview The Event System is system for direct peripheral to peripheral communication and signaling. It enables the possibility for a change in one peripheral to automatically trigger actions in others peripherals. It is designed for having a predictable system for short and guaranteed response time between peripherals. It is simple and powerful since it allows for autonomous peripheral control and interaction without use of interrupts, CPU or DMA Controller resources. It also enables synchronized timing of actions in several peripheral modules. The change in a peripheral is referred to as an event, and is it usually the same as the interrupt conditions for the peripheral. These events can be directly passed to other peripherals using a dedicated routing network called the Event Routing Network. How events are routed and used by other peripherals is configured in software. Figure 9-1 on page 17 shows a basic block diagram of all connected peripherals. The Event System can directly connect together Analog and Digital converters, Analog Comparators, I/O ports pins, the Real-time Counter, Timer/Counters, IR Communication Module (IRCOM), and USB. It can also be used to trigger DMA transactions (DMA Controller). Events can also be generated from software and the Peripheral Clock. 16 8387A–AVR–07/11 XMEGA A4U Figure 9-1. Event system block diagram CPU / Software DMA Controller Event Routing Network ADC AC clkPER Prescaler Real Time Counter Event System Controller Timer / Counters DAC USB Port pins IRCOM The Event Routing Network consists of eight software configurable multiplexers that control how events are routed and used. This is called Event Channels and it enables up to eight parallel event configurations and routings. The maximum routing latency between two peripherals is two Peripheral clock cycles. The Event System works in both Active mode and Idle sleep mode. 17 8387A–AVR–07/11 XMEGA A4U 10. System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: • • • • • • 10.2 – 32MHz run-time calibrated and tuneable oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz Ultra Low Power (ULP) oscillator with 1kHz output External clock options – 0.4 - 16MHz Crystal Oscillator – 32 kHz Crystal Oscillator – External clock PLL with 20 - 128MHz output frequency – Internal and external clock options and 1 to 31x multiplication – Lock detector Clock Prescalers with 1 to 2048x division Fast peripheral clocks running at 2 and 4 times the CPU clock frequency Automatic Run-Time Calibration of internal oscillators External oscillator and PLL lock failure detection with optional non maskable interrupt Overview The flexible clock system supports a large number of clock sources. It incorporates both accurate internal oscillators, and external crystal oscillators and resonator support. A high frequency Phase Locked Loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available, and can be used for automatic runtime calibration of the internal oscillators to remove frequency drift over voltage and temperate. An Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and switch to internal oscillator if the external oscillator or PLL fails. When a reset occur, all clock sources except 32kHz Ultra Low Power oscillator are disabled. After reset, the device will always start up running from the 2MHz internal oscillator. During normal operation, the System Clock source and prescalers can be changed from software at any time. Figure 10-1 on page 19 presents the principal clock system in the XMEGA. All of the clocks do not need to be active at a given time. The clocks to the CPU and peripherals can be stopped using sleep modes and power reduction registers. 18 8387A–AVR–07/11 XMEGA A4U Figure 10-1. The Clock system, clock sources and clock distribution Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clkPER clkPER2 clkCPU clkPER4 USB clkUSB System Clock Prescalers Brown-out Detector Prescaler Watchdog Timer clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC USBSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32 kHz Int. ULP 32.768 kHz Int. OSC 32.768 kHz TOSC 32 MHz Int. Osc 2 MHz Int. Osc XTAL2 XTAL1 10.3.1 TOSC2 TOSC1 10.3 0.4 – 16 MHz XTAL Clock Options 32kHz Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz Ultra Low Power (ULP) Internal Oscillator is a very low power clock source, and it is not designed for high accuracy. The oscillator employs a built in prescaler providing a 1kHz output. The oscillator is automatically enabled/disabled when used as clock source for any part of the device. This oscillator can be selected as clock source for the RTC. 10.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. A factory-calibrated value is written to the 32.768kHz oscillator calibration register during reset to ensure that the oscillator is runningwithin its specification. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built in prescaler providing both a 32.768kHz output and a 1.024kHz output. 19 8387A–AVR–07/11 XMEGA A4U 10.3.3 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between TOSC1 and TOSC2 pins and enable a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can be used as clock source for the System Clock, RTC and as the DFLL reference clock. 10.3.4 0.4 - 16MHz Crystal Oscillator The 0.4 - 16MHz Crystal Oscillator is a driver intended for driving both external resonators and crystals ranging from 400kHz to 16MHz. 10.3.5 2MHz Run-time Calibrated Internal Oscillator The 2MHz Run-time Calibrated Internal Oscillator is the default system clock source after reset. It is calibrated during production to provide a default frequency which is close to its nominal frequency. A Digital Frequency Looked Loop (DFLL) that can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift to optimize the oscillator accuracy. 10.3.6 32MHz Run-time Calibrated Internal Oscillator The 32MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to provide a default frequency which is close to its nominal frequency. A DFLL that can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift to optimize the oscillator accuracy This oscillator can also be adjusted and calibrated to any frequency between 30 and 55MHz. 10.3.7 External Clock input The external clock input gives the possibility to connect a clock from an external source to XTAL1. 10.3.8 PLL with Multiplication factor 1 - 31x The PLL provides the possibility of multiplying a frequency by any number from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources. 20 8387A–AVR–07/11 XMEGA A4U 11. Power Management and Sleep Modes 11.1 Features • Power management for adjusting power consumption and enabled functions • 5 sleep modes: – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction register to disable clock and turn off unused peripherals in Active and Idle mode 11.2 Overview Various sleep modes and clock gating are implemented in order to tailor power consumption to the application's requirement. This enables the microcontroller to stop unused modules to save power. All sleep modes are available and can be entered from Active mode. In Active mode the CPU is executing application code. When the device enters sleep mode, program execution is stopped and interrupts or reset is used to wake the device again. The application code decides when and what sleep mode to enter. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to Active mode. In addition, Power Reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen and there is no power consumption from that peripheral. This reduces the power consumption in Active mode and Idle sleep mode and enable much more fine-tuned power management than sleep modes alone. 11.3 Sleep Modes 11.3.1 Idle Mode In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the Interrupt Controller, Event System and DMA Controller are kept running. Any enabled interrupt will wake the device. 11.3.2 Power-down Mode In Power-down mode all clocks, including the Real Time Counter clock source are stopped. This only allows operation of asynchronous modules that does not require a running clock. The only interrupts that can wake up the MCU are the Two Wire Interface address match interrupt, asynchronous port interrupts and USB resume interrupt. 11.3.3 Power-save Mode Power-save mode is identical to Power-down, with one exception, if the Real Time Counter (RTC) is enabled, it will keep running during sleep and the device can also wake up from either RTC Overflow or Compare Match interrupt. 21 8387A–AVR–07/11 XMEGA A4U 11.3.4 Standby Mode Standby mode is identical to Power-down with the exception that the enabled system clock sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces the wake-up time. 11.3.5 Extended Standby Mode Extended Standby mode is identical to Power-save mode with the exception that the enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces the wake-up time. 22 8387A–AVR–07/11 XMEGA A4U 12. System Control and Reset 12.1 Features • Reset the microcontroller and set it to its initial state when a reset source goes active • Multiple reset sources that cover different situations – Power-On Reset – External Reset – Watchdog Reset – Brown-Out Reset – PDI reset – Software reset • Asynchronous operation – No running system clock in the device is required for the reset • Reset Status Register for reading the reset source from the application code 12.2 Overview The Reset System issues a microcontroller reset and set the device to its initial state. This is for situation where operation should not start or continue, for example when the microcontroller operates below its power supply rating. If a reset source goes active, the device enters and be kept in reset until all reset sources have released their reset. The I/O pins are immediately tristated. The program counter is set to the Reset Vector location and all I/O registers are set to the initial value. The SRAM content is kept, but not guaranteed. After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the Reset Vector address. By default this is the lowest program memory address, '0', but it is possible to move the Reset Vector to the lowest address in the Boot Section. The reset functionality is asynchronous, so no running system clock is required to reset the device. The software reset feature makes it possible to issue a controlled system reset from the user software. The reset status register has individual status flags for each reset source. It is cleared at Poweron Reset, it shows which sources that have issued a reset since the last power-on. 12.3 12.3.1 Reset Sources Power-On Reset The device is reset when the supply voltage VCC is below the Power-on Reset threshold voltage. 12.3.2 External Reset The device is reset when a low level is present on the RESET pin. 12.3.3 Watchdog Reset The device is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled. The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For more details see ”WDT - Watchdog Timer” on page 25. 23 8387A–AVR–07/11 XMEGA A4U 12.3.4 Brown-Out Reset The device is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable. 12.3.5 PDI reset The MCU can be reset through the Program and Debug Interface (PDI). 12.3.6 Software reset The MCU can be reset by the CPU writing to a special I/O register through a timed sequence. 24 8387A–AVR–07/11 XMEGA A4U 13. WDT - Watchdog Timer 13.0.1 Features • Issues a device reset if the timer is not reset before its timeout period • Asynchronously operation from dedicated oscillator – 1kHz output of the 32kHz Ultra Low Power oscillator • 11 selectable timeout periods, from 8ms to 8s. • Two operation modes – Normal mode – Window mode • Configuration lock to prevent unwanted changes 13.1 Overview The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as run-away or dead-lock code. The WDT is a timer, configured to a predefined timeout period and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller reset. The WDT is reset by executing the WDR (Watchdog Timer Reset) instruction from the application code. The window mode makes it possible to define a time slot window inside the total timeout period where WDT must be reset within. If the WDT is reset too early or too late and outside this window, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error also causes constant WDR execution. The WDT will run in Active mode and all sleep modes if enabled. It is asynchronous and runs from a CPU independent clock source, and will continue to operate to issue a system reset even if the main clocks fail. The Configuration Change Protection mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a fuse for locking the WDT settings is available. 25 8387A–AVR–07/11 XMEGA A4U 14. Interrupts and Programmable Multi-level Interrupt Controller 14.1 Features • Short and predictable interrupt response time • Separate interrupt configuration and vector address for each interrupt • Programmable Multi-level Interrupt Controller – Interrupt prioritizing according to level and vector address – 3 selectable interrupt levels for all interrupts: Low, Medium and High – Selectable round-robin priority scheme within low level interrupts – Non-Maskable Interrupts for critical functions • Interrupt vectors can be moved from the Application Section to the Boot Loader Section 14.2 Overview Atmel® AVR® XMEGA® have a Programmable Multi-level Interrupt Controller (PMIC). Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. The Programmable Multi-level Interrupt Controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed. All peripherals can select between three different priority levels for their interrupts; low, medium and high. Interrupts are prioritized according to their level and their interrupt vector address. Medium level interrupts will interrupt low level interrupt handlers. High level interrupts will interrupt both medium and low level interrupt handlers. Within each level, the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. Low level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. Non-Maskable Interrupts (NMI) is also supported and can be used for critical functions. If a bootloader is used, it is possible to move the interrupt vectors from the Application Section to the Boot Loader Sections so interrupts can be used and executed also during self-programming. 14.3 Interrupt vectors The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the XMEGA A4U devices are shown in Table 14-1 on page 27. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1 on page 27. The program address is the word address. 26 8387A–AVR–07/11 XMEGA A4U Table 14-1. Reset and Interrupt Vectors Program Address (Base Address) Source 0x000 RESET 0x002 OSCF_INT_vect Crystal Oscillator Failure Interrupt vector (NMI) 0x004 PORTC_INT_base Port C Interrupt base 0x008 PORTR_INT_base Port R Interrupt base 0x00C DMA_INT_base DMA Controller Interrupt base 0x014 RTC_INT_base Real Time Counter Interrupt base 0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base 0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base 0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base 0x030 SPIC_INT_vect SPI on port C Interrupt vector 0x032 USARTC0_INT_base USART 0 on port C Interrupt base 0x038 USARTC1_INT_base USART 1 on port C Interrupt base 0x03E AES_INT_vect AES Interrupt vector 0x040 NVM_INT_base Non-Volatile Memory Interrupt base 0x044 PORTB_INT_base Port B Interrupt base 0x056 PORTE_INT_base Port E Interrupt base 0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base 0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base 0x06A TCE1_INT_base Timer/Counter 1 on port E Interrupt base 0x074 USARTE0_INT_base USART 0 on port E Interrupt base 0x080 PORTD_INT_base Port D Interrupt base 0x084 PORTA_INT_base Port A Interrupt base 0x088 ACA_INT_base Analog Comparator on Port A Interrupt base 0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base 0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base 0x0A6 TCD1_INT_base Timer/Counter 1 on port D Interrupt base 0x0AE SPID_INT_vector SPI on port D Interrupt vector 0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base 0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base 0x0FA USB_INT_base USB on port D Interrupt base Interrupt Description 27 8387A–AVR–07/11 XMEGA A4U 15. I/O Ports 15.1 Features • General purpose input and output pins with several and individual configuration options • Output driver with configurable driver and pull settings: • • • • • • • • • • 15.2 – Totem-pole – Wired-AND – Wired-OR – Bus-keeper – Inverted I/O Input with synchronous and/or asynchronous sensing with port interrupts and events – Sense both edges – Sense rising edges – Sense falling edges – Sense low level Optimal pull-up and pull-down resistor on input and Wired-OR/AND configurations Optional slew rate control Asynchronous pin change sensing that can wake-up the device from all sleep modes Two port interrupts with pin masking per I/O port Efficient and safe access to port pins – Hardware read-modify-write through dedicated Toggle/Clear/Set registers – Configuration of multiple pins in a single operation – Mapping of port registers into bit-accessible I/O memory space Peripheral Clocks output on port pin Real Time Counter Clock output to port pin Event Channel output on port pin Remap of digital peripheral pin functions – Selectable USART, SPI and Timer/Counter input/output pin locations Overview One port consists of up to 8 pins ranging from pin 0 to 7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running. All functions are individual and configurable per pin, but several pins can be configured in one single operation. The pins have hardware Read-Modify-Write (RMW) functionality for safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin. The port pin configuration also controls input and output selection of other device function. It is possible to have both the peripheral clock and the real time clock output to a port pin, and available for external use. The same applies to events from the Event System that can be used to synchronize and control external functions. Other digital peripherals such as USART, SPI and Timer/Counters can be remapped to selectable pin location in order to optimize pinout versus application needs. 28 8387A–AVR–07/11 XMEGA A4U 15.3 Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole DIRn OUTn Pn INn 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input) DIRn OUTn Pn INn 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input) DIRn OUTn Pn INn 29 8387A–AVR–07/11 XMEGA A4U 15.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 15-4. I/O configuration - Totem-pole with bus-keeper DIRn OUTn Pn INn 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down OUTn Pn INn Figure 15-6. I/O configuration - Wired-AND with optional pull-up INn Pn OUTn 30 8387A–AVR–07/11 XMEGA A4U 15.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7 on page 31. Figure 15-7. Input sensing system overview Asynchronous sensing EDGE DETECT Interrupt Control IREQ Synchronous sensing Pn Synchronizer INn Q D D INVERTED I/O R Q EDGE DETECT Event R When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 15.5 Alternate Port Functions In addition to the input/output functions on all port pins, most pins have alternate functions. This means that other modules or peripherals connected to the port can use the port pins for their functions, such as communication or pulse-width modulation. ”Pinout and Pin Functions” on page 51 shows which modules on peripherals that enable alternate functions on a pin, and which alternate function is available on a pin. 31 8387A–AVR–07/11 XMEGA A4U 16. T/C - 16-bit Timer/Counter 16.1 Features • Five 16-bit Timer/Counters • • • • • • • • • • • • • 16.2 – Three Timer/Counters of type 0 – Two Timer/Counters of type 1 32-bit Timer/Counter support by cascading two Timer/Counters Up to 3 Compare or Capture (CC) Channels – 3 CC Channels for Timer/Counter of type 0 – 2 CC Channels for Timer/Counter of type 1 Double Buffered Timer Period Setting Double Buffered Compare or Capture Channels Waveform Generation: – Frequency Generation – Single Slope Pulse Width Modulation – Dual Slope Pulse Width Modulation Input Capture: – Input Capture with noise cancelling – Frequency capture – Pulse width capture – 32-bit input capture Timer Overflow and Error interrupts / events One Compare Match or Input Capture interrupt / event per CC Channel Can be used with Event System for – Quadrature Decoding – Count and direction control – Capture Can be used with DMA and trigger DMA transactions High-Resolution Extension – Increases frequency and waveform resolution by 4x (2-bit), or 8x (3-bit) Advanced Waveform Extension – Low and High-side output with programmable Dead-Time Insertion (DTI) Event controlled fault protection for safe disabling of external drivers Overview There are five flexible 16-bit Timer/Counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. Two Timer/Counters can be cascaded to create 32-bit Timer/Counter with optional 32-bit capture. A Timer/Counter consists of a Base Counter and a set of Compare or Capture (CC) channels. The Base Counter can be used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC channels can be used together with the Base Counter to do compare match control, frequency generation and pulse width waveform modulation, or various input capture operations. A Timer/Counter can be configured for either capture or compare functions, and not perform both at the same time. A Timer/Counter can be clocked and timed from the Peripheral Clock with optional prescaling or the Event System. The Event System can also be used for direction control, capture trigger or to synchronize operations. 32 8387A–AVR–07/11 XMEGA A4U Figure 16-1. Overview of a Timer/Counter and closely related peripherals Timer/Counter Base Counter Timer Period Counter Prescaler Control Logic clkPER Event System clkPER4 Buffer Capture Control Waveform Generation Dead-Time Insertion Pattern Generation Fault Protection PORT Comparator AWeX Hi-Res Compare/Capture Channel D Compare/Capture Channel C Compare/Capture Channel B Compare/Capture Channel A The only difference between Timer/Counter type 0 and 1 is the number of CC Channels. Timer/Counter 0 has four CC channels, and Timer/Counter 1 has two CC channels. All information related to CC channel 3 and 4 is only valid for Timer/Counter 0. Some Timer/Counters have extensions to enable more specialized waveform and frequency generation. The Advanced Waveform Extension (AWeX) is intended for motor control and other power control applications. It enables Low- and High Side output with Dead Time Insertion, and fault protection for disabling and shutdown of drivers. It can also generate a synchronized bit pattern across the port pins.See ”Hi-Res - High Resolution Extension” on page 35 for more details. The High Resolution (Hi-Res) extension can be used to increase the waveform output resolution by up to eight times, by using internal clock source running up to four times faster than the Peripheral Clock. See ”AWeX - Advanced Waveform Extension” on page 34 for more details. PORTC and PORTD each has one Timer/Counter 0 and one Timer/Counter1. PORTE has one Timer/Conter0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1 and TCE0, respectively. 33 8387A–AVR–07/11 XMEGA A4U 17. AWeX - Advanced Waveform Extension 17.1 Features • Wafeform output with complementary output from each Compare channel • 4 Dead-Time Insertion (DTI) Units – 8-bit Resolution – Separate High and Low Side Dead-Time Setting – Double Buffered Dead-Time – Optionally halts Timer during Dead-Time Insertion • Pattern Generation unit creating synchronised bit pattern across the port pins – Double buffered pattern generation – Optionally distribution of one Compare channel output across the port pins • Event controlled Fault Protection for instant and predictably fault triggering 17.2 Overview The Advanced Waveform Extension (AWeX) provides extra functions to the Timer/Counter in Waveform Generation (WG) modes. It is primarily intended for different types of motor control and other power control applications. It enables Low- and High Side output with Dead Time Insertion, and fault protection for disabling and shutdown of drivers. It can also generate a synchronized bit pattern across the port pins. Each of the waveform generator outputs from the Timer/Counter 0 are split into a complimentary pair of outputs when any AWeX features are enabled. These output pairs go through a DeadTime Insertion (DTI) unit that generates the non-inverted Low Side (LS) and inverted High Side (HS) of the WG output with dead time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. The Pattern Generation unit can be used to generate a synchronized bit pattern across the port it is connected to. In addition, the WG output from the Compare Channel A can be distributed to and override all the port pins. When the Pattern Generator unit is enabled the DTI unit is bypassed. The Fault Protection unit is connected to the Event System, enabling any event to trigger a fault condition that will disable the AWeX output. The Event System ensure predictable and instant fault reaction, and gives great flexibility in the selection of fault triggers. The AWEX is available for TCC0. The notation of this is AWEXC. 34 8387A–AVR–07/11 XMEGA A4U 18. Hi-Res - High Resolution Extension 18.1 Features • Increases Waveform Generator resolution by up to 8 times (3-bit) • Supports Frequency, Single Slope PWM and Dual Slope PWM generation • Supports the AWeX when this is used for the same Timer/Counter 18.2 Overview The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform generation output by a factor of four or eight. It can be used for a Timer/Counter doing Frequency, Single Slope PWM or Dual Slope PWM generation. It can also be used with the AWeX if this is used for the same Timer/Counter. Atmel® AVR® XMEGA® A4U have three Hi-Res Extensions that each can be enabled for each Timer/Counters pair on PORTC, PORTD and PORTE. The notation of these are HIRESC, HIRESD and HIRESE, respectively. 35 8387A–AVR–07/11 XMEGA A4U 19. RTC - 16-bit Real-Time Counter 19.1 Features • 16-bit resolution • Selectable clock source • • • • • 19.2 – 32.768kHz external crystal – External clock – 32.768kHz internal oscillator – 32kHz internal ULP oscillator Programmable 10-bit clock prescaling One Compare register One Period register Clear Counter on period overflow Optional Interrupt/ Event on overflow and compare match Overview The 16-bit Real Time Counter (RTC) is a counter that typically runs continuously, including in low power sleep modes, to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals. The reference clock is typically the 1.024kHz output from a high accuracy crystal of 32.768kHz, and this is the configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs a higher resolution than 1mS. The RTC can also be clocked from an external clock signal, the internal 32.768kHz oscillator or the internal 32kHz ULP oscillator. The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the Counter. A wide range of resolution and time-out periods can be configured. With a 32.768kHz clock source the maximum resolution of 30.5µs, time-out periods range up to 2000seconds. With a resolution of 1 second, the maximum time-out period is over 18hours (65536seconds). The RTC can give a compare interrupt and/or event when the counter equals the Compare register value, and an overflow interrupt and/event when it equals the Period register value. Figure 19-1. Real Time Counter overview External Clock TOSC1 TOSC2 32.768kHz Crystal Osc 32.768kHz Int. Osc DIV32 DIV32 32kHz int ULP (DIV32) PER RTCSRC clkRTC 10-bit prescaler = TOP/ Overflow = ”match”/ Compare CNT COMP 36 8387A–AVR–07/11 XMEGA A4U 20. USB - Universal Serial Bus Interface 20.1 Features • One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface • Integrated on-chip USB transceiver, no external components needed • 16 endpoint addresses with full endpoint flexibility for up to 32 endpoints • • • • • • • • • • 20.2 – One input endpoint per endpoint address – One output endpoint per endpoint address Endpoint address transfer type selectable to – Control transfers – Interrupt transfers – Bulk transfers – Isochronous transfers Configurable data payload size per endpoint, up to 1023bytes Endpoint configuration and data buffers located in internal SRAM – Configurable location for endpoint configuration data – Configurable location for each endpoint's data buffer Built in Direct Memory Access (DMA) to internal SRAM for – Endpoint configurations – Read and write of endpoint data Ping-Pong operation for higher throughput and double buffered operation – Input and output endpoint data buffers used in a single direction – CPU/DMA controller can update data buffer during transfer Multi-Packet transfer for reduced interrupt load and software intervention – Data payload exceeding max packet size is transferred in one continuous transfer – No interrupts or software interaction on packet transaction level Transaction Complete FIFO for easy flow management when using multiple endpoints – Tracks all completed transactions in a first come, first serve work-queue Clock selection independent of System Clock source selection Connection to Event System On chip debug possibilities during USB transactions Overview The USB interface is an USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface. It supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of 32 endpoints. Each endpoint address is fully configurable and can be configured for any of the four transfer types: control, interrupt, bulk or isochronous. The data payload size is also selectable and it supports data payloads up to 1023bytes. No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for each endpoint address, and the data buffer for each endpoint. The memory locations used for endpoint configurations and data buffers are fully configurable. The amount of memory allocated is fully dynamic according to the number of endpoints in use, and the configuration of these. The USB module has built-in Direct Memory Access (DMA) and will read/write data from/to the SRAM when a USB transaction takes place. To maximise throughput, an endpoint address can be configured for Ping-Pong operation. When this is done, the input and output endpoints are both used in the same direction. The CPU or 37 8387A–AVR–07/11 XMEGA A4U DMA Controller can then read/write one data buffer while the USB module writes/reads the other, and vice versa. This gives double buffered communication. Multi-packet transfer enables a data payload exceeding the maximum packet size of an endpointto be transferred as multiple packets without software intervention. This reduce the CPU intervention and the interrupts needed for USB transfers. For low power operation, the USB module can put the microcontroller in any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resume, the USB module can wake the microcontroller from any sleep mode. PORTD has one USB. Notation of this is USB. 38 8387A–AVR–07/11 XMEGA A4U 21. TWI - Two Wire Interface 21.1 Features • Two Identical Two Wire Interface peripherals • Bi-directional two-wire communication interface • • • • • • • • • 21.2 – Phillips I2C compatible – System Management Bus (SMBus) compatible Bus master and slave operation supported – Slave operation – Single bus master operation – Bus master in multi-master bus environment – Multi-master arbitration Flexible slave address match functions – 7-bit and General Call Address Recognition in Hardware – 10-bit addressing supported – Address mask register for dual address match or address range masking – Optional software address recognition for unlimited number of addresses Slave can operate in all sleep modes Slave address match can wake device from all sleep modes 100kHz and 400kHz bus frequency support Slew-rate limited output drivers Input filter for bus noise and spike suppression Support arbitration between START/Repeated START and Data Bit (SMBus) Slave arbitration allows support for Address Resolve Protocol (ARP) (SMBus) Overview The Two Wire Interface is a bi-directional two-wire communication interface. It is I2C and System Management Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line. The TWI module supports master and slave functionality. The master and slave functionality are separated from each other and can be enabled and configured separately. The master module supports multi-master bus operation and arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. A dedicated address mask register can act as a second address match register or as a register for address range masking. The slave continues to operate in all sleep modes, including Power down mode. This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address matching to let this be handled in software instead. Smart Mode can be enabled to auto trigger operations and reduce software complexity. The TWI module will detect START and STOP conditions, bus collision and bus errors. Arbitration lost, errors, collision and clock hold on the bus is also detected and indicated in separate status flags available in both master and slave mode. It is possible to disable the TWI drivers in the device, and enable a 4-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by the TWI bus. PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE, respectively. 39 8387A–AVR–07/11 XMEGA A4U 22. SPI - Serial Peripheral Interface 22.1 Features • • • • • • • • • 22.2 Two Identical SPI peripherals Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates Interrupt Flag at the End of Transmission Write collision flag to indicate data collision Wake-up from Idle Mode Double Speed Master Mode Overview The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It allows fast communication between an XMEGA device and peripheral devices or other microcontrollers. The SPI supports full duplex communication. A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions, and data is transferred both to and from the device simultaneously. PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID, respectively. 40 8387A–AVR–07/11 XMEGA A4U 23. USART 23.1 Features • Five Identical USART peripherals • Full Duplex Operation • Asynchronous or Synchronous Operation • • • • • • • 23.2 – Synchronous clock rates up to 1/2 o the device clock frequency – Asynchronous clock rates up to 1/8 of the device clock frequency Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits Fractional Baud Rate Generator – Can generate desired baud rate from any system clock frequency – No need for external oscillator with certain frequencies Built in error detection and correction schemes – Odd or Even Parity Generation and Parity Check – Data Over Run and Framing Error Detection – Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter Separate Interrupts for – Transmit Complete – Transmit Data Register Empty – Receive Complete Multi-Processor Communication Mode – Addressing scheme to address a specific devices on a multi-device bus – Enable unaddressed devices to automatically ignore all frames Master SPI Mode – Double Buffered Operation – Configurable Data Order – High Speed Operation up to 1/2 of the peripheral clock frequency IRCOM Module for IrDA compliant pulse modulation/demodulation Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a fast and flexible serial communication module. The USART supports full duplex communication, and both asynchronous and clocked synchronous operation. The USART can also be set in Master SPI mode and be used for SPI communication. Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both direction, enabling continued data transmission without any delay between frames. There are separate interrupts for receive and transmit complete, enabling fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled. The Clock Generation logic has a fractional baud rate generator that is able to generate a wide range of USART baud rates from any system clock frequencies. This remove the need to use an external crystal oscillator with a certain frequency in order to achieve a required baud rate. It also includes support external clock input in synchronous slave operation. One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2kbps. PORTC and PORTD each has two USARTs. PORTE has one USART. Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1 and USARTE0, respectively. 41 8387A–AVR–07/11 XMEGA A4U 24. IRCOM - IR Communication Module 24.1 Features • Pulse modulation/demodulation for infrared communication • IrDA Compatible for baud rates up to 115.2kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed pulse period, 8-bit programmable – Pulse modulation disabled • Built in filtering • Can be connected to and used by one USART at a time 24.2 Overview The Infrared Communication Module (IRCOM) is used for IrDA communication with baud rates up to 115.2kbps. There is one IRCOM available which can be connected to any USART to enable infrared pulse coding/decoding for that USART. 42 8387A–AVR–07/11 XMEGA A4U 25. AES and DES Crypto Engine 25.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) Crypto module • DES Instruction – Encryption and Decryption – Single-cycle DES instruction – Encryption/Decryption in 16 clock cycles per 8-byte block • AES Crypto Module – Encryption and Decryption – Supports 128-bit keys – Supports XOR data load mode to the State memory for Cipher Block Chaining – Encryption/Decryption in 375 clock cycles per 16-byte block 25.2 Overview The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the communication interfaces and the CPU can use these for fast encrypted communication and secure data storage. DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the Register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block. The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must be loaded into the key and state memory in the module before encryption/ decryption is started. It takes 375 Peripheral clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an optional interrupt can be generated. The AES Crypto Module also has DMA support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded. 43 8387A–AVR–07/11 XMEGA A4U 26. CRC - Cyclic Redundancy Check Generator 26.1 Features • Cyclic Redundancy Check (CRC) Generation and Checking for – Communication Data – Program or Data in Flash memory – Data in SRAM memory and I/O memory space • Integrated with Flash memory, DMA Controller and CPU – Continuous CRC on data going through a DMA Channel – Automatic CRC of the complete, or selectable range of the Flash memory – CPU can load data to CRC Generator through I/O interface • CRC polynomial software selectable to – CRC-16 (CRC-CCITT) – CRC-32 (IEEE 802.3) • Zero remainder detection 26.2 Overview A Cyclic Redundancy Check (CRC) is a test algorithm used to detect accidental errors on data, and is commonly used to determine the correctness of a data transmission, data memory and program memory. A CRC takes a data stream or block of data as input and generates a 16- or 32-bit output that can be kept with the data and used as checksum. When the same data is later received or read, the device or application repeats the calculation. If the new CRC calculation does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take corrective action such as requesting the data to be sent again. Typically, an n-bit CRC, applied to a data block of arbitrary length, will detect any single error burst not longer than n bits (in other words, any single alteration that spans no more than n bits of the data), and will detect a fraction 1-2-n of all longer error bursts.The CRC module in XMEGA supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). • CRC-16: Polynomial: x16+x12+x5+1 Hex value: 0x1021 • CRC-32: Polynomial: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1 Hex value: 0x04C11DB7 44 8387A–AVR–07/11 XMEGA A4U 27. ADC - 12-bit Analog to Digital Converter 27.1 Features • One Analog to Digital Converter (ADC) • 12-bit resolution • Up to 2Million Samples Per Second • • • • • • • • • • 27.2 – 4 inputs can be sampled within 1.5µs – Down to 2.5µs conversion time with 8-bit resolution – Down to 3.5µs conversion time with 12-bit resolution Differential and Single-ended input – Up to 16 single-ended inputs – 16x4 differential inputs without gain – 16x4 differential input with gain Built in differential gain stage – 1/2x, 1x, 2x, 4x, 8x, 16x, 32x and 64x gain options Single, continues and scan conversion options 4 internal inputs – Internal Temperature sensor – DAC Output – VCC voltage divided by 10 – 1.1V Bandgap voltage 4 conversion channels with individual input control and result registers – Enable 4 parallel configurations and results Internal and external reference options Compare function for accurate monitoring of user defined thresholds Optional event triggered conversion for accurate timing Optional DMA transfer of conversion results Optional interrupt/event on compare result Overview The Analog to Digital Converter (ADC) converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 2 Million Samples Per Second (MSPS). The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements an optional gain stage is available to increase the dynamic range. In addition several internal signal inputs are available. The ADC can provide both signed and unsigned results. This is a pipelined ADC that consists of several consecutive stages. The pipelined design allows high sample rate at a low System Clock frequency. It also means that a new input can be sampled and a new ADC conversion started while other ADC conversions are still ongoing. This remove dependencies between sample rate and propagation delay. The ADC has four conversion channels (Channel 0-3) with individual input selection, result registers and conversion start control. The ADC can then keep and use four parallel configurations and results, and this will ease use for applications with high data throughput or multiple modules using the ADC independently. It is possible to use DMA to move ADC results directly to memory or peripherals when conversions are done. 45 8387A–AVR–07/11 XMEGA A4U Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the ADC. The output from the DAC, VCC/10 and the Bandgap voltage can also be measured by the ADC. The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required. Figure 27-1. ADC overview ADC0 • • • ADC15 ADC4 • • • ADC7 Int. signals ADC0 • • • ADC3 Int. signals Compare Register Internal signals VINP ADC ½x - 64x Internal signals CH0 Result CH1 Result Threshold (Int Req) CH2 Result CH3 Result VINN Internal 1.00V Internal VCC/1.6V Internal VCC/2 AREFA AREFB < > Reference Voltage Four inputs can be sampled within 1.5µs without any intervention by the application. The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5µs for 12-bit to 2.5µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number). PORTA has one ADC. Notation of this peripheral is ADCA. 46 8387A–AVR–07/11 XMEGA A4U 28. DAC - 12-bit Digital to Analog Converter 28.1 Features • • • • • • • • • • • 28.2 One Digital to Analog Converter (DAC) 12-bit resolution Two independents and continues-time channels per DAC Up to 1Million Samples Per Second conversion rate per DAC channel Built in calibration that removes – Offset error – Gain error Multiple conversion trigger sources – On new available data – Events from the Event System High drive capabilities and support for – Resistive load – Capacitive load – Combined resistive and capacitive load Internal and external reference options DAC output available as input to Analog Comparator and ADC Low Power mode with reduced drive strength Optional DMA transfer of data Overview The Digital to Analog Converter (DAC) converts digital values to voltages. The DAC has two channels, 12-bit resolution, and is capable of converting 1Million Samples Per Second (MSPS) on each channels. The built-in calibration system can remove offset and gain error when loaded with calibration values from software. Figure 28-1. DAC overview DMA req (Data Empty) CH0DATA 12 D A T A DAC0 Output Driver Int. driver AVCC Internal 1.00V AREFA AREFB Reference selection 12 Select CTRLB Trigger CH1DATA DMA req (Data Empty) Trigger D A T A Enable CTRLA Select Enable DAC1 To AC/ADC Internal Output enable Output Driver A DAC conversion is automatically started when new data to be converted is available. Event from the Event System can also be used, and this enable synchronized and timed conversions between the DAC and other peripherals such as a Timer/Counter. The DMA Controller can be used to transfer data to the DAC. The DAC has high drive strengths and is capable of driving both resistive and capacitive loads, and a load which is a combination of this. A low power mode is available, and this will reduce the drive strengths of the output. Both internal and external voltage reference can be used. The DAC output is also internally available for use as input to the Analog Comparator or ADC. PORTB has one DAC. Notation of this peripheral is DACB. 47 8387A–AVR–07/11 XMEGA A4U 29. AC - Analog Comparator 29.1 Features • Two Analog Comparators • Selectable propagation delay vs current consumption • Selectable hysteresis • • • • • 29.2 – No – Small – Large Analog Comparator output available on pin Flexible Input Selection – All pins on the port – Output from the DAC – Bandgap reference voltage. – A 64-level programmable voltage scaler of the internal VCC voltage Interrupt and event generation on – Rising edge – Falling edge – Toggle Window function interrupt and event generation on – Signal above window – Signal inside window – Signal below window Constant current source with configurable output pin selection Overview The Analog Comparator (AC) compares the voltage level on two inputs and gives a digital output based on this comparison. The Analog Comparator may be configured to give interrupt requests and/or events upon several different combinations of input change. Two important properties of the Analog Comparator when it comes to the dynamic behavior, are hysteresis and propagation delay. Both these parameters may be adjusted in order to find the optimal operation for each application. The input section includes analog port pins, several internal signals and a 64-level programmable voltage scaler. The analog comparator output state can also be directly available on a pin for use by external devices. Using as pair they can also be set in Window mode to monitor a signal compared to a voltage window instead of a voltage level. A constant current source can be enabled, and output on a selectable pin. This can be used to replace for example external resistors used to charge capacitors in capacitive touch sensing applications. The Analog Comparators are always grouped in pairs on each port. They have identical behavior but separate control registers. PORTA has one AC pair. Notation of this peripheral is ACA. 48 8387A–AVR–07/11 XMEGA A4U Figure 29-1. Analog comparator overview Pin Input AC0OUT Pin Input Hysteresis DAC Voltage Scaler Enable ACnCTRL ACnMUXCTRL Interrupt Mode WINCTRL Enable Bandgap Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis Pin Input AC1OUT Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 29-2. Figure 29-2. Analog comparator window function + AC0 Upper limit of window Interrupt sensitivity control Input signal Interrupts Events + AC1 Lower limit of window - 49 8387A–AVR–07/11 XMEGA A4U 30. Programming and Debugging 30.1 Features • Programming – External programming through the PDI Minimal protocol overhead for fast operation Built in error detection and handling for reliable operation – Bootloader support for programming through any communication interface • Debugging – Non-Intrusive Real-Time On-Chip Debug System – No software or hardware resources required from device expect pin connection – Program Flow Control Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor – Unlimited Number of User Program Breakpoints – Unlimited Number of User Data Breakpoints, break on: Data location read, write or both read and write Data location content equal or not equal to a value Data location content is greater or smaller than a value Data location content is within or outside a range – No limitation on device clock frequency • Program and Debug Interface (PDI) – 2-pin interface for external programming and debugging – Uses the Reset pin and a dedicated pin – No I/O pins required during programming or debugging 30.2 Overview Atmel® AVR® XMEGA® devices together with Atmel’s development tool chain include the necessary functions for efficient development. All external programming and debugging are done through the Program and Debug Interface (PDI). The Program and Debug Interface is 2-pin interface that uses the Reset pin and a dedicated pin. No I/O pins are required during programming or debugging. In addition to the PDI, programming can also be done through a bootloader. A bootloader in the device can use any other communication interface such as UART, TWI or SPI to download and program new application code to the Flash memory. Debug is supported through a on-chip debug system that offers Non-Intrusive Real-Time debug. It does not require any software or hardware resources expect for the device expect pin connection. Using Atmel’s tool chain, it offers complete program flow control and has supported for unlimited number of program and complex data breakpoints. Application debug can be done from C and high level language source code level, as well as assembler and disassembler level. 50 8387A–AVR–07/11 XMEGA A4U 31. Pinout and Pin Functions The device pinout is shown in ”Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 31.1 Alternate Pin Functions Description The tables below shows the notation and description for all pin functions. 31.1.1 31.1.2 31.1.3 31.1.4 Operation/Power Supply VCC Digital supply voltage AVCC Analog supply voltage GND Ground Port Interrupt functions SYNC Port pin with full synchronous and limited asynchronous interrupt function ASYNC Port pin with full synchronous and full asynchronous interrupt function Analog functions ACn Analog Comparator input pin n ACnOUT Analog Comparator n Output ADCn Analog to Digital Converter input pin n DACn Digital to Analog Converter output pin n AREF Analog Reference input pin Timer/Counter and AWeX functions OCnxLS Output Compare Channel x Low Side for Timer/Counter n OCnxHS Output Compare Channel x High Side for Timer/Counter n 51 8387A–AVR–07/11 XMEGA A4U 31.1.5 31.1.6 31.1.7 Communication functions SCL Serial Clock for TWI SDA Serial Data for TWI XCKn Transfer Clock for USART n RXDn Receiver Data for USART n TXDn Transmitter Data for USART n SS Slave Select for SPI MOSI Master Out Slave In for SPI MISO Master In Slave Out for SPI SCK Serial Clock for SPI D- Data- for USB D+ Data+ for USB Oscillators, Clock and Event TOSCn Timer Oscillator pin n XTALn Input/Output for Oscillator pin n CLKOUT Peripheral Clock Output EVOUT Event Channel 0 Output RTCOUT RTC Clock Source Output Debug/System functions RESET Reset pin PDI_CLK Program and Debug Interface Clock pin PDI_DATA Program and Debug Interface Data pin 52 8387A–AVR–07/11 XMEGA A4U 31.2 Alternate Pin Functions he tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the the first table where this apply. Table 31-1. PORT A PIN # Port A - Alternate functions INTERRUPT ADCA POS/GAINPOS ADCA NEG ADCA GAINNEG ACA POS ACA NEG GND 38 AVCC 39 PA0 40 SYNC ADC0 ADC0 AC0 AC0 PA1 41 SYNC ADC1 ADC1 AC1 AC1 PA2 42 SYNC/ASYNC ADC2 ADC2 AC2 PA3 43 SYNC ADC3 ADC3 AC3 PA4 44 SYNC ADC4 ADC4 AC4 PA5 1 SYNC ADC5 ADC5 AC5 PA6 2 SYNC ADC6 ADC6 AC6 PA7 3 SYNC ADC7 ADC7 Table 31-2. PORT B ACA OUT REFA AREF AC3 AC5 AC1OUT AC7 AC0OUT Port B - Alternate functions PIN # INTERRUPT ADCA POS/GAINPOS DACB PB0 4 SYNC ADC8 PB1 5 SYNC ADC9 PB2 6 SYNC/ASYNC ADC10 DAC0 PB3 7 SYNC ADC11 DAC1 REFB AREF 53 8387A–AVR–07/11 XMEGA A4U Table 31-3. PORT C PIN # Port C - Alternate functions INTERRUPT TCC0(1) AWEXC USARTC0(2) TCC1 SPIC(3) USARTC1 TWIC CLOCKOUT(4) EVENTOUT(5) GND 8 VCC 9 PC0 10 SYNC OC0A OC0ALS PC1 11 SYNC OC0B OC0AHS XCK0 PC2 12 SYNC/ASYNC OC0C OC0BLS RXD0 PC3 13 SYNC OC0D OC0BHS PC4 14 SYNC OC0CLS OC1A PC5 15 SYNC OC0CHS OC1B XCK1 MOSI PC6 16 SYNC OC0DLS RXD1 MISO clkRTC PC7 17 SYNC OC0DHS TXD1 SCK clkPER EVOUT CLOCKOUT EVENTOUT clkPER EVOUT Notes: 1. 2. 3. 4. 5. SCL TXD0 SS Pin mapping of all TC0 can optionally be moved to high nibble of port. Pin mapping of all USART0 can optionally be moved to high nibble of port. Pins MOSI and SCK for all SPI can optionally be swapped. CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7. EVOUT can optionally be moved between port C, D and E and between pin 4 and 7. Table 31-4. PORT D SDA PIN # Port D - Alternate functions INTERRUPT TCD0 SYNC OC0A TCD1 USBD USARTD0 USARTD1 SPID GND 18 VCC 19 PD0 20 PD1 21 SYNC OC0B XCK0 PD2 22 SYNC/ASYNC OC0C RXD0 PD3 23 SYNC OC0D PD4 24 SYNC OC1A PD5 25 SYNC OC1B XCK1 MOSI PD6 26 SYNC D- RXD1 MISO PD7 27 SYNC D+ TXD1 SCK Table 31-5. PORT E TXD0 SS Port E - Alternate functions PIN # INTERRUPT TCE0 PE0 28 SYNC OC0A USARTE0 PE1 29 SYNC OC0B XCK0 GND 30 VCC 31 PE2 32 SYNC/ASYNC OC0C RXD0 PE3 33 SYNC OC0D TXD0 TWIE SDA SCL 54 8387A–AVR–07/11 XMEGA A4U Table 31-6. PORT R PIN # Port R- Alternate functions INTERRUPT PDI PDI 34 PDI_DATA PDI_CLOCK XTAL TOSC(1) RESET 35 PRO 36 SYNC XTAL2 TOSC2 PR1 37 SYNC XTAL1 TOSC1 Note: 1. TOSC pins can optionally be moved to PE2/PE3 55 8387A–AVR–07/11 XMEGA A4U 32. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A4U. For complete register description and summary for each peripheral module, refer to the XMEGA AU Manual. Base Address 0x0000 0x0010 0x0014 0x0018 0x001C 0x0030 0x0040 0x0048 0x0050 0x0060 0x0068 0x0070 0x0078 0x0080 0x0090 0x00A0 0x00B0 0x00C0 0x00D0 0x0100 0x0180 0x01C0 0x0200 0x0240 0x0300 0x0320 0x0380 0x0400 0x0480 0x04A0 0x04C0 0x0600 0x0620 0x0640 0x0660 0x0680 0x07E0 0x0800 0x0840 0x0880 0x0890 0x08A0 0x08B0 0x08C0 0x08F8 0x0900 0x0940 0x0990 0x09A0 0x09B0 0x09C0 0x0A00 0x0A80 0x0A90 0x0AA0 Name Description GPIO VPORT0 VPORT1 VPORT2 VPORT3 CPU CLK SLEEP OSC DFLLRC32M DFLLRC2M PR RST WDT MCU PMIC PORTCFG AES CRC DMA EVSYS NVM ADCA ADCB DACA DACB ACA RTC TWIC TWIE USB PORTA PORTB PORTC PORTD PORTE PORTR TCC0 TCC1 AWEXC HIRESC USARTC0 USARTC1 SPIC IRCOM TCD0 TCD1 HIRESD USARTD0 USARTD1 SPID TCE0 AWEXE HIRESE USARTE0 General Purpose IO Registers Virtual Port 0 Virtual Port 1 Virtual Port 2 Virtual Port 3 CPU Clock Control Sleep Controller Oscillator Control DFLL for the 32MHz Internal Oscillator DFLL for the 2MHz Internal Oscillator Power Reduction Reset Controller Watch-Dog Timer MCU Control Programmable Multilevel Interrupt Controller Port Configuration AES Module CRC Module DMA Controller Event System Non Volatile Memory (NVM) Controller Analog to Digital Converter on port A Analog to Digital Converter on port B Digital to Analog Converter on port A Digital to Analog Converter on port B Analog Comparator pair on port A Real Time Counter Two Wire Interface on port C Two Wire Interface on port E USB Device Port A Port B Port C Port D Port E Port R Timer/Counter 0 on port C Timer/Counter 1 on port C Advanced Waveform Extension on port C High Resolution Extension on port C USART 0 on port C USART 1 on port C Serial Peripheral Interface on port C Infrared Communication Module Timer/Counter 0 on port D Timer/Counter 1 on port D High Resolution Extension on port D USART 0 on port D USART 1 on port D Serial Peripheral Interface on port D Timer/Counter 0 on port E Advanced Waveform Extension on port E High Resolution Extension on port E USART 0 on port E 56 8387A–AVR–07/11 XMEGA A4U 33. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks Arithmetic and Logic Instructions ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H 1 ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C Z,C,N,V,S,H 1 ADIW Rd, K Add Immediate to Word Rd ← Rd + 1:Rd + K Z,C,N,V,S 2 SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H 1 SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,S,H 1 SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,S,H 1 SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C Z,C,N,V,S,H 1 SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ← Rd + 1:Rd - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Rd ← Rd • Rr Z,N,V,S 1 ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V,S 1 OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S 1 ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V,S 1 EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V,S 1 COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V,S 1 NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,S,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V,S 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V,S 1 INC Rd Increment Rd ← Rd + 1 Z,N,V,S 1 DEC Rd Decrement Rd ← Rd - 1 Z,N,V,S 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V,S 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V,S 1 SER Rd Set Register Rd ← $FF None 1 MUL Rd,Rr Multiply Unsigned R1:R0 ← Rd x Rr (UU) Z,C 2 MULS Rd,Rr Multiply Signed R1:R0 ← Rd x Rr (SS) Z,C 2 MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr (SU) Z,C 2 FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ← Rd x Rr<<1 (UU) Z,C 2 FMULS Rd,Rr Fractional Multiply Signed R1:R0 ← Rd x Rr<<1 (SS) Z,C 2 FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ← Rd x Rr<<1 (SU) Z,C 2 DES K Data Encryption if (H = 0) then R15:R0 else if (H = 1) then R15:R0 ← ← Encrypt(R15:R0, K) Decrypt(R15:R0, K) PC ← PC + k + 1 None 2 1/2 Branch Instructions RJMP k Relative Jump IJMP Indirect Jump to (Z) PC(15:0) PC(21:16) ← ← Z, 0 None 2 EIJMP Extended Indirect Jump to (Z) PC(15:0) PC(21:16) ← ← Z, EIND None 2 JMP k Jump PC ← k None 3 RCALL k Relative Call Subroutine PC ← PC + k + 1 None 2 / 3(1) ICALL Indirect Call to (Z) PC(15:0) PC(21:16) ← ← Z, 0 None 2 / 3(1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16) ← ← Z, EIND None 3(1) 57 8387A–AVR–07/11 XMEGA A4U Mnemonics Operands Description CALL k call Subroutine PC ← RET Subroutine Return PC RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate Operation Flags #Clocks k None 3 / 4(1) ← STACK None 4 / 5(1) PC ← STACK I 4 / 5(1) if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 Rd - Rr Z,C,N,V,S,H 1 Rd - Rr - C Z,C,N,V,S,H 1 Rd - K Z,C,N,V,S,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1/2/3 SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ← PC + 2 or 3 None 2/3/4 SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ← PC + 2 or 3 None 2/3/4 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1/2 MOV Rd, Rr Copy Register Rd ← Rr None 1 MOVW Rd, Rr Copy Register Pair Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LDS Rd, k Load Direct from data space Rd ← (k) None 2(1)(2) LD Rd, X Load Indirect Rd ← (X) None 1(1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X ← ← (X) X+1 None 1(1)(2) LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1, Rd ← (X) ← ← X-1 (X) None 2(1)(2) LD Rd, Y Load Indirect Rd ← (Y) ← (Y) None 1(1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y ← ← (Y) Y+1 None 1(1)(2) Data Transfer Instructions 58 8387A–AVR–07/11 XMEGA A4U Mnemonics Operands Description Flags #Clocks LD Rd, -Y Load Indirect and Pre-Decrement Y Rd ← ← Y-1 (Y) None 2(1)(2) LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2(1)(2) LD Rd, Z Load Indirect Rd ← (Z) None 1(1)(2) LD Rd, Z+ Load Indirect and Post-Increment Rd Z ← ← (Z), Z+1 None 1(1)(2) LD Rd, -Z Load Indirect and Pre-Decrement Z Rd ← ← Z - 1, (Z) None 2(1)(2) LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2(1)(2) STS k, Rr Store Direct to Data Space (k) ← Rd None 2(1) ST X, Rr Store Indirect (X) ← Rr None 1(1) ST X+, Rr Store Indirect and Post-Increment (X) X ← ← Rr, X+1 None 1(1) ST -X, Rr Store Indirect and Pre-Decrement X (X) ← ← X - 1, Rr None 2(1) ST Y, Rr Store Indirect (Y) ← Rr None 1(1) ST Y+, Rr Store Indirect and Post-Increment (Y) Y ← ← Rr, Y+1 None 1(1) ST -Y, Rr Store Indirect and Pre-Decrement Y (Y) ← ← Y - 1, Rr None 2(1) STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2(1) ST Z, Rr Store Indirect (Z) ← Rr None 1(1) ST Z+, Rr Store Indirect and Post-Increment (Z) Z ← ← Rr Z+1 None 1(1) ST -Z, Rr Store Indirect and Pre-Decrement Z ← Z-1 None 2(1) STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2(1) Load Program Memory R0 ← (Z) None 3 LPM Operation LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Increment Rd Z ← ← (Z), Z+1 None 3 Extended Load Program Memory R0 ← (RAMPZ:Z) None 3 ELPM ELPM Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None 3 ELPM Rd, Z+ Extended Load Program Memory and PostIncrement Rd Z ← ← (RAMPZ:Z), Z+1 None 3 Store Program Memory (RAMPZ:Z) ← R1:R0 None - (RAMPZ:Z) Z ← ← R1:R0, Z+2 None - Rd ← I/O(A) None 1 I/O(A) ← Rr None 1 STACK ← Rr None 1(1) SPM SPM Z+ Store Program Memory and Post-Increment by 2 IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd Pop Register from Stack Rd ← STACK None 2(1) XCH Z, Rd Exchange RAM location Temp Rd (Z) ← ← ← Rd, (Z), Temp None 2 LAS Z, Rd Load and Set RAM location Temp Rd (Z) ← ← ← Rd, (Z), Temp v (Z) None 2 LAC Z, Rd Load and Clear RAM location (Z) Rd ← ← ($FF – Rd) • (Z) (Z) None 2 59 8387A–AVR–07/11 XMEGA A4U Mnemonics Operands Description LAT Z, Rd Load and Toggle RAM location Operation Flags #Clocks (Z) Rd ← ← Rd ⊕ (Z) (Z) None 2 Rd(n+1) Rd(0) C ← ← ← Rd(n), 0, Rd(7) Z,C,N,V,H 1 Rd(n) Rd(7) C ← ← ← Rd(n+1), 0, Rd(0) Z,C,N,V 1 Rd(0) Rd(n+1) C ← ← ← C, Rd(n), Rd(7) Z,C,N,V,H 1 Rd(7) Rd(n) C ← ← ← C, Rd(n+1), Rd(0) Z,C,N,V 1 Bit and Bit-test Instructions LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 Rd(3..0) ↔ Rd(7..4) None 1 Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 1 CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None 1 BST Rr, b Bit Store from Register to T BLD Rd, b Bit load from T to Register T ← Rr(b) T 1 Rd(b) ← T None 1 SEC Set Carry C ← 1 C 1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1 N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z 1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S 1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Two’s Complement Overflow V ← 1 V 1 CLV Clear Two’s Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H 1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 None 1 MCU Control Instructions BREAK Break NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr. for WDR) None 1 Notes: (See specific descr. for BREAK) 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. 2. One extra cycle must be added when accessing Internal SRAM. 60 8387A–AVR–07/11 XMEGA A4U 34. Packaging information 34.1 44A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE Note 2 Note 2 0.80 TYP 2010-10-20 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 44A C 61 8387A–AVR–07/11 XMEGA A4U 34.2 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. NOTE 0.50 BSC L 0.59 0.64 0.69 K 0.20 0.26 0.41 9/26/08 Package Drawing Contact: [email protected] TITLE 44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) GPC ZWS DRAWING NO. REV. 44M1 H 62 8387A–AVR–07/11 XMEGA A4U 34.3 49C2 E A1 BALL ID 0.10 D A1 TOP VIEW A A2 SIDE VIEW E1 G e F E D D1 COMMON DIMENSIONS (Unit of Measure = mm) C B 1 A1 BALL CORNER MIN NOM MAX A – – 1.00 A1 0.20 – – A2 0.65 – – D 4.90 5.00 5.10 SYMBOL A 2 3 4 5 b 6 7 e BOTTOM VIEW 49 - Ø0.35 ± 0.05 D1 E 3.90 BSC 4.90 5.00 E1 b NOTE 5.10 3.90 BSC 0.30 0.35 e 0.40 0.65 BSC 3/14/08 Package Drawing Contact: [email protected] TITLE 49C2, 49-ball (7 x 7 Array), 0.65 mm Pitch, 5.0 x 5.0 x 1.0 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) GPC CBD DRAWING NO. REV. 49C2 A 63 8387A–AVR–07/11 XMEGA A4U 35. Electrical Characteristics All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. 35.1 Absolute Maximum Ratings* Operating Temperature.................................... -55°C to +85°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin with respect to Ground..-0.5V to VCC+0.5V Maximum Operating Voltage ............................................ 4.0V DC Current per I/O Pin ................................................ 20.0mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Current VCC and GND Pins................................. 200.0mA 35.2 DC Characteristics Table 35-1. Symbol Current Consumption for Active and sleep modes Parameter Condition 32kHz, Ext. Clk Active Power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk ICC 32kHz, Ext. Clk Idle Power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk Min ICC Power-down power consumption 50 VCC = 3.0V 130 VCC = 1.8V 260 VCC = 3.0V 540 VCC = 1.8V 460 600 0.96 1.4 9.8 12 VCC = 3.0V Units µA mA VCC = 1.8V 2.4 VCC = 3.0V 3.9 VCC = 1.8V 62 VCC = 3.0V 118 VCC = 1.8V 125 225 237 350 3.8 5.5 mA 0.1 1 µA 1.2 4.5 1.2 3 2.4 7 VCC = 3.0V VCC = 3.0V WDT and Sampled BOD enabled, T = 25°C WDT and Sampled BOD enabled, T=85°C Max VCC = 1.8V T = 25°C T = 85°C Typ µA VCC = 3.0V 64 8387A–AVR–07/11 XMEGA A4U Table 35-1. Symbol Current Consumption for Active and sleep modes (Continued) Parameter Condition Min RTC on ULP clock, WDT and sampled BOD enabled, T = 25°C Power-save power consumption(2) Max 1.2 RTC on 1.024kHz low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.5 2 VCC = 3.0V 0.7 2 RTC from low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.9 3 VCC = 3.0V 1.15 3.5 VCC = 3.0V 320 Current through RESET pin substracted Units 1.2 VCC = 3.0V ICC Reset power consumption Typ µA Module and peripheral power consumption(3) ULP oscillator 1 32.768kHz int. oscillator 27 85 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 115 270 32MHz int. oscillator PLL DFLL enabled with 32.768kHz int. osc. as reference 460 Multiplication factor = 10x 220 Real Time Counter µA 0.015 Watchdog Timer 1 Continuous mode 138 Sampled mode, include ULP oscillator 1.2 BOD ICC Internal 1.0V reference 100 Temperature sensor 95 3.05 ADC DAC 250 kSPS VREF = Ext ref 250kSPS’ VREF = Ext ref No load CURRLIMIT = LOW 2.61 CURRLIMIT = MEDIUM 2.16 CURRLIMIT = HIGH 1.75 Normal mode 1.63 Low Power mode 1.06 High Speed Mode 330 Low Power Mode 130 615KBps between I/O registers and SRAM 108 mA AC DMA Timer/Counter USART 16 Rx and Tx enabled, 9600 BAUD Flash memory and EEPROM programming Notes: µA 2.5 3.6 mA 1. All Power Reduction Registers set. 2. Maximum limits are based on characterization and not tested in production. 65 8387A–AVR–07/11 XMEGA A4U 3. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz External clock without prescaling, T = 25°C unless other conditiond are given . 35.3 Operating Voltage and Frequency Table 35-2. Symbol ClkCPU Operating voltage and frequency Parameter CPU clock frequency Condition Min Typ Max VCC = 1.6V 0 12 VCC = 1.8V 0 12 VCC = 2.7V 0 32 VCC = 3.6V 0 32 Units MHz The maximum System clock frequency of the Atmel® AVR® XMEGA A4U devices is depending on VCC. As shown in Figure 35-1 on page 66 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 35-1. Maximum Frequency vs. Vcc MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.6 V 66 8387A–AVR–07/11 XMEGA A4U 35.4 Wakeup time from sleep Table 35-3. Symbol Device wakeup time from sleep modes with various system clock sources Parameter Condition External 2MHz clock 32.768kHz internal oscillator Min Typ Max Units 2 120 Wake-up time from Idle 2MHz internal oscillator 2 32MHz internal oscillator 0.17 External 2MHz clock 32.768kHz internal oscillator 2 120 Wake-up time from Standby 2MHz internal oscillator 2 32MHz internal oscillator 0.17 External 2MHz clock twakeup Wake-up time from Extend Standby 32.768kHz internal oscillator 2 120 µs 2MHz internal oscillator 2 32MHz internal oscillator 0.17 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 8.8 32MHz internal oscillator 5 Wake-up time from Power-save External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 8.8 32MHz internal oscillator 5 Wake-up time from Power-down 67 8387A–AVR–07/11 XMEGA A4U 35.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCSMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 35-4. Symbol VIH VIL I/O Pin Characteristics Parameter High Level Input Voltage Low Level Input Voltage Condition VOL VCC+0.3 VCC = 2.3 - 2.7V 1.7 VCC+0.3 VCC = 1.6 - 2.7V 0.7*VCC VCC+0.3 VCC = 3.0 - 3.6V -0.3 0.8 VCC = 2.3 - 2.7V -0.3 0.7 VCC = 1.6 - 2.7V -0.3 0.2*VCC High Level Output Voltage VCC = 2.3 - 2.7V VOH 2.4 3.19 IOH = -1mA 2.0 2.43 IOH = -2mA 1.7 2.37 0.4 IOL = 1mA 0.03 0.4 IOL = 2mA 0.05 0.7 VCC = 3.3V IOL = 15mA 0.4 0.76 VCC = 3.0V IOL = 10mA 0.265 0.64 VCC = 1.8V IOL = 5mA 0.18 0.46 VCC = 3.3V IOH = -8mA 2.6 2.86 VCC = 3.0V IOH = -6mA 2.1 2.66 VCC = 1.8V IOH = -2mA 1.4 1.64 IIN Input Leakage Current I/O pin <0.001 0.1 IIL Input Leakage Current I/O pin <0.001 0.1 RP I/O pin Pull/Buss keeper Resistor 27 Reset pin Pull-up Resistor 25 Input hysteresis 0.2 RRST Units V 0.05 VCC = 2.3 - 2.7V Output High Voltage GPIO IOH = -2mA IOL = 2mA Low Level Output Voltage Output Low Voltage GPIO Max 2 VCC = 3.0 - 3.6V VOL Typ VCC = 3.0 - 3.6V VCC = 3.0 - 3.6V VOH Min µA kΩ V 4 tr Pad rise time No load nS slew rate limitation 7 68 8387A–AVR–07/11 XMEGA A4U 35.6 ADC Characteristics Table 35-5. ADC Characteristics Symbol Parameter RES Resolution ClkADC fADC Condition(2) Min Typ Max Units 8 12 12 Bits 5 8 ClkADC cycles µS Conversion time (latency) (RES+2)/2+(GAIN !=0), RES = 8 or 2 Sampling Time 1/2 ClkADC cycle 0.25 5 Max is 1/4 of Peripheral clock frequency 100 2000 Measuring internal signals 100 125 100 2000 CURRLIMIT = LOW 100 1500 CURRLIMIT = MEDIUM 100 1000 CURRLIMIT = HIGH 100 500 VCC- 0.3 VCC+ 0.3 1 AVCC- 0.6 ADC Clock frequency kHz Sample rate AVCC Analog supply voltage VREF Reference voltage kSPS V Rin Input resistance Switched 4.0 kΩ Cin Input capacitance Switched 4.4 pF RAREF Reference input resistance (leackage only) >10 MΩ CAREF Reference input capacitance Static load 7 pF Start-up time ADC clock cycles 12 24 After changing reference or input mode 7 7 After ADC flush 1 1 ADC settling time Vin Vin Input range Conversion range Differential mode, Vinp - Vinn Conversion range Single ended unsigned mode, Vinp 500kSPS INL(1) AVCC+ 0.1 -VREF VREF -ΔV VREF-ΔV ±1.2 2 ±1.5 3 ±1.0 2 ±1.5 3 ±0.8 1.2 ±0.5 1.5 ±0.8 1.2 ±0.5 1.5 V Integral non-linearity 2000kSPS DNL(1) VCC-1.0V < VREF< VCC-0.6V -0.1 ClkADC cycles VCC-1.0V < VREF< VCC-0.6V 500kSPS, guaranteed monotonic VCC-1.0V < VREF< VCC-0.6V 2000kSPS, guaranteed monotonic VCC-1.0V < VREF< VCC-0.6V LSB Differential non-linearity Offset Error -1 mV Temperature drift <0.01 mV/K Operating voltage drift <0.6 mV/V 69 8387A–AVR–07/11 XMEGA A4U Table 35-5. ADC Characteristics (Continued) Symbol Condition(2) Parameter Differential mode Min Typ External reference 1 AVCC/1.6 10 AVCC/2.0 8 Bandgap ±5 Max Units mV Gain Error Notes: Temperature drift <0.02 mV/K Operating voltage drift <0.5 mV/V 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used. Table 35-6. Symbol ADC Gain Stage Characteristics Parameter Condition Min Typ Max Units Rin Input resistance Switched in normal mode 4.0 kΩ Cin Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate Clock rate Same as ADC INL (1) DNL(1) Integral Non-Linearity 500kSPS Differential Non-Linearity Gain Error Offset Error, input refered Note: VCC- 0.6 0 ClkADC cycles 1 100 V 1000 All gain settings ±2.0 4 All gain setting, guaranteed monotonic ±0.9 1.5 kHz LSB 1x gain, normal mode -0.8 8x gain, normal mode -2.5 64x gain, normal mode -3.5 1x gain, normal mode -2 8x gain normal mode -5 64x gain normal mode -4 % mV 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 70 8387A–AVR–07/11 XMEGA A4U 35.7 DAC Characteristics Table 35-7. Symbol RES DAC Characteristics Parameter Condition Min Typ Input Resolution AVREF External reference voltage Rchannel DC output impedance 1.0 Linear output voltage range RAREF Reference input resistance CAREF Reference input capacitance Minimum Resistance load Units 12 Bits VCC-0.6 V 50 Ω AVCC-0.15 0.15 Static load Max >10 MΩ 7 pF 1 kΩ 100 pF 1 nF Maximum capacitance laod 1000Ω serial resistance Operating within specification AVCC/1000 Output sink/source Safe operation Enable, reset to code 0 INL(1) Integral non-linearity ±2.0 3 VCC = 3.6V ±1.5 2.5 VCC = 1.6V ±2.0 4 VCC = 3.6V ±1.5 4 VCC = 1.6V ±3.0 VCC = 3.6V ±3.0 VREF=Ext 1.0V, guaranteed monotonic VCC = 1.6V ±1.5 3 VCC = 3.6V ±0.6 1.5 VREF=AVCC, guaranteed monotonic VCC = 1.6V ±1.0 3.5 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±3.0 VCC = 3.6V ±3.0 VREF=AVCC VREF=INT1V DNL(1) Differential Non-Linearity VREF=INT1V Gain error Ox VCC = 1.6V VREF= Ext 1.0V mA 10 After calibration LSB <4 Gain calibration step size 4 Gain calibration drift VREF= Ext 1.0V <0.2 Offset error After calibration <1 mV/K LSB Offset calibration step size Fclk Note: Conversion rate 1 Fout=Fclk/4, Cload=100pF, Max step size 0 1000 0 1000 kSPS 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range. 71 8387A–AVR–07/11 XMEGA A4U 35.8 Analog Comparator Characteristics Table 35-8. Symbol Voff Ilk Analog Comparator Characteristics Parameter Condition Min Max <±10 mV Input Leakage Current <1000 pA -0.1 AC startup time Vhys1 Hysteresis, None Vhys2 Hysteresis, Small Vhys3 Hysteresis, Large AVCC+ 0.1 100 µs mode = High Speed (HS) 14 mode = Low Power (LP) 30 mode = HS 30 mode = LP 60 mode = HS 90 mode = HS mV 100 95 ns Propagation delay VCC = 3.0V, T= 85°C 64-Level Voltage Scaler V 0 VCC = 3.0V, T= 85°C tdelay Units Input Offset Voltage Input voltage range mode = LP 200 mode = LP 200 Integral non-linearity (INL) 0.5 Current source accuracy after calibration 500 1 5 Current source calibration range 35.9 Typ 4 LSB % 6 µA Bandgap and Internal 1.0V Reference Characteristics Table 35-9. Symbol Bandgap and Internal 1.0V Reference Characteristics Parameter Condition Min As reference for ADC or DAC Typ Max 1 ClkPER + 2.5µs Startup time As input voltage to ADC and AC Units µs 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference Variation over voltage and temperature T= 85°C, After calibration 0.99 1 ±0.5 1.01 % 72 8387A–AVR–07/11 XMEGA A4U 35.10 Brownout Detection Characteristics Table 35-10. Brownout Detection Characteristics(1) Symbol Parameter Condition BOD level 0 falling Vcc Min Typ Max 1.62 1.62 1.72 BOD level 1 falling Vcc 1.81 BOD level 2 falling Vcc 2.01 BOD level 3 falling Vcc 2.21 BOD level 4 falling Vcc 2.41 BOD level 5 falling Vcc 2.61 BOD level 6 falling Vcc 2.81 BOD level 7 falling Vcc 3.00 Units V VHYST Note: Continous mode 0,4 Sampled mode 1000 Detection time tBOD µs Hysteresis 1.6 % 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level. 35.11 External Reset Characteristics Table 35-11. External Reset Characteristics Symbol Parameter tEXT Minimum reset pulse width VRST Reset threshold voltage Condition Min Typ Max Units 90 1000 ns VCC = 2.7 - 3.6V 0.50*VCC VCC = 1.6 - 2.7V 0.40*VCC V 35.12 Power-on Reset Characteristics Table 35-12. Power-on Reset Characteristics Symbol Parameter VPOT- POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Condition Min Typ VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.2 1.3 Max Units V 1.59 73 8387A–AVR–07/11 XMEGA A4U 35.13 Flash and EEPROM Memory Characteristics Table 35-13. Endurance and Data Retention Symbol Parameter Condition Min 25°C 10K 85°C 10K 25°C 100 55°C 25 25°C 80K 85°C 30K 25°C 100 55°C 25 Typ Max Write/Erase cycles Units Cycle Flash Data retention Year Write/Erase cycles Cycle EEPROM Data retention Year Table 35-14. Programming time Symbol Parameter Condition Chip Erase (2) Flash EEPROM Notes: Flash, EEPROM Min and SRAM Erase Typ(1) Max Units 50 Page Erase 6 Page Write 6 Page WriteAutomatic Page Erase and Write 12 Page Erase 6 Page Write 6 Page WriteAutomatic Page Erase and Write 12 ms 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not erased if the EESAVE fuse is programmed. 35.14 Clock and Oscillator Characteristics 35.14.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 35-15. Calibrated 32.768kHz Internal Oscillator characteristics Symbol Parameter Condition Min Frequency Factory calibration accuracy User calibration accuracy Typ Max 32.768 T = 85°C, VCC = 3.0V Units kHz -0.5 0.5 -0.5 0.5 % 74 8387A–AVR–07/11 XMEGA A4U 35.14.2 Calibrated 2MHz RC Internal Oscillator characteristics Table 35-16. Calibrated 2MHz Internal Oscillator characteristics Symbol Parameter Condition Min Typ Max Units Frequency range DFLL can tune to this frequency over voltage and temperature 1.8 2.0 2.2 MHz Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5 -0.2 0.2 % User calibration accuracy DFLL calibration stepsize 35.14.3 0.21 Calibrated and tunable 32MHz Internal Oscillator characteristics Table 35-17. Calibrated 32MHz Internal Oscillator characteristics Symbol Parameter Condition Min Typ Max Units Frequency range DFLL can tune to this frequency over voltage and temperature 30 32 55 MHz Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5 -0.2 0.2 % Max Units User calibration accuracy DFLL calibration step size 35.14.4 0.22 32kHz Internal ULP Oscillator characteristics Table 35-18. 32kHz Internal ULP Oscillator characteristics Symbol Parameter Condition Min Output frequency 35.14.5 Typ 38 kHz Internal Phase Locked Loop (PLL) characteristics Table 35-19. Calibrated 32MHz Internal Oscillator characteristics Symbol fIN fOUT Parameter Input Frequnecy Ouput frequnecy (1) Condition Min Typ Output frequnecy must be within fOUT 0.4 64 20 32 20 128 Start-up time 25 re-lock time 25 Max Units MHz µs 1. The maximum ouput frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than 4 times the maximum CPU frequency. 75 8387A–AVR–07/11 XMEGA A4U 35.14.6 External 32.768kHz Crystal Oscillator and TOSC characteristics Table 35-20. External 32.768kHz Crystal Oscillator and TOSC characteristics Symbol Parameter ESR/R1 Recommended crystal equivalent series resistance (ESR) CIN_TOSC Condition Typ Max Crystal load capacitance 6.5pF 60 Crystal load capacitance 9.0pF 35 Units kΩ Normal mode 4.7 Low power mode 5.2 Input capacitance between TOSC pins pF capacitance load matched to crystal specification Recommended Safety factor Note: Min 3 1. See Figure 35-2 on page 76 for definition Figure 35-2. TOSC input capacitance CL1 TOSC1 CL2 Device internal External TOSC2 32.768 KHz crystal The input capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without external capacitors. 35.14.7 External Clock Characteristics Figure 35-3. External Clock Drive Waveform tCH tCH tCR tCF VIH1 VIL1 tCL tCK 76 8387A–AVR–07/11 XMEGA A4U Table 35-21. External Clock used as System Clock without prescaling Symbol Parameter Clock Frequency(1) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) ΔtCK Note: Condition Min Typ Max VCC = 1.6 - 1.8V 0 12 VCC = 2.7 - 3.6V 0 32 VCC = 1.6 - 1.8V 83.3 VCC = 2.7 - 3.6V 31.5 VCC = 1.6 - 1.8V 30.0 VCC = 2.7 - 3.6V 12.5 VCC = 1.6 - 1.8V 30.0 VCC = 2.7 - 3.6V 12.5 Units MHz ns VCC = 1.6 - 1.8V 10 VCC = 2.7 - 3.6V 3 VCC = 1.6 - 1.8V 10 VCC = 2.7 - 3.6V 3 Change in period from one clock cycle to the next 10 % 1. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions. Table 35-22. External Clock with prescaler(1) for System Clock Symbol 1/tCK Parameter Clock Frequency(2) tCK Clock Period tCH Clock High Time Condition Min Typ Max VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 MHz ns tCL Clock Low Time tCR Rise Time (for maximum frequency) 1.5 tCF Fall Time (for maximum frequency) 1.5 Change in period from one clock cycle to the next 10 ΔtCK Notes: Units % 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded. 2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions 77 8387A–AVR–07/11 XMEGA A4U 35.15 SPI Characteristics Figure 35-4. SPI Interface Requirements in Master mode SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH MOSI (Data Output) tMOH MSB LSB Figure 35-5. SPI Timing Requirements in Slave mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS MOSI (Data Input) tSIH MSB tSOSSS MISO (Data Output) tSSCK LSB tSOS MSB tSOSSH LSB 78 8387A–AVR–07/11 XMEGA A4U Table 35-23. SPI Timing Characteristics and Requirements Symbol Parameter Condition Min Typ Max tSCK SCK Period Master (See Table 21-4 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK Rise time Master 2.7 tSCKF SCK Fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.5*SCK tMOH MOSI hold after SCK Master 1 tSSCK Slave SCK Period Slave 4*t ClkPER tSSCKW SCK high/low width Slave 2*t ClkPER tSSCKR SCK Rise time Slave 1600 tSSCKF SCK Fall time Slave 1600 tSIS MOSI setup to SCK Slave tSIH MOSI hold after SCK Slave tSSS SS setup to SCK Slave 21 tSSH SS hold after SCK Slave 20 tSOS MISO setup SCK Slave 8 tSOH MISO hold after SCK Slave 13 tSOSS MISO setup after SS low Slave 11 tSOSH MISO hold after SS high Slave 8 Units ns 3 t ClkPER 79 8387A–AVR–07/11 XMEGA A4U 35.16 Two-Wire Interface Characteristics Table 2-1 describes the requirements for devices connected to the Two Wire Serial Bus. The XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 35-6. Figure 35-6. Two-Wire Interface Bus Timing tof tHIGH tLOW tr SCL tSU;STA tHD;DAT tHD;STA tSU;STO tSU;DAT SDA tBUF Table 35-24. Two Wire Serial Bus Characteristics Symbol Parameter VIH Input High Voltage 0.7VCC VCC+0.5 VIL Input Low Voltage 0.5 0.3*VCC Vhys Hysteresis of Schmitt Trigger Inputs VOL Output Low Voltage tr Rise Time for both SDA and SCL tof Output Fall Time from VIHmin to VILmax tSP Spikes Suppressed by Input Filter II Input Current for each I/O Pin CI Capacitance for each I/O Pin fSCL SCL Clock Frequency RP Value of Pull-up resistor tHD;STA Hold Time (repeated) START condition tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Set-up time for a repeated START condition Condition Min 0.05VCC 3mA, sink current 10pF < Cb < 400pF(2) 0.1VCC < VI < 0.9VCC fPER(3)>max(10fSCL, 250kHz) fSCL ≤ 100kHz Typ Max Unit s V (1) 0 0.4 20+0.1Cb(1)(2) 300 20+0.1Cb(1)(2) 250 0 50 -10 10 µA 10 pF 400 kHz 0 fSCL > 100kHz V CC – 0.4V ---------------------------3mA fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 fSCL > 100kHz 1.3 fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 300ms ----------------Cb ns Ω µs fSCL ≤ 100kHz fSCL > 100kHz 80 8387A–AVR–07/11 XMEGA A4U Table 35-24. Two Wire Serial Bus Characteristics (Continued) Symbol Parameter tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition tBUF Bus free time between a STOP and START condition Notes: Condition Min Typ Max fSCL ≤ 100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL ≤ 100kHz 250 fSCL > 100kHz 100 fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 fSCL > 100kHz 1.3 Unit s µs 1. Required only for fSCL > 100kHz 2. Cb = Capacitance of one bus line in pF 3. fPER = Peripheral clock frequency 81 8387A–AVR–07/11 XMEGA A4U 36. Typical Characteristics 36.1 Active Supply Current Figure 36-1. Active Supply Current vs. Frequency fSYS = 0 - 1.0MHz External clock, T = 25°C 700 3.3V 600 3.0V 500 ICC [µA] 2.7V 400 2.2V 300 1.8V 200 100 0 0 0.2 0.4 0.6 0.8 1 Frequency [MHz] Figure 36-2. Active supply current vs. frequency fSYS = 1 - 32MHz External clock, T = 25°C 12 3.3V 10 3.0V 2.7V ICC [mA] 8 6 2.2V 4 1.8V 2 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] 82 8387A–AVR–07/11 XMEGA A4U Figure 36-3. Active Supply Current vs. Vcc fSYS = 1.0MHz External Clock 0.8 -40°C 25°C 85°C 0.7 ICC [mA] 0.6 0.5 0.4 0.3 0.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-4. Active Supply Current vs. VCC fSYS = 2.0MHz internal oscillator 1.5 -40°C 1.4 25°C 85°C 1.3 1.2 ICC [mA] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 83 8387A–AVR–07/11 XMEGA A4U 36.2 Idle Supply Current Figure 36-5. Idle Supply Current vs. Frequency fSYS = 0 - 1.0MHz, T = 25°C ICC [µA] 140 3.3V 120 3.0V 100 2.7V 80 2.2V 60 1.8V 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 36-6. Idle Supply Current vs. Frequency fSYS = 1 - 32MHz, T = 25°C 4.5 3.3V 4.0 3.0V 3.5 2.7V ICC [mA] 3.0 2.5 2.0 2.2V 1.5 1.0 1.8V 0.5 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] 84 8387A–AVR–07/11 XMEGA A4U Figure 36-7. Idle Supply Current vs. Vcc fSYS = 32.768kHz internal oscillator 33 -40°C 85°C 32 25°C ICC [µA] 31 30 29 28 27 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-8. Idle Supply Current vs. Vcc fSYS = 1.0MHz internal oscillator 160 85 °C 25 °C -40 °C 150 140 130 ICC [µA] 120 110 100 90 80 70 60 50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 85 8387A–AVR–07/11 XMEGA A4U Figure 36-9. Idle Supply Current vs. Vcc fSYS = 2.0MHz internal oscillator 410 -40°C 25°C 85°C 380 350 ICC [µA] 320 290 260 230 200 170 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-10. Idle Supply Current vs. Vcc fSYS = 32MHz internal oscillator 5.6 -40°C 5.4 25°C 5.2 5.0 85°C ICC [mA] 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 86 8387A–AVR–07/11 XMEGA A4U Figure 36-11. Idle Supply Current vs. Vcc fSYS = 32MHz internal oscillator, prescaled to 8MHz 2.0 -40 °C 25 °C 85 °C 1.8 ICC [mA] 1.6 1.4 1.2 1.0 0.8 0.6 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 36.3 Power-down Supply Current Figure 36-12. Power-down Supply Current vs. Temperature All functions disabled 1.2 3.3V 3.0V 2.7V 1 2.2V 1.8V ICC [µA] 0.8 0.6 0.4 0.2 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 87 8387A–AVR–07/11 XMEGA A4U Figure 36-13. Power-down Supply Current vs. Temperature With WDT and sampled BOD enabled.p 2.6 3.3V 3.0V 2.7V ICC [µA] 2.3 2.2V 1.8V 2 1.7 1.4 1.1 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 36.4 Pin Pull-up Figure 36-14. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage VCC = 1.8V 70 60 IPIN [µA] 50 40 30 20 -40 °C 25 °C 85 °C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET [V] 88 8387A–AVR–07/11 XMEGA A4U Figure 36-15. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage VCC = 3.0V 120 108 96 IPIN [µA] 84 72 60 48 36 24 -40 °C 25 °C 85 °C 12 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] Figure 36-16. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage VCC = 3.3V 130 117 104 IPIN [µA] 91 78 65 52 39 26 -40 °C 25 °C 85 °C 13 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 VRESET [V] 89 8387A–AVR–07/11 XMEGA A4U 36.5 Pin Output Voltage vs. Sink/Source Current Figure 36-17. I/O Pin Output Voltage vs. Source Current Vcc = 1.8V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -1 -2 1.8 85 °C 25 °C -20 °C IOH [mA] -3 -4 -5 -6 -7 -8 -9 -10 VPIN [V] Figure 36-18. I/O Pin Output Voltage vs. Source Current Vcc = 3.0V 0 1.5 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 85 °C 25 °C -40 °C -2 -4 IOH [mA] -6 -8 -10 -12 -14 -16 -18 -20 VPIN [V] 90 8387A–AVR–07/11 XMEGA A4U Figure 36-19. I/O Pin Output Voltage vs. Source Current Vcc = 3.3V 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 0 -2 3.3 85 °C 25 °C -40 °C -4 IOH [mA] -6 -8 -10 -12 -14 -16 -18 -20 VPIN [V] Figure 36-20. I/O Pin Output Voltage vs. Source Current T = 25°C 3.6 3.6 V 3.3 V 3.3 3 2.7 V VOH [V] 2.7 2.4 2.2 V 2.1 1.8 1.8 V 1.5 1.2 0.9 0.6 0.3 0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] 91 8387A–AVR–07/11 XMEGA A4U Figure 36-21. I/O Pin Output Voltage vs. Sink Current Vcc = 1.8V 2.75 85°C 2.5 2.25 2 20°C VOL [V] 1.75 1.5 1.25 1 -40°C 0.75 0.5 0.25 0 0 2.5 5 7.5 10 12.5 15 17.5 20 IPIN [mA] Figure 36-22. I/O Pin Output Voltage vs. Sink Current T= 25°C 2 1.8 V 1.8 1.6 VOL [V] 1.4 1.2 1 2.2 V 2.7 V 3.3 V 3.6 V 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] 92 8387A–AVR–07/11 XMEGA A4U Figure 36-23. I/O Pin Sink Current vs. Output Voltage Vcc = 3.0V 20 -20 °C 25 °C 18 85 °C 16 IIOL [mA] 14 12 10 8 6 4 2 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 VPIN [V] Figure 36-24. I/O Pin Sink Current vs. Output Voltage Vcc = 3.3V 22 -20 °C 25 °C 85 °C 20 18 16 IIOL [mA] 14 12 10 8 6 4 2 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 VPIN [V] 93 8387A–AVR–07/11 XMEGA A4U 36.6 Pin Thresholds and Hysteresis Figure 36-25. I/O Pin Input Threshold Voltage vs. VCC T = 25°C VThreshold [V] 1.85 1.7 VIH 1.55 VIL 1.4 1.25 1.1 0.95 0.8 0.65 0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-26. I/O Pin Input Hysteresis vs. VCC T = 25°C 0.315 0.3 Hysteresis [V] 0.285 0.27 0.255 0.24 0.225 0.21 0.195 0.18 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 94 8387A–AVR–07/11 XMEGA A4U Figure 36-27. Reset Input Threshold Voltage vs. VCC VIH - I/O Pin Read as “1” -40°C 25°C 85°C 1.8 1.7 1.6 1.5 VTHRESHOLD [V] 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-28. Reset Input Threshold Voltage vs. VCC VIL - I/O Pin Read as “0” -40°C 25°C 85°C 1.8 1.7 1.6 1.5 VTHRESHOLD [V] 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 95 8387A–AVR–07/11 XMEGA A4U 36.7 Bod characteristics Figure 36-29. BOD Thresholds vs. Temperature BOD Level = 1.6V 1.629 1.626 1.623 Rising Vcc VBOT [V] 1.62 Falling Vcc 1.617 1.614 1.611 1.608 1.605 1.602 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 45 55 65 75 85 Temperature [°C] Figure 36-30. BOD Thresholds vs. Temperature BOD Level = 2.6V 2.648 2.642 2.636 2.63 VBOT [V] Rising Vcc 2.624 2.618 2.612 Falling Vcc 2.606 2.6 2.594 2.588 -45 -35 -25 -15 -5 5 15 25 35 Temperature [°C] 96 8387A–AVR–07/11 XMEGA A4U 36.8 36.8.1 Oscillators Internal 1kHz Oscillator Figure 36-31. 1kHz Ouput from Internal ULP Oscillator Frequency vs. Temperature 1.17 Frequency [kHz] 1.16 1.15 1.14 1.13 1.12 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 1.11 1.1 1.09 25 30 35 40 45 50 55 60 65 70 75 80 85 Temperature [°C] 36.8.2 32.768kHz Internal Oscillator Figure 36-32. 32.768kHz Internal Oscillator Frequency vs. Temperature 1.8V 2.2V 2.7V 3.3V 3.0V 32.81 32.79 Frequency [kHz] 32.77 32.75 32.73 32.71 32.69 32.67 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 97 8387A–AVR–07/11 XMEGA A4U 36.8.3 2MHz Internal Oscillator Figure 36-33. 2MHz Internal Oscillator CALA Calibration Step Size VCC = 3V 0.32 % 0.29 % Step size [%] 0.26 % 0.23 % 0.20 % -40°C 0.17 % 25°C 85°C 0.14 % 0 10 20 30 40 50 60 70 80 90 100 110 120 130 75 3.3V 3.0V 2.7V 2.2V 1.8V 85 CALA Frequency [MHz] Figure 36-34. 2MHz Internal Oscillator Frequency vs. Temperature 2.15 2.14 2.13 2.12 2.11 2.1 2.09 2.08 2.07 2.06 2.05 2.04 2.03 2.02 2.01 2 1.99 1.98 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 Temperature [°C] 98 8387A–AVR–07/11 XMEGA A4U Figure 36-35. 2MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from 32.768kHz internal oscillator 2.005 2.7V 2.2V 3.3V 3.0V 1.8V 2.004 Frequency [MHz] 2.003 2.002 2.001 2 1.999 1.998 1.997 1.996 1.995 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 36.8.4 32MHZ Internal Oscillator Figure 36-36. 32MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 35.7 35.2 Frequency [MHz] 34.7 34.2 33.7 33.2 32.7 3.3V 3.0V 2.7V 2.2V 1.8V 32.2 31.7 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 99 8387A–AVR–07/11 XMEGA A4U Figure 36-37. 32MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from 32.768kHz internal oscillator 2.2V 3.0V 2.7V 1.8V 3.3V 32.06 32.04 Frequency [MHz] 32.02 32 31.98 31.96 31.94 31.92 31.9 31.88 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 36-38. 32MHz Internal Oscillator CALA Calibration Step Size VCC = 3.0V 0.36 % 0.34 % 0.32 % 0.30 % Step size [%] 0.28 % 0.26 % 0.24 % 0.22 % 0.20 % 0.18 % 85°C 0.16 % 25°C 0.14 % -40°C 0.12 % 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA 100 8387A–AVR–07/11 XMEGA A4U 36.8.5 32MHz Internal Oscillator Calibrated to 48MHZ Figure 36-39. 48MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 53.5 Frequency [MHz] 52.5 51.5 50.5 49.5 3.3V 3.0V 2.7V 2.2V 1.8V 48.5 47.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 36-40. 48MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from 32.768kHz internal oscillator 48.08 2.2V 3.3V 1.8V 3.0V 2.7V 48.05 Frequency [MHz] 48.02 47.99 47.96 47.93 47.9 47.87 47.84 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 101 8387A–AVR–07/11 XMEGA A4U 36.9 Analog comparator characteristics Figure 36-41. AC current consumption vs. Vcc Low-power mode 147 85°C Current consumption [µA] 142 137 25°C 132 127 122 -40°C 117 112 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-42. AC current consumption vs. Vcc High speed mode 360 85°C Current consumption [µA] 350 340 25°C 330 320 310 -40°C 300 290 280 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 102 8387A–AVR–07/11 XMEGA A4U Figure 36-43. Analog comparator hysteresis vs. Vcc High-speed mode, small hysteresis 19 18 85°C -40°C 17 25°C VHYST [mV] 16 15 14 13 12 11 10 9 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-44. Analog comparator hysteresis vs. Vcc High-speed mode, large hysteresis 40 85°C 38 25°C -40°C 36 VHYST [mV] 34 32 30 28 26 24 22 20 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 103 8387A–AVR–07/11 XMEGA A4U Figure 36-45. Analog comparator propagation delay vs. Vcc High-speed mode 170 tPD [ns] 147 124 101 85°C 78 25°C -40°C 55 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 36-46. Analog comparator propagation delay vs. temperature High-speed mode. 170 1.6V tPD [ns] 147 124 101 2.7V 3.6V 78 55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 104 8387A–AVR–07/11 XMEGA A4U Figure 36-47. Analog comparator propagation delay vs. temperature Low-power mode 260 1.6V 250 240 tPD [ns] 230 220 210 200 2.7V 3.6V 190 180 170 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 36.10 ADC characteristics Figure 36-48. Gain Error vs. External VREF T = 25°C, VCC = 3.6V, ADC sampling speed = 500kSPS 3 Single-ended Signed Gain Error [mV] 2 1 Differential Mode 0 -1 Single-ended Unsigned -2 -3 -4 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF 105 8387A–AVR–07/11 XMEGA A4U Figure 36-49. Gain Error vs. VCC T = 25°C, VREF= External 1.0V, ADC sampling speed = 500kSPS 2.2 1.9 Single-ended Signed Gain Error [mV] 1.6 1.3 Differential Mode 1 0.7 0.4 Single-ended Unsigned 0.1 -0.2 -0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2.4 2.6 2.8 3 VCC [V] Figure 36-50. Offset Error vs. External VREF T = 25°C, VCC = 3.6V, ADC sampling speed = 500kSPS -1 1 1.2 1.4 1.6 1.8 2 2.2 Offset Error [mV] -1.1 -1.2 -1.3 -1.4 -1.5 Differential Mode -1.6 -1.7 -1.8 -1.9 -2 VREF [V] 106 8387A–AVR–07/11 XMEGA A4U Figure 36-51. Offset Error vs. VCC T = 25°C, VREF = External 1.0V, ADC sampling rate = 500kSPS. -0.3 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 -0.4 Offset Error [mV] -0.5 -0.6 -0.7 Differential Mode -0.8 -0.9 -1 -1.1 -1.2 VCC [V] Figure 36-52. Gain Error vs. Temperature VCC = 3.0V, VREF = External 2.0V 3 2 Gain Error [mV] Single-ended Signed 1 Differential Mode 0 -1 Single-ended Unsigned -2 -3 -4 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [ºC] 107 8387A–AVR–07/11 XMEGA A4U Figure 36-53. INL error vs. External VREF T = 25°C, VCC = 3.6V. 1.8 1.7 1.6 Differential Mode INL [LSB] 1.5 Single-ended Unsigned 1.4 1.3 1.2 1.1 1 0.9 Single-ended Signed 0.8 0.7 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 2.6 2.8 3 VREF [V] Figure 36-54. DNL error vs. External VREF T = 25°C, VCC = 3.6V 0.9 0.88 0.86 DNL [LSB] Differential Mode 0.84 Single-ended Signed 0.82 0.8 0.78 Single-ended Unsigned 0.76 0.74 0.72 1 1.2 1.4 1.6 1.8 2 2.2 2.4 VREF [V] 108 8387A–AVR–07/11 XMEGA A4U Figure 36-55. INL error vs. Sample Rate T = 25°C, VCC = 3.6V, VREF = 3.0V External Reference. 1.4 1.35 1.3 Differential Mode INL [LSB] 1.25 1.2 Single-ended Unsigned 1.15 1.1 1.05 Single-ended Signed 1 0.95 0.9 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 1850 2000 ADC Sample Rate [kSPS] Figure 36-56. DNL error vs. Sample Rate T = 25°C, VCC = 3.6V, VREF = 3.0V External Reference. 0.9 0.89 Differential Mode 0.88 DNL [LSB] 0.87 0.86 0.85 Single-ended Signed 0.84 0.83 0.82 0.81 Single-ended Unsigned 0.8 0.79 500 650 800 950 1100 1250 1400 1550 1700 ADC Sample Rate [kSPS] 109 8387A–AVR–07/11 XMEGA A4U 36.11 DAC characteristics Figure 36-57. DNL error vs. External VREF VCC = 3.6V 0.9 0.85 DNL 0.8 0.75 0.7 0.65 25ºC 0.6 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 36-58. INL error vs. External VREF VCC = 3.6V 1.9 1.8 INL [LSB] 1.7 1.6 1.5 1.4 1.3 1.2 25ºC 1.1 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] 110 8387A–AVR–07/11 XMEGA A4U 36.12 PDI characteristics Figure 36-59. Maximum PDI speed vs. Vcc 32 25°C -40°C 85°C 29.5 fMAX [MHz] 27 24.5 22 19.5 17 14.5 12 1.6 1.85 2.1 2.35 2.6 2.85 3.1 3.35 3.6 VCC [V] 36.13 Power-on reset characteristics Figure 36-60. Power-on reset threshold vs. temperature. 1.295 uBOD threshold [V] 1.285 Rising Vcc 1.275 Falling Vcc 1.265 1.255 1.245 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 111 8387A–AVR–07/11 XMEGA A4U Figure 36-61. Power-on reset current consumption vs. Vcc. 2000 -40°C 25°C 85°C 1800 1600 ICC [µA] 1400 1200 1000 800 600 400 200 0 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 VCC [V] 36.14 Bandgap and internal 1.0V characteristics Figure 36-62. Internal 1.0V reference voltage vs. temperature. 1.004 1.8V 2.2V 2.7V 3.2V 3.6V 1.002 Bandgap Voltage [V] 1 0.998 0.996 0.994 0.992 0.99 0.988 0.986 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 112 8387A–AVR–07/11 XMEGA A4U 36.15 Reset pin characteristics Figure 36-63. Minimum Reset Pulse vs. Vcc. 130 125 120 tRST [ns] 115 110 105 100 95 85°C 90 25°C -40°C 85 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 113 8387A–AVR–07/11 XMEGA A4U 37. Errata 37.1 37.1.1 ATxmega16A4U, ATxmega32A4U rev. E • CRC fails for Range CRC when end address is the last word address of a flash section • AWeX fault protection restore is not done correct in Pattern Generation Mode 1. CRC fails for Range CRC when end address is the last word address of a flash section If boot read lock is enabled, the range CRC cannot end on the last address of the application section. If application table read lock is enabled, the range CRC cannot end on the last address before the application table. Problem fix/Workaround Ensure that the end address used in Range CRC does not end at the last address before a section with read lock enabled. Instead, use the dedicated CRC commands for complete applications sections. 2. AWeX fault protection restore is not done correctly in Pattern Generation Mode When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation Mode (PGM), OUTOVEN should instead have been restored according to the DTILSBUF register. Problem fix/Workaround For CWCM no workaround is required. For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable the correct outputs again. For PGM in cycle-by-cycle mode there is no workaround. 37.1.2 rev. A - D Not sampled. 114 8387A–AVR–07/11 XMEGA A4U 38. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 38.1 8387A – 07/11 1. Initial revision. 115 8387A–AVR–07/11 XMEGA A4U Table of Contents Features ..................................................................................................... 1 Typical Applications ................................................................................ 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ................................................................................................... 5 3.1Block Diagram ...........................................................................................................6 4 Resources ................................................................................................. 7 4.1Recommended reading .............................................................................................7 5 Capacitive touch sensing ........................................................................ 7 6 AVR CPU ................................................................................................... 8 6.1Features ....................................................................................................................8 6.2Overview ...................................................................................................................8 6.3ALU - Arithmetic Logic Unit .......................................................................................9 6.4Program Flow ............................................................................................................9 6.5Register File ..............................................................................................................9 7 Memories ................................................................................................ 10 7.1Features ..................................................................................................................10 7.2Overview .................................................................................................................10 7.3Flash Program Memory ...........................................................................................11 7.4Data Memory ...........................................................................................................11 7.5Production Signature Row .......................................................................................12 7.6User Signature Row ................................................................................................13 7.7Flash and EEPROM Page Size ...............................................................................14 8 DMAC - Direct Memory Access Controller .......................................... 15 8.1Features ..................................................................................................................15 8.2Overview .................................................................................................................15 9 Event System ......................................................................................... 16 9.1Features ..................................................................................................................16 9.2Overview .................................................................................................................16 10 System Clock and Clock options ......................................................... 18 10.1Features ................................................................................................................18 i 8387A–AVR–07/11 XMEGA A4U 10.2Overview ...............................................................................................................18 10.3Clock Options ........................................................................................................19 11 Power Management and Sleep Modes ................................................. 21 11.1Features ................................................................................................................21 11.2Overview ...............................................................................................................21 11.3Sleep Modes .........................................................................................................21 12 System Control and Reset .................................................................... 23 12.1Features ................................................................................................................23 12.2Overview ...............................................................................................................23 12.3Reset Sources .......................................................................................................23 13 WDT - Watchdog Timer ......................................................................... 25 13.1Overview ...............................................................................................................25 14 Interrupts and Programmable Multi-level Interrupt Controller .......... 26 14.1Features ................................................................................................................26 14.2Overview ...............................................................................................................26 14.3Interrupt vectors ....................................................................................................26 15 I/O Ports .................................................................................................. 28 15.1Features ................................................................................................................28 15.2Overview ...............................................................................................................28 15.3Output Driver .........................................................................................................29 15.4Input sensing .........................................................................................................31 15.5Alternate Port Functions ........................................................................................31 16 T/C - 16-bit Timer/Counter ..................................................................... 32 16.1Features ................................................................................................................32 16.2Overview ...............................................................................................................32 17 AWeX - Advanced Waveform Extension .............................................. 34 17.1Features ................................................................................................................34 17.2Overview ...............................................................................................................34 18 Hi-Res - High Resolution Extension ..................................................... 35 18.1Features ................................................................................................................35 18.2Overview ...............................................................................................................35 19 RTC - 16-bit Real-Time Counter ............................................................ 36 19.1Features ................................................................................................................36 ii 8387A–AVR–07/11 XMEGA A4U 19.2Overview ...............................................................................................................36 20 USB - Universal Serial Bus Interface ................................................... 37 20.1Features ................................................................................................................37 20.2Overview ...............................................................................................................37 21 TWI - Two Wire Interface ....................................................................... 39 21.1Features ................................................................................................................39 21.2Overview ...............................................................................................................39 22 SPI - Serial Peripheral Interface ............................................................ 40 22.1Features ................................................................................................................40 22.2Overview ...............................................................................................................40 23 USART ..................................................................................................... 41 23.1Features ................................................................................................................41 23.2Overview ...............................................................................................................41 24 IRCOM - IR Communication Module .................................................... 42 24.1Features ................................................................................................................42 24.2Overview ...............................................................................................................42 25 AES and DES Crypto Engine ................................................................ 43 25.1Features ................................................................................................................43 25.2Overview ...............................................................................................................43 26 CRC - Cyclic Redundancy Check Generator ....................................... 44 26.1Features ................................................................................................................44 26.2Overview ...............................................................................................................44 27 ADC - 12-bit Analog to Digital Converter ............................................. 45 27.1Features ................................................................................................................45 27.2Overview ...............................................................................................................45 28 DAC - 12-bit Digital to Analog Converter ............................................. 47 28.1Features ................................................................................................................47 28.2Overview ...............................................................................................................47 29 AC - Analog Comparator ....................................................................... 48 29.1Features ................................................................................................................48 29.2Overview ...............................................................................................................48 30 Programming and Debugging .............................................................. 50 iii 8387A–AVR–07/11 XMEGA A4U 30.1Features ................................................................................................................50 30.2Overview ...............................................................................................................50 31 Pinout and Pin Functions ...................................................................... 51 31.1Alternate Pin Functions Description ......................................................................51 31.2Alternate Pin Functions .........................................................................................53 32 Peripheral Module Address Map .......................................................... 56 33 Instruction Set Summary ...................................................................... 57 34 Packaging information .......................................................................... 61 34.144A ........................................................................................................................61 34.244M1 .....................................................................................................................62 34.349C2 ......................................................................................................................63 35 Electrical Characteristics ...................................................................... 64 35.1Absolute Maximum Ratings* .................................................................................64 35.2DC Characteristics ................................................................................................64 35.3Operating Voltage and Frequency ........................................................................66 35.4Wakeup time from sleep ........................................................................................67 35.5I/O Pin Characteristics ...........................................................................................68 35.6ADC Characteristics .............................................................................................69 35.7DAC Characteristics .............................................................................................71 35.8Analog Comparator Characteristics .......................................................................72 35.9Bandgap and Internal 1.0V Reference Characteristics .........................................72 35.10Brownout Detection Characteristics ....................................................................73 35.11External Reset Characteristics ............................................................................73 35.12Power-on Reset Characteristics ..........................................................................73 35.13Flash and EEPROM Memory Characteristics .....................................................74 35.14Clock and Oscillator Characteristics ....................................................................74 35.15SPI Characteristics ..............................................................................................78 35.16Two-Wire Interface Characteristics .....................................................................80 36 Typical Characteristics .......................................................................... 82 36.1Active Supply Current ............................................................................................82 36.2Idle Supply Current ................................................................................................84 36.3Power-down Supply Current .................................................................................87 36.4Pin Pull-up .............................................................................................................88 36.5Pin Output Voltage vs. Sink/Source Current .........................................................90 iv 8387A–AVR–07/11 36.6Pin Thresholds and Hysteresis ..............................................................................94 36.7Bod characteristics ................................................................................................96 36.8Oscillators ..............................................................................................................97 36.9Analog comparator characteristics ......................................................................102 36.10ADC characteristics ...........................................................................................105 36.11DAC characteristics ...........................................................................................110 36.12PDI characteristics ............................................................................................111 36.13Power-on reset characteristics ..........................................................................111 36.14Bandgap and internal 1.0V characteristics ........................................................112 36.15Reset pin characteristics ...................................................................................113 37 Errata ..................................................................................................... 114 37.1ATxmega16A4U, ATxmega32A4U ......................................................................114 38 Datasheet Revision History ................................................................ 115 38.18387A – 07/11 .....................................................................................................115 Table of Contents....................................................................................... i Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 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Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 8387A–AVR–07/11