C8051F018 25 MIPS, 16 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU Analog Peripherals High-Speed 8051 µC Core - 10-Bit ADC - ±1 LSB INL; no missing codes Programmable throughput up to 100 ksps 8 external inputs; programmable as single-ended or differential Data-dependent windowed interrupt generator Built-in temperature sensor (±3 °C) - Memory - Two Comparators - 16 programmable hysteresis values Configurable to generate interrupts or reset - On-Chip JTAG Debug & Boundary Scan - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor Inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets IEEE1149.1 compliant boundary scan Supply Voltage: 2.8 to 3.6 V - Typical operating current: 12.5 mA at 25 MHz Multiple power saving sleep and shutdown modes - Clock Sources - SMBus Analog Power JTAG Logic 5-Chnl PCA Boundary Scan Debug HW Reset VDD Monitor External Oscillator Circuit XTAL1 XTAL2 WDT System Clock Internal Oscillator VREF VREF AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 A M U X CP0CP1- Lead-free package: C8051F018-GQ Standard package: C8051F018 SPI Bus RST CP1+ 64-pin TQFP (standard lead and lead-free packages) UART Digital Power TCK TMS TDI TDO CP0+ Internal programmable oscillator: 2–16 MHz External oscillator: Crystal, RC, C, or Clock Can switch between clock sources on-the-fly Ordering Part Numbers - AV+ AV+ AGND AGND 32 port I/O; all are 5 V tolerant Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports available concurrently Programmable 16-bit counter/timer array with five capture/compare modules 4 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Package Temperature Range: –40 to +85 °C VDD VDD VDD DGND DGND DGND 1280 bytes data RAM 16 kB Flash; in system programmamble in 512-byte sectors (512 bytes are reserved) Digital Peripherals Internal Voltage Reference VDD Monitor/Brown-out Detector - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler 8 0 5 1 C o r e 16 kB FLASH Timers 0,1,2 256 Byte RAM Timer 3 1024 Byte XRAM Port 0 Latch Port 1 Latch Port 2 Latch SFR Bus Port 3 Latch C R O S S B A R S W I T C H P 0 D r v P 1 D r v P 2 D r v P 3 D r v ADC 100 ksps (10-Bit) P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 NC NC TEMP SENSOR CP0 CP1 Precision Mixed Signal Copyright © 2005 by Silicon Laboratories 5.5.2005 C8051F018 25 MIPS, 16 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = –40 to +85 C°, VDD = 2.8 V unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Supply Voltage Supply Current Clock = 25 MHz (CPU active) Clock = 1 MHz Clock = 32 kHz Supply Current Oscillator not running (shutdown) Clock Frequency Range A/D CONVERTER Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Distortion Throughput Rate Input Voltage Range COMPARATORS Supply Current (each Comparator) Response Time | (CP+) – (CP-) | = 100 mV MIN TYP 2.8 MAX UNITS 3.6 V mA mA µA µA 25 MHz ±1 ±1 bits LSB LSB dB 100 VREF ksps V 12.5 0.5 20 10 DC 59 10 ±½ ±½ 61 0 1.3 4 µA µs C8051F005DK Development Kit Package Information D D1 MIN NOM MAX (mm) (mm) (mm) A E1 E - 1.20 A1 0.05 - 0.15 A2 0.95 - 1.05 b 64 PIN 1 DESIGNATOR 1 A2 e A b Precision Mixed Signal - 0.17 0.22 0.27 D - 12.00 - D1 - 10.00 - e - 0.50 - E - 12.00 - E1 - 10.00 - A1 Copyright © 2005 by Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders 5.5.2005