Freescale AN1241D Interfacing the mc68hc705j1a to 9356/9366 eeprom Datasheet

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AN1241
Interfacing the MC68HC705J1A to
9356/9366 EEPROMs
Freescale Semiconductor, Inc...
By Mark Glenewinkel
CSIC Applications
INTRODUCTION
This application note describes the hardware and software interface used to communicate between the
Freescale MC68HC705J1A MCU and 9356/9366 EEPROM chips. The 93XX series of EEPROMs are an
industry standard used widely to store nonvolatile bits of information. The software listing in this application
note will work with 9356 and 9366 EEPROMs. The EEPROM bits are arranged in 128 or 256 16-bit
registers, respectively. With some modification, the software will work with other 93XX series EEPROMs.
Some of the applications in which EEPROMs can be utilized are listed below.
•
ID number for remote addressing or security
•
Storage of telecommunication information like phone number recall and speed dialing
•
Power down information storage for consumer electronics like TVs and VCRs
•
Reprogrammable calibration data for test/measurement equipment
The 93XX EEPROMs communicate with the outside world using a serial link. Since the MC68HC705J1A
does not have the hardware on chip to communicate to the EEPROM, a software driver is used. This
method bit programs an I/O port to properly transfer data to and from the EEPROM. A National
NM93C56N was used for testing the software routines in this application note.
HARDWARE INTERFACE
The 9356 is a very simple 8-pin device. Appendix A shows a typical connection between the
MC68HC705J1A and the 9356. The serial interface connection uses only four pins of the 9356. They are
as follows:
•
CS — Chip Select
•
SK — Serial Clock
•
DO — Serial Data Output
•
DI
— Serial Data Input
These signals must be clocked in a certain way in order to transfer the correct serial data to and from the
MC68HC705J1A.
©MOTOROLA, INC., 1995
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SOFTWARE INTERFACE
Communication between the MC68HC705J1A and the 9356 is done with a synchronous serial protocol. As
mentioned earlier, the MC68HC705J1A bit programs its I/O pins to communicate with the 9356. A timing
diagram of the serial link can be found in the 9356 data sheet if needed.
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The 9356 will accept seven different commands. They are as follows:
1)
READ —
Read a 16-bit data word from an address in memory
2)
WRITE —
Write a 16-bit data word from an address in memory
3)
WRALL —
Write all addresses with the same 16-bit data word
4)
ERASE —
Erase a 16-bit data word from an address in memory
5)
ERAL
—
Erase all addresses within the memory map
6)
WEN
—
Erase/write enable the EEPROM memory
7)
WDS
—
Erase/write disable the EEPROM memory
The 9356 transmission format is a frame of data bits containing an opcode, an address, and if needed, a
word of data. The opcode is three bits long, the address is eight bits long, and the data word is 16 bits long.
Table 1 illustrates the bit information each instruction needs.
Table 1.
Instruction
Opcode
Address
Data
READ
110
A7–A0
WEN
100
11XXXXXX
ERASE
111
A7–A0
ERAL
100
10XXXXXX
WRITE
101
A7–A0
D15–D0
WRALL
100
01XXXXXX
D15–D0
WDS
100
00XXXXXX
IMPLEMENTATION AND TEST
Software was written to provide subroutines to perform each of the seven commands. A total of four bytes
of RAM are needed to support the subroutines. These bytes are described below.
1)
OP_CODE — Contains the opcode needed for the command
2)
ADDR
— Contains the address for the command
3)
DATA_H
— The high byte for the data word
4)
DATA_L
— The low byte for the data word
As needed, each EEPROM command subroutine will call other supporting subroutines to execute the
transmission of data between the MC68HC705J1A and the 9356. Appendix B contains flowcharts for all of
these subroutines.
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Each EEPROM command subroutine has input data and output data. This data is inherent with some
commands while others need the information passed to them before the subroutine is called. Table 2 lists
the input data needed and output data generated for each of the seven commands.
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Table 2:
Command
Subroutine Input
Subroutine Output
READ
ADDR
DATA_H/L
EWEN
—
—
ERASE
ADDR
—
ERAL
—
—
WRITE
ADDR & DATA_H/L
—
WRALL
DATA_H/L
—
EWDS
—
—
Code was written and tested with a level of quality equal to the Carnegie-Mellon Software Engineering
Institute (SEI) Level 2. A test routine consisting of writing and reading the EEPROM is listed in Appendix C.
Refer to Appendix A for the schematic used in the design and test of the software. An LED is used to verify
that the test code works properly. The test routine executes the following:
1)
Initializes the port on the HC705J1A for serial transmission. LED is turned off.
2)
Writes EEPROM address $00 with $AA55.
3)
Writes EEPROM address $20 with $1234.
4)
Reads EEPROM address $00 and stores it to RAM location TEST1 and TEST2.
5)
Reads EEPROM address $20 and stores it to RAM location TEST3 and TEST4.
6)
Checks if TEST1 = $AA, TEST2 = $55, TEST3 = $12, and TEST4 = $34.
7)
If check is good, then light the LED. If check is bad, do not light the LED.
8)
Continue to run in an infinite loop until reset.
For increased reliability, the software watchdog on the MC68HC705J1A is used. Also, a low voltage inhibit
circuit, the MC34064, is used to decrease susceptibility to brown out or short power failure conditions.
SUMMARY
This application note has described the interface needed to successfully communicate between the
MC68HC705J1A and the 9356. For more information on the MC68HC705J1A, please consult the
Technical Data Manual, MC68HC705J1A/D. Contact National Semiconductor or SGS Thompson for
technical data on the 93XX series of EEPROM memories.
An electronic copy of the code listing in Appendix C and a listing of the test program to fully test all the
EEPROM commands can be found on the Freescale MCU BBS. The BBS number is (512) 891-3733. The
filename is j1a_9356.arc and is on the CSIC BBS under the APPNOTES directory.
Also, Freescale Application Note AN1221/D further details the software and hardware interfaces needed
between the 93XX series and other HC05 MCUs.
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APPENDIX A
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AN1241/D
AN1241/D
GND
VDD
3
2
VDD
U3
INPUT
RESET
GND
MC34064
1
GND
VDD
8
7
6
5
4
3
19
20
9
10
C1
0.1uF
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
OSC1
PB3
OSC2
PB4
PB5
MC68HC705J1AP
IRQ/VPP
RESET
U1
VDD
VSS
1
2
18
17
16
15
14
13
12
11
GND
2
X1
CER RES
3
1
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-->
-->
-->
<--
1
2
3
4
D1
LED
R1
390
VDD
U2
VCC
CS
NC
SK
DI
NC
DO
GND
NM93C56N
VDD
GND
8
7
6
5
HC705J1A -> 93C56 EEPROM
Size Document Number
A
705J1A.SCH
Date:
February
1 of
9, 1995 Sheet
Title
Freescale- CSIC Strategic Applications
CHIP_SELECT
SERIAL_CLOCK
SERIAL_OUT
SERIAL_IN
HC705J1A to 93C56 Interface
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REV
1
1
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APPENDIX B
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MAIN ROUTINE TEST
INITIALIZE PORT A
FOR BIT
PROGRAMMING
LED IS OFF
ADDR = $20
JSR J9356_EWEN
ERASE/WRITE
ENABLE THE EEPROM
JSR J9356_READ
READ DATA FROM
EEPROM ADDRESS
JSR J9356_ERAL
ERASE ALL THE
EEPROM
TEST3 = DATA_H
TEST4 = DATA_L
ADDR = $00
DATA_H = $AA
DATA_L = $55
TEST1 =
$AA?
NO
YES
JSR J9356_WRITE
WRITE DATA TO
EEPROM ADDRESS
ADDR = $00
DATA_H = $12
DATA_L = $34
TEST2 =
$55?
NO
YES
JSR J9356_WRITE
WRITE DATA TO
EEPROM ADDRESS
TEST3 =
$12?
YES
TEST4 =
$34?
ADDR = $00
NO
NO
YES
6
JSR J9356_READ
READ DATA FROM
EEPROM ADDRESS
LED IS ON
TEST PASSED
TEST1 = DATA_H
TEST2 = DATA_L
KICK THE
WDOG
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J9356_EWDS
J9356_EWEN
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OPCODE = $80
ADDR = $00
CS = 1
OPCODE = $80
ADDR = $C0
CS = 1
J9356_WRITE
J9356_WRAL
OPCODE = $A0
CS =1
OPCODE = $80
ADDR = $40
CS = 1
JSR J9356_WR_OP
WRITE THE
OPCODE
JSR J9356_WR_OP
WRITE THE
OPCODE
JSR J9356_WR_ADDR
WRITE THE
ADDRESS
JSR J9356_WR_ADDR
WRITE THE
ADDRESS
CS = 0
JSR J9356_WR_DATA
WRITE THE
DATA
RTS
SER_OUT = 0
CS = 0
JSR J9356_WAIT
WAIT UNTIL EEPROM
IS READY
RTS
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J9356_ERASE
J9356_ERAL
J9356_READ
OPCODE = $E0
CS =1
OPCODE = $80
ADDR = $80
CS = 1
OPCODE = $C0
CS =1
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JSR J9356_WR_OP
WRITE THE
OPCODE
JSR J9356_WR_ADDR
WRITE THE
ADDRESS
JSR J9356_WR_ADDR
WRITE THE
ADDRESS
CLOCK
SER_CLK
CS = 0
JSR J9356_WAIT
WAIT UNTIL EEPROM
IS READY
RTS
JSR J9356_WR_OP
WRITE THE
OPCODE
JSR J9356_RD_DATA
READ THE
ADDRESS
SER_OUT = 0
CS = 0
RTS
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J9356_WR_OP
J9356_WR_ADDR
J9356_WR_DATA
X=3
X=8
X=16
PUT BIT 7 OF
OPCODE
ON SER_OUT
SHIFT LEFT
OPCODE
X = X-1
PUT BIT 7 OF
OPCODE
ON SER_OUT
SHIFT LEFT ADDR
X = X-1
PUT BIT 7 OF
DATA_H ON
SER_OUT
SHIFT LEFT DATA_L
SHIFT LEFT DATA_H
X = X-1
NO
X = 0?
NO
X = 0?
YES
YES
KICK THE
WDOG
NO
X = 0?
YES
RTS
RTS
J9356_WAIT
RTS
J9356_RD_DATA
CS = 1
X=16
KICK THE
WDOG
READ SER_IN
PUT IN C BIT
ROTATE LEFT
DATA_L
ROTATE LEFT
DATA_H
X = X-1
EEPROM
READY?
SER_IN = 0?
YES
NO
NO
X = 0?
CS = 0
YES
RTS
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RTS
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APPENDIX C
*****************************************************************************
*****************************************************************************
*
*
*
Main Routine J1A_9356 - 705J1A to 9356 EEPROM
*
*
*
*****************************************************************************
*
*
* File Name: J1A_9356.RTN
Copyright (c) Motorola 1995
*
*
*
* Full Functional Description Of Routine Design:
*
*
Program flow:
*
*
Reset: Initializes ports for bit banging.
*
*
Calls EWEN sub to enable write to EEPROM.
*
*
Calls ERAL to erase all EEPROM
*
*
Writes $AA55 to EEPROM $00
*
*
Writes $1234 to EEPROM $20
*
*
Reads EEPROM $00 and $20
*
*
Check for correct data, light LED if correct
*
*
Execute endless loop
*
*
*
*****************************************************************************
*
*
*
Part Specific Framework Includes Section
*
*
*
*****************************************************************************
#nolist
#INCLUDE 'H705J1A.FRK'
;Include the equates for the HC705J1A
;so that all labels can be used.
#list
*****************************************************************************
*
*
*
MOR Bytes Definitions for Main Routine
*
*
*
*****************************************************************************
org
db
10
MOR
$21
;COP enabled, osc resistor enabled
;If used on a mask rom part,
; be sure to specify this option.
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*****************************************************************************
*
*
*
*
Equates and RAM Storage
*
*
*
*****************************************************************************
*
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CS
SER_CLK
SER_OUT
SER_IN
***
equ
equ
equ
equ
0
1
2
3
RAM storage variables
OPCODE
ADDR
DATA_H
DATA_L
TEST1
TEST2
TEST3
TEST4
org
rmb
rmb
rmb
rmb
rmb
rmb
rmb
rmb
RAM
1
1
1
1
1
1
1
1
;bit
;bit
;bit
;bit
#
#
#
#
for
for
for
for
chip select
serial clock
serial data out
serial data in
***
;start of static RAM at $C0
;command byte
;EEPROM address byte
;MSByte of data
;LSByte of data
;test byte #1
;test byte #2
;test byte #3
;test byte #4
*****************************************************************************
*
*
*
*
Program Initialization
*
*
*
* This section sets up the port for bit banging.
*
*
*
* To prevent floating inputs and associated high current draw,
*
* the HC705J1A has pulldown devices on all I/O pins. This
*
* initialization should enable these pulldowns on unused I/O
*
* pins. RESET_ enables the pulldowns, so no code is required.
*
*
*
*****************************************************************************
*
J9356_START
AN1241/D
org
lda
sta
sta
lda
sta
EPROM
#$80
PORTA
COPR
#$87
DDRA
;init portA
;
;kick the wdog
;init i/o of port A
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*****************************************************************************
*
*
*
J1A_9356 Main Program Loop
*
*
*
* It then runs through the test routine to check for
*
* proper serial transmission. The LED is lit if the test passes.
*
*
*
*****************************************************************************
***
Enable erase/write mode of EEPROM
jsr
J9356_EWEN
;call ewen routine
***
Erase all EEPROM memory map
jsr
J9356_ERAL
***
***
***
Write $AA55 to $00
lda
#$00
sta
ADDR
lda
#$AA
sta
DATA_H
lda
#$55
sta
DATA_L
jsr
J9356_WRITE
Write $1234 to $20
lda
#$20
sta
ADDR
lda
#$12
sta
DATA_H
lda
#$34
sta
DATA_L
jsr
J9356_WRITE
;load data byte high
;load data byte low
;call write routine
;load address
;load data byte high
;load data byte low
;call write routine
#$00
ADDR
J9356_READ
DATA_H
TEST1
DATA_L
TEST2
;load address
#$20
ADDR
J9356_READ
DATA_H
TEST3
DATA_L
TEST4
;load address
;call read routine
;store away data_h to test1
;store away data_l to test2
Read $20
lda
sta
jsr
lda
sta
lda
sta
12
;load address
Read $00
lda
sta
jsr
lda
sta
lda
sta
***
;call eral routine
;call read routine
;store away data_h to test3
;store away data_l to test4
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***
Check results of write and read, light LED if good
J9356_CKSUM
lda
TEST1
;check test1
cmpa
#$AA
bne
J9356_BRANCH
;branch if no good, no LED
J9356_BRANCH
AN1241/D
lda
cmpa
bne
TEST2
#$55
J9356_BRANCH
;check test2
lda
cmpa
bne
TEST3
#$12
J9356_BRANCH
;check test3
lda
cmpa
bne
TEST4
#$34
J9356_BRANCH
;check test4
bclr
7,PORTA
;EEPROM write and read is good
; light LED
clra
sta
bra
COPR
J9356_BRANCH
;kick the wdog
;branch if no good, no LED
;branch if no good, no LED
;branch if no good, no LED
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*****************************************************************************
*
*
*
EEPROM Command SubRoutines
*
*
*
* These 7 subroutines execute each of the 7 commands
*
* that the EEPROM will respond to
*
*
*
*****************************************************************************
***
EWEN - subroutine to enable write/erase ******************************
J9356_EWEN
lda
#$80
;load opcode
sta
OPCODE
lda
#$C0
;load address
sta
ADDR
bset
CS,PORTA
;CS line is high
jsr
J9356_WR_OP
;write opcode
jsr
J9356_WR_ADDR
;write address
bclr
CS,PORTA
;CS line is low
rts
;return
***
EWDS - subroutine to disable write/erase *****************************
J9356_EWDS
lda
#$80
;load opcode
sta
OPCODE
clr
ADDR
;load addr
bset
CS,PORTA
;CS line is high
jsr
J9356_WR_OP
;write opcode
jsr
J9356_WR_ADDR
;write address
bclr
CS,PORTA
;CS line is low
rts
;return
***
WRITE - subroutine to write EEPROM ***********************************
J9356_WRITE
lda
#$A0
;load opcode
sta
OPCODE
bset
CS,PORTA
;CS line is high
jsr
J9356_WR_OP
;write opcode
jsr
J9356_WR_ADDR
;write address
jsr
J9356_WR_DATA
;write data
bclr
SER_OUT,PORTA
bclr
CS,PORTA
;CS line is low
jsr
J9356_WAIT
;wait until EEPROM is ready
rts
;return
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***
WRAL - subroutine to write all EEPROM ********************************
J9356_WRAL
lda
#$80
;load opcode
sta
OPCODE
lda
#$40
;load addr
sta
ADDR
bset
CS,PORTA
;CS line is high
jsr
J9356_WR_OP
;write opcode
jsr
J9356_WR_ADDR
;write address
jsr
J9356_WR_DATA
;write data
bclr
SER_OUT,PORTA
bclr
CS,PORTA
;CS line is low
jsr
J9356_WAIT
;wait until EEPROM is ready
rts
;return
***
READ - subroutine to read EEPROM *************************************
J9356_READ
lda
#$C0
;load opcode
sta
OPCODE
bset
CS,PORTA
;CS line is high
jsr
J9356_WR_OP
;write opcode
jsr
J9356_WR_ADDR
;write address
bset
SER_CLK,PORTA
;clock the EE
bclr
SER_CLK,PORTA
jsr
J9356_RD_DATA
;read data
bclr
SER_OUT,PORTA
bclr
CS,PORTA
;CS line is low
rts
;return
***
ERASE - subroutine to erase EEPROM ***********************************
J9356_ERASE
lda
#$E0
;load opcode
sta
OPCODE
bset
CS,PORTA
;CS line is high
jsr
J9356_WR_OP
;write opcode
jsr
J9356_WR_ADDR
;write address
bclr
CS,PORTA
;CS line is low
jsr
J9356_WAIT
;wait until EEPROM is ready
rts
***
ERAL - subroutine to erase all EEPROM ********************************
J9356_ERAL
lda
#$80
;load opcode and addr
sta
OPCODE
sta
ADDR
bset
CS,PORTA
;CS line is high
jsr
J9356_WR_OP
;write opcode
jsr
J9356_WR_ADDR
;write address
bclr
CS,PORTA
;CS line is low
jsr
J9356_WAIT
;wait until EEPROM is ready
rts
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*****************************************************************************
*
*
*
EEPROM Supporting SubRoutines
*
*
*
* These subroutines support the functions called from the Command subs
*
*
*
*****************************************************************************
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***
Subroutine to write 3 bit opcode ************************************
J9356_WR_OP
ldx
#3T
;init counter for LOOP1
*
Write to the serial output pin
J9356_LOOP1
brclr
7,OPCODE,J9356_L1_2
;if opcode bit7 = 0, goto L1_2
bset
SER_OUT,PORTA
;ser_out = 1
bra
J9356_L1_3
;goto L1_3
J9356_L1_2
bclr
SER_OUT,PORTA
;ser_out = 0
*
Clock the serial clock pin
J9356_L1_3
bset
SER_CLK,PORTA
bclr
SER_CLK,PORTA
asl
OPCODE
decx
bne
J9356_LOOP1
clra
sta
COPR
rts
;ser_clk = 1
;ser_clk = 0
;rotate the opcode
;decrease counter loop
;is LOOP1 finished?
;kick the wdog
;return
*** Subroutine to write 8 bit address ****************************************
J9356_WR_ADDR
ldx
#8T
;init counter for LOOP2
*
Write to the serial output pin
J9356_LOOP2
brclr
7,ADDR,J9356_L2_2
;if addr bit7 = 0, goto L2_2
bset
SER_OUT,PORTA
;ser_out = 1
bra
J9356_L2_3
;goto L2_3
J9356_L2_2
bclr
SER_OUT,PORTA
;ser_out = 0
*
Clock the serial clock pin
J9356_L2_3
bset
SER_CLK,PORTA
bclr
SER_CLK,PORTA
asl
ADDR
decx
bne
J9356_LOOP2
rts
16
;ser_clk = 1
;ser_clk = 0
;rotate the addr
;decrease counter loop
;is LOOP2 finished?
;return
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*** Subroutine to write 16 bit data ******************************************
J9356_WR_DATA
ldx
#16T
;init counter for LOOP4
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*
Write the serial output pin with data
J9356_LOOP4
brclr
7,DATA_H,J9356_L4_2
;if addr bit7 = 0, goto L4_2
bset
SER_OUT,PORTA
;ser_out = 1
bra
J9356_L4_3
;goto L4_3
J9356_L4_2
bclr
SER_OUT,PORTA
;ser_out = 0
*
Clock the serial clock pin
J9356_L4_3
bset
SER_CLK,PORTA
bclr
SER_CLK,PORTA
asl
DATA_L
rol
DATA_H
decx
bne
J9356_LOOP4
rts
;ser_clk = 1
;ser_clk = 0
;rotate the DATA_L
;rotate the DATA_H
;decrease counter loop
;is LOOP4 finished?
;return
***
Subroutine to read 16 bit data ***************************************
J9356_RD_DATA
ldx
#16T
;init counter for LOOP3
*
Read the serial
J9356_LOOP3
brclr
J9356_L3
rol
rol
*
input pin
SER_IN,PORTA,J9356_L3 ;carry bit = serial in
DATA_L
;rotate left result
DATA_H
Clock the serial clock pin
bset
SER_CLK,PORTA
bclr
SER_CLK,PORTA
decx
bne
J9356_LOOP3
rts
;ser_clk = 1
;ser_clk = 0
;decrease counter loop
;is LOOP3 finished?
;return
*
Wait until write cycle is over
J9356_WAIT
bset
CS,PORTA
;CS line is high
J9356_W2
clra
sta
COPR
;kick the wdog
brclr
SER_IN,PORTA,J9356_W2
bclr
CS,PORTA
;CS line is low
rts
;return
AN1241/D
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17
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*****************************************************************************
*
*
*
Interrupt and Reset vectors for Main Routine
*
*
*
*****************************************************************************
RESET
J9356_START
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org
fdb
18
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AN1241/D
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NOTES
AN1241/D
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NOTES
20
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AN1241/D
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