ICS557-05A Quad Differential PCI-Express Clock Source Description Features The ICS557-05A is a spread-spectrum clock generator that supports PCI-Express requirements. It is used in PC or embedded systems to substantially reduce electro-magnetic interference (EMI). The device provides four differential HCSL or LVDS high-frequency outputs with spread spectrum capability. The output frequency and spread type are selectable using external pins. • • • • • • • • • • • Packaged in 20-pin TSSOP Available in Pb (lead) free package Supports PCI-Express applications Four differential spread spectrum clock outputs Spread spectrum for EMI reduction Uses external 25 MHz clock or crystal input Power down pin turns off chip OE control tri-states outputs Spread and frequency selection via external pins Spread Bypass option available Industrial temperature range available Block Diagram VDD 2 SEL[2:0] Spread Spectrum/ Output clock selection 3 PD OE Spread Spectrum Circuitry CLKOUTA 25 MHz crystal or clock X1 CLKOUTA CLKOUTB Clock Oscillator PLL Clock Synthesis X2 CLKOUTB CLKOUTC CLKOUTC CLKOUTD CLKOUTD Optional tuning crystal capacitors 2 Rr(IREF) GND 1 MDS 557-05A E Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Quad Differential PCI-Express Clock Source Pin Assignment VDDXD 1 20 CLKA S0 2 19 CLKA S1 3 18 CLKB S2 4 17 CLKB X1 5 16 GNDODA X2 6 15 VDDODA PD 7 14 CLKC OE 8 13 CLKC GNDXD 9 12 CLKD 10 11 CLKD IREF 20-pin (173 mil) TSSOP Spread Spectrum Selection Table S2 S1 S0 Spread% Spread Type Output Frequency (MHz) 0 0 0 -0.5 Down 100 0 0 1 -1.0 Down 100 0 1 0 -1.5 Down 100 0 1 1 No Spread Not Applicable 100 1 0 0 -0.5 Down 200 1 0 1 -1.0 Down 200 1 1 0 -1.5 Down 200 1 1 1 No Spread Not Applicable 200 2 MDS 557-05A E Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Quad Differential PCI-Express Clock Source Pin Descriptions Pin Pin Name Pin Type 1 VDDXD Power Connect to +3.3 V digital supply. 2 S0 Input Spread spectrum select pin #0. See table above. Internal pull-up resistor. 3 S1 Input Spread spectrum select pin #1. See table above Internal pull-up resistor. 4 S2 Input Spread spectrum select pin #2. See table above. Internal pull-up resistor. 5 X1 Input Crystal connection. Connect to a fundamental mode crystal or clock input. 6 X2 Output Crystal connection. Connect to a fundamental mode crystal or leave open. 7 PD Input Powers down all PLL’s and tri-states outputs when low. Internal pull-up resistor. 8 OE Input Provides output on, tri-states output (High = enable outputs; Low = disable outputs). Internal pull-up resistor. Pin Description 9 GND Power Connect to digital ground. 10 IREF Output Precision resistor attached to this pin is connected to the internal current reference. 11 CLKD Output Selectable 100/200 MHz spread spectrum differential Compliment output clock D. 12 CLKD Output Selectable 100/200 MHz spread spectrum differential True output clock D. 13 CLKC Output Selectable 100/200 MHz spread spectrum differential Compliment output clock C. 14 CLKC Output Selectable 100/200 MHz spread spectrum differential True output clock C. 15 VDDODA Power Connect to +3.3 V analog supply. 16 GND Power Connect to analog ground. 17 CLKB Output Selectable 100/200 MHz spread spectrum differential Compliment output clock B. 18 CLKB Output Selectable 100/200 MHz spread spectrum differential True output clock B. 19 CLKA Output Selectable 100/200 MHz spread spectrum differential Compliment output clock A. 20 CLKA Output Selectable 100/200 MHz spread spectrum differential True output clock A. 3 MDS 557-05A E Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Quad Differential PCI-Express Clock Source Application Information Decoupling Capacitors Load Resistors RL As with any high-performance mixed-signal IC, the ICS557-05A must be isolated from system power supply noise to perform optimally. Since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. Output Termination PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. The PCI-Express differential clock outputs of the ICS557-05A are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-05A can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS557-05A. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 µF should be connected between VDD and GND pairs (1,9 and 15,16) as close to the device as possible. On chip capacitors- Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value (in pf) of these crystal caps equal (CL-12)*2 in this equation, CL=crystal load capacitance in pf. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 8 pF. [(16-12)x2]=8. Current Reference Source Rr (Iref) If board target trace impedance (Z) is 50Ω, then Rr = 475Ω (1%), providing IREF of 2.32 mA, output current (IOH) is equal to 6*IREF. 4 MDS 557-05A E Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Quad Differential PCI-Express Clock Source Output Structures 6*IREF IREF =2.3 mA R R 475Ω See Output Termination Sections - Pages 3 ~ 5 General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-05A.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. 5 MDS 557-05A E Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Quad Differential PCI-Express Clock Source PCI-Express Layout Guidelines Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. RS RT Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Differential Routing on a Single PCB L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Unit inch inch Differential Routing to a PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch PCI-Express Device Routing L1 L2 L4 RS L1’ L4’ L2’ RS RT ICS557-05A Output Clock L3’ RT PCI-Express Load or Connector L3 Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 500 ps 500 ps 0.52 V 0.175 V 0.52 V 0.175 V 6 MDS 557-05A E Integrated Circuit Systems, Inc. tOF ● 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Quad Differential PCI-Express Clock Source LVDS Compatible Layout Guidelines LVDS Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. RP RQ RT L3 length, Route as coupled 50 ohm differential trace. L3 length, Route as coupled 50 ohm differential trace. Dimension or Value 0.5 max 0.2 max 100 100 150 Unit inch inch ohm ohm ohm LVDS Device Routing L1 L3 RQ L1’ RT ICS557-05A Clock Output RP L3’ RT L2’ LVDS Device Load L2 Typical LVDS Waveform 1325 mV 1000 mV tOR 500 ps 500 ps 1250 mV 1150 mV 1250 mV 1150 mV 7 MDS 557-05A E Integrated Circuit Systems, Inc. tOF ● 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Quad Differential PCI-Express Clock Source Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-05A. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD, VDDA 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70°C Ambient Operating Temperature (industrial) -40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C ESD Protection (Input) 2000 V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C Parameter Symbol Supply Voltage Conditions V 1 Min. Typ. Max. 3.135 3.465 Units Input High Voltage VIH 2.0 VDD +0.3 V Input Low Voltage1 VIL VSS-0.3 0.8 V Input Leakage Current2 IIL 0 < Vin < VDD -5 5 µA Operating Supply Current IDD 50Ω, 2pF load@ 100MHz Input Capacitance Output Capacitance 105 mA IDDOE OE =Low 40 mA IDDPD No load, PD =Low 500 µA CIN COUT Input pin capacitance 7 pF Output pin capacitance 6 pF Pin Inductance LPIN Output Resistance Rout CLK outputs Pull-up Resistance RPUP OE, SEL, PD pins 5 1 Single edge is monotonic when transitioning through 2 Inputs with pull-ups/-downs are not included. ● nH kΩ 110 kΩ region. 8 MDS 557-05A E Integrated Circuit Systems, Inc. 3.0 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Quad Differential PCI-Express Clock Source AC Electrical Characteristics - CLKOUTA/CLKOUTB Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85°C Parameter Symbol Conditions Min. Input Frequency Typ. Max. 25 Output Frequency MHz HCSL termination 200 MHz LVDS termination 100 MHz 850 mV 1,2 Output High Voltage VOH 660 700 Output Low Voltage1,2 VOL -150 0 250 350 Crossing Point Voltage1,2 Absolute Crossing Point Voltage1,2,4 Variation over all edges Jitter, Cycle-to-Cycle1,3 Rise Time1,2 1,2 Fall Time mV 550 mV 140 mV 60 Modulation Frequency Units ps Spread spectrum 30 31.5 33 kHz tOR From 0.175 V to 0.525 V 175 332 700 ps tOF From 0.525 V to 0.175 V 175 344 700 ps Skew between outputs At crossing point Voltage Duty Cycle1,3 45 50 ps 55 % 5 All outputs 10 us 5 All outputs 10 us Output Enable Time Output Disable Time Power-up Time tSTABLE Spread Change Time tSPREAD Settling period after spread change From power-up VDD=3.3 V 3.0 ms 3.0 ms 1 Test setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%). 2 Measurement taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is low. asserted. CLKOUT is driven differential when OE is high unless its PD= low. Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Min. Typ. Max. Units θJA Still air 93 °C/W θJA 1 m/s air flow 78 °C/W θJA 3 m/s air flow 65 °C/W 20 °C/W θJC 9 MDS 557-05A E Integrated Circuit Systems, Inc. Conditions ● 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Quad Differential PCI-Express Clock Source PCI-Express Layout Guidelines Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. RS RT Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Differential Routing on a Single PCB L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Unit inch inch Differential Routing to a PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch PCI-Express Device Routing L1 L2 L4 RS L1’ L4’ L2’ RS RT ICS557-03 Output Clock L3’ RT PCI-Express Load or Connector L3 Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 500 ps 0.52 V 0.175 V tOF 0.52 V 0.175 V 10 MDS 557-05A E Integrated Circuit Systems, Inc. 500 ps ● 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Quad Differential PCI-Express Clock Source Package Outline and Package Dimensions (20-pin TSSOP, 173 mil Body) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters 20 Symbol E1 E INDEX AREA 1 2 D Max 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max 0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.252 0.260 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 *For reference only. Controlling dimensions in mm. A A2 Min A A1 A2 b c D E E1 e L α aaa Inches* A1 c -Ce SEATING PLANE b L aaa C 11 MDS 557-05A E Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com ICS557-05A Quad Differential PCI-Express Clock Source Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS557G-05A ICS557G-05A Tubes 20-pin TSSOP 0 to +70°C ICS557G-05ATR ICS557G-05A Tape and Reel 20-pin TSSOP 0 to +70°C ICS557G-05ALF 557G-05ALF Tubes 20-pin TSSOP 0 to +70°C ICS557G-05ALFTR 557G-05ALF Tape and Reel 20-pin TSSOP 0 to +70°C ICS557GI-05A 557GI-05A Tubes 20-pin TSSOP -40 to +85°C ICS557GI-05ATR 557GI-05A Tape and Reel 20-pin TSSOP -40 to +85°C ICS557GI-05ALF 557GI05ALF Tubes 20-pin TSSOP -40 to +85°C ICS557GI-05ALFTR 557GI05ALF Tape and Reel 20-pin TSSOP -40 to +85°C Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 12 MDS 557-05A E Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 011606 ● tel (408) 297-1201 ● www.icst.com