Product Folder Sample & Buy Support & Community Tools & Software Technical Documents DAC8811 SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 DAC8811 16-Bit, Serial Input Multiplying Digital-to-Analog Converter 1 • • • • • • • 1 • • • • • • • • 2 • • • • Features 3 ±0.5 LSB DNL 16-Bit Monotonic ±1 LSB INL Low Noise: 12 nV/√Hz Low Power: IDD = 2 µA 2.7-V to 5.5-V Analog Power Supply 2-mA Full-Scale Current ±20%, with VREF = 10 V 50-MHz Serial Interface 0.5-μs Settling Time 4-Quadrant Multiplying Reference Reference Bandwidth: 10 MHz ±10-V Reference Input Reference Dynamics: –105 THD Tiny 8-Lead 3 × 3 mm VSON and 3 × 5 mm VSSOP Packages Industry-Standard Pin Configuration Description The DAC8811 multiplying digital-to-analog converter (DAC) is designed to operate from a single 2.7-V to 5.5-V supply. The applied external reference input voltage VREF determines the full-scale output current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale output when combined with an external I-to-V precision amplifier. A serial data interface offers high-speed, three-wire microcontroller-compatible inputs using data-in (SDI), clock (CLK), and chip-select (CS). On power-up, the DAC register is filled with zeroes, and the DAC output is at zero scale. The DAC8811 is packaged in space-saving 8-lead VSON and VSSOP packages. Device Information(1) PART NUMBER DAC8811 Applications PACKAGE BODY SIZE (NOM) VSSOP (8) 3.00 mm × 3.00 mm VSON (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Automatic Test Equipment Instrumentation Digitally Controlled Calibration Industrial Control PLCs Simplified Schematic DAC8811 RFB VDD D/A Converter VREF Power-On Reset CS IOUT 16 DAC Register 16 CLK SDI Shift Register GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC8811 SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 1 1 1 2 4 4 5 Absolute Maximum Ratings ..................................... 5 ESD Ratings ............................................................ 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics........................................... 6 Timing Requirements ................................................ 7 Typical Characteristics: VDD = 5 V........................... 8 Typical Characteristics: VDD = 2.7 V...................... 10 Detailed Description ............................................ 11 8.1 Overview ................................................................ 11 8.2 Functional Block Diagram ....................................... 11 8.3 Feature Description................................................. 11 8.4 Device Functional Mode ......................................... 14 8.5 Programming........................................................... 15 9 Application and Implementation ........................ 16 9.1 Application Information............................................ 16 9.2 Typical Application ................................................. 16 10 Power Supply Recommendations ..................... 17 11 Layout................................................................... 18 11.1 Layout Guidelines ................................................. 18 11.2 Layout Example .................................................... 18 12 Device and Documentation Support ................. 19 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 19 13 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (October 2015) to Revision D Page • Changed the DAC8811 Timing Diagram image to show the setup and hold time with respect to rising edge .................... 7 • Changed two instances of falling to rising in the DAC8811 Input Shift Register section ..................................................... 15 • Changed the SYNC Interrupt Facility image ........................................................................................................................ 15 Changes from Revision B (February 2007) to Revision C Page • Added ESD Ratings table, Recommended Operating Conditions table, Thermal Information table, Timing Requirements table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sections. .............................................................................................. 1 • Changed R3' From: 50 kΩ To: 50 Ω in Figure 23 ................................................................................................................ 14 Changes from Revision A (December 2004) to Revision B Page • Added a new paragraph to the Description , "On power-up,..." ............................................................................................. 1 • Changed the Simplified Schematic to include the Power-On Reset ...................................................................................... 1 • Added VREF, RFB to GND to the Absolute Maximum Ratings ................................................................................................ 5 • Changed the ESD rating of HBM From: 1500 To: 4000 in the Absolute Maximum Ratings ................................................ 5 • Added table note: " All ac characteristic tests are performed.." to the Electrical Characteristics........................................... 6 • Added test conditions to the Output voltage settling time of the AC characteristics section in the Timing Requirements ........................................................................................................................................................................ 7 • Added table note: " All ac characteristic tests are performed.." to the Electrical Characteristics........................................... 7 • Changed Figure 9................................................................................................................................................................... 8 2 Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 DAC8811 www.ti.com SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 Changes from Original (November 2004) to Revision A Page • Removed the Product Preview label ...................................................................................................................................... 1 • Added information to the Features ........................................................................................................................................ 1 • Added Output leakage current Data = 0000h, TA = TMAX in the Electrical Characteristics .................................................... 6 • Added Input high voltage for VDD = 2.7 V and 2.5 V in the Electrical Characteristics ........................................................... 6 • Changed the values of the Power Requirements and the AC characteristics section in the Electrical Characteristics ....... 6 Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 3 DAC8811 SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 www.ti.com 5 Device Comparison Table 6 PART NUMBER INL (LSB) DNL (LSB) DAC8811ICDGK ±1 ±1 DAC8811IBDGK ±2 ±1 DAC8811ICDRB ±1 ±1 DAC8811IBDRB ±2 ±1 Pin Configuration and Functions DRB Package 8-Pins VSON Top View DGK Package 8-Pins VSSOP Top View CLK 1 8 CS CLK 1 8 CS SDI 2 7 VDD SDI 2 7 VDD RFB 3 6 GND RFB 3 6 GND VREF 4 5 IOUT VREF 4 5 IOUT Pin Functions PIN NAME NO. TYPE DESCRIPTION CLK 1 I Clock input; positive edge triggered clocks data into shift register SDI 2 I Serial register input; data loads directly into the shift register MSB first. Extra leading bits are ignored. RFB 3 O Internal matching feedback resistor. Connect to external op amp output. VREF 4 I DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance versus code. IOUT 5 O DAC current output. Connects to inverting terminal of external precision I/V op amp. GND 6 G Analog and digital ground. VDD 7 I Positive power supply input. Specified operating range of 2.7 V to 5.5 V. CS 8 I Chip-select; active low digital input. Transfers shift register data to DAC register on rising edge. See Table 1 for operation. 4 Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 DAC8811 www.ti.com SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Input voltage MIN MAX UNIT VDD to GND –0.3 7 V V (IOUT) to GND –0.3 VDD + 0.3 V Digital input voltage GND –0.3 VDD + 0.3 V Reference voltage, VREF RFB to GND –25 25 V –40 105 °C 125 °C Operating temperature Junction temperature, TJ Storage temperature, Tstg (1) –65 150 Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. 7.2 ESD Ratings MAX V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged device model (CDM), per JEDEC specification JESD22C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage to GND 2.7 5.5 V Operating ambient temperature, TA –40 125 °C 7.4 Thermal Information DAC8811 THERMAL METRIC (1) DGK (VSSOP) DRB (VSON) UNIT 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 169.6 46.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 64.2 61.3 °C/W RθJB Junction-to-board thermal resistance 90.3 22 °C/W ψJT Junction-to-top characterization parameter 7.7 1.1 °C/W ψJB Junction-to-board characterization parameter 88.8 22.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 3.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 5 DAC8811 SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 www.ti.com 7.5 Electrical Characteristics VDD = 2.7 V to 5.5 V; IOUT = Virtual GND, GND = 0 V; VREF = 10 V; TA = full operating temperature. All specifications -40°C to 85°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±1 LSB ±2 LSB ±1 LSB nA STATIC PERFORMANCE Resolution 16 Relative accuracy DAC8811C Relative accuracy DAC8811B Differential nonlinearity Bits ±0.5 Output leakage current Data = 0000h, TA = 25°C 10 Output leakage current Data = 0000h, TA = TMAX 10 nA Full-scale gain error All ones loaded to DAC register ±4 mV ±1 Full-scale tempco ±3 ppm/°C 2 mA 50 pF OUTPUT CHARACTERISTICS (1) Output current Output capacitance Code dependent REFERENCE INPUT (1) VREF Range –15 15 V Input resistance 5 kΩ Input capacitance 5 pF LOGIC INPUTS AND OUTPUT (1) VIL Input low voltage VDD = 2.7V VDD = 5V 0.6 V 0.8 V VDD = 2.7V 2.1 V VDD = 5V 2.4 V VIH Input high voltage IIL Input leakage current 10 µA CIL Input capacitance 10 pF 5.5 V POWER REQUIREMENTS VDD 2.7 IDD (normal operation) Logic inputs = 0 V 5 µA VDD = 4.5 V to 5.5 V VIH = VDD and VIL = GND 3 5 µA VDD = 2.7 V to 3.6 V VIH = VDD and VIL = GND 1 2.5 µA AC CHARACTERISTICS BW –3 dB (1) (2) 6 (1) (2) Reference mutiplying BW VREF = 5 VPP, Data = FFFFh DAC glitch impulse VREF = 0 V to 10 V, Data = 7FFFh to 8000h to 7FFFh Feed through error VOUT/VREF Data = 0000h, VREF = 100 mVRMS, f = 100kHz Digital feed through CS = 1 and fCLK = 1 MHz Total harmonic distortion VREF = 5 VPP, Data = FFFFh, f = 1 kHz Output spot noise voltage f = 1 kHz, BW = 1 Hz 10 MHz 2 nV/s –70 2 –105 12 dB nV/s dB nV/√Hz Specified by design and characterization; not production tested. All ac characteristic tests are performed in a closed-loop system using the THS4011 I-to-V converter amplifier. Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 DAC8811 www.ti.com SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 7.6 Timing Requirements MIN NOM MAX UNIT 50 MHz INTERFACE TIMING fCLK Clock input frequency t(CH) Clock pulse width high 10 ns t(CL) Clock pulse width low 10 ns t(CSS) CS to Clock setup time 0 ns t(CSH) Clock to CS hold time 10 ns t(DS) Data setup time 5 ns t(DH) Data hold time 10 ns AC CHARACTERISTICS (1) ts (1) (2) (2) Output voltage settling time To ±0.1% of full-scale, Data = 0000h to FFFFh to 0000h 0.3 µs To ±0.0015% of full-scale, Data = 0000h to FFFFh to 0000h 0.5 µs Specified by design and characterization; not production tested. All ac characteristic tests are performed in a closed-loop system using the THS4011 I-to-V converter amplifier. SDI DB15 DB14 DB13 DB1 DB0 tDS tDH CLK 1 16 tCL tCH tCSH tCSS CS Figure 1. DAC8811 Timing Diagram Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 7 DAC8811 SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 7.7 www.ti.com Typical Characteristics: VDD = 5 V 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) At TA = 25°C, +VDD = 5 V, unless otherwise noted. 0.2 0 - 0.2 0.2 0 - 0.2 - 0.4 - 0.4 - 0.6 - 0.6 - 0.8 - 0.8 - 1.0 - 1.0 0 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code TA = 25°C TA = 25°C Figure 3. Differential Linearity Error vs Digital Input Code 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) Figure 2. Linearity Error vs Digital Input Code 0.2 0 - 0.2 0.2 0 - 0.2 - 0.4 - 0.4 - 0.6 - 0.6 - 0.8 - 0.8 - 1.0 - 1.0 0 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code Figure 5. Differential Linearity Error vs Digital Input Code Figure 4. Linearity Error vs Digital Input Code 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code TA = –40°C TA = –40°C 0.2 0 - 0.2 0.2 0 - 0.2 - 0.4 - 0.4 - 0.6 - 0.6 - 0.8 - 0.8 - 1.0 - 1.0 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code TA = 85°C TA = 85°C Figure 6. Linearity Error vs Digital Input Code 8 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code Figure 7. Differential Linearity Error vs Digital Input Code Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 DAC8811 www.ti.com SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 Typical Characteristics: VDD = 5 V (continued) At TA = 25°C, +VDD = 5 V, unless otherwise noted. A ttenuation (dB) 0xFFFF 0x8000 0x4000 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 Digital Code 6 0 −6 − 12 − 18 − 24 − 30 − 36 − 42 − 48 − 54 − 60 − 66 − 72 − 78 − 84 − 90 − 96 − 102 − 108 − 114 10 0x0000 1 00 1k 10k 10 0k 1M 10 M 100M Bandwidth (H z ) Figure 9. Reference Multiplying Bandwidth Code: 7FFFh to 8000h Output Voltage (5 V/div) Output Voltage (50 mV/div) Figure 8. Supply Current vs Logic Input Voltage Voltage Output Setting Trigger Pulse Trigger Pulse Time (0.1 Ps/div) Time (0.2 Ps/div) Figure 10. DAC Glitch Figure 11. DAC Settling Time Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 9 DAC8811 SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 7.8 www.ti.com Typical Characteristics: VDD = 2.7 V 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) At TA = 25°C, +VDD = 2.7 V, unless otherwise noted. 0.2 0 - 0.2 0.2 0 - 0.2 - 0.4 - 0.4 - 0.6 - 0.6 - 0.8 - 0.8 - 1.0 - 1.0 0 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code TA = 25°C TA = 25°C Figure 13. Differential Linearity Error vs Digital Input Code 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) Figure 12. Linearity Error vs Digital Input Code 0.2 0 - 0.2 0.2 0 - 0.2 - 0.4 - 0.4 - 0.6 - 0.6 - 0.8 - 0.8 - 1.0 - 1.0 0 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code Figure 15. Differential Linearity Error vs Digital Input Code Figure 14. Linearity Error vs Digital Input Code 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code TA = –40°C TA = –40°C 0.2 0 - 0.2 0.2 0 - 0.2 - 0.4 - 0.4 - 0.6 - 0.6 - 0.8 - 0.8 - 1.0 - 1.0 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code TA = 85°C 0 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code TA = 85°C Figure 16. Linearity Error vs Digital Input Code 10 8192 16384 24576 32768 40960 49512 57344 65536 Digital Input Code Figure 17. Differential Linearity Error vs Digital Input Code Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 DAC8811 www.ti.com 8 SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 Detailed Description 8.1 Overview The DAC8811 is a single channel current output, 16-bit digital-to-analog converter (DAC). The device includes a 3-wire serial interface to communicate with most DSPs. 8.2 Functional Block Diagram DAC8811 RFB VDD D/A Converter VREF Power-On Reset IOUT 16 DAC Register CS 16 Shift Register CLK SDI GND 8.3 Feature Description The DAC8811 is a single channel current output, 16-bit digital-to-analog converter (DAC). The architecture, illustrated in Figure 18, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the ladder is either switched to GND or the IOUT terminal. The IOUT terminal of the DAC is held at a virtual GND potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference input VREF that determines the DAC full-scale current. The R-2R ladder presents a code independent load impedance to the external reference of 5 kΩ ±25%. The external reference voltage can vary in a range of -15 V to 15 V, thus providing bipolar IOUT current operation. By using an external I/V converter and the DAC8811 RFB resistor, output voltage ranges of -VREF to VREF can be generated. Figure 18. Equivalent R-2R DAC Circuit When using an external I/V converter and the DAC8811 RFB resistor, the DAC output voltage is given by Equation 1: CODE VOUT VREF x 65536 (1) Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 11 DAC8811 SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 www.ti.com Feature Description (continued) Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output impedance as seen looking into the IOUT terminal changes versus code, the external I/V converter noise gain will also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage such that the amplifier offset is not modulated by the DAC IOUT terminal impedance change. External op amps with large offset voltages can produce INL errors in the transfer function of the DAC8811 due to offset modulation versus DAC code. For best linearity performance of the DAC8811, an operational amplifier (OPA277) is recommended (Figure 19). This circuit allows VREF swinging from -10 V to +10 V. Figure 19. Voltage Output Configuration 8.3.1 Stability Circuit For a current-to-voltage design (see Figure 20), the DAC8811 current output (IOUT) and the connection with the inverting node of the op amp should be as short as possible and according to correct PCB layout design. For each code change, there is a step function. If the GBP of the op amp is limited and parasitic capacitance is excessive at the inverting node then gain peaking is possible. Therefore, for circuit stability, a compensation capacitor C1 (4 pF to 20 pF typ) can be added to the design, as shown in Figure 20. Figure 20. Gain Peaking Prevention Circuit With Compensation Capacitor 8.3.2 Positive Voltage Output Circuit As Figure 21 illustrates, in order to generate a positive voltage output, a negative reference is input to the DAC8811. This design is suggested instead of using an inverting amp to invert the output due to tolerance errors of the resistor. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual ground and a –2.5 V input to the DAC8811 with an op amp. 12 Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 DAC8811 www.ti.com SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 Feature Description (continued) 0 ” VOUT ” +2.5V Figure 21. Positive Voltage Output Circuit 8.3.3 Bipolar Output Circuit The DAC8811, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the full-scale output IOUT is the inverse of the input reference voltage at VREF. Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 22, external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A 4quadrant multiplying circuit is implemented by using a 2.5-V offset of the reference voltage to bias U4. According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full scale produces output voltages of VOUT = -2.5 V to VOUT = +2.5 V. VOUT § D · ¨ 32,768 - 1 ¸ x VREF © ¹ (2) External resistance mismatching is the significant error in Figure 22. 10 k: 10 k: 5 k: -2.5V ” VOUT ” +2.5V (-10s G sOUT G +10V) Figure 22. Bipolar Output Circuit 8.3.4 Programmable Current Source Circuit A DAC8811 can be integrated into the circuit in Figure 23 to implement an improved Howland current pump for precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two features of the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 3: R2 R3 / R1 IL x VREF x D R3 (3) The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can drive ±20 mA in both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the circuit compensation capacitor C1 in the circuit is not suggested as a result of the change in the output impedance ZO, according to Equation 4: Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 13 DAC8811 SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 www.ti.com Feature Description (continued) ZO R1'R3 R1 R2 R1(R2' R3') R1'(R2 R3) (4) As shown in Equation 4, with matched resistors, ZO is infinite and the circuit is optimum for use as a current source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a value of several pF is suggested. R2’ 15 kW C1 10 pF R1’ 150 kW VDD VDD VREF VREF U2 OPA277 R3’ 50 W − RFB U1 DAC8811 IOUT + R3 50 W R2 15 kW − GND VOUT + U2 OPA277 R1 150 kW IL LOAD Figure 23. Programmable Bidirectional Current Source Circuit 8.4 Device Functional Mode Table 1. Control Logic Truth Table (1) CLK CS SERIAL SHIFT REGISTER DAC REGISTER X H No effect Latched ↑+ L Shift register data advanced one bit Latched X H No effect Latched X ↑+ Shift register data transferred to DAC register New data loaded from serial register (1) ↑+ Positive logic transition; X = Don't care 14 Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 DAC8811 www.ti.com SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 8.5 Programming 8.5.1 DAC8811 Input Shift Register The DAC8811 has a 3-wire serial interface (CS, SCLK, and DIN) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See Figure 1 for an example of a typical write sequence. The input shift register is 16 bits wide, as shown in Figure 25. The write sequence begins by bringing the CS line low. Data from the DIN line are clocked into the 16-bit shift register on each rising edge of CLK. The serial clock frequency can be as high as 50 MHz, making the DAC8811 compatible with high-speed DSPs. On the 16th rising edge of the serial clock, the last data bit is clocked in and the programmed function is executed. At this point, the CS line may be kept low or brought high. In either case, it must be brought high for a minimum of 20 ns before the next write sequence so that a falling edge of CS can initiate the next write sequence. Figure 24. Data Input Register DB15 D15 D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DB0 D0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset CLK CS DIN DB15 DB0 Invalid Write Sequence: CS HIGH before 16th Rising Edge DB15 DB0 Valid Write Sequence: Output Updates on 16th Rising Edge Figure 25. CS Interrupt Facility Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 15 DAC8811 SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information This design features the DAC8811 followed by a four-quadrant circuit for multiplying DACs. The circuit conditions the current output of an MDAC into a symmetrical bipolar voltage. The design uses an operational amplifier in a transimpedance configuration to convert the MDAC current into a voltage followed by an additional amplifier in a summing configuration to apply an offset voltage. 9.2 Typical Application Trans-Impedance Stage Gain and Offset Stage RG2 VREF REFIN RFB IOUT RG1 + MDAC RFB2 A1 VDAC + VOUT A2 Figure 26. Typical Application 9.2.1 Design Requirements Using a multiplying DAC requires a transimpedance stage with an amplifier with minimal input offset voltage. The tolerance of the external resistors will vary depending on the goals of the application, but for optimal performance with the DAC8811 the tolerance should be 0.1 % for all of the external resistors. The summing stage amplifier also needs low input-offset voltage and enough slew rate for the output range desired. 9.2.2 Detailed Design Procedure The first stage of the design converts the current output of the MDAC (IOUT) to a voltage (VOUT) using an amplifier in a transimpedance configuration. A typical MDAC features an on-chip feedback resistor sized appropriately to match the ratio of the resistor values used in the DAC R-2R ladder. This resistor is available using the input shown in Figure 26 called RFB on the MDAC. The MDAC reference and the output of the transimpedance stage are then connected to the inverting input of the amplifier in the summing stage to produce the output that is defined by Equation 5. VOUT Code 16 § 2FB2 · V x Code · § RFB2 x REF bits x VREF ¸ ¨ ¸ ¨ R R 2 © G1 ¹ © G2 ¹ Submit Documentation Feedback (5) Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 DAC8811 www.ti.com SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 Typical Application (continued) 9.2.3 Application Curves Figure 27 shows the output voltage vs code of this design, while Figure 28 shows the output error vs code. Keep in mind that the error gets worse as the output code increases because the contribution of the gain error increases with code. 10 0.014 0.012 Output Error (%FSR) Output Voltage (V) 5 0 -5 0.01 0.008 0.006 0.004 0.002 -10 0 0 8192 16384 24576 32768 40960 49152 57344 65536 Input Code (decimal) D001 0 Figure 27. Output Voltage vs Input Code 8192 16384 24576 32768 40960 49152 57344 65536 Input Code (decimal) D002 Figure 28. Output Current vs Input Code 10 Power Supply Recommendations These devices can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to AVDD should be well-regulated and low-noise. In order to further minimize noise from the power supplies, a strong recommendation is to include a pair of 100 pF and 1 nF capacitors and a 0.1 μF to 1 μF bypass capacitor. The current consumption of the AVDD pin, the short-circuit current limit, and the load current for these devices are listed in the Electrical Characteristics table. Choose the power supplies for these devices to meet the aforementioned current requirements. Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 17 DAC8811 SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 www.ti.com 11 Layout 11.1 Layout Guidelines A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8811devices offer single-supply operation, and are often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output. As a result of the single ground pin of the DAC8811, all return currents (including digital and analog return currents for the DAC) must flow through a single point. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. The power applied to AVDD should be wellregulated and low noise. Switching power supplies and dc-dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, AVDD should be connected to a power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, a pair of 100-pF to 1-nF capacitors and a 0.1-μF to 1-μF bypass capacitor are strongly recommended. In some situations, additional bypassing may be required, such as a 100 μF electrolytic capacitor or even a pi filter made up of inductors and capacitors – all designed essentially to provide low-pass filtering for the supply and remove the high-frequency noise. While all the other recommendations apply to most DACs, multiplying DACs also require that the transimpedance amplifier be placed in close proximity in order to minimize non-linearity errors introduced by any resistance between the IOUT pin and V- pin of the amplifier. 11.2 Layout Example Figure 29. DAC8811 Layout Example 18 Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 DAC8811 www.ti.com SLAS411D – NOVEMBER 2004 – REVISED FEBRUARY 2016 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • DAC8801/11EVM, SLAU151 • Interfacing the DAC8811 to the MSP430F449, SLAA238 • Topology and Noise Using Multiplying DAC, SBAA146 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2004–2016, Texas Instruments Incorporated Product Folder Links: DAC8811 19 PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DAC8811IBDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D11 DAC8811IBDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D11 DAC8811IBDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D11 DAC8811IBDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D11 DAC8811IBDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D11 DAC8811ICDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D11 DAC8811ICDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D11 DAC8811ICDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D11 DAC8811ICDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D11 DAC8811ICDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D11 DAC8811ICDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D11 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2016 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8811IBDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC8811IBDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC8811IBDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DAC8811ICDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC8811ICDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC8811ICDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8811IBDGKR VSSOP DGK 8 2500 366.0 364.0 50.0 DAC8811IBDGKT VSSOP DGK 8 250 366.0 364.0 50.0 DAC8811IBDRBT SON DRB 8 250 210.0 185.0 35.0 DAC8811ICDGKR VSSOP DGK 8 2500 366.0 364.0 50.0 DAC8811ICDGKT VSSOP DGK 8 250 366.0 364.0 50.0 DAC8811ICDRBT SON DRB 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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