Sony CXP86548 Cmos 8-bit single chip microcomputer Datasheet

CXP86540/86548/86560
CMOS 8-bit Single Chip Microcomputer
Description
The CXP86540/86548/86560 are the CMOS 8-bit
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time-base
timer, on-screen display function, I2C bus interface,
PWM output, remote control reception circuit,
HSYNC counter, watchdog timer, 32kHz timer/counter
besides the basic configurations of 8-bit CPU, ROM,
RAM, I/O ports.
The CXP86540/86548/86560 also provide a Sleep
function that enables to lower the power consumption.
64 pin SDIP (Plastic)
64 pin QFP (Plastic)
Features
64 pin LQFP (Plastic)
• A wide instruction set (213 instructions) which
covers various types of data
– 16-bit operation/multiplication and division/
Boolean bit operation instructions
• Minimum instruction cycle 250ns at 16MHz operation
122µs at 32kHz operation
• Incorporated ROM
40K bytes (CXP86540)
48K bytes (CXP86548)
60K bytes (CXP86560)
• Incorporated RAM
1536 bytes
(Excludes VRAM for onscreendisplay and sprite
Structure
RAM)
Silicon gate CMOS IC
• Peripheral functions
– A/D converter
8-bit 6-channel successive approximation method
(Conversion time of 3.25µs at 16 MHz)
– Serial interface
8-bit clock sync type, 1 channel
– Timer
8-bit timer
8-bit timer/counter
19-bit time-base timer
32kHz timer/counter
– On-screen display (OSD) function 12 × 16 dots,
512 character types,
15 character colors, 2 lines × 24 characters,
frame background 8 colors/ half blanking,
background on full screen 15 colors/ half blanking
edging/ shadowing/ rounding for every line,
background with shadow for every character,
double scanning,
sprite OSD,
12 × 16 dots, 1 screen, 8 colors for every dot
– I2C bus interface
– PWM output
8 bits, 8 channels
14 bits, 1 channel
– Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
– HSYNC counter
2 channels
– Watchdog timer
• Interruption
13 factors, 13 vectors, multi-interruption possible
• Standby mode
Sleep
• Package
64-pin plastic SDIP/QFP/LQFP
• Piggyback/evaluator
CXP86400 64-pin ceramic PQFP
CXP86490 64-pin ceramic PSDIP (Supports custom font)
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96Z14A86
HSYNC COUNTER 1
ON SCREEN
DISPLAY
XLC
EXLC
R
G
B
I
YS
YM
HSYNC
VSYNC
HS1
8 BIT TIMER 1
TO
HSYNC COUNTER 0
8 BIT TIMER/
COUNTER 0
EC
HS0
SERIAL INTERFACE
UNIT
FIFO
SI
SO
SCK
REMOCON
2
2
I2C BUS
INTERFACE UNIT
SDA0
RMC
INTERRUPT CONTROLLER
INT0
INT1
INT2
SDA1
A/D CONVERTER
6CH
SCL0
6
SCL1
AN0 to AN5
2
ADJ
RAM
352/704/1536 BYTES
ROM
12K/16K/24K/32K/
40K/48K/60K BYTES
8
14 BIT PWM
8 BIT PWM
32kHz
TIMER/COUNTER
WATCHDOG TIMER
PRESCALER/
TIME BASE TIMER
CLOCK GENERATOR
/SYSTEM CONTROL
SPC700 CPU CORE
TEX
TX
EXTAL
XTAL
RST
MP
VDD
VSS
PWM0 to PWM7
–2–
PWM
PORT A
PORT B
PORT C
PORT D
PC0 to PC5
PC6 to PC7
6
2
PE2 to PE3
PE4 to PE6
PF0 to PF7
2
3
8
5
PG3 to PG7
PE0 to PE1
PD0 to PD7
PB0 to PB7
8
8
PA0 to PA7
8
2
PORT E
PORT F
PORT G
Block Diagram
CXP86540/86548/86560
CXP86540/86548/86560
Pin Assignment (Top View) 64-pin SDIP
PC3
1
64
PC4
PC2
2
63
PC5
PC1
3
62
PC6/PWM6
PC0
4
61
PC7/PWM7
EC/PD7
5
60
PF0/PWM0
RMC/PD6
6
59
PF1/PWM1
HS1/PD5
7
58
PF2/PWM2
HS0/PD4
8
57
PF3/PWM3
SI/PD3
9
56
PF4/SCL0
SO/PD2
10
55
PF5/SCL1/PWM4
SCK/PD1
11
54
PF6/SDA0
INT2/PD0
12
53
PF7/SDA1/PWM5
HSYNC/PA7
13
52
PE0/TO/ADJ
VSYNC/PA6
14
51
PE1/PWM
RST
15
50
PE2/TEX/INT0
VSS
16
49
PE3/TX
XTAL
17
48
VSS
EXTAL
18
47
VDD
PA5/AN5
19
46
NC
PA4/AN4
20
45
EXLC
PA3/AN3
21
44
XLC
PA2/AN2
22
43
PE4/YM
PA1/AN1
23
42
PE5/YS
PA0/AN0
24
41
PE6/I
PB7
25
40
B
PB6
26
39
G
PB5
27
38
R
PB4
28
37
PB0
PB3
29
36
PB1
INT1/PG7
30
35
PB2
PG6
31
34
PG3
PG5
32
33
PG4
Note)
1. NC (Pin 46) is left open.
2. Vss (Pins 16 and 48) are both connected to GND.
–3–
CXP86540/86548/86560
PF2/PWM2
PF1/PWM1
PF0/PWM0
PC7/PWM7
PC6/PWM6
PC5
PC4
PC3
PC1
PC2
PC0
PD7/EC
PD6/RMC
Pin Assignment (Top View) 64-pin QFP
64 63 62 61 60 59 58 57 56 55 54 53 52
HS1/PD5
1
51
PF3/PWM3
HS0/PD4
2
50
PF4/SCL0
SI/PD3
3
49
PF5/SCL1/PWM4
SO/PD2
4
48
PF6/SDA0
SCK/PD1
5
47
PF7/SDA1/PWM5
INT2/PD0
6
46
PE0/TO/ADJ
HSYNC/PA7
7
45
PE1/PWM
VSYNC/PA6
8
44
PE2/TEX/INT0
RST
9
43
PE3/TX
VSS
10
42
VSS
XTAL
11
41
VDD
EXTAL
12
40
NC
PA5/AN5
13
39
EXLC
PA4/AN4
14
38
XLC
PA3/AN3
15
37
PE4/YM
PA2/AN2
16
36
PE5/YS
PA1/AN1
17
35
PE6/I
PA0/AN0
18
34
B
PB7
19
33
G
R
PB0
PB1
PB2
PG3
PG4
PG5
PG6
PB3
INT1/PG7
PB4
PB5
PB6
20 21 22 23 24 25 26 27 28 29 30 31 32
Note)
1. NC (Pin 40) is left open.
2. Vss (Pins 10 and 42) are both connected to GND.
–4–
CXP86540/86548/86560
PF2/PWM2
PF3/PWM3
PF1/PWM1
PC7/PWM7
PF0/PWM0
PC6/PWM6
PC5
PC4
PC3
PC1
PC2
PC0
PD7/EC
PD6/RMC
PD5/HS1
PD4/HS0
Pin Assignment (Top View) 64-pin LQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SI/PD3
1
48
PF4/SCL0
SO/PD2
2
47
PF5/SCL1/PWM4
PF6/SDA0
SCK/PD1
3
46
INT2/PD0
4
45
PF7/SDA1/PWM5
HSYNC/PA7
5
44
PE0/TO/ADJ
VSYNC/PA6
6
43
PE1/PWM
RST
7
42
PE2/TEX/INT0
VSS
8
41
PE3/TX
XTAL
9
40
VSS
EXTAL
10
39
VDD
PA5/AN5
11
38
NC
PA4/AN4
12
37
EXLC
PA3/AN3
13
36
XLC
PA2/AN2
14
35
PE4/YM
PA1/AN1
15
34
PE5/YS
PA0/AN0
16
33
PE6/I
B
G
R
PB0
PB1
PB2
PG3
PG5
PG4
PG6
INT1/PG7
PB3
PB4
PB5
PB6
PB7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note)
1. NC (Pin 38) is left open.
2. Vss (Pins 8 and 40) are both connected to GND.
–5–
CXP86540/86548/86560
Pin Description
I/O
Symbol
PA0/AN0
to
PA5/AN5
I/O/
Analog input
PA6/VSYNC
I/O/Input
PA7/HSYNC
I/O/Input
PB0 to PB7
I/O
Description
(Port A)
8-bit I/O port.
I/O can be set in a
unit of single bits.
(8 pins)
Analog inputs to A/D converter.
(6 pins)
OSD display vertical sync signal input.
OSD display horizontal sync signal input.
(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
(Port C)
Lower 6 bits are I/O ports; I/O can be set in a unit of single bits. Upper
2 bits are output port and large current (12mA) N-channel open drain
output. Upper 2 bits are midium drive voltage (12V); lower 6 bits
are 5Vdrive.
(8 pins)
8-bit PWM output.
(2 pins)
PC0 to PC5
I/O
PC6/PWM6 to
PC7/PWM7
Output/Output
PD0/INT2
I/O/Input
PD1/SCK
I/O/I/O
PD2/SO
I/O/Output
PD3/SI
I/O/Input
PD4/HS0
I/O/Input
PD5/HS1
I/O/Input
PD6/RMC
I/O/Input
Remote control reception circuit input.
PD7/EC
I/O/Input
External event input for timer/counter.
PE0/TO/ADJ
I/O/Output/
Output
Rectangular wave output
for 8-bit timer/counter.
PE1/PWM
I/O/Output
PE2/TEX/INT0
Input/Input/
Input
PE3/TX
Input/Output
PE4/YM
Output/Output
PE5/YS
Output/Output
PE6/I
Output/Output
B
Output
G
Output
R
Output
External interruption request input. Active at the
falling edge.
(Port D)
8-bit I/O port. I/O
can be set in a
unit of single bits.
Can drive 12mA
synk current.
(8 pins)
(Port E)
Bits 0 and 1 are I/O
port; I/O can be set
in a unit of single bits.
Bits 2 and 3 are for
input. Bits 4, 5 and
6 are for output.
(7 pins)
Serial clock I/O.
Serial data output.
Serial data input.
HSYNC counter (CH0) input.
HSYNC counter (CH1) input.
14-bit PWM output.
External interruption
Connects a crystal for
request input. Active at
32kHz timer/counter
the falling edge.
clock oscillation. When
used as an event
counter, input to TEX pin and leave TX pin open.
OSD display 6-bit output.
(6 pins)
–6–
32kHz oscillation
frequency dividing output.
CXP86540/86548/86560
Symbol
I/O
Description
(Port F)
8-bit output port
and large current
(12mA) N-channel
open drain output.
Lower 4 bits are
midium drive voltage
(12V); upper 4 bits
are 5V drive.
(8 pins)
8-bit PWM output.
(4 pins)
PF0/PWM0 to
PF3/PWM3
Output/Output
PF4/SCL0
Output/I/O
PF5/SCL1/
PWM4
Output/I/O/
Output
PF6/SDA0
Output/I/O
PF7/SDA1/
PWM5
Output/I/O/
Output
PG3 to PG6
I/O
PG7/INT1
I/O/Input
EXTAL
Input
XTAL
Output
Connects a crystal for system clock oscillation. When a clock is
supplied externally, input it to EXTAL pin and input a reversed phase
clock to XTAL pin.
RST
Input
System reset; active at Low level.
EXLC
Input
XLC
Output
OSD display clock oscillation I/O. Oscillation frequency is determined
by the external L and C.
I2C bus interface transfer clock I/O.
(2 pins)
8-bit PWM output.
I2C bus interface transfer data I/O.
(2 pins)
8-bit PWM output.
(Port G)
5-bit I/O port. I/O can be set in a unit of single bits.
(5 pins)
External interruption request input.
Active at the falling edge.
NC
No connected.
VDD
Positive power supply.
Vss
GND. Connect two Vss pins to GND.
–7–
CXP86540/86548/86560
Input/Output Circuit Formats for Pins
Pin
Circuit format
When reset
Port A
Port A data
Port A direction
PA0/AN0
to
PA5/AN5
“0” when reset
IP
Data bus
Input
protection
circuit
RD (Port A)
Port A function selection
“0” when reset
A/D converter
Hi-Z
Input multiplexer
6 pins
Port A
Port A data
Port A direction
“0” when reset
PA6/VSYNC
PA7/HSYNC
Schmitt input
Data bus
Hi-Z
IP
RD (Port A)
HSYNC, VSYNC
Input polarity
2 pins
“0” when reset
Port B
Ports B, C, G data
Port C
PB0 to PB7
PC0 to PC5
PG3 to PG6
PG7/INT1
Port G
Ports B, C, G direction
“0” when reset
Schmitt input
for PB0, PB1, PB2,
PG7
Data bus
Hi-Z
IP
RD (Ports B, C, G)
19 pins
INT1
Port C
Port F
PC6/PWM6
PC7/PWM7
PF0/PWM0
to
PF3/PWM3
PWM0 to PWM3
PWM6, PWM7
Ports C and F
function selection
Hi-Z
∗
“0” when reset
Ports C and F data
∗ 12V drive voltage
Large current 12mA
“1” when reset
6 pins
–8–
CXP86540/86548/86560
Pin
Circuit format
When reset
Port D
Port D data
PD0/INT2
PD3/SI
PD4/HS0
PD5/HS1
PD6/RMC
PD7/EC
Port D direction
∗
“0” when reset
Hi-Z
Schmitt input
Data bus
IP
RD (Port D)
6 pins
∗ Large current 12mA
INT2, SI, HS0,
HS1, RMC, EC
Port D
SCK, SO
SIO output enable
Port D data
PD1/SCK
PD2/SO
∗
Port D direction
Hi-Z
“0” when reset
Schmitt input
only for PD1
Data bus
IP
RD (Port D)
2 pins
∗ Large current 12mA
SCK only
Port E
Internal reset signal
PE0/TO/ADJ
Port E data
00
“1” when reset
TO
ADJ16K∗1
ADJ2K∗1
01
10
11
MPX
∗2
Port E function selection (Upper)
Port E function selection (Lower)
“00” when reset
Port E direction
“1” when reset
Data bus
1 pin
∗1 ADJ signals are frequency
dividing outputs for 32kHz
oscillation frequency
IP
adjustment. ADJ2K provides
usage as buzzer output.
∗2 Pull-up resistors approx. 150kΩ
RD (Port E)
–9–
High level
(with
approximately
150kΩ
resistor when
reset)
CXP86540/86548/86560
Pin
Circuit format
When reset
Port E
PWM
Port E function selection
“0” when reset
Port E data
“1” when reset
PE1/PWM
High level
Port E direction
“1” when reset
IP
Data bus
RD (Port E)
1 pin
Port E
32kHz oscillation circuit control
“1” when reset
Schmitt input
INT0
Data bus
RD (Port E)
PE2/TEX/INT0
PE3/TX
Data bus
RD (Port E)
Schmitt input
PE2/
TEX/
INT0
2 pins
IP
Oscillation
halted
Port input
IP
Clock input
PE3/
TX
Port E
YM, YS, I
Output polarity
PE4/YM
PE5/YS
PE6/I
“0” when reset
Port E function selection
Hi-Z
“0” when reset
Port E data
Writing data to output polarity
register and port data register
brings output to active.
3 pins
– 10 –
CXP86540/86548/86560
Pin
Circuit format
Port F
When reset
SCL, SDA
I2C bus enable
PF4/SCL0
PF5/SCL1/PWM4
PF6/SDA0
PF7/SDA1/PWM5
∗
PWM4, PWM5
Port F function selection
“0” when reset
Hi-Z
Port F data
Schmitt input
“1” when reset
SCL, SDA
(I2C bus circuit)
IP
BUS SW
4 pins
I 2C
To internal
pins
(SCL1 for SCL0)
∗ Large current 12mA
R, G, B
R
G
B
Output polarity
“0” when reset
Hi-Z
Writing data to output
polarity register brings
output to active.
3 pins
Oscillation control
EXLC
XLC
EXLC
2 pins
XLC
EXTAL
XTAL
2 pins
IP
IP
OSD display clock
Oscillation
halted
IP
EXTAL
• Diagram shows the
circuit composition
during oscillation.
• Feedback resistor is
removed during stop mode.
(This device does not
enter stop mode.)
XTAL
Oscillation
Pull-up resistor
RST
1 pin
AA
AA
OP Mask option
Schmitt input
– 11 –
Low level
CXP86540/86548/86560
Absolute Maximum Ratings
Item
(Vss = 0V reference)
Symbol
Ratings
Unit
V
Supply voltage
VDD
Input voltage
VIN
–0.3 to +7.0
–0.3 to +7.0∗1
Output voltage
VOUT
–0.3 to +7.0∗1
V
–0.3 to +15.0
V
Mid-voltage drive output voltage VOUTP
Remarks
V
High level output current
IOH
–5
mA
High level total output current
∑IOH
–50
mA
Total of all output pins
IOL
15
mA
Ports excluding large current output
(value per pin)
IOLC
20
mA
Large current output ports
(value per pin∗2)
Low level total output current
∑IOL
130
mA
Total of all output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
1000
mW
SDIP-64P-01
600
mW
QFP-64P-L01
380
mW
LQFP-64P-L01
Low level output current
Allowable power dissipation
PD
∗1 VIN and VOUT should not exceed VDD + 0.3 V.
∗2 The large current output port is Port C (PC6, PC7), Port D (PD) and Port F (PF).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
Recommended Operating Conditions
Item
Supply voltage
High level input
voltage
Symbol
(Vss = 0V reference)
Min.
Max.
Unit
4.5
5.5
V
Guaranteed operation range for 1/2 and 1/4
frequency dividing modes
3.5
5.5
V
Guaranteed operation range for 1/16 frequency
dividing mode or sleep mode
2.7
5.5
V
—
—
V
Guaranteed operation range for TEX mode
Guaranteed data hold range for stop mode∗5
VIH
0.7VDD
VDD
V
∗1
VIHS
0.8VDD
VDD
V
∗2
V
VDD
Remarks
VIL
0
0.3VDD
V
EXTAL pin∗3, TEX pin∗4
∗1
VILS
0
0.2VDD
V
∗2
VILEX
–0.3
0.4
V
EXTAL pin∗3, TEX pin∗4
Operating temperature Topr
–20
+75
°C
VIHEX
Low level input
voltage
∗1
∗2
∗3
∗4
∗5
VDD – 0.4 VDD + 0.3
PA1 to PA5, PB3 to PB7, PC0 to PC5, PD2, PE0, PE1, PE3, PG3 to PG6, SCL0, SCL1, SDA0, SDA1 pins
VSYNC, HSYNC, INT2, SCK, SI, HS0, HS1, RMC, EC, INT0, INT1, RST, PB0, PB1, PB2 pins
Specifies only during external clock input.
Specifies only during external event count input
This device does not enter the stop mode.
– 12 –
CXP86540/86548/86560
Electrical Characteristics
(Ta = –20 to +75°C, Vss = 0V reference)
DC characteristics
Item
High level output
voltage
Low level output
voltage
Symbol
VOH
VOL
Pins
PA, PB, PC0 to PC5,
VDD = 4.5V, IOH = –0.5mA
PD, PE0 to PE1,
PE4 to PE6, PG, R,
VDD = 4.5V, IOH = –1.2mA
G, B
Input current
IIHT
IILT
Min.
Typ.
Max.
Unit
4.0
V
3.5
V
PA to PD, PE0 to PE1, VDD = 4.5V, IOL = 1.8mA
PE4 to PE6, PF0 to
VDD = 4.5V, IOL = 3.6mA
PF3, PG, R, G, B
0.4
V
0.6
V
PC6, PC7, PD, PF
VDD = 4.5V, IOL = 12.0mA
1.5
V
PF4 to PF7
(SCL0, SCL1,
SDA0, SDA1)
VDD = 4.5V, IOL = 3.0mA
0.4
V
VDD = 4.5V, IOL = 4.0mA
0.6
V
IIHE
IILE
Conditions
EXTAL
TEX
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIH = 5.5V
0.1
10
µA
–0.1
–10
µA
–1.5
–400
µA
IILR
RST∗1
VDD = 5.5V, VIL = 0.4V
I/O leakage current
IIZ
PA to PE, PG, R,
G, B, RST∗1
VDD = 5.5V,
VI = 0, 5.5V
±10
µA
Open drain I/O
leakage current
(in N-ch Tr off state)
PC6, PC7, PF0 to PF3
VDD = 5.5V, VOH = 12.0V
50
µA
ILOH
PF4 to PF7
VDD = 5.5V, VOH = 5.5V
10
µA
I2C bus switch
connection impedance
(in output Tr off state)
RBS
SCL0: SCL1
SDA0: SDA1
VDD = 4.5V
VSCL0 = VSCL1 = 2.25V
VSDA0 = VSDA1 = 2.25V
120
Ω
18
28
mA
30
80
µA
1.2
2.1
mA
12
35
µA
—
—
µA
1/2 frequency dividing mode
VDD = 5.5V,
16MHz crystal oscillation
(C1 = C2 = 15pF)
IDD1
VDD = 3.3V,
32MHz crystal oscillation
(C1 = C2 = 47pF)
IDD2
Sleep mode
Supply current∗2
IDDS1
IDDS2
IDDS3
VDD
VDD = 5.5V,
16MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3.3V,
32MHz crystal oscillation
(C1 = C2 = 47pF)
Stop mode∗3
VDD = 5.5V,
termination of 16MHz
and 32MHz oscillation
– 13 –
—
CXP86540/86548/86560
Item
Input capacitance
Symbol
CIN
Pins
Conditions
PA to PD, PE0 to PE3, Clock 1MHz
R, G, B, PF4 to PF7,
0V other than the
PG3 to PG7, EXTAL,
measured pins
TEX, EXLC, RST
Min.
Typ.
Max.
Unit
10
20
pF
∗1 For RST pin, specifies the input current when pull-up resistance is selected, and specifies the leakage
current when non-resistor is selected.
∗2 When all output pins are left open. Specifies only when the OSD oscillation is halted.
∗3 This device does not enter the stop mode.
– 14 –
CXP86540/86548/86560
AC Characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
(1) Clock timing
Item
Symbol
System clock frequency
fC
Event count input clock rise
and fall times
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
System clock frequency
fC
Event count input clock
pulse width
tTL,
tTH
tTR,
tTF
System clock input pulse width
System clock input rise and fall
times
Event count input clock pulse
width
Event count input clock rise
and fall times
Pins
Conditions
Min.
XTAL
EXTAL
Fig. 1, Fig.2
8
EXTAL
Fig. 1, Fig.2
External clock drive
28
EXTAL
Fig. 1, Fig.2
External clock drive
EC
Fig. 3
EC
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied conditions)
TEX
Fig. 3
TEX
Fig. 3
Typ.
Max
Unit
16
MHz
ns
ns
200
4tsys∗1
ns
ms
20
kHz
32.768
µs
10
20
∗1 Indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits
(CPU clock selection).
tsys (ns) = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
AAAAAAAAA AAAA
AAAAA
AAAA
AAAA
AAAAAAAAA AAAA
Fig.2. Clock applied conditions
Crystal oscillation
Ceramic oscillation
EXTAL
C1
External clock
EXTAL
XTAL
C2
32kHz clock applied condition
Crystal oscillation
TEX
XTAL
74HC04
TX
C2
C1
Fig. 3. Event count clock timing
0.8VDD
TEX
EC
0.2VDD
tEF
tTF
tEH
tTH
– 15 –
tEL
tTL
tER
tTR
ms
CXP86540/86548/86560
(2) Serial transfer
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pins
tKCY
SCK
SCK High and Low level
widths
tKH
tKL
SCK
SI input setup time
(for SCK ↑)
tSIK
SI
SI hold time
(for SCK ↑)
tKSI
SI
SCK ↓ → SO delay time
tKSO
SO
SCK cycle time
Conditions
Min.
Input mode
Max.
1000
ns
8000/fc
ns
400
ns
4000/fc – 50
ns
SCK input mode
100
ns
SCK output mode
200
ns
SCK input mode
200
ns
SCK output mode
100
ns
Output mode
SCK input mode
SCK output mode
SCK input mode
200
ns
SCK output mode
100
ns
Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
Fig. 4. Serial transfer timing
tKCY
tKL
tKH
0.8VDD
SCK
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI
Unit
0.2VDD
tKSO
0.8VDD
SO
Output data
0.2VDD
– 16 –
CXP86540/86548/86560
(3) A/D converter
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Max.
Unit
Resolution
8
Bits
Linearity error
±3
LSB
Zero transition
voltage
VZT∗1
Full-scale transition
voltage
VFT∗2
Conversion time
Sampling time
tCONV
tSAMP
Analog input voltage
VIAN
Pins
Conditions
Ta = 25°C
VDD = 5.0V
Vss = 0V
Min.
Typ.
–10
10
70
mV
4910
4970
5030
mV
26/fADC∗3
6/fADC∗3
AN0 to AN5
0
µs
µs
VDD
V
Fig. 5. Definitions of A/D converter terms
Digital conversion value
FFh
FEh
∗1 VZT: Value at which the digital conversion value changes
from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes
from FEh to FFh and vice versa.
∗3 fADC indicates the below values due to the contents of bit
6 (CKS) of the A/D control register (ADC: 00F6h):
Linearity error
01h
00h
fADC = fc (CKS = “0”), fc/2 (CKS = “1”)
VZT
VFT
Analog input
– 17 –
CXP86540/86548/86560
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Max.
Unit
External interruption High,
Low level widths
tIH
tIL
INT0
INT1
INT2
1
µs
Reset input Low level width
tRSL
RST
32/fc
µs
Fig. 6. Interruption input timing
tIH
INT0
INT1
INT2
(falling edge)
tIL
0.8VDD
0.2VDD
Fig. 7. RST input timing
tRSL
RST
0.2VDD
– 18 –
CXP86540/86548/86560
(5) I2C bus timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Max.
Unit
0
100
kHz
SCL clock frequency
fSLC
SCL
Bus-free time before starting transfer
tBUF
tHD; STA
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tR
tF
tSU; STO
SDA, SCL
4.7
µs
SDA, SCL
4.0
µs
SCL
4.7
µs
SCL
4.0
µs
SDA, SCL
µs
SDA, SCL
4.7
0∗1
SDA, SCL
250
ns
Hold time for starting transfer
Clock Low level width
Clock High level width
Setup time for repeated transfers
Data hold time
Data setup time
SDA, SCL rise time
SDA, SCL fall time
Setup time for transfer completion
µs
SDA, SCL
1
µs
SDA, SCL
300
ns
SDA, SCL
4.7
µs
∗1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it.
Fig. 8. I2C bus transfer timing
SDA
tBUF
tR
tF
tHD; STA
SCL
tHD; STA
tSU; STA
P
S
tLOW
tHD; DAT
tHIGH
St
tSU; DAT
tSU; STO
P
Fig. 9. I2C bus device recommended circuit
I2C bus
device
RS
I2C bus
device
RS RS
R S RP
RP
SDA0
(or SDA1)
SCL0
(or SCL1)
• A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the
spike noise caused by CRT flashover.
– 19 –
CXP86540/86548/86560
(6) OSD timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Max
Unit
30.4
MHz
EXLC
XLC
Fig. 11
4
tHWD
tVWD
HSYNC
Fig. 10
2
VSYNC
Fig. 10
1
HSYNC afterwrite rise and fall
times
tHCG
HSYNC
Fig. 10
200
ns
VSYNC beforewrite rise and fall
times
tVCG
VSYNC
Fig. 10
1.0
µs
OSD clock frequency
fOSC
HSYNC pulse width
VSYNC pulse width
µs
H∗2
∗1 The maximum value of fosc is specified with the following equation.
fosc [max] ≤ fc × 1.9
∗2 H indicates 1HSYNC period.
Fig. 10. OSD timing
tHWD
tHCG
0.8VDD
HSYNC
For OSD I/O polarity register
(OPOL: 01FEh)
bit 7 at “0”
0.2VDD
tVCG
tVWD
0.8VDD
VSYNC
For OSD I/O polarity register
(OPOL: 01FEh)
bit 6 at “0”
0.2VDD
Fig. 11. LC oscillation circuit connection
EXLC
XLC
R∗1
L
C2
C1
∗1 The series resistor for XLC (R = 1kΩ or less) is used to reduce the frequency of occurrence of the
undesired radiation.
– 20 –
CXP86540/86548/86560
Appendix
Fig. 12. Recommended oscillation circuit
AAAA
AAAA
AAAAA
AAAA
AAAA
AAAAA
AAAA AAAA
AAAAA
AA
A
A
(i) Main clock
EXTAL
XTAL
(ii) Main clock
(iii) Sub clock
EXTAL
TEX
XTAL
Rd
C1
TX
Rd
Rd
C2
C2
C1
C1 C2
Manufacture
Model
MURATA MFG
CO., LTD.
RIVER
ELETEC CO.,
LTD.
fc (MHz)
CSA10.0MTZ
10.0
CSA12.0MTZ
12.0
CSA16.00MXZ040
CST10.0MTW∗
16.0
10.0
C1 (pF)
C2 (pF)
30
30
5
5
30
30
12.0
CST16.00MXW0C1∗
16.0
5
5
8.0
18
18
12.0
12
12
16.0
10
10
8.0
10
10
12.0
5
5
16.0
Open
Open
32.768kHz
30
33
HC-49/U (-S)
KINSEKI LTD.
P3
Circuit example
(i)
CST12.0MTW∗
HC-49/U03
Rd (Ω)
0 ∗1
(ii)
330 ∗1
(i)
0 ∗1
120k
(iii)
∗ Models with an astarisk have the built-in ground capacitance (C1, C2).
∗1 The series resistor for XTAL (Rd = 500Ω or less) can reduce the effect of the noise caused by the
electrostatic discharge.
Mask Option Table
Item
Reset pin pull-up resistor
Content
Non-existent
– 21 –
Existent
CXP86540/86548/86560
Fig. 13. Characteristic curve
IDD vs. VDD
IDD vs. fc
(fc = 16MHz, Ta = 25°C, Typical)
(VDD = 5V, Ta = 25°C, Typical)
100
1/2 dividing mode
1/4 dividing mode
15
IDD – Supply current [mA]
1/16 dividing mode
Sleep mode
1
0.1
32kHz operation mode
1/2 dividing mode
10
1/4 dividing mode
5
32kHz sleep mode
1/16 dividing mode
0.01
Sleep mode
1
2
3
4
5
6
0
7
0
5
VDD – Supply voltage [mA]
10
Frequency [MHz]
Parameter curve for OSD oscillator L vs. C
(Analytically calculated value)
100
10
L – Inductance [µH]
IDD – Supply current [mA]
10
16MHz
20MHz
24MHz
28MHz
30MHz
1
fOSC =
1
2π√LC
C = C1//C2
0.1
0.01
0
10
20
30
40
50
60
70
C1, C2 – Capacitance [pF]
– 22 –
80
90 100
15
CXP86540/86548/86560
Unit: mm
+ 0.1
0.05
0.25 –
64PIN SDIP (PLASTIC) 750mil
+ 0.4
57.6 – 0.1
64
19.05
+ 0.3
17.1 – 0.1
33
1
0° to 15°
32
3 MIN
0.5 MIN
+ 0.4
4.75 – 0.1
1.778
0.5 ± 0.1
0.9 ± 0.15
PACKAGE STRUCTURE
MOLDING COMPOUND
EPOXY / PHENOL RESIN
SONY CODE
SDIP-64P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SDIP064-P-0750-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
8.6g
JEDEC CODE
64PIN QFP(PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
51
0.15
32
64
20
1
16.3
52
17.9 ± 0.4
33
+ 0.4
14.0 – 0.1
+ 0.2
0.1 – 0.05
19
+ 0.35
2.75 – 0.15
+ 0.15
0.4 – 0.1
1.0
0.8 ± 0.2
Package Outline
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP–64P–L01
LEAD TREATMENT
EIAJ CODE
∗ QFP064–P–1420
LEAD MATERIAL
SOLDER/PALLADIUM
PLATING
COPPER /42 ALLOY
PACKAGE WEIGHT
1.5g
JEDEC CODE
– 23 –
CXP86540/86548/86560
64PIN LQFP (PLASTIC)
12.0 ± 0.2
∗
10.0 ± 0.1
48
33
32
64
17
(0.22)
0.5 ± 0.2
(11.0)
49
A
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
16
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-64P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
LQFP064-P-1010
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.3g
JEDEC CODE
– 24 –