Supertex inc. HV430 High-Voltage Ring Generator Features ► ► ► ► ► ► ► The RESET input functions as a power-on reset when connected to an external capacitor. The FAULT output indicates an overcurrent condition and is cleared after 4 consecutive cycles with no overcurrent condition. A logic low on RESET or ENABLE clears the FAULT output. It is activelow and open-drain to allow wire OR’ing of multiple drivers. 105Vrms ring signal Output overcurrent protection 5.0V CMOS logic control Logic enable/disable to save power Adjustable deadband in single-control mode Power-on reset Fault output for problem detection PGATE and NGATE are controlled independently by logic inputs PIN and NIN when the MODE pin is at logic high. A logic high on PIN will turn on the external P-channel MOSFET. Similarly, a logic high on NIN will turn on the external N-channel MOSFET. Lockout circuitry prevents the N and P switches from turning on simultaneously. A pulse width limiter restricts pulse widths to no less than 100 - 200ns. Applications ► Line access cards ► Set-top/Street box For applications where a single control input is desired, the MODE pin should be connected to SGND. The PWM control signal is then input to the NIN pin. A user-adjustable deadband in the control logic ensures break-before-make on the outputs, thus avoiding cross conduction on the high voltage output during switching. A logic high on NIN will turn the external PChannel MOSFET on and the N-Channel off, and vice versa. The IC can be powered down by applying a logic low on the ENABLE pin, placing both external MOSFETs in the off state. General Description The Supertex HV430 is a high voltage PWM ring generator integrated circuit. The high voltage outputs, VPGATE and VNGATE, are used to drive the gates of external high voltage N-channel and P-channel MOSFETs in a push-pull configuration. Overcurrent protection is implemented for both the P-channel and N-channel MOSFETs. External sense resistors set the over-current trip point. Functional Block Diagram VDD VPP1 +5.0V VPP2 FAULT De-glitcher VPP1 VPP2 Regulator VDD clk reset RSENSE PIN MODE DEADBAND Control Logic NIN ENABLE VDD 10µA RESET SIG GND VPSEN Down Translator Current Trip Up Translator P Driver VPGATE Up Translator N Driver VNGATE Down Translator Current Trip PWR GND Ringer Output VNSEN RSENSE VNN2 Regulator VNN1 VNN2 VNN1 Doc.# DSFP-HV430 A031414 Supertex inc. www.supertex.com HV430 Pin Configuration Ordering Information Part Number Package Option Packing HV430WG-G 20-Lead SOW 20 1 1000/Reel -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value VPP1 - VNN1, power supply voltage +340V VPP1, positive high voltage supply +220V VPP2, positive gate voltage supply +220V VNN1, negative high voltage supply -220V VNN2, negative gate voltage supply -220V VDD, logic supply (top view) Product Marking YY = Year Sealed WW = Week Sealed HV430WG LLLLLLLLLL A = Assembler ID L = Lot Number Bottom Marking C = Country of Origin* = “Green” Packaging CCCCCCCCCCC Top Marking YYWW AAA +7.5V Operating temperature range Storage temperature range 20-Lead SOW -40 C to +85OC O -65 C to +150 C Power dissipation O O *May be part of top marking Package may or may not include the following marks: Si or 20-Lead SOW 600mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Typical Thermal Resistance Package θja 20-Lead SOW 66OC/W Electrical Characteristics (Over operating supply voltage unless otherwise specified. T = -40°C to +85°C) A Sym Parameter Min Typ Max Units Conditions 50 - 200 V --- External Supplies VPP1 High voltage positive supply IPP1Q VPP1 quiescent current - 250 500 µA PIN = NIN = 0V IPP1 VPP1 operating current - - 2.0 mA No load, VOUTP and VOUTN switching at 100KHz VNN1 High voltage negative supply VPP1 -325 - -50 V --- INN1Q VNN1 quiescent current - 250 500 µA PIN = NIN = 0V, RDB = 18kΩ INN1 VNN1 operating current - - 1.0 mA No load, VOUTP and VOUTN switching at 100KHz VDD Logic supply voltage 4.50 - 5.50 V --- IDDQ VDD quiescent current - 300 400 µA PIN = NIN = 0V, RDB = 18kΩ IDD VDD operating current - - 1.0 mA PIN = NIN = 100KHz, RDB = 18kΩ Doc.# DSFP-HV430 A031414 2 Supertex inc. www.supertex.com HV430 Electrical Characteristics (cont.)(Over operating supply voltage unless otherwise specified. T = -40°C to +85°C) A Sym Parameter Min Typ Max Units Conditions VPP1 -16 - VPP1 -10 V --- VPP1 +10 - VPP1 +14 V --- VPP2 - VPP1 V No load on VPGATE VPGATE source resistance - - 12.5 Ω IOUT = 80mA RSINKP VPGATE sink resistance - - 12.5 Ω IOUT = -80mA tRISEP VPGATE rise time - - 50 ns CLOAD = 1.4nF tFALLP VPGATE fall time - - 50 ns CLOAD = 1.4nF 100 150 200 ns --- - - 300 ns Mode = 1 Internal Supplies VPP2 VNN2 Positive linear regulator output voltage Negative linear regulator output voltage Positive High Voltage Output VPGATE RSOURCEP Output voltage swing tPWP(MIN) VPGATE minimum pulse width (internally limited) tDELAYP PIN to PGATE delay time VPSEN VPGATE current sense voltage VPP1 -0.85 VPP1 -1.0 VPP1 -1.15 V --- tSHORTP VPGATE current sense off time - - 150 ns --- VNN2 - VNN1 V No load on VNGATE VNGATE source resistance - - 15.0 Ω IOUT = 80mA RSINKN VNGATE sink resistance - - 15.0 Ω IOUT = 80mA tRISEN VNGATE rise time - - 50 ns CLOAD = 1.4nF tFALLN VNGATE fall time - - 50 ns CLOAD = 1.4nF 100 150 200 ns --- - - 300 ns Mode = 1 Negative High Voltage Output VNGATE RSOURCEN Output voltage swing tPWN(MIN) VNGATE minimum pulse width (internally limited) tDELAYN NIN to NGATE delay time VNSEN VNGATE current sense voltage VNN1 +0.85 VNN1 +1.0 VNN1 +1.15 V --- tSHORTN VNGATE current sense off time - - 150 ns --- Control Circuitry VIL Logic input low voltage 0 - 0.60 V VDD = 5.0V VIH Logic input high voltage 2.7 - 5.0 V VDD = 5.0V IINDN Input pull-down current 0.5 1.0 5.0 µA PIN, NIN, ENABLE RUP Input pull-up resistance 100 200 300 KΩ MODE VOL Logic output low voltage - - 0.50 V VDD = 5.0V, IOUT = -0.5mA VOH Logic output high voltage 4.50 - - V VDD = 5.0V, IOUT = +0.5mA VRST(OFF) RESET voltage, device off 3.2 - 3.5 V VDD = 5.0V VRST(ON) RESET voltage, device on 3.7 - 4.0 V VDD = 5.0V Doc.# DSFP-HV430 A031414 3 Supertex inc. www.supertex.com HV430 Electrical Characteristics (cont.)(over operating supply voltage unless otherwise specified. T = -40°C to +85°C) A Sym Parameter Min Typ Max Units RESET hysteresis voltage 0.3 - - V VDD = 5.0V IRESET RESET pull-up current 7.0 10 13 µA VRESET = 0 - 4.5V tRST(ON) RESET on delay - - 1.0 µs --- tRST(ON) RESET off delay - - 1.0 µs --- tEN(ON) ENABLE on delay 50 100 150 µs --- tEN(OFF) ENABLE off delay - - 1.0 µs --- tFLT(HOLD) FAULT hold time - 4 - NIN/PIN cycles tDB Deadband time 35 50 70 105 140 175 VRST(HYS) ns Conditions ENABLE = 1 Mode = 0, RDB = 5.6kΩ Mode = 0, RDB = 18kΩ tDELAY(N-P) N-off to P-on transistion delay - - 300 ns Mode = 0, RDB < 27kΩ tDELAY(P-N) P-off to N-on transistion delay - - 300 ns Mode = 0, RDB < 27kΩ ∆tDELAY(N-P) Delay difference: tdelayN(off) - tdelayP(on) -80 0 80 ns Mode = 1 ∆tDELAY(P-N) Delay difference: tdelayP(off) - tdelayN(on) -80 0 80 ns Mode = 1 Truth Table Logic Inputs* Output RESET Externel N-Channel MOSFET Externel P-Channel MOSFET H >VRESET(ON) OFF OFF H H >VRESET(ON) OFF ON L H H >VRESET(ON) ON OFF H H H H >VRESET(ON) OFF OFF H X L H >VRESET(ON) OFF ON L X L H >VRESET(ON) ON OFF X X X L X OFF OFF X X X X <VRESET(OFF) OFF OFF NIN PIN Mode EN L L H L H H Note: * Unused logic inputs should be connected to VDD or GND. Doc.# DSFP-HV430 A031414 4 Supertex inc. www.supertex.com HV430 Single-Control Mode Timing VDD 1 NIN 0 GND tN-P DELAY tP-N DELAY VPP2 ON POUT OFF tP RISE VPP1 tP FALL tP-N DEADBAND tN-P DEADBAND VNN2 ON NOUT OFF tN FALL VNN1 tN RISE Dual-Control Mode Timing VDD 1 PIN 0 tP DELAY(ON) tP PULSE(MIN) GND tP DELAY(OFF) ON VPP2 POUT OFF tP RISE VPP1 tP FALL VDD 1 NIN 0 tN DELAY(ON) tN PULSE(MIN) tN DELAY(OFF) GND VNN2 ON NOUT OFF Doc.# DSFP-HV430 A031414 tN RISE 5 tN FALL VNN1 Supertex inc. www.supertex.com HV430 ENABLE Timing 1 VDD 0 GND 1 VDD NIN/PIN Switching 0 POUT NOUT GND tEN(ON) tEN(OFF) VPP2 ON Off Switching Off OFF VPP1 ON VNN2 Off Switching Off VNN1 OFF RESET Timing VRESET(ON) VRESET(OFF) RESET GND VDD 1 NIN/PIN Switching 0 tRST(OFF) tRST(ON) VPP2 ON POUT Off Switching Off OFF VPP1 VNN2 ON NOUT Doc.# DSFP-HV430 A031414 GND Off Switching Off VNN1 OFF 6 Supertex inc. www.supertex.com HV430 FAULT Timing ENABLE or RESET 1 VDD 0 GND 1 VDD 0 GND NIN ON VPP2 OFF VPP1 ON VNN2 OFF VNN1 POUT NOUT Over NSENSE OK tFAULT(HOLD) ENABLE or RESET clears fault immediately. VDD FAULT w/ext pull-up GND Note: NSENSE overcurrent shown. PSENSE operates identically. Doc.# DSFP-HV430 A031414 7 Supertex inc. www.supertex.com HV430 Pin Description Pin # Name 1 VDD 2 FAULT Logic output. Fault is at logic low when either current limit sense pin, VPSEN or VNSEN, is activated. Remains active until overcurrent condition clears or ENABLE = 0 or RESET = 0. 3 MODE Logic mode input. 0 = single-control; 1 = dual-control. When MODE is high, NIN and PIN independently control NOUT and POUT, respectively. When MODE is low, NIN controls both outputs in a complementary manner. (See Truth Table) 4 PIN Logic control input. When mode is high, logic input high turns on the external high voltage P-channel MOSFET. Internally pulled low. 5 NIN Logic control input. When mode is high, logic input high turns on the external high voltage N-channel MOSFET. Internally pulled low. 6 ENABLE 7 RESET Power-on reset. A capacitor connected between this pin and ground determines the delay time between application of VDD and when the device outputs are enabled. Low leakage tantalum recommended. 8 DEADBAND A resistor between this pin and ground sets the ‘break-before-make’ time between output transitions. Applicable only in single-control mode. For minimum deadtime, a 5.6kΩ resistor to ground should be used. For dual-input mode, tie to VDD. 9 SGND Low voltage logic ground. 10 PGND High voltage logic ground. 11 VNN2 Negative gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should beconnected between VNN2 and VNN1. 12 VNN1 Negative high voltage supply. 13 VNSEN Pulse by pulse over current sensing for N-Channel MOSFET. 14 VNGATE Gate drive for external N-channel MOSFET. 15 N/C 16 Description Logic supply voltage. Logic enable input. Logic high enables IC. Internally pulled low. No connect. 17 VPGATE Gate drive for external P-channel MOSFET. 18 VPSEN Pulse by pulse over current sensing for P-Channel MOSFET. 19 VPP1 Positive high voltage supply. 20 VPP2 Positive gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should beconnected between VPP2 and VPP1. Doc.# DSFP-HV430 A031414 8 Supertex inc. www.supertex.com HV430 20-Lead SOW (Wide Body) Package Outline (WG) 12.80x7.50mm body, 2.65mm height (max), 1.27mm pitch D 20 θ1 Note 1 (Index Area 0.25D x 0.75E1) L2 L L1 e 1 E1 E b Top View Gauge Plane Seating Plane θ View B View B Note 1 A h h A A2 Seating Plane A1 Side View View A-A A Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b D E E1 2.15* 0.10 2.05 0.31 12.60* 9.97* 7.40* - - - - 12.80 10.30 7.50 2.65 0.30 2.55* 0.51 13.00* 10.63* 7.60* e 1.27 BSC h L 0.25 0.40 - - 0.75 1.27 L1 L2 1.40 0.25 REF BSC θ θ1 0O 5O - - 8O 15O JEDEC Registration MS-013, Variation AC, Issue E, Sep. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-20SOWWG, Version D041309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV430 A031414 9 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com