www.fairchildsemi.com
FMS6403
Triple Video Drivers with Selectable HD/PS/SD/
Bypass Filters for RGB and YPbPr Signals
Features
Description
• Three video anti-aliasing or reconstruction filters
• 2:1 Mux inputs for YPbPr and RGB inputs
• Supports D1, D2, D3 and D4 video D-connector
(EIAJ CP-4120)
• Selectable 8MHz/15MHz/30MHz 6th order filters plus bypass
• Works with SD (480i), Progressive (480p) and HD
(1080i/ 720p)
• AC-coupled inputs include DC restore /bias circuitry
• All outputs can drive AC or DC coupled 75Ω loads and
provide either 0dB or 6dB of gain
• 0.40% differential gain, 0.25° differential phase
• Lead (Pb)-free TSSOP-20 packaging
The FMS6403 offers comprehensive filtering for TV, set top
box or DVD applications. This part consists of a triple 6th
order filter with selectable 30MHz, 15MHz, or 8MHz cutoff
frequencies. The filters may also be bypassed so that the
bandwidth is limited only by the output amplifiers.
Applications
• Progressive scan
• Cable set top boxes
• Home theaters
• Satellite set top boxes
• DVD players
• HDTV
• Personal Video Recorders (PVR)
• Video On Demand (VOD)
A 2 to 1 multiplexer is provided on each filter channel.
The triple filters are intended for YPbPr and RGB signals.
The DC clamp levels are set according to the RGB_SEL
control input. YPbPr sync tips are clamped to 250mV,
1.125V and 1.125V respectively while RGB sync tips are all
clamped to 250mV. Sync clamp timing can be derived from
the Y/G inputs or from the external SYNC_IN pin. The 8MHz
and 15MHz filter settings support bi-level sync while the
30MHz filter setting and bypass mode support tri-level sync.
All channels nominally accept AC coupled 1Vpp signals.
Selectable 0dB or 6dB gain allows the outputs to drive 1Vpp
or 2Vpp signals into AC or DC coupled terminated loads
with a 1Vpp input. Input signals cannot exceed 1.5Vpp and
outputs cannot exceed 2.5Vpp.
Functional Block Diagram
Sync Strip
SYNC_IN
Y1/G1
Y/GOUT
8MHz, 15MHz, 30MHz, Bypass
Y2/G2
EXT_SYNC
gM
250mV
Pb1/B1
Pb/BOUT
8MHz, 15MHz, 30MHz, Bypass
Pb2/B2
gM
RGB_SEL
250mV
Selectable
0dB or 6dB
output gain
1.125V
Pr1/R1
8MHz, 15MHz, 30MHz, Bypass
Pr2/R2
Pr/ROUT
250mV
IN2_SEL
1.125V
gM
FSEL0
0dB_SEL
FSEL1
REV. 1C March 2005
DATA SHEET
FMS6403
DC Electrical Specifications
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω,
referenced to 400kHz; unless otherwise noted)
Symbol
Parameter
Conditions
Current1
Min
VCC no load
Typ
Max Units
90
130
ICC
Supply
Vi
Input Voltage Max
Vil
Digital Input Low1
FSEL0, FSEL1, RGB_SEL, 0dB_SEL,
EXT_SYNC, IN2_SEL, SYNC_IN
0
0.8
V
Vih
Digital Input High1
FSEL0, FSEL1, RGB_SEL, 0dB_SEL,
EXT_SYNC, IN2_SEL, SYNC_IN
2.4
VCC
V
VCLAMP1
Output Clamp Voltage
R,G,B,Y
VCLAMP2
Output Clamp Voltage
Pb and Pr
PSRR
Power Supply Rejection Ratio
DC (All Channels)
1.5
mA
Vpp
250
mV
1.125
V
-40
dB
Standard Definition Electrical Specifications
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 0, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC
coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Symbol
AVSD
Parameter
SD Gain, 0dB_SEL =
Conditions
Min
Typ
Max Units
‘0’1
All Channels SD Mode
5.6
6.0
6.4
dB
1
All Channels SD Mode
-0.4
0
0.4
dB
All Channels
5.5
7.6
MHz
8.5
MHz
56
dB
%
AVSD
SD Gain, 0dB_SEL = ‘1’
f1dBSD
1
-1dB Bandwidth for SD
fCSD
-3dB Bandwidth for SD
All Channels
1
fSBSD
Attenuation: SD (Stopband Reject)
All Channels at f = 27MHz
40
dG
Differential Gain
All Channels
0.40
dφ
Differential Phase
All Channels
0.25
°
THD
Output Distortion (All Channels)
Vout = 1.8Vpp at 1MHz
0.4
%
XTALK
Crosstalk (Channel-to-Channel)
at 1.0MHz
-68
dB
INMUXISO
INMUX Isolation
at 1.0MHz
-70
dB
SNR
Signal-to-Noise Ratio
All Channels, NTC-7 Weighting,
4.2MHz lowpass, 100kHz Highpass
74
dB
tpdSD
Propagation Delay for SD
Delay from Input to Output at 4.5MHz
80
ns
T1
SYNC to SYNC_IN Delay
10
ns
T2
SYNC_IN Min Pulse Width
4
µs
Progressive Scan (PS) Electrical Specifications
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC
coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Symbol
AVPS
Parameter
Conditions
Min
Typ
Max Units
1
All Channels PS Mode
5.6
6.0
6.4
dB
1
All Channels PS Mode
-0.4
0
0.4
dB
10
15
PS Gain, 0dB_SEL = ‘0’
AVPS
PS Gain, 0dB_SEL = ‘1’
f1dBPS
1
-1dB Bandwidth for PS
All Channels
MHz
Note:
1. 100% tested at 25°C.
2
REV. 1C March 2005
FMS6403
DATA SHEET
Progressive Scan (PS) Electrical Specifications (Continued)
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC
coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Symbol
Parameter
Conditions
fCPS
-3dB Bandwidth for PS
Min
All Channels
fSBPS
Attenuation: PS (Stopband
tpdPS
Propagation Delay for PS
T1
T2
Reject)1
All Channels at f = 54MHz
40
Typ
Max Units
17
MHz
48
dB
45
ns
SYNC to SYNC_IN Delay
10
ns
SYNC_IN Min Pulse Width
2
µs
Delay from Input to Output at 10MHz
High Definition Electrical Specifications
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 1, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC
coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Symbol
AVHD
Parameter
Conditions
Min
Typ
Max Units
1
All Channels HD Mode
5.6
6.0
6.4
dB
1
All Channels HD Mode
-0.4
0
0.4
dB
20
29
MHz
33
MHz
40
dB
HD Gain, 0dB_SEL = ‘0’
AVHD
HD Gain, 0dB_SEL = ‘1’
f1dBHD
-1dB Bandwidth for
HD1
fCHD
-3dB Bandwidth for HD
fSBHD
Attenuation: HD (Stopband
All Channels
All Channels
Reject)1
All Channels at f = 74.25MHz
30
tpdHD
Propagation Delay for HD
26
ns
T1
SYNC to SYNC_IN Delay
10
ns
T2
SYNC_IN Min Pulse Width
1.5
µs
Delay from Input to Output at 20MHz
Unfiltered 1080p Bypass (Wide Bandwidth) Electrical Specifications
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 1, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC
coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Symbol
Conditions
Min
Typ
Max Units
Gain, 0dB_SEL =
‘0’1
All Channels Bypass Mode
5.6
6.0
6.4
dB
AVWB
Gain, 0dB_SEL =
‘1’1
All Channels Bypass Mode
-0.4
0
0.4
dB
AVWB
Parameter
f1dBWB
-1dB Bandwidth
All Channels
63
MHz
fCWB
-3dB Bandwidth
All Channels
91
MHz
tpdWB
Propagation Delay
Delay from Input to Output at 20MHz
10
ns
Note:
1. 100% tested at 25°C.
REV. 1C March 2005
3
DATA SHEET
FMS6403
Absolute Maximum Ratings (beyond which the device may be damaged)
Parameter
Min
Max
Units
DC Supply Voltage
-0.3
6
V
Analog and Digital I/O
-0.3
VCC + 0.3
V
60
mA
Output Current, Any One Channel (Do not exceed)
Note:
Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if operating
conditions are not exceeded.
Reliability Information
Parameter
Min
Typ
Junction Temperature
Storage Temperature Range
-65
Lead Temperature (Soldering, 10s)
θJA),
Thermal Resistance (θ
JEDEC Standard Multi-layer Test Boards, Still Air
Max
Units
150
°C
150
°C
300
°C
74
°C/W
Recommended Operating Conditions
Parameter
Operating Temperature Range
VCC Range
Input Source Resistance (Rsource)
4
Min
Typ
0
4.75
5.0
Max
Units
70
°C
5.25
V
150
Ω
REV. 1C March 2005
FMS6403
DATA SHEET
Standard Definition Typical Performance Characteristics
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 0, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC
coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Figure 1. SD Frequency Response
Figure 2. SD Group Delay vs. Frequency
10
60
0
1
40
2
-30
-40
1
20
-20
Delay (ns)
Gain (dB)
-10
Mkr Frequency
Ref 400kHz
1
2
3
-50
-60
Gain
6dB
7.58MHz
8.47MHz
27MHz
-1dB BW
-3dB BW
-53.80dB
0
-20
-40
-60
3
1 = 8.2MHz (36.80ns)
fSBSD = Gain(ref) – Gain(3) = 59.80dB
-70
400kHz
5
10
20
15
25
-80
400kHz
30
5
Frequency (MHz)
10
15
20
25
30
Frequency (MHz)
Figure 3. SD Noise vs. Frequency
Figure 4. SD Differential Gain
-60
0.1
NTSC
Differential Gain (%)
-70
Noise (dB)
-80
-90
0
-0.1
-100
-0.2
-110
-120
-0.3
-130
-140
Min = -0.40
Max = 0.00
ppMax = 0.40
-0.4
400kHz
1
2
4
3
5
1st
2nd
3rd
4th
5th
6th
Frequency (MHz)
Figure 5. SD Differential Phase
0.25
Differential Phase (deg)
NTSC
0.20
Min = -0.00
Max = 0.25
ppMax = 0.25
0.15
0.10
0.05
0
1st
REV. 1C March 2005
2nd
3rd
4th
5th
6th
5
DATA SHEET
FMS6403
Progressive Scan (PS) Typical Performance Characteristics
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC
coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Figure 6. PS Frequency Response
Figure 7. PS Group Delay vs. Frequency
20
5
1
-15
-25
-35
-45
-55
Mkr Frequency
Ref 400kHz
1
2
3
1
10
2
Delay (ns)
Noise (dB)
-5
Gain
6dB
14.78MHz
16.57MHz
54MHz
-1dB BW
-3dB BW
-56.57dB
3
0
-10
-20
-30
1 = 15MHz (15.95ns)
fSBSD = Gain(ref) – Gain(3) = 62.57dB
-65
-40
400kHz
10
20
40
30
50
60
400kHz
10
Frequency (MHz)
20
40
30
50
60
Frequency (MHz)
High Definition Typical Performance Characteristics
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 1, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC
coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Figure 8. HD Frequency Response
Figure 9. HD Group Delay vs. Frequency
10
10
0
1
2
5
1
Delay (ns)
Gain (dB)
-10
-20
-30
-40
-50
Mkr
Ref
1
2
3
Frequency
400kHz
29.07MHz
32.57MHz
74.25MHz
3
Gain
6dB
-1dB BW
-3dB BW
-35.82dB
0
-5
-10
1 = 32MHz (7.07ns)
fSBSD = Gain(ref) – Gain(3) = 41.82dB
-60
400kHz 10
-15
20
30
40
50
60
70
Frequency (MHz)
6
80
90 100
400kHz 10
20
30 40
50
60
70
80
90 100
Frequency (MHz)
REV. 1C March 2005
FMS6403
DATA SHEET
Unfiltered 1080p Bypass (WB) Typical Performance Characteristics
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 1, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC
coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Figure 10. Bypass Mode Frequency Response
Figure 11. Bypass Mode Group Delay
vs. Frequency
6.5
2
6
1
5
Delay (ns)
Gain (dB)
5.5
1
4.5
4
3.5
3
2.5
Mkr Frequency
Ref 400kHz
1
2
62.54MHz
90.51MHz
Gain
6dB
-1dB BW
-3dB BW
2
2
400kHz 10
-1
-2
1
-3
1 = 80MHz (-2.22ns)
-4
20
30
40
50
60
70
Frequency (MHz)
REV. 1C March 2005
0
80
90 100
400kHz 10
20
30 40
50
60
70
80
90 100
Frequency (MHz)
7
DATA SHEET
FMS6403
Pin Configuration
EXT_SYNC
1
20
VCC
RGB_SEL
2
19
VCC
Y1/G1
3
18
SYNC_IN
8
FMS6403
20-pin
TSSOP
Y2/G2
4
17
In2_SEL
Pb1/B1
5
16
Y/GOUT
Pb2/B2
6
15
Pb/BOUT
Pr1/R1
7
14
Pr/ROUT
Pr2/R2
8
13
0dB_SEL
FSEL0
9
12
GND
FSEL1
10
11
GND
Pin#
Pin
Type
Description
1
EXT_SYNC
Input
Selects the external SYNC_IN
signal when set to logic ‘1’, do not
float
2
RGB_SEL
Input
Selects RGB clamp levels when set
to logic ‘1’, YPbPr clamp levels
when set to logic ‘0’, do not float
3
Y1/G1
Input
Y or G input 1 - may be connected
to a signal which includes sync
4
Y2/G2
Input
Y or G input 2 - may be connected
to a signal which includes sync
5
Pb1/B1
Input
Pb or B input 1
6
Pb2/B2
Input
Pb or B input 2
7
Pr1/R1
Input
Pr or R input 1
8
Pr2/R2
Input
Pr or R input 2
9
FSEL0
Input
Selects filter corner frequency or
bypass, see table, do not float
10
FSEL1
Input
Selects filter corner frequency or
bypass, see table, do not float
11
GND
Input
Must be tied to Ground, do not float
12
GND
Input
Must be tied to Ground, do not float
13
0dB_SEL
Input
Selects output gain of 0dB when set
to logic ‘1’, 6dB when set to logic ‘0’,
do not float
14
Pr/ROUT
Output
Pr or R output
15
Pb/BOUT
Output
Pb or B output
16
Y/GOUT
Output
Y or G output
17
IN2_SEL
Input
Selects mux input 2 when set to
logic ‘1’, mux input 1 when set to
logic ‘0’, do not float
18
SYNC_IN
Input
External sync input signal, square
wave crossing Vil and Vih input
thresholds, do not float
19
VCC
Input
+5V supply, do not float
20
VCC
Input
+5V supply, do not float
REV. 1C March 2005
FMS6403
DATA SHEET
Gain Settings
Sync Settings
0dB_SEL, Pin 13
Gain (dB)
VIN*
VOUT*
EXT_SYNC, Pin1
Sync Source
0
6
1Vpp
2Vpp
0
Y/G input, Pin 3/4
1
0
1Vpp
1Vpp
1
SYNC_IN input, Pin 2
* Video level, does not include clamp voltage which will offset the input
above ground.
Filter Settings
FSEL1, Pin 10
FSEL0, Pin 9
Filter -3dB Freq
Video Format
Sync Format
0
0
8MHz
SD, 480i
Bi-level, 4.7µs pulse width
0
1
15MHz
PS, 480p
Bi-level, 2.35µs pulse width
1
0
32MHz
HD, 1080i, 720p
Tri-level, 589ns pulse width
1
1
Filter Bypass
Unfiltered 1080p
Tri-level, 290ns, pulse width
Clamp Settings
RGB_SEL, Pin 2
Input
Output
Clamp Voltage
0
Y1, Pin 3
Y, Pin 16
250mV
Pb1, Pin 5
Pb, Pin 15
1.125V
Pr1, Pin 7
Pr, Pin 14
1.125V
G1, Pin 3
G, Pin 16
250mV
B1, Pin 5
B, Pin 15
250mV
R1, Pin 7
R, Pin 14
250mV
1
REV. 1C March 2005
9
DATA SHEET
Functional Description
Introduction
The FMS6403 is a next generation filter solution from
Fairchild Semiconductor addressing the expanding filtering
needs for televisions, set top boxes, and DVD players including
progressive scan capability. The product provides selectable
filtering with cutoff frequencies of 30MHz, 15MHz, and
8.0MHz for all three channels. In addition, the filters can be
bypassed for wider bandwidth applications. The FMS6403
allows consumer devices to support a variety of resolution
standards with the same hardware.
Multiplexers on the channel inputs are controlled by the
IN2_SEL pin. The RGB_SEL pin can be used to set the sync
tip clamp voltages for YPbPr or RGB applications. All three
channels are set for 250mV sync tips to reduce DC-coupled
power dissipation for RGB inputs. The lower output bias
voltage is not suitable for the PbPr outputs so for YPbPr
inputs these signals are clamped to 1.125V while Y is still
clamped to 250mV. Sync tip clamping voltages are set by
forcing the desired DC bias level during the active sync
period. For systems without sync on Y/G, an external sync
input is provided. If sync exists on one input Y/G signal
but not on the other Y/G input signal, the IN2_SEL and
EXT_SYNC control inputs may be wired together on the
PCB to switch the sync source with the input source.
Both standard definition (bi-level) and high definition (trilevel) sync are supported at the Y/G inputs and SYNC_IN
depending on the FSEL[1:0] inputs. See the Sync Processing
section for further details.
Standard definition (480i) and progressive (480p) signals are
clamped by forcing the signal to the desired voltage during
the sync pulse. For signals with sync, the sync tip itself will
be forced to the clamp voltage (typically 250mV). When
high definition sync is present (tri-level sync) the sync tip
duration is too short to allow this approach. In order to accurately clamp HD signals, the sync pulse starts a timer and the
actual clamping is done at the blanking level right after the
sync pulse. The sync tip will still typically be placed at 250mV
if its amplitude is 300mV.
All three outputs are driven by amplifiers with selectable gains
of 0dB or +6dB. The gain is set with the 0dB_SEL pin. These
amplifiers can drive two terminated video loads (75Ω) to 2Vpp
with a 1Vpp input when set to 6dB gain. The input range is
limited to 1.5Vpp and the output range is limited to 2.5Vpp.
All control inputs must be driven high or low. Do not leave
them floating.
External SYNC Mode
The FMS6403 can properly recover sync timing from video
signals that include sync. If the Y-input video signals does
10
FMS6403
not include sync, the FMS6403 can be used in External
SYNC Mode. When the FMS6403 is used in external sync
mode, (EXT_SYNC pin is high), a pulsed input must be
applied to the SYNC_IN pin. If there is no video signal
present, therefore no sync signal present, there must still be
an input applied to the SYNC_IN pin. When there is no
video signal on the video inputs SYNC_IN can be a sync
pulse every 60µs to mimic the slowest sync in a regular
video signal. The following two sections discuss the sync
processing and timing required in more detail.
SD and Progressive Scan
Video Sync Processing
The FMS6403 must control the DC offset of AC-coupled
input signals since the average DC level of video varies with
image content. If the input offset is allowed to wander, the
common mode input range of the amplifiers can be exceeded
leading to signal distortion. DC offset adjustment is referred
to as clamping or in some cases, biasing, and must be done at
the correct time during each video line. The optimum time is
during the sync pulse since it is the lowest input voltage.
This approach works well for 480i and 480p signals since the
sync tip duration is long enough to allow the DC-offset
errors to be compensated from line to line. The DC-offset of
the sync tip is adjusted as illustrated in Figure 12 by forcing
a current on the input during the sync pulse. The sync tip will
be clamped to approximately 250mV. Signals like Pb and Pr
with a symmetric voltage range (±350mV) will be clamped
to approximately 1.125V. Note that the following diagrams
illustrate DC restore functionality and indicate output voltage levels for both 0dB and 6dB gain (1Vpp and 2Vpp video
signals at the FMS6403 output pin).
0dB Gain 6dB
Required Pb Offset
1475mV 1875mV
1125mV 1125mV
775mV
425mV
1250mV 2250mV
Av = 1 (0dB) or 2 (6dB)
Av*700mV
550mV
850mV
250mV
250mV
0mV
0mV
Active
Active
Video
Av*300mV
Required Sync Tip Offset
Figure 12. Bi-Level Sync
Tip Clamping and Bias
In some cases, the sync voltage may be compressed to less
than the nominal 300mV value. The FMS6403 can successfully recover SD and Progressive Scan sync which is greater
than 100mV (compressed to 33% of nominal).
The FMS6403 can properly recover sync timing from luma
and green which include sync. If none of the video signals
REV. 1C March 2005
FMS6403
DATA SHEET
includes sync, the EXT_SYNC control input can be set high
and an external sync signal must be input on the SYNC_IN
pin. Refer to the External Sync section for more details. The
timing required for this operating mode is shown in Figure 13.
SYNC timings, T1 and T2, are defined in the SD Electrical
Specifications table on page 2.
0dB Gain 6dB
Av = 1 (0dB) or 2 (6dB)
950mV 1650mV
Active
Video
Av*700mV
250mV
250mV
0mV
0mV
Required Blanking Offset
NOTE: Tri-level sync may only be compressed 5%. If HD
sync is compressed more than 5% it may not be properly
located.
Sync Timing
Normally, the FMS6403 will respond to bi-level sync and
clamp the sync tip during period ‘B’ in Figure 15(a). When
the filters are switched to high definition mode (30MHz)
or bypass mode the sync processing will respond to tri-level
sync and clamp to the blanking level during period ‘C’ in
Figure 15(b).
NOTE: The diagram indicates SYNC timings at the
output pin.
True Sync Position
T1
T2
(a)
Allowable SYNC_IN
2250mV
480i and 480p
Figure 13. Bi-Level External
Sync Clamping and Bias
850mV
HD and Bypass Mode Video Sync Processing
When the input signal is a high definition signal, the tri-level
sync pulse is too short to allow proper clamp operation.
Rather than clamp during the sync pulse, the sync pulse is
located and the signal is clamped to the blanking level. This
is done in such a way that the sync tip will still be set to
approximately 250mV for signals with 300mV sync tip
amplitude. The EXT_SYNC control input selects the sync
stripper output or the SYNC_IN pin for use by the clamp circuit.
NOTE: The SYNC_IN timing for HD signals is different
than the timing for SD or PS signals.
250mV
A
(b)
0dB Gain 6dB
Av = 1 (0dB) or 2 (6dB)
1250mV 2250mV
850mV 1450mV
550mV
850mV
250mV
250mV
0mV
0H
Av*700mV
Active
Video
Av*300mV
0mV
Av*300mV
Required Sync Tip
Offset (Next Sync Tip
Will Be Offset Correctly)
C
2250mV
720p, 1080i, 1080p
1450mV
850mV
250mV
A
For HD signals, the SYNC_IN signal must be high when the
clamp must be active. This is during the time immediately
after the sync pulse while the signal is at the blanking level.
This operation is shown in Figure 14. Note that the following
diagrams illustrate DC restore functionality and indicate output
voltage levels for both 0dB and 6dB gain (1Vpp and 2Vpp video
signals at the FMS6403 output pin). SYNC timings, T1 and T2,
are defined in the HD Electrical Specifications table on page 3.
B
B
B
C
Figure 15. Sync Timing; Bi-Level (a), Tri-Level (b)
The tri-level sync pulse is located such that the broad pulses
in the vertical interval do not trigger the clamp. In order to
improve the system settling at turn-on, the broad pulses will
be clamped to just above ground. Once the broad pulses (and
tri-level sync tips) are above ground, the normal clamping
process takes over and clamps to the blanking level during
period ‘C’ in Figure 15(b).
The FMS6403 is designed to support the video standards
and associated sync timings shown in Table 1, (additional
standards such as 483p59.94 will also work correctly). The
Filter Settings table from page 9 is repeated on page 12 for
convenience..
True Sync Position
T1
T2
Allowable SYNC_IN
Figure 14. Tri-Level Blanking Clamp
REV. 1C March 2005
11
DATA SHEET
FMS6403
Filter Settings
FSEL1, Pin 10
FSEL0, Pin 9
Filter -3dB Freq
Video Format
Sync Format
0
0
8MHz
SD, 480i
Bi-level, 4.7µs pulse width
0
1
15MHz
PS, 480p
Bi-level, 2.35µs pulse width
1
0
32MHz
HD, 1080i, 720p
Tri-level, 589ns pulse width
1
1
Filter Bypass
Unfiltered 1080p
Tri-level, 290ns, pulse width
Table I
Format
Refresh
Sample Rate
Period (T)
A
B
C
H-Rate
480i
30Hz
13.5MHz
74ns
20T = 1.5µs
64T = 4.7µs
61T = 4.5µs
15.75kHz
480p
60Hz
27MHz
37ns
20T = 750ns
64T = 2.35µs
61T = 2.25µs
31.5kHz
720p
60Hz
74.25MHz
13.4ns
70T = 938ns
40T = 536ns
220T = 2.95µs
45kHz
1080i
30Hz
74.25MHz
13.4ns
44T = 589ns
44T = 589ns
148T = 1.98µs
33.75kHz
1080p
60Hz
148.5MHz
6.7ns
44T = 296ns
44T = 296ns
148T = 996ns
67.5kHz
Note: Timing values are approximate for 30Hz/60Hz refresh rates.
Application Information
Input Circuitry
The DC restore circuit in the FMS6403 requires a source
impedance (Rsource = Rs || RT) of less than or equal to 150Ω
for correct operation. Driving the FMS6403 with a highimpedance source (e.g. a DAC loaded with 330Ω) will not
yield optimum results. Refer to the Typical Application
Circuit diagram on page 13 for more details.
Output Drive
The FMS6403 is specified to operate with output currents
typically less than 60mA, more than sufficient for a dual
(75Ω) video load. Internal amplifiers are current limited to
approximately 100mA and should withstand brief duration
short circuit conditions, however this capability is not guaranteed.
The maximum specified input voltage of 1.5Vpp can be
sustained for all inputs. When the input is clamped to
1.125V, this does not result in a meaningful output signal.
With a gain of 6dB, the output should be 1.125V ±1.5V
which is not possible since the output cannot drive below
ground. This condition will not damage the part; however,
the output will be clipped. For signals which are clamped to
250mV, this does not occur.
Signals that are at midscale during SYNC (Pb and Pr) must
be clamped to 1.125V and signals that are at their lowest
during SYNC (Y, R, G, B) must be clamped to 250mV for
proper operation. Clamping a Pr signal to 250mV will result
in clipping the bottom of the signal.
12
The 220uF capacitor coupled with the 150Ω termination, as
shown in the Typical Application Circuit of Figure 5, forms a
high pass filter that blocks the DC while passing the video
frequencies and avoiding tilt. Any value lower than 220µF
will create problems, such as video tilt. Higher values, such
as 470µF - 1000µF are the most optimal output coupling
capacitor. By AC coupling, the average DC level is zero.
Thus, the output voltages of all channels will be centered
around zero.
Sync Recovery
The FMS6403 will typically recover bi-level sync with
amplitude greater than 100mV (33% compressed relative to
the nominal 300mV amplitude). The FMS6403 looks for the
lowest signal voltage and clamps this to approximately
250mV at the output.
Tri-level sync may not be compressed more than 5% (15mV)
for correct operation. Tri-level sync is located by finding the
edges of the tri-level pulse and running a timer to operate the
clamp during the back porch interval.
The selection of the 8MHz or 15MHz filters enables bi-level
sync recovery. Selection of the 30MHz filter or bypass mode
enables tri-level sync recovery. Bi-level and tri-level sync
recovery are not interchangeable. See the detailed sync
processing section for more information.
REV. 1C March 2005
FMS6403
Power Dissipation
TheFMS6403 output drive configuration must be considered
when calculating overall power dissipation. Care must be
taken not to exceed the maximum die junction temperature.
The following example can be used to calculate the
FMS6403’s power dissipation and internal temperature rise.
DATA SHEET
use as a guide for layout and to aid in device testing and
characterization. The FMS6403DEMO is a 4-layer board
with a full power and ground plane. For optimum results,
follow the steps below as a basis for high frequency layout:
•
Include 10µF and 0.1µF ceramic bypass capacitors
•
Place the 10µF capacitor within 0.75 inches of the
power pin
•
Place the 0.1µF capacitor within 0.1 inches of the
power pin
where
VO = 2Vin + 0.280V
•
Connect all external ground pins as tightly as possible,
preferably with a large ground plane under the package
ICH = (ICC / 3) + (VO/RL)
•
Layout channel connections to reduce mutual trace
inductance
•
Minimize all trace lengths to reduce series inductances.
If routing across a board, place device such that longer
traces are at the inputs rather than the outputs.
Tj = TA + Pd • ΘJA
where Pd = PCH1 + PCH2 + PCH3
and PCHx = Vs • ICH - (VO2/RL)
Vin = RMS value of input signal
ICC = 90mA
Vs = 5V
RL = channel load resistance
Board layout can also affect thermal characteristics. Refer to
the Layout Considerations Section for more information.
The FMS6403 is specified to operate with output currents
typically less than 60mA, more than sufficient for a single
(150Ω) video load. Internal amplifiers are current limited
to a maximum of 100mA and should withstand brief duration short circuit conditions, however this capability is not
guaranteed.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance and thermal characteristics.
Fairchild offers a demonstration board, FMS6403DEMO, to
REV. 1C March 2005
If using multiple, low impedance DC coupled outputs, special
layout techniques may be employed to help dissipate heat.
For dual-layer boards, place a 0.5” to 1” (1.27cm to 2.54cm)
square ground plane directly under the device and on the
bottom side of the board. Use multiple vias to connect the
ground planes. For multi-layer boards, additional planes
(connected with vias) can be used for additional thermal
improvements.
Worse case additional die power due to DC loading can be
estimated at (VCC2/4Rload) per output channel. This assumes
a constant DC output voltage of VCC2. For 5V VCC with a
dual DC video load, add 25/(4*75) = 83mW, per channel.
13
DATA SHEET
Y1/G1
FMS6403
0.1µF
Rs
3
75Ω
Y1/G1
RT
75Ω
Y2/G2
0.1µF
Rs
4
75Ω
VCC
VCC
Pb1/B1
Y2/G2
5
75Ω
Pb1/B1
Pb/BOUT
6
75Ω
Pb2/B2
Pr/ROUT
RT
75Ω
Pr1/R1
75Ω Video Cables
15 75Ω
220µF
75Ω Video Cables
14 75Ω
220µF
75Ω Video Cables
75Ω
0.1µF
Rs
220µF
75Ω
0.1µF
Rs
16 75Ω
75Ω
RT
75Ω
Pb2/B2
1µF
May also be DC
coupled
Y/GOUT
0.1µF
Rs
0.1µF
19
FMS6403
20L TSSOP
RT
75Ω
+5V
20
7
75Ω
Pr1/R1
RT
75Ω
Pr2/R2
0.1µF
Rs
75Ω
RT
75Ω
8
GND
12
Pr2/R2
GND
11
Note: Pins 1, 2, 9, 10, 13, 17, and 18 will need
to be set according to the input signal format
Figure 16. Typical Application Circuit
14
REV. 1C March 2005
FMS6403
DATA SHEET
Package Dimensions
TSSOP-20
6
e
–B–
7
N
5
(b)
2X E/2
1.0 DIA
TSSOP-20
8
E1 E
c
c1
1.0
b1
ddd C B A
2X
N/2 TIPS
1 2 3
6
SECTION AA
e /2 9
1.0
ccc
7 –A–
A2
D 8 3
aaa C
A
–C–
b NX
A1
(02)
(0.20)
bbb M C B A
R1
–H–
R
GAGE
PLANE
10
A
0.25
(03)
A
L
(L1)
01
SYMBOL
A
A1
A2
L
R
R1
b
b1
c
c1
01
L1
aaa
bbb
ccc
ddd
e
02
03
D
E1
E
e
N
MIN
–
0.05
0.85
0.50
0.09
0.09
0.19
0.19
0.09
0.09
0°
6.50
4.30
NOM
–
–
0.90
0.60
–
–
–
0.22
–
–
–
1.0 REF
0.10
0.10
0.05
0.20
0.65 BSC
12° REF
12° REF
6.50
4.40
6.4 BSC
0.65 BSC
20
MAX
1.10
0.15
0.95
0.75
–
–
0.30
0.25
0.20
0.16
8°
6.60
4.50
NOTES:
1 All dimensions are in millimeters (angle in degrees).
2
Dimensioning and tolerancing per ASME Y14.5–1994.
3
Dimensions "D" does not include mold flash, protusions or gate burrs. Mold flash protusions or gate burrs shall not exceed 0.15 per side .
4
Dimension "E1" does not include interlead flash or protusion. Interlead flash or protusion shall not exceed 0.25 per side.
5
Dimension "b" does not include dambar protusion. Allowable dambar protusion shall be 0.08mm total in excess of the "b" dimension at maximum
material condition. Dambar connot be located on the lower radius of the foot. Minimum space between protusion and adjacent lead is 0.07mm
for 0.5mm pitch packages.
6
Terminal numbers are shown for reference only.
7
Datums – A – and – B – to be determined at datum plane – H – .
8
Dimensions "D" and "E1" to be determined at datum plane – H – .
9
This dimensions applies only to variations with an even number of leads per side. For variation with an odd number of leads per side, the "center"
lead must be coincident with the package centerline, Datum A.
10 Cross sections A – A to be determined at 0.10 to 0.25mm from the leadtip.
REV. 1C March 2005
15
DATA SHEET
FMS6403
Ordering Information
Model
Part Number
Lead
Free
Package
Container
Pack Qty
FMS6403
FMS6403MTC20_NL
Yes
TSSOP-20
Tube
94
FMS6403
FMS6403MTC20X_NL
Yes
TSSOP-20
Tape and Reel
2500
Temperature range for all parts: 0°C to +70°C.
16
REV. 1C March 2005
FMS6403
DATA SHEET
75$'(0$5.6
7KHIROORZLQJDUHUHJLVWHUHGDQGXQUHJLVWHUHGWUDGHPDUNV)DLUFKLOG6HPLFRQGXFWRURZQVRULVDXWKRUL]HGWRXVHDQGLV
QRWLQWHQGHGWREHDQH[KDXVWLYHOLVWRIDOOVXFKWUDGHPDUNV
$&([
,QWHOOL0$;
)$67¡
$FWLYH$UUD\
,623/$1$5
)$67U
%RWWRPOHVV
/LWWOH)(7
)36
&RRO)(7
0,&52&283/(5
)5)(7
&526692/7 *OREDO2SWRLVRODWRU 0LFUR)(7
'20(
0LFUR3DN
*72
(FR63$5. +L6H&
0,&52:,5(
(&026
06;
,&
(Q6LJQD
06;3UR
L/R
)$&7
,PSOLHG'LVFRQQHFW 2&;
)$&74XLHW6HULHV
2&;3UR
¡
$FURVVWKHERDUG$URXQGWKHZRUOG 2372/2*,&
23723/$1$5
7KH3RZHU)UDQFKLVH¡
3$&0$1
3URJUDPPDEOH$FWLYH'URRS
323
3RZHU
3RZHU(GJH
3RZHU6DYHU
3RZHU7UHQFK¡
4)(7¡
46
472SWRHOHFWURQLFV
4XLHW6HULHV
5DSLG&RQILJXUH
5DSLG&RQQHFW
M6HU'HV
6,/(176:,7&+(5¡
60$5767$57
630
6WHDOWK
6XSHU)(7
6XSHU627
6XSHU627
6XSHU627
6\QF)(7
7LQ\/RJLF¡
7,1<2372
7UX7UDQVODWLRQ
8+&
8OWUD)(7¡
8QL)(7
9&;
',6&/$,0(5
)$,5&+,/'6(0,&21'8&7255(6(59(67+(5,*+7720$.(&+$1*(6:,7+287)857+(5127,&(72$1<
352'8&76+(5(,172,03529(5(/,$%,/,7<)81&7,2125'(6,*1)$,5&+,/''2(6127$6680($1</,$%,/,7<
$5,6,1*2872)7+($33/,&$7,212586(2)$1<352'8&725&,5&8,7'(6&5,%('+(5(,11(,7+(5'2(6,7
&219(<$1</,&(16(81'(5,763$7(175,*+761257+(5,*+762)27+(56
/,)(683325732/,&<
)$,5&+,/'¶6352'8&76$5(127$87+25,=(')2586($6&5,7,&$/&20321(176,1/,)(6833257
'(9,&(6256<67(06:,7+2877+((;35(66:5,77(1$33529$/2))$,5&+,/'6(0,&21'8&725&25325$7,21
$V XVHG KHUHLQ
$FULWLFDOFRPSRQHQWLVDQ\FRPSRQHQWRIDOLIH
/LIH VXSSRUW GHYLFHV RU V\VWHPV DUH GHYLFHV RU
VXSSRUWGHYLFHRUV\VWHPZKRVHIDLOXUHWRSHUIRUPFDQ
V\VWHPVZKLFK D DUHLQWHQGHGIRUVXUJLFDOLPSODQWLQWR
EHUHDVRQDEO\H[SHFWHGWRFDXVHWKHIDLOXUHRIWKHOLIH
WKH ERG\ RU E VXSSRUW RU VXVWDLQ OLIH RU F ZKRVH
VXSSRUW GHYLFH RU V\VWHP RU WR DIIHFW LWV VDIHW\ RU
IDLOXUH WR SHUIRUP ZKHQ SURSHUO\ XVHG LQ DFFRUGDQFH
ZLWKLQVWUXFWLRQVIRUXVHSURYLGHGLQWKHODEHOLQJFDQEH
HIIHFWLYHQHVV
UHDVRQDEO\H[SHFWHGWRUHVXOWLQVLJQLILFDQWLQMXU\WRWKH
XVHU
352'8&767$786'(),1,7,216
'HILQLWLRQ RI 7HUPV
'DWDVKHHW ,GHQWLILFDWLRQ
3URGXFW6WDWXV
'HILQLWLRQ
$GYDQFH,QIRUPDWLRQ
)RUPDWLYHRU
,Q'HVLJQ
7KLV GDWDVKHHW FRQWDLQV WKH GHVLJQ VSHFLILFDWLRQV IRU
SURGXFWGHYHORSPHQW6SHFLILFDWLRQVPD\FKDQJHLQ
DQ\PDQQHUZLWKRXWQRWLFH
3UHOLPLQDU\
)LUVW3URGXFWLRQ
7KLVGDWDVKHHWFRQWDLQVSUHOLPLQDU\GDWDDQG
VXSSOHPHQWDU\GDWDZLOOEHSXEOLVKHGDWDODWHUGDWH
)DLUFKLOG6HPLFRQGXFWRUUHVHUYHVWKHULJKWWRPDNH
FKDQJHVDWDQ\WLPHZLWKRXWQRWLFHLQRUGHUWRLPSURYH
GHVLJQ
1R,GHQWLILFDWLRQ1HHGHG
)XOO3URGXFWLRQ
7KLV GDWDVKHHW FRQWDLQV ILQDO VSHFLILFDWLRQV )DLUFKLOG
6HPLFRQGXFWRUUHVHUYHVWKHULJKWWRPDNHFKDQJHVDW
DQ\WLPHZLWKRXWQRWLFHLQRUGHUWRLPSURYHGHVLJQ
2EVROHWH
1RW,Q3URGXFWLRQ
7KLV GDWDVKHHW FRQWDLQV VSHFLILFDWLRQV RQ D SURGXFW
WKDWKDVEHHQGLVFRQWLQXHGE\)DLUFKLOGVHPLFRQGXFWRU
7KHGDWDVKHHWLVSULQWHGIRUUHIHUHQFHLQIRUPDWLRQRQO\
5HY,
www.fairchildsemi.com
© 2005 Fairchild Semiconductor Corporation