ICST ICS8745BYLF 1:5 differential-to-lvds zero delay clock generator Datasheet

ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8745B is a highly versatile 1:5 LVDS Clock
Generator and a member of the HiPerClockS™
HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8745B has a fully integrated PLL
and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz
to 700MHz. The Reference Divider, Feedback Divider and
Output Divider are each programmable, thereby allowing for
the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks.
The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock
is routed around the PLL and into the internal output dividers.
• 5 differential LVDS outputs designed to meet
or exceed the requirements of ANSI TIA/EIA-644
ICS
• Selectable differential clock inputs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 30ps (maximum)
• Output skew: 35ps (maximum)
• Static phase offset: 25ps ± 125ps
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
GND
Q2
nQ2
32 31 30 29 28 27 26 25
0
1
Q3
nQ3
PLL
Q4
nQ4
CLK_SEL
FB_IN
nFB_IN
nQ4
1
Q1
nQ1
Q4
CLK1
nCLK1
VDDO
0
SEL3
CLK0
nCLK0
VDDA
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
VDD
PLL_SEL
PLL_SEL
Q0
nQ0
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
SEL0
1
24
Q3
SEL1
2
23
nQ3
CLK0
3
22
VDDO
nCLK0
4
21
Q2
CLK1
5
20
nQ2
nCLK1
6
19
GND
CLK_SEL
7
18
Q1
MR
8
17
nQ1
ICS8745B
9 10 11 12 13 14 15 16
VDDO
Q0
nQ0
GND
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
SEL3
MR
8745BY
SEL2
SEL2
FB_IN
SEL1
nFB_IN
VDD
SEL0
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1
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
SEL0
Type
Input
Description
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
2
SEL1
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
3
CLK0
Input
Pulldown Non-inver ting differential clock input.
4
nCLK0
Input
5
CLK1
Input
6
nCLK1
Input
7
CLK_SEL
Input
8
MR
Input
9, 32
VDD
Power
10
nFB_IN
Input
11
FB_IN
Input
Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
12
SEL2
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pullup
Inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Clock select input. When HIGH, selects CLK1, nCLK1.
Pulldown
When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inver ted outputs nQx to go
Pulldown
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Core supply pins.
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
13, 19, 25
GND
Power
Power supply ground.
14, 15
nQ0, Q0
Output
Differential output pair. LVDS interface levels.
16, 22, 28
VDDO
Power
Output supply pins.
17, 18
nQ1, Q1
Output
Differential output pair. LVDS interface levels.
20, 21
nQ2, Q2
Output
Differential output pair. LVDS interface levels.
23, 24
nQ3, Q3
Output
Differential output pair. LVDS interface levels.
26, 27
nQ4, Q4
Output
Differential output pair. LVDS interface levels.
29
SEL3
Input
30
VDDA
Power
31
PLL_SEL
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pullup
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
8745BY
Test Conditions
Minimum
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2
Typical
Maximum
Units
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)*
Outputs
PLL_SEL = 1
PLL Enable Mode
Q0:Q4, nQ0:nQ4
0
0
0
0
250 - 700
÷1
0
0
0
1
125 - 350
÷1
Inputs
0
0
1
0
62.5 - 175
÷1
0
0
1
1
31.25 - 87.5
÷1
0
1
0
0
250 - 700
÷2
0
1
0
1
125 - 350
÷2
0
1
1
0
62.5 - 175
÷2
0
1
1
1
250 -700
÷4
1
0
0
0
125 - 350
÷4
1
0
0
1
250 - 700
÷8
1
0
1
0
125 - 350
x2
1
0
1
1
62.5 - 175
x2
1
1
0
0
31.25 - 87.5
x2
1
1
0
1
62.5 - 175
x4
1
1
1
0
31.25 - 87.5
x4
1
1
1
1
31.25 - 87.5
x8
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
SEL3
SEL2
SEL1
SEL0
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q0:Q4, nQ0:nQ4
0
0
0
0
÷4
0
0
0
1
÷4
Inputs
8745BY
0
0
1
0
÷4
0
0
1
1
÷8
0
1
0
0
÷8
0
1
0
1
÷8
0
1
1
0
÷ 16
0
1
1
1
÷ 16
1
0
0
0
÷ 32
1
0
0
1
÷ 64
1
0
1
0
÷2
1
0
1
1
÷2
1
1
0
0
÷4
1
1
0
1
÷1
1
1
1
0
÷2
1
1
1
1
÷1
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3
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
125
mA
IDDA
Analog Supply Current
17
mA
IDDO
Output Supply Current
59
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input High Current
Input Low Current
Test Conditions
Minimum
Maximum
Units
2
Typical
VDD + 0.3
V
-0.3
0.8
V
VDD = VIN = 3.465V
150
µA
VDD = VIN = 3.465V
5
µA
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
PLL_SEL
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
VDD = 3.465V, VIN = 0V
-5
µA
PLL_SEL
VDD = 3.465V, VIN = 0V
-150
µA
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Maximum
Units
CLK0, CLK1, FB_IN
VDD = VIN = 3.465V
Test Conditions
Minimum
Typical
150
µA
VDD = VIN = 3.465V
5
µA
IIH
Input
High Current
nCLK0, nCLK1, nFB_IN
IIL
Input
Low Current
CLK0, CLK1, FB_IN
VDD = 3.465V, VIN = 0V
-5
µA
nCLK0, nCLK1, nFB_IN
VDD = 3.465V, VIN = 0V
-150
µA
VPP
Peak-to-Peak Input Voltage
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.15
1.3
V
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
8745BY
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4
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VOD
Differential Output Voltage
Test Conditions
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
Minimum
Typical
Maximum
Units
320
440
550
mV
0
50
mV
1.05
1.2
1.35
V
25
mV
Maximum
Units
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fIN
Input Frequency
CLK0, nCLK0,
CLK1, nCLK1
Test Conditions
Minimum
PLL_SEL = 1
31.25
Typical
PLL_SEL = 0
700
MHz
700
MHz
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
tsk(Ø)
Static Phase Offset; NOTE 2, 5
tsk(o)
Output Skew; NOTE 3, 5
Test Conditions
Minimum
Typical
PLL_SEL = 0V, f ≤ 700MHz
3.1
3. 4
PLL_SEL = 3.3V
-100
25
Maximum
Units
700
MHz
3. 7
ns
150
ps
35
ps
tjit(cc)
Cycle-to-Cycle Jitter ; NOTE 5, 6
30
ps
tjit(θ)
Phase Jitter ; NOTE 4, 5, 6
±52
ps
odc
Output Duty Cycle
54
%
tL
PLL Lock Time
1
ms
70 0
ps
46
50
tR / tF
Output Rise/Fall Time; NOTE 7
200
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback
input signal across all conditions, when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.
8745BY
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5
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VDD
3.3V
SCOPE
Qx
nCLK0,
nCLK1
Power Supply
+
Float GND
V
LVDS
-
V
Cross Points
PP
CMR
CLK0,
CLK1
nQx
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nCLK0,
nCLK1
CLK0,
CLK1
VOH
nQx
VOL
Qx
nFB_IN
VOH
FB_IN
VOL
Qy
➤
➤ t (Ø)
nQy
t sk(o)
tjit(Ø) = t (Ø) — t (Ø) mean = Phase Jitter
t (Ø) mean = Static Phase Offset
(where t (Ø) is any random sample, and t (Ø) mean is the average
of the sampled cycles measured on controlled edges)
PHASE JITTER
AND
STATIC PHASE OFFSET
OUTPUT SKEW
nQ0:nQ4
80%
80%
Q0:Q4
VOD
n
➤
tcycle
➤
tcycle n+1
Clock
Outputs
➤
20%
20%
tR
tF
➤
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYLE-TO-CYCLE JITTER
8745BY
OUTPUT RISE/FALL TIME
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6
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
nCLK0,
nCLK1
nQ0:nQ4
CLK0,
CLK1
Q0:Q4
Pulse Width
t
nQ0:nQ4
Q0:Q4
tPD
odc =
PERIOD
t PW
t PERIOD
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
VDD
out
out
➤
DC Input
LVDS
➤
VOD/Δ VOD
VOS/Δ VOS
➤
out
OFFSET VOLTAGE SETUP
8745BY
100
➤
LVDS
➤
DC Input
➤
out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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7
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100Ω differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver in-
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
8745BY
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8
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8745B provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 3 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01μF
10Ω
VDDA
10 μF
.01μF
FIGURE 3. POWER SUPPLY FILTERING
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER
BY
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
BY
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
Receiv er
R2
84
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER
8745BY
nCLK
Zo = 50 Ohm
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVDS DRIVER
BY
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9
BY
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
LAYOUT GUIDELINE
The schematic of the ICS8745B layout example is shown in
Figure 5A. The ICS8745B recommended PCB board layout
for this example is shown in Figure 5B. This layout example
is used as a general guideline. The layout in the actual sys-
tem will depend on the selected component types, the density of the components, the density of the traces, and the
stack up of the P.C. board.
VDD
SP = Space (i.e. not intstalled)
R7
RU2
SP
RU3
1K
RU4
1K
RU5
SP
RU6
1K
VDD
VDDA
RU7
SP
10
C11
0.01u
CLK_SEL
PLL_SEL
SEL0
SEL1
SEL2
SEL3
RD4
SP
RD5
1K
RD6
SP
RD7
1K
Zo = 50 Ohm
+
SEL3
RD3
SP
(77.76 MHz)
PLL_SEL
RD2
1K
C16
10u
VDD
R4
100
VDDO
-
LVDS_input
(155.5 MHz)
SEL0
SEL1
Zo = 50 Ohm
CLK_SEL
R8A
50
R9
50
8745
R10
50
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
VDD
nFB_IN
FB_IN
SEL2
GND
nQ0
Q0
VDDO
3.3V PECL Driver
1
2
3
4
5
6
7
8
Q3
nQ3
VDDO
Q2
nQ2
GND
Q1
nQ1
24
23
22
21
20
19
18
17
VDD=3.3V
VDDO=3.3V
9
10
11
12
13
14
15
16
Zo = 50 Ohm
VDD
PLL_SEL
VDDA
SEL3
VDDO
Q4
nQ4
GND
U3
3.3V
32
31
30
29
28
27
26
25
Zo = 50 Ohm
SEL[3:0] = 0101,
Divide by 2
SEL2
R2
100
Decoupling capacitor located near the power pins
(U1-9) VDD
C1
0.1uF
(U1-32)
C6
0.1uF
(U1-22)
C4
0.1uF
VDDO
(U1-28)
C5
0.1uF
(U1-16)
C2
0.1uF
FIGURE 5A. ICS8745B LVDS ZERO DELAY BUFFER SCHEMATIC EXAMPLE
8745BY
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10
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
The following component footprints are used in this layout
example:
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
All the resistors and capacitors are size 0603.
POWER
AND
GROUNDING
• The differential 50Ω output traces should have same
length.
Place the decoupling capacitors C1, C6, C2, C4, and C5, as
close as possible to the power pins. If space allows, placement
of the decoupling capacitor on the component side is preferred.
This can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
GND
R7
C16
C11
C5
VDDO
C6
VDD
U1
Pin 1
C4
VDDA
VIA
50 Ohm
Traces
C1
C2
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8745B
8745BY
www.icst.com/products/hiperclocks.html
11
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8745B is: 2772
8745BY
www.icst.com/products/hiperclocks.html
12
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
FOR
32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
8745BY
www.icst.com/products/hiperclocks.html
13
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS8745BY
ICS8745BY
32 Lead LQFP
tray
0°C to 70°C
ICS8745BYT
ICS8745BY
32 Lead LQFP
1000 tape & reel
0°C to 70°C
ICS8745BYLF
ICS8745BYLF
32 Lead "Lead-Free" LQFP
tray
0°C to 70°C
ICS8745BYLFT
ICS8745BYLF
32 Lead "Lead-Free" LQFP
1000 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
8745BY
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14
REV. B DECEMBER 2, 2004
ICS8745B
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
Page
B
T4D
5
T9
1
14
1
T9
14
B
B
8745BY
Description of Change
LVDS DC Characteristics Table - modified VOS 0.90V min. to 1.05V min,
1.15V typical to 1.2V typical, and 1.4V max. to 1.35V max.
Added Lead-Free bullet.
Ordering Information Table - added Lead-Free par t.
Features Section - delete bullet, "Industrial temperature available upon
request."
Ordering Information Table - added Lead-Free note.
www.icst.com/products/hiperclocks.html
15
Date
3/17/04
12/2/04
3/18/05
REV. B DECEMBER 2, 2004
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