Cypress CY2SSTV16859ZCT 13-bit to 26-bit registered buffer pc2700-/pc3200-compliant Datasheet

CY2SSTV16859
13-Bit to 26-Bit Registered Buffer
PC2700-/PC3200-Compliant
Features
• Differential clock inputs up to 280 MHz
• Supports LVTTL switching levels on the RESET# pin
• Output drivers have controlled edge rates, so no
external resistors are required.
• Two KV ESD protection
• Latch-up performance exceeds 100 mA per JESD78,
Class II
• 64-pin TSSOP/JEDEC and 56-pin QFN package availability
• JEDEC specification supported
Description
This 13-bit to 26-bit registered buffer is designed for 2.3V to
2.7 VDD operations.
All inputs are compatible with the JEDEC Standard for SSTL-2,
except the LVCMOS reset (RESET#) input. All outputs are
SSTL_2, Class II compatible.
The CY2SSTV16859 operates from a differential clock (CLK
and CLK#) of frequency up to 280 MHz. Data are registered at
crossing of CLK going high and CLK# going low.
When RESET# is low, the differential input receivers are
disabled, and undriven (floating) data and clock inputs are
allowed. The LVCMOS RESET# input must always be held at
a valid logic high or low level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET# must be held in the low
state during power up.
In the DDR DIMM application, RESET# is completely
asynchronous with respect to CLK# and CLK. Therefore, no
timing relationship can be guaranteed between the two. When
entering reset, the register is cleared and the outputs are
driven low quickly, relative to the time to disable the differential
input receivers, thus ensuring no glitches on the output.
However, when coming out of reset, the register becomes
active quickly, relative to the time to enable the differential
input receivers.
Pin Configuration
Block Diagram
RESET #
CLK
CLK #
D1
Q1A
D
VREF
C
Q1B
R
To 12 Other Channels
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CY2SSTV16859
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDQ
GND
D13
D12
VDD
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESET #
GND
CLK #
CLK
VDDQ
VDD
VREF
D6
GND
D5
D4
D3
GND
VDDQ
VDD
D2
D1
GND
VDDQ
64 TSSOP Package
Cypress Semiconductor Corporation
Document #: 38-07463 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 29, 2003
CY2SSTV16859
D11
VDDQ
VDD
D12
D13
GND
VDDQ
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
Q8A
Pin Configuration (continued)
6
37
GND
Q1A
7
36
CLK#
Q13B
8
35
CLK
VDDQ
Q12B
9
34
VDDQ
10
33
VDD
Q11B
11
32
VREF
Q10B
12
31
D6
Q9B
13
30
D5
Q8B
14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29
D4
D10
D8
D3
Q7B
VDDQ
Q2A
VDD
RESET#
D2
38
D1
5
VDDQ
Q3A
Q1B
D7
Q2B
39
Q3B
4
Q4B
Q4A
Q5B
2
3
D9
Q5A
41
40
Q6A
Q6B
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
VDDQ
1
Q7A
56 QFN Package
Pin Description
Pin
TSSOP
Name
Description
QFN
51
38
RESET#
Disable Clocking and Reset Latch
7,15,34,39,43,50,54,58,63
37,48
GND
Ground
37,46,60
26,33,45
VDD
Supply Voltage
6,18,27,33,38,47,59,64
9,17,23,27,34,44,49,55
VDDQ
Supply Voltage, Quiet
45
32
VREF
Reference Voltage for Data Inputs
D(1:13)
16,14,13,12,11,10,9,8,5,4,3,2,1
7,6,5,4,3,2,1,56,54,53,52,51,50
QA(1:13)
Data Outputs
32,31,30,29,28,25,24,23,22,21,20, 22,21,20,19,18,16,15,14,13,12
19,17
11,10,8
QB(1:13)
Data Outputs
35,36,40,41,42,44,52,53,55,56,57, 24,25,28,29,30,31,39,40,41,42
61,62
43,46,47
D(1:13)
48,49
35,36
Table 1. Function Table
Data Inputs
CLK, CLK# Differential Clock Signals
[1,2,3]
INPUTS
OUTPUT
RESET#
CLK
CLK#
D
Q
H
↑
↓
L
L
H
↑
↓
H
H
H
L or H
L or H
X
Q0
L
X or floating
X or floating
X or floating
L
Notes:
1. H = High voltage level.
2. L = Low voltage level.
3. X = Don’t care.
Document #: 38-07463 Rev. *B
Page 2 of 8
CY2SSTV16859
Absolute Maximum Conditions[4,5]
Parameter
Description
Condition
Max.
Unit
–0.5
3.6
V
–0.5
VDD + 0.5
V
Storage Temperature
–65°
150°C
°C
DC Output Current
–50
50
mA
VI<0 or VI>VSS
–50
50
mA
VO<0 or VO>VDD
–50
50
mA
–100
100
mA
[6]
Terminal Voltage with respect to VSS
VTERM[7]
Terminal Voltage with respect to VSS
TSTG
IOUT
IIK
Continuous Clamp Current
IOK
Continuous Clamp Current
Idd
ISS
Continuous Current through each VDD, VDDQ or VSS
VTERM
Min.
Recommended Operating Conditions[8]
Parameter
VDD
VDDQ
Description
Min.
Typ.
Max.
Unit
2.3
2.5
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
PC1600,PC2100,PC2700
1.15
1.25
1.35
V
PC3200
1.25
1.3
1.35
V
VREF – 40 mV
VREF
VREF + 40 mV
V
0
–
VDD
V
Supply voltage
Output supply voltage PC1600,PC2100,PC2700
PC3200
VREF
VTT
Reference voltage
(VREF = VDDQ/2)
Termination voltage
VI
Input voltage
VIH
AC Data Input high-level voltage
VREF + 310 mV
–
–
V
VIL
AC Data Input low-level voltage
–
–
VREF – 310 mV
V
VIH
DC Data Input high-level voltage
VREF + 150 mV
–
–
V
VIL
DC Data Input low-level voltage
–
–
VREF – 150 mV
V
VIH
RESET# Input high-level voltage
1.7
–
–
V
VIL
RESET# Input low-level voltage
–
–
0.7
V
VICR
CLK, CLK# Common-mode input voltage range
0.97
–
1.53
V
VI(PP)
CLK, CLK# Peak-to-peak input voltage
360
–
–
mV
IOH
High-level output current
–
–
–20
mA
IOL
Low-level output current
–
–
20
mA
TA
Operating free-air temperature
0
–
85
°C
DC Electrical Specifications
Parameter
Description
Condition
Min.
Typ.[9]
Max.
Unit
2.3V
–
–
–1.2
V
VIK
Clamp Voltage
VOH
High level output IOH = –100 µA
voltage
IOH = –16 mA
2.3 to 2.7V
VDD – 0.2
–
–
V
2.3V
1.95
–
–
V
Low level output IOL = 100 µA
voltage
IOL = 16 mA
2.3 to 2.7V
–
–
0.2
V
2.3
–
–
0.35
V
VOL
II = –18 mA
VDD
II
All Inputs
VI = VDD or VSS
IDD
Static Standby
RESET# = VSS
IO = 0
2.7V
–
–
±5
µA
2.7V
–
–
10
µA
Static Operating RESET# = VDD, VI = VIH(AC) or VIL(AC)
2.7
–
–
40.0
mA
Notes:
4. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. Stresses greater than those listed under Absolute Maximum Conditions may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended period may affect reliability.
6. VDD/VDDQ terminals.
7. All terminals except VDD.
8. The RESET# input of the device must be held at VDD or VSS to ensure proper device operation.
9. All typical values are measured at TAMB = 25°C
Document #: 38-07463 Rev. *B
Page 3 of 8
CY2SSTV16859
DC Electrical Specifications (continued)
Parameter
IDDD
Description
Condition
Dynamic
RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0
operating – clock CLK and CLK# switching 50% duty
cycle
only
VDD
Min.
Typ.[9]
Max.
Unit
2.7V
–
30.0
–
µA/
clock
MHz
2.7
–
15.0
–
µA/
clock
MHz
/data
input
Ω
Dynamic
operating – per
each data input
RESET# = VDD, VI = VIH(AC) or VIL(AC),
CLK and CLK# switching 50% duty
cycle. One data input switching at half
clock frequency, 50% duty cycles.
rOH
Output high
IOH = –20 mA
2.3 to 2.7V
7
–
20
rOL
Output low
IOL = 20 mA
2.3 to 2.7V
7
–
20
Ω
rO(∆)
|rOH – rOL| each IO = 20 mA, TA = 25°C
separate bit
2.5V
–
–
4
Ω
Ci
Data Inputs
VI = VREF + 310 mV
2.5
2.5
–
3.5
pF
CLK and CLK#
VICR = 1.25V, VI(PP) = 360 mV
2.5
2.5
–
3.5
pF
RESET#
VI = VDD or VSS
2.5
2.5
–
3.5
pF
AC Electrical Specifications
VDD = 2.5V± 0.2V
Parameter
Description
fclock
Clock Frequency
tw
Pulse duration, CLK, CLK# high or low
tact
tinact
tsu
Set-up time, fast slew rate[10, 12]
Max.
Unit
–
280
MHz
2.0
–
ns
Differential inputs active time (data inputs must be held low after RESET# is taken high).
–
22
ns
Differential inputs inactive time (data and clock inputs must be held at valid levels
(not floating) after RESET# is taken low).
–
22
ns
Data before CLK↑, CLK#↓
0.75
–
ns
0.9
–
ns
Data after CLK ↑, CLK#↓
0.75
–
ns
0.9
–
ns
[11, 12]
Set-up time, slow slew rate
th
Min.
Hold time, fast slew rate[10, 12]
Hold time, slow slew rate[11, 12]
Table 2. Switching Characteristics Over Recommended Operating Conditions[13]
Parameter
From (Input)
To (Output)
fmax
tPHL
RESET#
Q
tPD
CLK and CLK#
Q
VDD = 2.5V ± 0.2V
Unit
Min.
Max.
280
–
5
ns
1.1
2.8
ns
MHz
Notes:
10. For data signal input slew rate ≥ 1 V/ns.
11. For data signal input slew rate ≥ V/ns and < 1V/ns.
12. CLK and CLK# signals input slew rates are ≥ 1 V/ns.
13. See test circuits and waveforms. TA = 0°C to +85°C.
Document #: 38-07463 Rev. *B
Page 4 of 8
CY2SSTV16859
Output Buffer Characteristics
Table 3. Output Buffer Voltage vs. Current (V/I) Characteristics
Pull-Down
Pull-Up
Voltage (V)
Min. I(mA)
Max. I(mA)
Min. I(mA)
Max. I(mA)
0
0
0
–55
–162
0.1
6
13
–55
–161
0.2
10
25
–54
–160
0.3
15
38
–54
–159
0.4
19
49
–54
–157
0.5
23
60
–54
–156
0.6
27
71
–53
–154
0.7
30
81
–53
–152
0.8
34
91
–53
–149
0.9
36
100
–52
–146
1.0
38
108
–52
–143
1.1
40
115
–52
–140
1.2
42
123
–51
–137
1.3
43
130
–50
–134
1.4
44
137
–48
–130
1.5
44
144
–46
–125
1.6
45
150
–44
–120
1.7
45
158
–40
–112
1.8
45
165
–38
–104
1.9
45
172
–35
–96
2.0
45
179
–31
–83
2.1
46
185
–28
–72
2.2
46
191
–23
–60
2.3
46
196
–19
–49
2.4
46
201
–15
–38
2.5
46
206
–10
–27
2.6
46
211
–5
–15
2.7
46
216
0
0
Table 4. Output Buffer Slew-Rate Characteristics
dV/dt
Min.
Max.
Rise
0.85 V/ns
15.9 V/ns
Fall
1.00 V/ns
18.9 V/ns
Document #: 38-07463 Rev. *B
Page 5 of 8
CY2SSTV16859
Parameter Measurement Information[14]
VDD = 2.5V ± 0.2V
Timing Diagrams
V TT*
LVCMOS
RESET#
Input
R L = 50 O h m
F ro m
O u tpu t
U n de r
T es t
VIH
V DD /2
VIL
tPHL
T es t P oin t
Output
C L = 30 pF
Figure 1. Load Circuit[15]
V OH
VTT
V OL
Figure 4. Voltage Waveforms Propagation Delay Times
V I(PP)
V ICR
Timing Input
t su
Data Input
th
tw
V REF *
V REF *
V IH **
V IL***
Figure 2. Voltage Waveforms Set-up and Hold Times
VI(PP)
VICR
Input
Input
V REF *
LVCMOS
RESET#
Input
IDD
tPHL
VTT
Output
VTT
V IH **
V IL ***
Figure 5. Voltage Waveforms Pulse Duration[18,19]
VICR
tPLH
V REF *
VDD/2
tinact
VDD/2
tact
10%
90%
VOH
VOL
Figure 3. Voltage Waveforms Propagation
Delay Times[16, 17]
VDD
0V
IDDH
IDDL
Figure 6. Voltage Waveforms Enable and Disable Times
Low- and High-level Enabling
Ordering Information
Part Number
Package Type
Product Flow
CY2SSTV16859ZC
64-pin TSSOP
Commercial, 0° to 70°C
CY2SSTV16859ZCT
64-pin TSSOP– Tape and Reel
Commercial, 0° to 70°C
CY2SSTV16859ZI
64-pin TSSOP
Industrial, –40° to 85°C
CY2SSTV16859ZIT
64-pin TSSOP – Tape and Reel
Industrial, –40° to 85°C
CY2SSTV16859LFC
56-pin QFN
Commercial, 0° to 70°C
CY2SSTV16859LFCT
56-pin QFN – Tape and Reel
Commercial, 0° to 70°C
CY2SSTV16859LFI
56-pin QFN
Industrial, –40° to 85°C
CY2SSTV16859LFIT
56-pin QFN– Tape and Reel
Industrial, –40° to 85°C
Notes:
14. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, ZO = 50-ohm output slew rate = 1 V/ns ±20% (unless otherwise
specified).
15. CL includes probe and jig capacitance.
16. the outputs are measured one at a time with one transition per measurement.
17. *VTT = VREF = VDDQ/2.
18. **VIH = VREF + 350 mV (AC voltage levels).
19. ***VIL = VREF - 350 mV (AC voltage levels).
Document #: 38-07463 Rev. *B
Page 6 of 8
CY2SSTV16859
Package Drawing and Dimension
64-lead Thin Shrunk Small Outline Package (6 mm x 17 mm) Z64
51-85153-**
56-Lead QFN 8 x 8 MM LF56A
51-85144-*D
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07463 Rev. *B
Page 7 of 8
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2SSTV16859
Document History Page
Document Title:CY2SSTV16859 13-Bit to 26-Bit Registered Buffer
PC2700-/PC3200-Compliant
Document Number: 38-07463
REV.
ECN No.
Issue
Date
Orig. of
Change
**
123052
04/14/03
RGL
New Data Sheet
*A
126277
04/21/02
KKV
Added commercial information to ordering information table, was not added
in previous rev **
Added to title “PC2700-/PC3200- Compliant“
*B
128326
07/30/03
RGL
Added 56 QFN packages (Industrial and Commercial) in the device
Document #: 38-07463 Rev. *B
Description of Change
Page 8 of 8
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