AD ADF4111BRU 50 mhz to 1000 mhz quadrature demodulator Datasheet

50 MHz to 1000 MHz
Quadrature Demodulator
AD8348
FEATURES
ENBL 15
VREF
IMXO
IOFS
IAIN
IOPP
IOPN
14
8
13
6
4
3
BIAS
CELL
VREF
5
VCMO
1
LOIP
28
LOIN
VCMO
IFIP 11
DIVIDE
BY 2
IFIN 10
PHASE
SPLITTER
AD8348
VGIN 17
GAIN
CONTROL
VCMO
18
19
24
MXIP MXIN ENVG
21
16
23
QXMO
QOFS
QAIN
25
26
QOPP QOPN
03678-001
Integrated I/Q demodulator with IF VGA amplifier
Operating IF frequency 50 MHz to 1000 MHz
(3 dB IF BW of 500 MHz driven from RS = 200 Ω)
Demodulation bandwidth 75 MHz
Linear-in-decibel AGC range 44 dB
Third-order intercept
IIP3 +28 dBm @ minimum gain (FIF = 380 MHz)
IIP3 −8 dBm @ maximum gain (FIF = 380 MHz)
Quadrature demodulation accuracy
Phase accuracy 0.5°
Amplitude balance 0.25 dB
Noise figure 11 dB @ maximum gain (FIF = 380 MHz)
LO input −10 dBm
Single supply 2.7 V to 5.5 V
Power-down mode
Compact, 28-lead TSSOP package
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
APPLICATIONS
QAM/QPSK demodulator
W-CDMA/CDMA/GSM/NADC
Wireless local loop
LMDS
GENERAL DESCRIPTION
The AD8348 is a broadband quadrature demodulator with an
integrated intermediate frequency (IF), variable gain amplifier
(VGA), and integrated baseband amplifiers. It is suitable for use in
communications receivers, performing quadrature demodulation
from IF directly to baseband frequencies. The baseband amplifiers
are designed to interface directly with dual-channel ADCs, such
as the AD9201, AD9283, and AD9218, for digitizing and postprocessing.
The IF input signal is fed into two Gilbert cell mixers through
an X-AMP® VGA. The IF VGA provides 44 dB of gain control.
A precision gain control circuit sets a linear-in-decibel gain characteristic for the VGA and provides temperature compensation.
The LO quadrature phase splitter employs a divide-by-2 frequency
divider to achieve high quadrature accuracy and amplitude balance
over the entire operating frequency range.
Optionally, the IF VGA can be disabled and bypassed. In this
mode, the IF signal is applied directly to the quadrature mixer
inputs via the MXIP and MXIN pins.
Separate I- and Q-channel baseband amplifiers follow the baseband
outputs of the mixers. The voltage applied to the VCMO pin sets
the dc common-mode voltage level at the baseband outputs.
Typically, VCMO is connected to the internal VREF voltage, but
it can also be connected to an external voltage. This flexibility
allows the user to maximize the input dynamic range to the ADC.
Connecting a bypass capacitor at each offset compensation input
(IOFS and QOFS) nulls dc offsets produced in the mixer. Offset
compensation can be overridden by applying an external voltage
at the offset compensation inputs.
The mixers’ outputs are brought off-chip for optional filtering
before final amplification. Inserting a channel selection filter
before each baseband amplifier increases the baseband amplifiers’
signal handling range by reducing the amplitude of high level,
out-of-channel interferers before the baseband signal is fed into
the I/Q baseband amplifiers. The single-ended mixer output is
amplified and converted to a differential signal for driving ADCs.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8348
TABLE OF CONTENTS
Features .............................................................................................. 1
Enable........................................................................................... 18
Applications....................................................................................... 1
Baseband Offset Cancellation................................................... 18
Functional Block Diagram .............................................................. 1
Applications..................................................................................... 20
General Description ......................................................................... 1
Basic Connections...................................................................... 20
Revision History ............................................................................... 2
Power Supply............................................................................... 20
Specifications..................................................................................... 3
Device Enable ............................................................................. 20
Absolute Maximum Ratings............................................................ 6
VGA Enable ................................................................................ 20
ESD Caution.................................................................................. 6
Gain Control ............................................................................... 20
Pin Configuration and Function Descriptions............................. 7
LO Inputs..................................................................................... 20
Equivalent Circuits ........................................................................... 9
IF Inputs ...................................................................................... 20
Typical Performance Characteristics ........................................... 11
MX Inputs ................................................................................... 20
VGA and Demodulator ............................................................. 11
Baseband Outputs ...................................................................... 21
Demodulator Using MXIP and MXIN.................................... 14
Output DC Bias Level ................................................................ 21
Final Baseband Amplifiers ........................................................ 15
Interfacing to Detector for AGC Operation............................... 21
VGA/Demodulator and Baseband Amplifier......................... 16
Baseband Filters.......................................................................... 22
Theory of Operation ...................................................................... 18
LO Generation ............................................................................ 23
VGA.............................................................................................. 18
Evaluation Board ........................................................................ 23
Downconversion Mixers ........................................................... 18
Outline Dimensions ....................................................................... 28
Phase Splitter............................................................................... 18
Ordering Guide .......................................................................... 28
I/Q Baseband Amplifiers........................................................... 18
REVISION HISTORY
4/06—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Specifications ................................................................ 3
Changes to IF Inputs Section ........................................................ 20
Changes to Evaluation Board Section.......................................... 23
Changes to Table 6.......................................................................... 27
Changes to Ordering Guide .......................................................... 28
8/03—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD8348
SPECIFICATIONS
VS = 5 V, TA = 25oC, FLO = 380 MHz, FIF = 381 MHz, PLO = −10 dBm, RS (LO) = 50 Ω, RS (IFIP and MXIP/MXIN) = 200 Ω, unless
otherwise noted.
Table 1.
Parameter
OPERATING CONDITIONS
LO Frequency Range
IF Frequency Range
Baseband Bandwidth
LO Input Level
VSUPPLY (VS)
Temperature Range
IF FRONT END WITH VGA
Input Impedance
Gain Control Range
Maximum Conversion Voltage Gain
Minimum Conversion Voltage Gain
3 dB Bandwidth
Gain Control Linearity
IF Gain Flatness
Input 1 dB Compression Point (P1dB)
Second-Order Input Intercept (IIP2)
Third-Order Input Intercept (IIP3)
LO Leakage
Demodulation Bandwidth
Quadrature Phase Error 1
Conditions
Min
External input = 2 × LO frequency
100
50
50 Ω source
−12
2.7
−40
IFIP to IMXO (QMXO),
ENVG = 5 V, IMXO/QMXO load = 1.5 kΩ
Measured differentially across MXIP/MXIN
Unit
2000
1000
MHz
MHz
MHz
dBm
V
°C
0
5.5
+85
Ω||pF
dB
dB
dB
MHz
dB
dB p-p
dB p-p
VGIN = 0.2 V (maximum gain)
VGIN = 1.2 V (maximum gain)
IF1 = 385 MHz, IF2 = 386 MHz
+3 dBm each tone from 200 Ω source,
VGIN = 1.2 V (minimum gain)
−42 dBm each tone from 200 Ω source,
VGIN = 0.2 V (maximum gain)
IF1 = 381 MHz, IF2 = 381.02 MHz
Each tone 10 dB below P1dB from
200 Ω source,
VGIN = 1.2 V (minimum gain)
Each tone 10 dB below P1dB from
200 Ω source,
VGIN = 0.2 V (maximum gain)
−22
+13
dBm
dBm
65
dBm
18
dBm
28
dBm
−8
dBm
Measured at IFIP, IFIN
Measured at IMXO/QMXO (LO = 50 MHz)
Small signal 3 dB bandwidth
LO = 380 MHz (LOIP/LOIN 760 MHz)
vs. temperature
vs. baseband frequency (dc to 30 MHz)
−80
−60
75
±0.1
−0.0032
+0.01
±0.05
0
±0.0125
10.75
dBm
dBm
MHz
Degrees
°/°C
°/MHz
dB
dB/°C
dB
dB
VGIN = 0.2 V (maximum voltage gain)
VGIN = 1.2 V (minimum voltage gain)
VGIN = 0.4 V (+21 dB) to 1.1 V (−14 dB)
FIF = 380 MHz ± 5% (VGIN = 1.2 V)
FIF = 900 MHz ± 5% (VGIN = 1.2 V)
−0.7
−0.3
vs. temperature
vs. baseband frequency (dc to 30 MHz)
Maximum gain, from 200 Ω source,
FIF = 380 MHz
Mixer Output Impedance
Capacitive Load
Resistive Load
Mixer Peak Output Current
75
−10
Max
200||1.1
44
25.5
−18.5
500
±0.5
0.1
1.3
I/Q Amplitude Imbalance1
Noise Figure (Double Sideband)
Typ
+0.7
+0.3
40
Shunt from IMXO, QMXO to VCMO
Shunt from IMXO, QMXO to VCMO
Rev. A | Page 3 of 28
0
200
Ω
10
1.5
2.5
pF
kΩ
mA
AD8348
Parameter
IF FRONT END WITHOUT VGA
Input Impedance
Conversion voltage Gain
3 dB Output Bandwidth
IF Gain Flatness
Input 1 dB Compression Point (P1dB)
Third-Order Input Intercept (IIP3)
LO Leakage
Demodulation Bandwidth
Quadrature Phase Error
I/Q Amplitude Imbalance
Noise Figure (Double Sideband)
I/Q BASEBAND AMPLIFIER
Gain
Bandwidth
Output DC Offset (Differential)
Output Common-Mode Offset
Group Delay Flatness
Input-Referred Noise Voltage
Output Swing Limit (Upper)
Output Swing Limit (Lower)
Peak Output Current
Input Impedance
Input Bias Current
RESPONSE FROM IF AND MX INPUTS TO
BASEBAND AMPLIFIER OUTPUT
Gain
CONTROL INPUT/OUTPUTS
VCMO Input Range
VREF Output Voltage
Gain Control Voltage Range
Gain Slope
Gain Intercept
Gain Control Input Bias Current
LO INPUTS
LOIP Input Return Loss
Conditions
From MXIP, MXIN to IMXO (QMXO),
ENVG = 0 V, IMXO/QMXO load = 1.5 kΩ
Measured differentially across MXIP/MXIN
Min
FIF = 380 MHZ ± 5%
FIF = 900 MHZ ± 5%
IF1 = 381 MHz, IF2 = 381.02 MHz
Each tone 10 dB below P1dB from
200 Ω source
Measured at MXIP/MXIN
Measured at IMXO, QMXO
Small signal 3 dB bandwidth
LO = 380 MHz (LOIP/LOIN 760 MHz,
single-ended)
−2
From 200 Ω source, FIF = 380 MHz
From IAIN to IOPP/IOPN and QAIN to QOPP/
QOPN, RLOAD = 2 kΩ, single-ended to ground
10 pF differential load
LO leakage offset corrected using 500 pF
capacitor on IOFS, QOFS (VIOPP − VIOPN)
(VIOPP + VIOPN)/2 − VCMO
0 MHz to 50 MHz
Frequency = 1 MHz
−50
−75
Typ
Max
200||1.5
10.5
75
0.1
0.15
−4
14
Ω||pF
dB
MHz
dB p-p
dB p-p
dBm
dBm
−70
−60
75
±0.5
dBm
dBm
MHz
Degrees
+2
0.25
21
dB
dB
20
125
±12
dB
MHz
mV
±35
3
8
+50
+75
1
50||1
2
mV
ns p-p
nV/√Hz
V
V
mA
kΩ||pF
μA
30.5
45.5
1.5
dB
dB
dB
VS −1
0.5
IMXO and QMXO connected directly to
IAIN and QAIN, respectively
From MXIP/MXIN
From IFIP/IFIN, VGIN = 0.2 V
From IFIP/IFIN, VGIN = 1.2 V
VS = 5 V
VS = 2.7 V
VGIN
Linear extrapolation back to theoretical
gain at VGIN = 0 V
LOIN ac-coupled to ground
(760 MHz applied to LOIP)
Rev. A | Page 4 of 28
0.5
0.5
0.95
0.2
−55
55
Unit
1
1
1
−50
61
4
1.7
1.05
1.2
−45
67
V
V
V
V
dB/V
dB
1
μA
−6
dB
AD8348
Parameter
POWER-UP CONTROL
ENBL Threshold Low
ENBL Threshold High
Input Bias Current
Power-Up Time
Power-Down Time
POWER SUPPLIES
Voltage
Current (Enabled)
Current (Standby)
1
Conditions
Min
Typ
Max
Unit
Low = standby
High = enable
0
VS − 1
VS/2
VS/2
2
45
1
VS
V
V
μA
μs
Time for final baseband amplifiers to be
within 90% of final amplitude
Time for supply current to be <10% of
enabled value
VPOS1, VPOS2, VPOS3
VS = 5 V, VENBL = 5 V
VS = 5 V, VENBL = 0 V
These parameters are guaranteed but not tested in production. Limits are ±6 Σ from the mean.
Rev. A | Page 5 of 28
700
2.7
38
48
75
ns
5.5
58
V
mA
μA
AD8348
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage on VPOS1, VPOS2, VPOS3 Pins
LO Input Power
IF Input Power
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
5.5 V
10 dBm (re: 50 Ω)
18 dBm (re: 200 Ω)
450 mW
68°C/W
150°C
−40°C to +85°C
−65°C to +125°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 28
AD8348
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LOIP 1
IOPN 3
IOPP 4
VCMO 5
IAIN 6
28 LOIN
AD8348
27 COM1
TOP VIEW
(Not to Scale)
26 QOPN
25 QOPP
24 ENVG
23 QAIN
COM3 7
22 COM3
IMXO 8
21 QMXO
COM2 9
20 VPOS3
IFIN 10
19 MXIN
IFIP 11
18 MXIP
VPOS2 12
17 VGIN
IOFS 13
16 QOFS
VREF 14
15 ENBL
03678-002
VPOS1 2
Figure 2. 28-Lead TSSOP Pin Configuration
Table 3. Pin Function Descriptions—28-Lead TSSOP
Pin No.
1, 28
Mnemonic
LOIP, LOIN
2, 12, 20
5
VPOS1, VPOS2,
VPOS3
IOPN, IOPP,
QOPP, QOPN
VCMO
6, 23
IAIN, QAIN
7, 22
8, 21
COM3
IMXO, QMXO
9
10, 11
COM2
IFIN, IFIP
13, 16
IOFS, QOFS
14
VREF
3, 4, 25, 26
Description
LO Inputs. For optimum performance, these inputs should be ac-coupled and driven
differentially. Differential drive from single-ended sources can be achieved via a balun.
To obtain a broadband 50 Ω input impedance, connect a 60.4 Ω shunt resistor between
LOIP and LOIN. Typical input drive level is equal to −10 dBm.
Positive Supply for LO, IF, and Biasing and Baseband Sections, Respectively. These pins
should be decoupled with 0.1 μF and 100 pF capacitors.
I- and Q-Channel Differential Baseband Outputs. Typical output swing is equal to 2 V p-p
differential. The dc common-mode voltage level on these pins is set by the voltage on VCMO.
Baseband DC Common-Mode Voltage. The voltage applied to this pin sets the dc
common-mode levels for all the baseband outputs and inputs (IMXO, QMXO, IOPP, IOPN,
QOPP, QOPN, IAIN, and QAIN). This pin can be connected either to VREF or to a reference
voltage from another device (typically an ADC).
I- and Q-Channel Baseband Amplifier Inputs. The single-ended signals on these pins are
referenced to VCMO and must have a dc bias equal to the dc voltage on the VCMO pin. If
IMXO (QMXO) is dc-coupled to IAIN (QAIN), biasing will be provided by IMXO (QMXO). If
an ac-coupled filter is placed between IMXO and IAIN, these pins can be biased from the
source driving VCMO through a 1 kΩ resistor. The gain from IAIN/QAIN to the differential
outputs (IOPP/IOPN and QOPP/QOPN) is 20 dB.
Ground for Biasing and Baseband Sections.
I- and Q-Channel Mixer Baseband Outputs. These are low impedance (40 Ω) outputs whose
bias levels are set by the voltage applied to the VCMO pin. These pins are typically connected
to IAIN and QAIN, respectively, either directly or through a filter. Each output can drive a
maximum current of 2.5 mA.
IF Section Ground.
IF Inputs. IFIN should be ac-coupled to ground. The single-ended IF input signal should
be ac-coupled into IFIP. The nominal differential input impedance of these pins is 200 Ω.
For a broadband 50 Ω input impedance, a minimum-loss L pad should be used; RSERIES = 174 Ω,
RSHUNT = 57.6 Ω. This provides a 200 Ω source impedance to the IF input. However, the AD8348
does not necessarily require a 200 Ω source impedance, and a single shunt 66.7 Ω resistor
can be placed between IFIP and IFIN.
I- and Q-Channel Offset Nulling Inputs. DC offsets on the I-channel mixer output (IMXO)
can be nulled by connecting a 0.1 μF capacitor from IOFS to ground. Driving IOFS with a
fixed voltage (typically a DAC calibrated such that the offset at IOPP/IOPN is nulled) can
extend the operating frequency range to include dc. The QOFS pin can likewise be used
to null offsets on the Q-channel mixer output (QMXO).
Reference Voltage Output. This output voltage (1 V) is the main bias level for the device
and can be used to externally bias the inputs and outputs of the baseband amplifiers.
The typical maximum drive current for this output is 2 mA.
Rev. A | Page 7 of 28
Equivalent
Circuit
A
B
C
D
H
E
F
G
AD8348
Pin No.
15
17
Mnemonic
ENBL
VGIN
18, 19
MXIP, MXIN
24
ENVG
27
COM1
Description
Chip Enable Input. Active high. Threshold is equal to VS/2.
Gain Control Input. The voltage on this pin controls the gain on the IF VGA. The gain
control voltage range is from 0.2 V to 1.2 V and corresponds to a conversion gain range
from +25.5 dB to −18.5 dB. This is the gain to the output of the mixers (that is, IMXO and
QMXO). There is an additional 20 dB of fixed gain in the final baseband amplifiers (IAIN to
IOPP/IOPN and QAIN to QOPP/QOPN). Note that the gain control function has a negative
sense (that is, increasing voltage decreases gain).
Auxiliary Mixer Inputs. If ENVG is low, the IFIP and IFIN inputs are disabled and MXIP and
MXIN are enabled, allowing the VGA to be bypassed. The auxiliary mixer inputs are fully
differential inputs that should be ac-coupled to the signal source.
Active High VGA Enable. When ENVG is high, IFIP and IFIN inputs are enabled and MXIP
and MXIN inputs are disabled. When ENVG is low, MXIP and MXIN inputs are enabled and
IFIP and IFIN inputs are disabled.
LO Section Ground.
Rev. A | Page 8 of 28
Equivalent
Circuit
D
D
I
D
AD8348
EQUIVALENT CIRCUITS
VPOS1
VPOS3
LOIN
LOIP
COM1
03678-006
03678-003
IAIN, QAIN, VGIN,
ENBL, ENVG
COM3
Figure 3. Circuit A
Figure 6. Circuit D
VPOS3
VPOS2
IFIP
IOPP, IOPN,
QOPP, QOPN
IFIN
03678-007
COM3
03678-004
VCMO
COM3
Figure 7. Circuit E
Figure 4. Circuit B
VPOS3
50µA
MAX
VPOS3
03678-005
COM3
COM3
Figure 5. Circuit C
Figure 8. Circuit F
Rev. A | Page 9 of 28
03678-008
IOFS,
QOFS
VCMO
AD8348
VPOS3
VPOS2
MXIP
VREF
COM2
COM3
Figure 9. Circuit G
Figure 11. Circuit I
VPOS3
COM3
03678-010
IMXO,
QMXO
Figure 10. Circuit H
Rev. A | Page 10 of 28
03678-011
03678-009
MXIN
AD8348
TYPICAL PERFORMANCE CHARACTERISTICS
VGA AND DEMODULATOR
3
20
LINERR T = +25°C, VPOS = 2.7V, FREQ = 900MHz
3
2
15
LINERR T = –40°C, VPOS = 2.7V,
FREQ = 900MHz
2
15
1
10
0
5
–1
–2
0
–5
T = +85°C, VPOS = 5V, FREQ = 380MHz
T = +25°C, VPOS = 5V, FREQ = 380MHz
–10
–15
–20
0.2
–3
–4
–5
T = –40°C, VPOS = 5V, FREQ = 380MHz
0.3
0.4
0.5
0.6
0.7
0.8
VGIN (V)
0.9
1.0
1.1
LINERR T = –40°C, VPOS = 5V,
FREQ = 900MHz
–2
T = +85°C, VPOS = 2.7V,
FREQ = 900MHz
–3
T = +25°C, VPOS = 2.7V, FREQ = 900MHz
–15
–4
–5
T = –40°C, VPOS = 2.7V, FREQ = 900MHz
–25
0.2
0.3
0.4
0.5
0.6
0.7
0.8
VGIN (V)
0.9
1.0
–6
1.2
1.1
Figure 15. Mixer Gain and Linearity Error vs. VGIN, VPOS = 2.7 V, FIF = 900 MHz,
FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C
26
5
0
0
–1
–2
T = +85°C, VPOS = 5V,
FREQ = 900MHz
–3
–10
T = +25°C, VPOS = 5V, FREQ = 900MHz
VGA AND MIXER GAIN (dB)
VGA AND MIXER GAIN (dB)
1
–15
–5
2
10
–5
–1
3
LINERR T = +25°C, VPOS = 5V, FREQ = 900MHz
15
0
0
28
LINEARITY ERROR (dB)
20
5
–10
4
LINERR T = +85°C, VPOS = 5V, FREQ = 900MHz
1
–20
–6
1.2
Figure 12. Mixer Gain and Linearity Error vs. VGIN, VPOS = 5 V, FIF = 380 MHz,
FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C
25
10
LINEARITY ERROR (dB)
VGA AND MIXER GAIN (dB)
LINERR T = –40°C, VPOS = 5V, FREQ = 380MHz
4
LINERR T = +85°C, VPOS = 2.7V, FREQ = 900MHz
03678-015
LINERR T = +25°C, VPOS = 5V, FREQ = 380MHz
20
25
VGA AND MIXER GAIN (dB)
25
4
LINEARITY ERROR (dB)
LINERR T = +85°C, VPOS = 5V, FREQ = 380MHz
03678-012
30
–4
24
5V, 0.2V, +25°C
22
2.7V, 0.2V, +25°C
5V, 0.2V, +85°C
2.7V, 0.2V, +85°C
20
5V, 0.2V, –40°C
0.4
0.5
0.6
0.7
0.8
VGIN (V)
0.9
1.0
1.1
18
Figure 13. Mixer Gain and Linearity Error vs. VGIN, VPOS = 5 V, FIF = 900 MHz,
FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C
LINERR T = –40°C, VPOS = 2.7V,
FREQ = 380MHz
1
10
0
5
–1
0
–2
T = +85°C, VPOS = 2.7V,
FREQ = 380MHz
–5
–10
–20
0.2
–3
T = +25°C, VPOS = 2.7V, FREQ = 380MHz
–15
–4
0.4
0.5
0.6
0.7
0.8
VGIN (V)
0.9
800
900
1000
5V, 1.2V, +85 °C
2.7V, 1.2V, +85 °C
–20
5V, 1.2V, –40°C
2.7V, 1.2V, +25°C
2.7V, 1.2V, –40°C
–25
5V, 1.2V, +25 °C
–5
T = –40°C, VPOS = 2.7V, FREQ = 380MHz
0.3
400
500
600 700
IF FREQUENCY (MHz)
2
15
VGA AND MIXER GAIN (dB)
VGA AND MIXER GAIN (dB)
20
300
3
LINEARITY ERROR (dB)
25
–15
4
LINERR T = +85°C, VPOS = 2.7V, FREQ = 380MHz
LINERR T = +25°C, VPOS = 2.7V, FREQ = 380MHz
200
Figure 16. Gain vs. FIF, VGIN = 0.2 V, FBB = 1 MHz,
Temperature = −40°C, +25°C, +85°C
1.0
1.1
–6
1.2
03678-014
30
100
03678-016
0.3
2.7V, 0.2V, –40°C
–6
1.2
Figure 14. Mixer Gain and Linearity Error vs. VGIN, VPOS = 2.7 V, FIF = 380 MHz,
FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C
Rev. A | Page 11 of 28
–30
100
200
300
400
500
600 700
IF FREQUENCY (MHz)
800
900
Figure 17. Gain vs. FIF, VGIN = 1.2 V, FBB = 1 MHz,
Temperature = −40°C, +25°C, +85°C
1000
03678-017
–25
0.2
–5
T = –40°C, VPOS = 5V, FREQ = 900MHz
03678-013
–20
AD8348
26
VGA AND MIXER GAIN (dB)
25
2.7V, 0.2V, +85°C
24
5V, 0.2V, –40°C
2.7V, 0.2V, +25°C
23
2.7V, 0.2V, –40°C
22
5V, 0.2V, +85°C
21
20
19
17
0
10
20
30
40
50
60
70
80
BASEBAND FREQUENCY (MHz)
90
03678-018
18
100
Figure 18. Gain vs. FBB, VGIN = 0.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
INPUT 1dB COMPRESSION POINT (dBm) (re 200Ω)
20
5V, 0.2V, +25°C
–40°C, 5V, 900MHz
15
+25°C, 2.7V, 900MHz
10
+25°C, 5V, 900MHz
5
+85°C, 2.7V, 900MHz
0
–5 +85°C, 5V, 900MHz
–10
–15
–20
0.2
–40°C, 2.7V, 900MHz
0.3
0.4
0.5
0.6
0.7
0.8
VGIN (V)
0.9
1.0
1.1
1.2
03678-021
27
Figure 21. Input 1 dB Compression Point (IP1dB) vs. VGIN, FIF = 900 MHz,
FBB = 1 MHz, VPOS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°C
–17
30
29
5V, 1.2V, +85°C
–20
5V, 1.2V, +85°C
2.7V, 1.2V, +25°C
5V, 1.2V, +25°C
–23
2.7V, 1.2V, –40°C
10
20
30
40
50
60
70
80
BASEBAND FREQUENCY (MHz)
90
100
Figure 19. Gain vs. FBB, VGIN = 1.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
2.7V, 1.2V, +25°C
5V, 1.2V, –40°C
2.7V, 1.2V, –40°C
100
200
300
400
500
600
700
IF FREQUENCY (MHz)
800
900
1000
Figure 22. IIP3 vs. FIF, VGIN = 1.2 V, FBB = 1 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C, Tone Spacing = 20 kHz
15
0
+25°C, 5V, 380MHz
10
5V, 0.2V, +85°C
–40°C, 5V, 380MHz
2.7V, 0.2V, +85°C
+25°C, 2.7V, 380MHz
0
+85°C, 2.7V, 380MHz
–5
–10
INPUT IIP3 (dBm) (re 200Ω)
5
+85°C, 5V, 380MHz
–15
–5
2.7V, 0.2V, +25°C
5V, 0.2V, –40°C
–10
5V, 0.2V, +25°C
2.7V, 0.2V, –40°C
–20
0.3
0.4
0.5
0.6
0.7
0.8
VGIN (V)
0.9
1.0
1.1
1.2
Figure 20. Input 1 dB Compression Point (IP1dB) vs. VGIN, FIF = 380 MHz,
FBB = 1 MHz, VPOS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°C
Rev. A | Page 12 of 28
–15
100
200
300
400
500
600 700
IF FREQUENCY (MHz)
800
900
1000
Figure 23. IIP3 vs. FIF, VGIN = 0.2 V, FBB = 1 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
03678-023
–40°C, 2.7V, 380MHz
–25
0.2
03678-020
INPUT 1dB COMPRESSION POINT (dBm) (re 200Ω)
2.7V, 1.2V, +85°C
26
24
03678-019
0
27
5V, 1.2V, +25°C
25
5V, 1.2V, –40°C
–26
28
03678-022
INPUT IIP3 (dBm) (re 200Ω)
VGA AND MIXER GAIN (dB)
2.7V, 1.2V, +85°C
AD8348
32
45
35
2.7V, 1.2V, +85°C
5V, 1.2V, +25°C
26
5V, 1.2V, +85°C
10
20
30
40
50
60
70
80
BASEBAND FREQUENCY (MHz)
90
100
30
20
25
15
20
10
15
5
10
0
5
–5
0
0.2
Figure 24. IIP3 vs. FBB, VGIN = 1.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
0.4
0.5
0.6
0.7
0.8
VGIN (V)
0.9
1.0
1.1
–10
1.2
Figure 27. Noise Figure and IIP3 vs. VGIN, Temperature = 25°C,
FIF = 380 MHz, FBB = 1 MHz, VPOS = 2.7 V
40
0
2.7V, 0.2V, +85°C
VGA AND MIXER INPUT IIP3 (dBm) (re 200Ω)
0.3
35
NF
35
30
5V, 0.2V, +85°C
25
30
NOISE FIGURE (dB)
–5
5V, 0.2V, +25°C
–10
2.7V, 0.2V, –40°C
5V, 0.2V, –40°C
–15
IIP3
20
25
15
20
10
15
5
10
0
2.7V, 0.2V, +25°C
5
0
10
20
30
40
50
60
70
80
BASEBAND FREQUENCY (MHz)
90
100
–5
0
0.2
03678-025
–20
Figure 25. IIP3 vs. FBB, VGIN = 0.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
INPUT IIP3 (dBm) (re 200Ω)
0
03678-024
22
25
IIP3
INPUT IIP3 (dBm) (re 200Ω)
NOISE FIGURE (dB)
35
28
24
30
NF
03678-027
40
5V, 1.2V, –40°C
2.7V, 1.2V, +25°C
30
0.3
0.4
0.5
0.6
0.7
0.8
VGIN (V)
0.9
1.0
1.1
–10
1.2
03678-028
VGA AND MIXER INPUT IIP3 (dBm) (re 200Ω)
2.7V, 1.2V, –40°C
Figure 28. Noise Figure and IIP3 vs. VGIN, Temperature = 25°C,
FIF = 380 MHz, FBB = 1 MHz, VPOS = 5 V
16
16
15
15
2.0
1.5
NF @ LO = 900MHz
11
850
950
Figure 26. Noise Figure vs. FIF, T = 25°C, VGIN = 0.2 V, FBB = 1 MHz
–0.5
NF @ LO = 380MHz
9
750
0
11
9
350
450
550
650
IF FREQUENCY (MHz)
0.5
PHASE ERROR 900MHz
10
250
PHASE ERROR 380MHz
12
10
150
PHASE ERROR 50MHz
8
–12
–1.0
–1.5
NF @ LO = 50MHz
–10
–8
–6
–4
LO INPUT LEVEL (V)
PHASE ERROR (Degrees)
12
13
–2
0
–2.0
03678-029
NOISE FIGURE (dB)
13
8
50
1.0
14
NF VGIN = 0.2V
03678-026
NOISE FIGURE (dB)
14
Figure 29. Noise Figure and Quadrature Phase Error IMXO/QMXO vs. LO Input
Level, Temperature = 25°C, VGIN = 0.2 V, VPOS = 5 V for FIF = 50 MHz,
380 MHz, and 900 MHz
Rev. A | Page 13 of 28
AD8348
DEMODULATOR USING MXIP AND MXIN
18
11.0
23.0
TEMP = +25°C,
VPOS = 5V
TEMP = +85°C,
VPOS = 2.7V
9.0
TEMP = +25°C,
VPOS = 2.7V
8.5
8.0
100
200
300
400
500
600
700
IF FREQUENCY (MHz)
800
900
1000
MIXER INPUT P1dB (dBm) (re 200Ω)
TEMP = +25°C, VPOS = 5V
–3.0
TEMP = –40°C, VPOS = 5V
–3.5
–4.0
–4.5
TEMP = +85°C, VPOS = 2.7V
TEMP = –40°C, VPOS = 2.7V
–6.0
TEMP = +25°C, VPOS = 2.7V
–6.5
–7.0
100
200
300
400 500
600
700
IF FREQUENCY (MHz)
800
900
1000
03678-031
–7.5
–8.0
22.0
15
21.5
14
21.0
IIP3 5V
13
20.5
NF 2.7V
12
20.0
19.5
IIP3 2.7V
150
250
350 450
550
650
IF FREQUENCY (MHz)
750
850
950
19.0
Figure 32. IIP3 and Noise Figure vs. FIF, VPOS = 2.7 V, 5 V, Temperature = 25°C
TEMP = +85°C, VPOS = 5V
–2.5
–5.5
16
10
50
–1.5
–5.0
22.5
11
TEMP = +85°C, VPOS = 5V
Figure 30. Mixer Gain vs. FIF, VPOS = 2.7 V, 5 V, FBB = 1 MHz,
Temperature = −40°C, +25°C, +85°C
–2.0
17
03670-032
TEMP = –40°C, VPOS = 5V
10.0
9.5
INPUT IIP3 (dBm) (re 200Ω)
TEMP = –40°C, VPOS = 2.7V
03678-030
MIXER GAIN (dB)
10.5
NOISE FIGURE (dB)
NF 5V
Figure 31. Input 1 dB Compression Point vs. FIF, FBB = 1 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
Rev. A | Page 14 of 28
AD8348
FINAL BASEBAND AMPLIFIERS
21
35
–40°C, 5V
–40°C, 2.7V
20
+85°C, 5V
+85°C, 5V
20
+25°C, 5V
OIP3 (dBV)
18
GAIN (dB)
+25°C, 5V
25
+25°C, 2.7V
19
–40°C, 5V
30
+85°C, 2.7V
17
16
+85°C, 2.7V
15
10
5
+25°C, 2.7V
0
15
–5
14
1000
–15
10
03678-033
1
10
100
BASEBAND FREQUENCY (MHz)
Figure 33. Gain vs. FBB, VVCMO = VREF = 1 V, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
+25°C, 5V
–40°C, 5V
30
50
70
90
110
130 150
BASEBAND FREQUENCY (MHz)
170
190
03678-035
–10
13
0.1
5
–40°C, 2.7V
Figure 35. OIP3 vs. FBB, VVCMO = VREF = 1 V, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
10
+85°C, 5V
OP1dB (dBV)
+25°C, 2.7V
–5
–40°C, 2.7V
+85°C, 2.7V
–10
–20
0.1
1
10
100
BASEBAND FREQUENCY (MHz)
1000
03678-034
–15
Figure 34. OP1dB Compression vs. FBB, VVCMO = VREF = 1 V, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
Rev. A | Page 15 of 28
8
7
6
5
4
3
2
1
0
1
10
100
1000
FREQUENCY (kHz)
10000
Figure 36. Noise Spectral Density
100000
03678-036
BASEBAND AMPLIFIER INPUT NOISE
SPECTRAL DENSITY (nV/ Hz)
9
0
AD8348
2.0
1.5
1.5
I/Q AMPLITUDE MISMATCH (dB)
2.0
1.0
2.7V, 0.2V, –40°C
0.5
5V, 0.2V, +85°C
0
5V, 0.2V, –40°C
2.7V, 0.2V, +85°C
–0.5
2.7V, 0.2V, +25°C
5V, 0.2V, +25°C
–1.0
–1.5
0
–0.5
–1.0
300
400 500 600 700
IF FREQUENCY (MHz)
800
900
1000
–2.0
200
300
400 500
600 700
IF FREQUENCY (MHz)
800
900
1000
Figure 40. I/Q Amplitude Imbalance vs. FIF, Temperature = 25°C, VPOS = 5 V
2.0
2.7V, 0.7V, +25°C
1.5
100
300
2.2
280
2.0
260
1.8
240
1.6
SHUNT RESISTANCE (Ω)
2.7V, 0.7V, –40°C
1.0
5V, 0.7V, –40°C
0.5
0
5V, 0.7V, +85°C
–0.5
5V, 0.7V, +25°C
–1.0 2.7V, 0.7V, +85°C
0
5
10
15
20
25
30
BASEBAND FREQUENCY (MHz)
35
40
03678-038
–1.5
03678-040
200
1.4
220
SHUNT CAPACITANCE
200
180
1.2
1.0
SHUNT RESISTANCE
160
0.8
140
0.6
120
0.4
100
50
Figure 38. Quadrature Phase Error vs. FBB, VGIN = 0.7 V, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C, FIF = 380 MHz
150
250
350 450
550 650
IF FREQUENCY (MHz)
750
850
950
SHUNT CAPACITANCE (pF)
100
Figure 37. Quadrature Phase Error vs. FIF, VGIN = 0.7 V, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
QUADRATURE PHASE ERROR (Degrees)
0.5
0.2
03678-041
–2.0
–2.0
1.0
–1.5
03678-037
QUADRATURE PHASE ERROR (Degrees)
VGA/DEMODULATOR AND BASEBAND AMPLIFIER
Figure 41. Input Impedance of IF Input vs. FIF, VGIN = 0.7 V, VPOS = 5 V
90
60
120
0.4
I/Q AMPLITUDE MISMATCH (dB)
150
30
0.2
180
5V, 0.7V, 25°C
0
0
IFIP WITH L PAD
210
330
IFIP WITHOUT L PAD
–0.2
IMPEDANCE CIRCLE
240
5
10
15
20
25
30
BASEBAND FREQUENCY (MHz)
35
40
Figure 39. I/Q Amplitude Imbalance vs. FBB, Temperature = 25°C, VPOS = 5 V
Rev. A | Page 16 of 28
300
270
03678-042
0
03678-039
–0.4
Figure 42. S11 of IF Input vs. FIF, FIF = 50 MHz to 1 GHz, VGIN = 0.7 V,
VPOS = 5 V (with L Pad, with No Pad, Normalized to 50 Ω)
AD8348
300
0
2.5
280
–5
2.0
200
1.0
180
(SHUNT RESISTANCE)
160
0.5
140
RETURN LOSS (dB)
1.5
220
–10
SHUNT CAPACITANCE (pF)
(SHUNT CAPACITANCE)
240
RETURN LOSS LO INPUT, THROUGH BALUN
WITH 60.4Ω IN SHUNT BETWEEN LOIP/LOIN
–15
–20
–25
–30
120
2000
FREQUENCY APPLIED TO LOIP/LOIN (MHz)
Figure 43. Input Impedance of Mixer Input vs. FIF, VGIN = 0.7 V, VPOS = 5 V
03678-046
1900
1800
1700
1600
1500
1400
1300
1100
1200
900
1000
800
700
600
500
400
300
100
03678-043
950
1000
900
850
800
750
700
650
600
550
500
450
400
350
300
200
250
150
100
IF FREQUENCY (MHz)
200
–35
0
50
100
Figure 46. Return Loss of LO Input vs. External LO Frequency
Through Balun, with Termination Resistor
90
60
120
65
150
30
60
180
SUPPLY CURRENT (mA)
MX INPUTS WITH 4:1 BALUN
0
MXIP INPUT PIN
210
330
55
50
VS = 5V
VS = 2.7V
45
40
240
03678-044
300
270
Figure 44. S11 of Mixer Input vs. FIF, FIF = 50 MHz to 1 GHz,
VGIN = 0.7 V, VPOS = 5 V (With and Without Balun)
–5
RETURN LOSS LOIP PIN SINGLE-ENDED,
LOIN AC-COUPLED TO GROUND.
–15
–20
–25
–30
2000
EXTERNAL LO FREQUENCY (MHz)
03678-045
1900
1800
1700
1600
1500
1400
1300
1200
1100
900
1000
800
700
600
500
400
300
200
–35
100
0
10 20 30 40
TEMPERATURE (°C)
50
60
Figure 47. Supply Current vs. Temperature
0
–10
35
–40 –30 –20 –10
Figure 45. Return Loss of LOIP Input vs. External LO Frequency
Rev. A | Page 17 of 28
70
80
03678-047
IMPEDANCE CIRCLE
RETURN LOSS (dB)
SHUNT RESISTANCE (Ω)
260
AD8348
THEORY OF OPERATION
ENBL 15
VREF
IMXO
IOFS
IAIN
IOPP
IOPN
14
8
13
6
4
3
BIAS
CELL
PHASE SPLITTER
VREF
5
VCMO
1
LOIP
28
LOIN
VCMO
DIVIDE
BY 2
IFIP 11
PHASE
SPLITTER
IFIN 10
AD8348
VGIN 17
GAIN
CONTROL
19
24
MXIP MXIN ENVG
21
16
23
QXMO
QOFS
QAIN
25
03678-049
VCMO
18
26
QOPP QOPN
Figure 48. Functional Block Diagram
VGA
The VGA is implemented using the patented X-AMP architecture.
The single-ended IF signal is attenuated in eight discrete 6 dB
steps by a passive R-2R ladder. Each discrete attenuated version
of the IF signal is applied to the input of a transconductance
stage. The current outputs of all transconductance stages are
summed together and drive a resistive load at the output of the
VGA. Gain control is achieved by smoothly turning on and
off the relevant transconductance stages with a temperaturecompensated interpolation circuit. This scheme allows the gain
to continuously vary over a 44 dB range with linear-in-decibel
gain control. This configuration also keeps the relative dynamic
range constant (for example, IIP3 − NF in dB) over the gain
setting; however, the absolute intermodulation intercepts and
noise figure vary directly with gain. The analog voltage VGIN
sets the gain. VGIN = 0.2 V is the maximum gain setting, and
VGIN = 1.2 V is the minimum voltage gain setting.
DOWNCONVERSION MIXERS
The output of the VGA drives two (I and Q) double-balanced
Gilbert cell downconversion mixers. Alternatively, driving the
ENVG pin low can disable the VGA, and the mixers can be
externally driven directly via the MXIP and MXIN ports. At
the input of the mixer, a degenerated differential pair performs
linear voltage-to-current conversions. The differential output
current feeds into the mixer core where it is downconverted by
the mixing action of the Gilbert cell. The phase splitter provides
quadrature LO signals that drive the LO ports of the in-phase
and quadrature mixers.
Buffers at the output of each mixer drive the IMXO and QMXO
pins. These linear, low output impedance buffers drive 40 Ω,
temperature-stable, passive resistors in series with each output
pin (IMXO and QMXO). This 40 Ω should be considered when
calculating the reverse termination if an external filter is inserted
between IMXO (QMXO) and IAIN (QAIN). The VCMO pin sets
the dc output level of the buffer. This can be set externally or
connected to the on-chip 1.0 V reference, VREF.
Quadrature generation is achieved using a divide-by-2 frequency
divider. Unlike a polyphase filter that achieves quadrature over
a limited frequency range, the divide-by-2 approach maintains
quadrature over a broad frequency range and does not attenuate
the LO. The user, however, must provide an external signal XLO
that is twice the frequency of the desired LO frequency. XLO drives
the clock inputs of two flip-flops that divide down the frequency
by a factor of 2. The outputs of the two flip-flops are one-half
period of XLO out of phase. Equivalently, the outputs are onequarter period (90°) of the desired LO frequency out of phase.
Because the transitions on XLO define the phase difference at
the outputs, deviation from 50% duty cycle translates directly to
quadrature phase errors.
If the user generates XLO from a 1× frequency (fREF) and a
frequency-doubling circuit (XLO = 2 × fREF), fundamentally
there is a 180° phase uncertainty between fREF and the AD8348
internal quadrature LO. The phase relationship between I and Q
LO, however, is always 90°.
I/Q BASEBAND AMPLIFIERS
Two (I and Q) fixed gain (20 dB), single-ended-to-differential
amplifiers are provided to amplify the demodulated signal
after off-chip filtering. The amplifiers use voltage feedback to
linearize the gain over the demodulation bandwidth. These
amplifiers can be used to maximize the dynamic range at the
input of an ADC following the AD8348.
The input to the baseband amplifiers, IAIN (QAIN), feeds into
the base of a bipolar transistor with an input impedance of
roughly 50 kΩ. The baseband amplifiers sense the single-ended
difference between IAIN (QAIN) and VCMO. IAIN (QAIN)
can be dc biased by terminating it with a shunt resistor to
VCMO, such as when an external filter is inserted between
IMXO (QMXO) and IAIN (QAIN). Alternatively, any dc
connection to IMXO (QXMO) can provide appropriate bias via
the offset-nulling loop.
ENABLE
A master biasing cell that can be disabled using the ENBL pin
controls the biasing for the chip. If the ENBL pin is held low,
the entire chip powers down to a low power sleep mode,
typically consuming 75 μA at 5 V.
BASEBAND OFFSET CANCELLATION
A low output current integrator senses the output voltage offset
at IOPP and IOPN (QOPP and QOPN) and injects a nulling
current into the signal path. The integration time constant of the
offset-nulling loop is set by Capacitor COFS from IOFS (QOFS) to
Rev. A | Page 18 of 28
AD8348
The IOFS (QOFS) pin must be connected to either a bypass
capacitor (>0.1 μF) or an external voltage source to prevent the
feedback loop from oscillating.
VCMO. This forms a high-pass response for the baseband
signal path with a lower 3 dB frequency of
f PASS =
1
2π × 2650 Ω × COFS
Alternatively, the user can externally adjust the dc offset by driving
IOFS (QOFS) with a digital-to-analog converter or other voltage
source. In this case, the baseband circuit operates all the way down
to dc (fPASS = 0 Hz). The integrator output current is only 50 μA
and can be easily overridden with an external voltage source.
The nominal voltage level applied to IOFS (QOFS) to produce
a 0 V differential offset at the baseband outputs is 900 mV.
The feedback loop will be broken at dc if an ac-coupled baseband
filter is placed between the mixer outputs and the baseband
amplifier inputs. If an ac-coupled filter is implemented, the user
must handle the offset compensation via some external means.
Rev. A | Page 19 of 28
AD8348
APPLICATIONS
LO
BASIC CONNECTIONS
4
5
3
1
Figure 49 shows the basic connections schematic for the AD8348.
J21
LO
ETC1-1-13
4 5
1000pF
T21
ETC1-1-13
1000pF
60.4Ω
3 1
R21
60.4Ω
C22
1000pF
1 LOIP
LOIN 28
03678-050
C21
1000pF
AD8348
C52
0.1µF
C51
100pF
J2I
IOPP
VREF
3 IOPN
QOPN 26
4 IOPP
QOPP 25
5 VCMO
6 IAIN
R31
57.6Ω
+VS
R32
174Ω
C31
1000pF
C54
0.1µF
COM3 22
8 IMXO
QMXO 21
C53
100pF
C0l
0.1µF
C11
4.7µF
10 IFIN
MXIN 19
11 IFIP
MXIP 18
12 VPOS2
VGIN 17
13 IOFS
QOFS 16
14 VREF
ENBL 15
+VS
SW12
MX
QAIN 23
7 COM3
Alternatively, the LO port can be driven from a single-ended source
without a balun (Figure 51). The LO signal is ac-coupled directly
into the LOIP pin via an ac-coupling capacitor, and the LOIN pin
is ac-coupled to ground. Driving the LO port from a singleended source results in an increase in both quadrature phase
error and LO leakage.
J2Q
QOPP
IF
ENVG 24
9 COM2 VPOS3 20
C32
1000pF
IFIP
Figure 50. Differential LO Drive with Balun
J3Q
QOPN
C55
100pF
C56
0.1µF
+VS
R42
C43
1000pF 0Ω
MXIP
C42
1000pF
VGIN
C0Q
0.1µF
LO
T41
ETK4-2T
C41
1µF
1000pF
1000pF
60.4Ω
ENBL
+VS
SW11
1
03678-064
J3I
IOPN
LOIN 28
2 VPOS1 COM1 27
DENBL
LOIP
LOIN 28
03678-051
1 LOIP
+VS
Figure 49. Basic Connections Schematic
Figure 51. Single-Ended LO Drive
POWER SUPPLY
The voltage supply for the AD8348, between 2.7 V and 5 V, should
be provided to the +VPOSx pins, and ground should be connected
to the COMx pins. Each supply pin should be decoupled separately
using two capacitors whose recommended values are 100 pF and
0.1 μF (values close to these can also be used).
The recommended LO drive level is between −12 dBm and
0 dBm. The LO frequency at the input to the device should be
twice that of the desired LO frequency at the mixer core. The
applied LO frequency range is between 100 MHz and 2 GHz.
DEVICE ENABLE
The IF inputs have an input impedance of 200 Ω. A broadband
50 Ω match can be presented to the driving source through the use
of a minimum-loss L pad. This minimum-loss pad introduces
an 11.46 dB loss in the input path and must be taken into account
when calculating metrics such as gain and noise figure. Figure 42
shows the S11 of the IF input with and without the L pad.
VGA ENABLE
Driving the voltage on the ENVG pin to VS enables the VGA. In
this mode, the MX inputs are disabled and the IF inputs are
used. Grounding the ENVG pin disables the VGA and the IF
inputs. When the VGA is disabled, the MX inputs should be used.
1000pF
10
IFIN
11
IFIP
57.6Ω
IFIP
GAIN CONTROL
174Ω
1000pF
When the VGA is enabled, the voltage applied to the VGIN pin sets
the gain. The gain control voltage range is between 0.2 V and 1.2 V.
This corresponds to a gain range between +25.5 dB and −18.5 dB.
LO INPUTS
For optimum performance, the local oscillator port should be
driven differentially through a balun. The recommended balun
is M/A-COM ETC1-1-13. The LO inputs to the device should
be ac-coupled, unless an ac-coupled transformer is being used.
For a broadband match to a 50 Ω source, a 60.4 Ω resistor
should be placed between the LOIP and LION pins.
03678-052
To enable the device, the ENBL pin should be driven to VS.
Grounding the ENBL pin disables the device.
IF INPUTS
Figure 52. Minimum-Loss L Pad for 50 Ω IF Input
MX INPUTS
The mixer inputs, MXIP and MXIN, have a nominal impedance
of 200 Ω and should be driven differentially. When driven from
a differential source, the input should be ac-coupled to the
source via capacitors, as shown in Figure 53.
Rev. A | Page 20 of 28
AD8348
LO
1000pF
MXIN 19
4 5
MXIN
1:1
3 1
1000pF
+VS
If the MX inputs are to be driven from a single-ended 50 Ω source,
a 4:1 balun can be used to transform the 200 Ω impedance of
the inputs to 50 Ω while performing the required single-endedto-differential conversion. The recommended transformer is the
M/A-COM ETK4-2T.
0.1µF
100pF
TO BASEBAND
I ADC
VREF
1.02kΩ
1000pF
MXIN 19
ETK4-2T
MXIP
1000pF
03678-066
1µF
1000pF
AD8348
Figure 53. Driving the MX Inputs from a Differential Source
MXIP 18
60.4Ω
1
LOIP
LOIN 28
2
VPOS1 COM1 27
3
IOPN
QOPN 26
4
IOPP
QOPP 25
5
VCMO
ENVG 24
6
IAIN
7
COM3
COM3 22
8
IMXO
QMXO 21
Figure 54. Driving the MX Inputs from a Single-Ended 50 Ω Source
+VS
9
COM2 VPOS3 20
10
IFIN
MXIN 19
11
IFIP
MXIP 18
BASEBAND OUTPUTS
100pF
100pF
VREF
The baseband amplifier outputs, IOPP, IOPN, QOPP, and QOPN,
should be presented with loads of at least 2 kΩ (single-ended to
ground). They are not designed to drive 50 Ω loads directly. The
typical swing for these outputs is 2 V p-p differential (1 V p-p
single-ended), but larger swings are possible as long as care is taken
to ensure that the signals remain within the lower limit of 0.5 V
and the upper limit of VS − 1 V of the output swing. To achieve
a larger swing, it is necessary to adjust the common-mode bias of
the baseband output signals. Increasing the swing can have the
benefit of improving the signal-to-noise ratio of the baseband
amplifier output.
1000pF
1.24kΩ
100pF
VCMO
+VS
0.1µF
1000pF
1000pF
1000pF
0.1µF
+VS
QAIN 23
1000pF
IF INPUT
ZO = 200Ω
TO BASEBAND
Q ADC
12
VPOS2
13
IOFS
QOFS 16
VGIN 17
14
VREF
ENBL 15
1
COMM ACOM 16
2
CHPF
3
DECL
VTGT 14
4
INHI
VPOS 13
5
INLO
VOUT 12
6
DECL
VSET 11
7
PWDN ACOM 10
8
COMM
100pF
100pF
+VS
AD8362
1µF
VREF 15
1µF
1µF
100pF
1µF
0.1µF
+VS
VSET
1µF
When connecting the baseband outputs to other devices, care
should be taken to ensure that the outputs are not capacitively
loaded by approximately 20 pF or more. Such loads could
potentially overload the output or induce oscillations. The effect
of capacitive loading on the baseband amplifier outputs can be
mitigated by inserting series resistors of approximately 200 Ω.
OUTPUT DC BIAS LEVEL
The dc bias of the mixer outputs and the baseband amplifier
inputs and outputs is determined by the voltage that is driven
onto the VCMO pin. The range of this voltage is typically
between 500 mV and 4 V when operating with a 5 V supply.
To achieve maximum voltage swing from the baseband amplifiers,
VCMO should be driven at 2.25 V; this allows a swing of up to
7 V p-p differential (3.5 V p-p single-ended).
INTERFACING TO DETECTOR FOR AGC OPERATION
The AD8348 can be interfaced with a detector such as the
AD8362 rms-to-dc converter to provide an automatic signalleveling function for the baseband outputs.
CLPF 9
03678-0-055
MXIP
1000pF
03678-053
MXIP 18
Figure 55. AD8362 Configuration for AGC Operation
Assuming the I and Q channels have the same rms power, the
mixer output (or the output of the baseband filter) of one channel
can be used as the input of the AD8362. The AD8362 should be
operated in a region where its linearity error is small. Also, a
voltage divider should be implemented with an external resistor
in series with the 200 Ω input impedance of the AD8362 input.
This attenuates the AD8348 mixer output so that the AD8362
input is not overdriven. The size of the resistor between the
mixer output and the AD8362 input should be chosen so that
the peak signal level at the input of the AD8362 is about 10 dB
less than the approximately 10 dBm maximum of the AD8362
dynamic range.
The other side of the AD8348 baseband output should be
loaded with a resistance equal to the series resistance of the
attenuating resistor in series with the AD8362’s 200 Ω input
impedance. This resistor should be tied to the source driving
VCMO so that there is no dc drawn from the mixer output.
Rev. A | Page 21 of 28
AD8348
Care should be taken to ensure that blockers—unwanted signals
in the band of interest that are demodulated along with the desired
signal—do not dominate the rms power of the AD8362 input.
This can cause an undesired reduction in the level of the mixer
output. To overcome this, baseband filtering can be implemented
to filter out undesired signals before the signal is presented to
the AD8362.
Figure 56 shows the effectiveness of the AGC loop in
maintaining a baseband amplifier output amplitude with less
than 0.5 dB of amplitude error over an IF input range of 40 dB
while demodulating a QPSK-modulated signal at 380 MHz.
The AD8362 is insensitive to crest factor variations and
therefore provides similar performance regardless of the
modulation of the incoming signal.
140
3
–5.1dBm re 10kΩ
QPSK
2
The frequency response and group delay of this filter are shown
in Figure 58 and Figure 59.
0
–10
–20
–30
–40
–50
–60
120
1
110
0
100
–1
90
–2
–80
10
FREQUENCY (MHz)
1
100
03678-057
ERROR
ERROR (dB)
–70
Figure 58. Baseband Filter Response
50
–3
–45
–35
–25
–15
–5
IFIP POWER INPUT (dBm, ZO = 200Ω)
5
–4
Figure 56. AD8348 Baseband Amplifier Output vs.
IF Input Power with AD8362 AGC Loop
BASEBAND FILTERS
Baseband low-pass or band-pass filtering can be conveniently
performed between the mixer outputs (IMXO and QMXO) and
the input to the baseband amplifiers. Consideration should be
given to the output impedance of the mixers (40 Ω).
C2
8.2pF
L1
0.68µH
L2
1.2µH
C5
150pF
30
25
1
20
2
15
10
5
0
1
10
FREQUENCY (MHz)
Figure 59. Baseband Filter Group Delay
R1
60Ω
IMXO
35
C6
82pF
VCMO
TO AD8362
INPUT IF AGC
LOOP IS USED
R2
100Ω
IAIN
AD8348
03678-056
C1
4.7pF
40
Figure 57. Baseband Filter Schematic
Rev. A | Page 22 of 28
100
03678-058
70
–55
45
GROUP DELAY (ns)
80
03678-065
I CHANNEL VOLTAGE OUTPUT
(IOPP – IOPN) (mV rms)
130
Figure 57 shows the schematic for a 100 Ω, fourth-order elliptic
low-pass filter with a 3 dB cutoff frequency of 20 MHz. Source
and load impedances of approximately 100 Ω ensure that the
filter sees a matched source and load. This also ensures that the
mixer output is driving an overall load of 200 Ω. Note that the
shunt termination resistor is tied to the source driving VCMO
and not to ground. This ensures that the input to the baseband
amplifier is biased to the proper reference level. VCMO is not
an output pin and must be biased by a low impedance source.
ATTENUATION (dB)
The level of the mixer output (or the output of the baseband
filter) can then be set by varying the setpoint voltage fed to
Pin 11 (VSET) of the AD8362.
AD8348
The device is enabled by moving Switch SW11 (at the bottom left
of the evaluation board) to the ENBL position. The device is
disabled by moving SW11 to the DENBL position. If desired, the
device can be enabled and disabled from an external source that
can be fed into the ENBL SMA connector or the VENB test point,
in which case SW11 should be placed in the DENBL position.
LO GENERATION
Analog Devices has a line of PLLs that can be used for
generating the LO signal. Table 4 lists the PLLs and their
maximum frequency and phase noise performance.
Table 4. ADI PLL Selection Table
ADI Model
ADF4001BRU
ADF4001BCP
ADF4110BRU
ADF4110BCP
ADF4111BRU
ADF4111BCP
ADF4112BRU
ADF4112BCP
ADF4116BRU
ADF4117BRU
ADF4118BRU
Frequency FIN
(MHz)
165
165
550
550
1200
1200
3000
3000
550
1200
3000
@ 1 kHz ΦN
dBc/Hz,
200 kHz PFD
−99
−99
−91
−91
−78
−78
−86
−86
−89
−87
−90
The IF and MX inputs are selected via SW12. The switch should
be moved in the direction of the desired input.
Gain Control
For convenience, a potentiometer, R15, is provided to allow for
changes in gain without the need for an additional dc voltage
source. To use the potentiometer, the SW13 switch must be set
to the POT position. Alternatively, an external voltage applied
to either the test point or SMA connector labeled VGIN can set
the gain. SW13 must be set to the EXT position when an
external gain control voltage is used.
LO Input
ADI also offers the ADF4360 fully integrated synthesizer and
VCO on a single chip that offers differential outputs for driving
the local oscillator input of the AD8348. This means that the user
can eliminate the use of a balun for single-ended-to-differential
conversions. The ADF4360 comes as a family of chips with six
operating frequency ranges. One can be chosen depending on
the local oscillator frequency required. Table 5 shows the
options available.
Table 5. ADF4360 Family Operating Frequencies
ADI Model
ADF4360-1
ADF4360-2
ADF4360-3
ADF4360-4
ADF4360-5
ADF4360-6
ADF4360-7
Output Frequency Range (MHz)
2150 to 2450
1800 to 2150
1550 to 1950
1400 to 1800
1150 to 1400
1000 to 1250
Lower frequencies set by external L
EVALUATION BOARD
Figure 60 shows the schematic for the AD8348 evaluation
board. Note that uninstalled components are indicated with the
OPEN designation. The board is powered by a single supply in
the range of 2.7 V to 5.5 V. Table 6 details the various configuration options of the evaluation board. Table 7 shows the various
jumper configurations for operating the evaluation board with
different signal paths.
Power to operate the board can be fed to a single VS test point
located near the LO input port at the top of the evaluation
board. A GND test point is conveniently provided next to the
VS test point for the return path.
The local oscillator signal should be fed to the SMA Connector
J21. This port is terminated in 50 Ω. The acceptable LO power
input range is from −12 dBm to 0 dBm and must be at a
frequency double that of the IF/MX frequency. Remember that
the AD8348 uses a 2:1 frequency divider in the LO path to
generate the internally required quadrature-phase-related LO
signals.
IF Input
The IF input should be fed into the SMA connector IFIP. The
VGA must be enabled when this port is used (SW12 in the IF
position). When this IF input is chosen, the signal path includes
a minimum-loss attenuator to transform a 50 Ω input source to
the 200 Ω source impedance level for which the VGA was
designed. This pad provides a very broadband input match at
the expense of an 11.46 dB power attenuation in the input path.
It is very important to take this into account when measuring
the noise and distortion performance of the unmodified board
using the IFIP input; the apparent noise figure will be degraded
by 11.46 dB, and the apparent IIP3 will be 11.46 dB higher than
actual. If full weak-signal performance is desired from the
evaluation board, the attenuator (comprising R31 and R32)
should be removed and replaced with a low-loss RF transformer
providing the desired 4:1 impedance ratio. When a transformer
is used, IFIN should be ac-coupled to ground and not driven
differentially with IFIP.
MX Input
The evaluation board is by default set for a differential MX drive
through a balun (T41) from a single-ended source fed into the
MXIP SMA connector. When the MX inputs are used, the
internal VGA is bypassed. To change to a differential driving
source, T41 should be removed along with Resistor R42. The
0 Ω R43 and R44 resistors should be installed in place of T41 to
bridge the gap between the input traces. This presents a nominal
Rev. A | Page 23 of 28
AD8348
Baseband Outputs
differential impedance of 200 Ω (100 Ω per side). The
differential inputs should then be fed into SMA connectors
MXIP and MXIN.
The baseband outputs are made available at the IOPP, IOPN,
QOPP, and QOPN test points and SMA connectors. These
outputs are not designed to be connected directly to 50 Ω loads
and should be presented with loads of approximately 2 kΩ or
greater.
Mixer Outputs
The I and Q mixer outputs are available through the IMXO and
QMXO SMA connectors. These outputs are biased to VCMO
and are not designed to drive loads smaller than 200 Ω. To
prevent damage to test equipment that cannot tolerate dc biases,
pads for series dc-blocking capacitors are provided. These pads
are populated with 0 Ω by default.
J21
LO
C52
0.1µF
GND
T21
ETC1-1-13
IOPN
J3I
IOPN
QOPN
3 1
GND
C9I
OPEN
R5I
0Ω
IOPP
C8I
OPEN
R4I
0Ω
C21
1000pF
R21
60.4Ω
C22
1000pF
R5Q
0Ω
C9Q
OPEN
GND
R4Q
0Ω
C8Q
OPEN
QOPP
J3Q
QOPN
AD8348
J2I
IOPP
VCMO
J1I
IMXO
C10I
0Ω
C13
0.1µF
LK2I
C3I
OPEN
C7I
OPEN
LK4I
IMXO
L3I
OPEN
C6I
OPEN
L2I
OPEN
L1I
OPEN
C2I
OPEN
C1I
OPEN
C5I
OPEN
C4I
OPEN
LK1I
R1I
OPEN
R32
174Ω
C31
1000pF
+VS
C54
0.1µF
C53
100pF LK5I
LOIN 28
VPOS1 COM1 27
3
IOPN
+VS
QOPN 26
4
IOPP
QOPP 25
5
VCMO
ENVG 24
R3Q
49.9Ω
ENBL
MX
VCMO
LK4Q
IAIN
QAIN 23
7
COM3
COM3 22
8
IMXO
QMXO 21
9
COM2 VPOS3 20
10
IFIN
L1Q
OPEN
L2Q
OPEN
L3Q
OPEN
LK1Q
C1Q
OPEN
C2Q
OPEN
C3Q
OPEN
R1Q
OPEN
IFIP
MXIP 18
12
VPOS2
VGIN 17
13
IOFS
QOFS 16
14
VREF
ENBL 15
C4Q
OPEN
C55
100pF
MXIN 19
11
QMXO
LK3Q
C5Q
OPEN
C55
0.1µF
C6Q
OPEN
J1Q
QMXO
C10Q
0Ω
LK2Q
C7Q
OPEN
VREF
R44
OPEN
R42
C43
1000pF 0Ω
MXIN
T41
ETK4-2T
MXIP
R43
OPEN
C42
1000pF
DENBL
IOFS
C11
4.7µF
POT
C0I
0.1µF
QOFS
Figure 60. Evaluation Board Schematic
Rev. A | Page 24 of 28
R41
OPEN
R14
10kΩ
LK5Q
SW13
R11
49.9Ω
R2Q
OPEN
VCMO
+VS
C41
1µF
SW11
ENBL
IF
J2Q
QOPP
+VS
R12
10kΩ
VENB
2
6
LK3I
C32
1000pF
IFIP
LOIP
LK11
VCMO
R31
57.6Ω
1
SW12
R3I
49.9Ω
R2I
OPEN
4 5
C51
100pF
C0Q
0.1µF
C12
0.1µF
EXT
R13
OPEN
R15
10kΩ
POT
VGIN
03678-059
+VS
The dc bias level of the baseband amplifier outputs are by
default tied to VREF through LK11. If desired, the dc bias level
can be changed by removing LK11 and driving a dc voltage
onto the VCMO test point.
03678-060
AD8348
03678-061
Figure 61. Evaluation Board Top Layer
Figure 62. Evaluation Board Top Silkscreen
Rev. A | Page 25 of 28
03678-062
AD8348
03678-063
Figure 63. Evaluation Board Bottom Layer
Figure 64. Evaluation Board Bottom Silkscreen
Rev. A | Page 26 of 28
AD8348
Table 6. Evaluation Board Configuration Options
Component
VS, GND
SW11, ENBL
SW13, R15,
VGIN
SW12
IFIP, R31, R32
MXIP, MXIN,
T41,
R41, R42,
C42, C43
LK11, VCMO
C8, C9, R4, R5
(I and Q)
C10 (I and Q)
C1 to C7,
R1, R2,
L1 to L3
(I and Q)
LK5 (I and Q)
Function
Power supply and ground vector pins.
Device enable: Place SW11 in the ENBL position to connect the ENBL pin to VS. Place SW11 in
the DENBL position to disable the device by grounding the Pin ENBL through a 50 Ω pull-down
resistor. The device can also be enabled via an external voltage applied to ENBL or VENB.
Gain control selection: With SW13 in the POT position, the gain of the VGA can be set using the
R15 potentiometer. With SW13 in the EXT position, the VGA gain can be set by an external
voltage to the SMA connector VGIN. For VGA operation, the VGA must first be enabled by
setting SW12 to the IF position.
VGA enable selection: With SW12 in the IF position, the ENVG pin is connected to VS and the
VGA is enabled. The IF input should be used when SW12 is in the IF position. With SW12 in the
MX position, the ENVG pin is grounded and the VGA is disabled. The MX inputs should be used
when SW12 is in the MX position.
IF inputs: The single-ended IF signal should be connected to this SMA connector. R31 and R32
form an L pad that presents a 50 Ω termination to the driving source. This L pad introduces an
11.46 dB loss in the input signal path and should be taken into consideration when calculating
the gain of the AD8348.
Mixer inputs: These inputs can be configured for either differential or single-ended operation.
The evaluation board is by default set for differential MX drive through a balun (T41) from a
single-ended source fed into the MXIP SMA connector. To change to a differential driving source,
T41 should be removed along with Resistor R42. The 0 Ω Resistors R43 and R44 should be installed in
place of T41 to bridge the gap between the input traces. This will present a nominal differential
impedance of 200 Ω (100 Ω per side). The differential inputs should then be fed into SMA
connectors MXIP and MXIN.
Baseband amplifier output bias: Installing LK11 connects VREF to VCMO. This sets the bias level
on the baseband amplifiers to VREF, which is equal to approximately 1 V. Alternatively, with
LK11 removed, the bias level of the baseband amplifiers can be set by applying an external
voltage to the VCMO test point.
Baseband amplifier outputs and output filter: Additional low-pass filtering can be provided at
the baseband output with these filters.
Mixer output dc-blocking capacitors: The mixer outputs are biased to VCMO. To prevent
damage to test equipment that cannot tolerate dc biases, C10 is provided to block the dc
component, thus protecting the test equipment.
Baseband filter: These components are provided for baseband filtering between the mixer
outputs and the baseband amplifier inputs. The baseband amplifier input impedance is high
and the filter termination impedance is set by R2. See Table 7 for the jumper settings.
Default Condition
Not applicable
SW11 = ENBL
Offset compensation loop disable: Installing these jumpers will disable the offset compensation
loop for the corresponding channel.
LK5x = OPEN
SW13 = POT
SW12 = IF
R31 = 57.6 Ω
R32 = 174 Ω
T41 = M/A-COM ETK4-2T;
R41= OPEN; C42, C43 =
1000 pF; R42 = 0 Ω
LK11 installed
R4, R5 = 0 Ω
C10 = 0 Ω
All = OPEN
Table 7. Filter-Jumper Configuration Options
Condition
xMXO to xAIN Directly
xMXO to xAIN via Filter
xMXO to J1x Directly, xAIN Unused
xMXO to J1x via Filter, xAIN Unused
Drive xAIN from J1x
LK1x
LK2x
LK3x
•
•
•
•
•
•
Rev. A | Page 27 of 28
LK4x
•
•
•
AD8348
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
1
6.40 BSC
14
PIN 1
0.65
BSC
0.15
0.05
COPLANARITY
0.10
0.30
0.19
1.20 MAX
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 65. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8348ARU
AD8348ARU-REEL7
AD8348ARUZ 1
AD8348ARUZ-REEL71
AD8348-EVAL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP] 7” Tape and Reel
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP] 7” Tape and Reel
Evaluation Board
Z = Pb-free part.
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C03678-0-4/06(A)
Rev. A | Page 28 of 28
Package Option
RU-28
RU-28
RU-28
RU-28