ICST ICS9248-55 Pentium/pro/iitm system clock chip Datasheet

Integrated
Circuit
Systems, Inc.
ICS9248-55
Pentium/Pro/IITM System Clock Chip
General Description
Features
The ICS9248-55 is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Desktop/Notebook systems that will
provide all necessary clock timing.
•
Features include four CPU and eight PCI clocks. Three
reference outputs are available equal to the crystal frequency.
Additionally, the device meets the Pentium power-up
stabilization requirement, assuring that CPU and PCI clocks
are stable within 2ms after power-up.
PD# pin enables low power mode by stopping crystal OSC
and PLL stages. Other power management features include
CPU_STOP#, which stops CPU (0:3) clocks, and PCI_STOP#,
which stops PCICLK (0:6) clocks.
High drive CPUCLK outputs typically provide greater than 1
V/ns slew rate into 20pF loads. PCICLK outputs typically
provide better than 1V/ns slew rate into 30pF loads while
maintaining 50±5% duty cycle. The REF clock outputs typically
provide better than 0.5V/ns slew rates.
•
•
•
•
•
•
•
•
•
•
Generates system clocks for CPU, IOAPIC, PCI, plus
14.314 MHz REF (0:2), USB, and Super I/O
Supports single or dual processor systems
Supports Spread Spectrum modulation for CPU & PCI
clocks, down spread -0.5%
Skew from CPU (earlier) to PCI clock (rising edges for
100/33.3MHz) 1.5 to 4ns
Two fixed outputs at 48MHz.
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V output: CPU, IOAPIC
3.3V outputs: PCI, REF, 48MHz
No power supply sequence requirements
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal
48 pin 300 mil SSOP
The ICS9248-55 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Pin Configuration
Block Diagram
48-Pin SSOP
Power Groups
VDD = Supply for PLL core
VDD1 = REF (0:2), X1, X2
VDD2 = PCICLK_F, PCICLK (0:6)
VDD3 = 48MHz0, 48MHz1
VDDL1 = IOAPIC (0:1)
VDDL2 = CPUCLK (0:3)
9248-55 Rev B 12/04/98
Ground Groups
* Internal Pull-down Resistor of
240K to GND. on indicated inputs
GND = Ground for PLL core
GND1 = REF (0:2), X1, X2
GND2 = PCICLK_F, PCICLK (0:6)
GND3 = 48MHz0, 48MHz1
GNDL1 = IOAPIC (0:1)
GNDL2 = CPUCLK (0:3)
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-55
Pin Descriptions
PIN NUMBER
1, 2
3
PIN NAME
REF0, REF1
GND1
TYPE
OUT
PWR
4
X1
IN
5
6, 12, 18
7
8, 10, 11, 13, 14, 16, 17
9, 15
19, 33
20, 32
21
22, 23
24
25, 26, 27
28
29
30
31
37, 41
34, 38
35, 36, 39, 40
42
43
44, 45
46
X2
GND2
PCICLK_F
PCICLK (0:6)
VDD2
VDD
GND
VDD3
48MHz (0:1)
GND3
FS (0:2)
SPREAD#
PD#
CPU_STOP#
PCI_STOP#
VDDL2
GNDL2
CPUCLK (3:0)
N/C
GNDL1
IOAPIC (0:1)
VDDL1
OUT
PWR
OUT
OUT
PWR
PWR
PWR
PWR
OUT
PWR
IN
IN
IN
IN
IN
PWR
PWR
OUT
PWR
OUT
PWR
SS_SEL
IN
REF2
VDD1
OUT
PWR
DESCRIPTION
14.318MHz clock output
Ground for REF outputs
XTAL_IN 14.318MHz Crystal input, has internal 33pF
load cap and feed back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Isolated power for core, nominally 3.3V
Isolated ground for core
Power for 48MHz outputs, nominally 3.3V
48MHz outputs
Ground for 48MHz outputs
Frequency Select pins
Enables Spread Spectrum feature when LOW
Powers down chip, active low
Halts CPU clocks at logic "0" level when low
Halts PCI Bus at logic "0" level when low
Power for CPU outputs, nominally 2.5V
Ground for CPU outputs.
CPU and Host clock outputs @ 2.5V
Not internally connected
Ground for IOAPIC outputs
IOAPIC outputs (14.318MHz) @ 2.5V
Power for IOAPIC outputs, nominally 2.5V
±.25% Spread Spectrum Selector at power up.
Logic 0 for Downspread
Logic 1 for Centerspread
14.318MHz clock output
Supply for REF (0:2), X1, X2, nominal 3.3V
REF
IOAPIC
48 MHz
Selection
HI - Z
HI - Z
HI - Z
1
1
47
48
Select Functions
Functionality
CPU
Tristate
HI - Z
Testmode
Spread Spectrum
FS2
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
TCLK/2
PCI,
PCI_F
HI - Z
1
Modulated
FS0
0
1
0
1
0
1
0
1
TCLK/6
2
1
Modulated
CPU MHz
133
83.3
75
66.6
124
133
112
100
2
TCLK
TCLK
14.318MHz
14.318MHz
PCI MHz
33.25
41.65
37.5
33.3
41.33
44.3
37.3
33.3
2
TCLK/21
48.0MHz
ICS9248-55
Power Management
Clock Enable Configuration
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
PCICLK
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
Running
Running
Low
Low
Running
Low
Running
Other Clocks,
REF,
IOAPICs,
48 MHz 0
48 MHz 1
Stopped
Running
Running
Running
Running
Crystal
VCOs
Off
Running
Running
Running
Running
Off
Running
Running
Running
Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# select pin will not cause clocks of a shorter or longer pulse than that of the
running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network
charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-55 Power Management Requirements
SIGNAL
SIGNAL STATE
CPU_ STOP#
0 (Disabled) 2
1 (Enabled) 1
0 (Disabled) 2
1 (Enabled) 1
1 (Normal Operation) 3
0 (Power Down) 4
PCI_STOP#
PD#
Latency
No. of rising edges of free
running PCICLK
1
1
1
1
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF and IOAPIC will be stopped independent of these.
3
ICS9248-55
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-55. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to
the CPUCLKs inside the ICS9248-55.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-55. It is used to turn off the PCICLK (0:6) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-55 internally. The minimum that the PCICLK (0:6) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:6) clocks. PCICLK (0:6) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:6) clock on latency cycles are only one rising PCICLK. Clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-55.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
4
ICS9248-55
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9248-55 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on
latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
5
ICS9248-55
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Power Down
Supply Current
Input frequency
Input Capacitance1
Transition Time1
Settling Time1
Clk Stabilization 1
Skew1
1
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP66
IDD3.3OP100
IDD3.3PD
Fi
CIN
C INX
Ttrans
Ts
TSTAB
TCPU-PCI1
CONDITIONS
MIN
2
VSS-0.3
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
C L = 0 pF; Select @ 66MHz
C L = 0 pF; Select @ 100MHz
-5
-200
TYP
0.1
2.0
-100
60
66
C L = 0 pF; With input address to Vdd or GND
VDD = 3.3 V;
Logic Inputs
X1 & X2 pins
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V;
MAX UNITS
VDD+0.3
V
0.8
V
5
µA
µA
µA
170
mA
170
mA
70
600
µA
11
14.318
27
36
16
5
45
3
MHz
pF
pF
ms
ms
ms
ns
5
1.5
3
4
3
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
Supply Current
Skew1
1
SYMBOL
IDD2.5OP66
IDD2.5OP100
tCPU-PCI2
CONDITIONS
CL = 0 pF; Select @ 66.8 MHz
CL = 0 pF; Select @ 100 MHz
VT = 1.5 V; VTL = 1.25 V
Guaranteed by design, not 100% tested in production.
6
MIN
TYP
16
23
MAX
72
100
UNITS
mA
mA
1.5
3
4
ns
ICS9248-55
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
CONDITIONS
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
MIN
2
19
TYP
2.3
0.2
-41
37
MAX UNITS
V
0.4
V
-19
mA
mA
Rise Time
tr2B
1
VOL = 0.4 V, VOH = 2.0 V
1.25
1.6
ns
Fall Time
tf2B1
VOH = 2.0 V, VOL = 0.4 V
1
1.6
ns
Duty Cycle
d t2B1
tsk2B1
VT = 1.25 V
48
55
%
VT = 1.25 V
30
175
ps
tjcyc-cyc2B1
tj1s2B1
tjabs2B1
VT = 1.25 V
150
200
ps
Skew
Jitter, Cycle-to-cycle
Jitter, One Sigma
Jitter, Absolute
1
SYMBOL
VOH2B
VOL2B
IOH2B
IOL2B
45
VT = 1.25 V
VT = 1.25 V
40
150
ps
-250
140
+250
ps
MIN
2
TYP
2.2
0.33
-41
37
MAX UNITS
V
0.4
V
-28
mA
mA
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH4B
VOL4B
IOH4B
IOL4B
Tr4B
VOL = 0.4 V, VOH = 2.0 V
1.5
2
ns
Fall Time1
1.3
2
ns
IOH = -18 mA
IOL = 18 mA
VOH = 1.7 V
VOL = 0.7 V
29
Tf4B
VOH = 2.0 V, VOL = 0.4 V
Duty Cycle1
Dt4B
VT = 1.25 V
54
55
%
Skew1
tsk4B1
VT = 1.25 V
60
250
ps
Tj1s4B
Tjabs4B
VT = 1.25 V
VT = 1.25 V
1
3
%
5
%
Jitter, One Sigma
Jitter, Absolute1
1
CONDITIONS
1
45
-5
Guaranteed by design, not 100% tested in production.
7
ICS9248-55
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
CONDITIONS
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.4
16
TYP
3.1
0.1
-62
57
MAX UNITS
V
0.4
V
-22
mA
mA
tr1
VOL = 0.4 V, VOH = 2.4 V
1.5
2
ns
tf1
VOH = 2.4 V, VOL = 0.4 V
1.1
2
ns
dt1
VT = 1.5 V
50
55
%
Skew
tsk1
VT = 1.5 V
140
500
ps
Jitter, One Sigma1
Jitter, Absolute1
tj1s1
tjabs1
VT = 1.5 V
VT = 1.5 V
17
150
ps
-500
70
500
ps
MIN
2.6
TYP
3.1
0.17
-44
42
Fall Time
1
1
Duty Cycle
1
1
SYMBOL
VOH1
VOL1
IOH1
IOL1
45
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
CONDITIONS
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
29
tr5
VOL = 0.4 V, VOH = 2.4 V
Fall Time1
tf5
VOH = 2.4 V, VOL = 0.4 V
Duty Cycle1
dt5
VT = 1.5 V
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
Jitter, One Sigma
Jitter, Absolute1
1
SYMBOL
VOH5
VOL5
IOH5
IOL5
1
1.4
45
Guaranteed by design, not 100% tested in production.
8
MAX UNITS
V
0.4
V
-22
mA
mA
2
ns
1.1
2
ns
53
55
%
1
3
%
3
5
%
ICS9248-55
Electrical Characteristics - 48 MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Frequency Accuracy1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
1
Duty Cycle
Jitter, One Sigma
Jitter, Absolute1
1
1
SYMBOL
FACC48m
VOH5
VOL5
IOH5
IOL5
CONDITIONS
MIN
TYP
MAX UNITS
2.6
3
0.14
-44
42
0.4
-22
167
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
16
ppm
V
V
mA
mA
tr5
VOL = 0.4 V, VOH = 2.4 V
1.2
4
ns
tf5
VOH = 2.4 V, VOL = 0.4 V
1.2
4
ns
dt5
VT = 1.5 V
52
55
%
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
1
3
%
3
5
%
45
Guaranteed by design, not 100% tested in production.
9
ICS9248-55
SSOP Package
SYMBOL
A
A1
A2
B
C
D
E
e
H
h
L
N
∝
X
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095
.101
.110
.008
.012
.016
.088
.090
.092
.008
.010
.0135
.005
.006
.0085
See Variations
.292
.296
.299
0.025 BSC
.400
.406
.410
.010
.013
.016
.024
.032
.040
See Variations
0°
5°
8°
.085
.093
.100
VARIATIONS
AC
AD
MIN.
.620
.720
D
NOM.
.625
.725
N
MAX.
.630
.730
48
56
This table in inches
Ordering Information
ICS9248BF-55
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
10
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.