HUFA75329G3, HUFA75329P3, HUFA75329S3S
Data Sheet
June 2002
49A, 55V, 0.024 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET® process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable
and battery-operated products.
Features
• 49A, 55V
• Ultra Low On-Resistance, rDS(ON) = 0.024Ω
• Temperature Compensating PSPICE® and SABER™
Models
- Available on the web at: www.fairchildsemi.com
• Thermal Impedance PSPICE and SABER Models
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Formerly developmental type TA75329.
D
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUFA75329G3
TO-247
75329G
HUFA75329P3
TO-220AB
75329P
HUFA75329S3S
TO-263AB
75329S
G
S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUFA75329S3ST.
Packaging
JEDEC STYLE TO-247
JEDEC TO-220AB
SOURCE
DRAIN
GATE
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN
(TAB)
JEDEC TO-263AB
GATE
DRAIN
(FLANGE)
SOURCE
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (R GS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg
UNITS
V
V
V
55
55
±20
49
Figure 4
Figures 6, 14, 15
128
0.86
-55 to 175
A
W
W/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
55
-
-
V
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 11)
VDS = 50V, VGS = 0V
-
-
1
µA
VDS = 45V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS , ID = 250µA (Figure 10)
2
-
4
V
Drain to Source On Resistance
rDS(ON)
ID = 49A, VGS = 10V (Figure 9)
-
0.020
0.024
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
(Figure 3)
-
-
1.17
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-247
-
-
30
oC/W
TO-220, TO-263
-
-
62
oC/W
VDD = 30V, ID ≅ 49A,
RL = 0.61Ω, VGS = 10V,
RGS = 9.1Ω
-
-
105
ns
-
12
-
ns
tr
-
58
-
ns
td(OFF)
-
33
-
ns
tf
-
33
-
ns
tOFF
-
-
100
ns
-
60
75
nC
-
35
43
nC
-
2.0
2.5
nC
-
5
-
nC
-
13
-
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
tON
td(ON)
GATE CHARGE SPECIFICATIONS
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Total Gate Charge
Gate to Source Gate Charge
Qgs
Gate to Drain “Miller” Charge
Qgd
©2002 Fairchild Semiconductor Corporation
VDD = 30V,
ID ≅ 49A,
RL = 0.61Ω
Ig(REF) = 1.0mA
(Figure 13)
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
TC = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
1060
-
pF
-
405
-
pF
-
95
-
pF
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
MIN
TYP
MAX
UNITS
ISD = 49A
-
-
1.25
V
trr
ISD = 49A, dISD/dt = 100A/µs
-
-
72
ns
QRR
ISD = 49A, dISD/dt = 100A/µs
-
-
120
nC
VSD
Reverse Recovery Time
Reverse Recovered Charge
TEST CONDITIONS
1.2
60
1.0
50
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
40
30
20
10
0.2
0
0
0
25
50
75
100
125
150
25
175
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01 -5
10
10-4
10-3
10 -2
10-1
100
101
t , RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
Typical Performance Curves
(Continued)
I DM, PEAK CURRENT (A)
1000
TC = 25 oC
FOR TEMPERATURES
ABOVE 25 oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I 25
VGS = 10V
150
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10 -4
10 -3
10 -2
10 -1
10 0
10 1
t , PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
500
TJ = MAX RATED
TC = 25 oC
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
500
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r DS(ON)
10ms
VDSS(MAX) = 55V
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
STARTING TJ = 25 oC
STARTING TJ = 150oC
10
0.001
1
1
10
100
200
0.01
1
0.1
tAV, TIME IN AVALANCHE (ms)
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
100
VGS = 20V
VGS = 10V
VGS = 8V
VGS = 7V
80
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
100
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
VGS = 6V
60
40
VGS = 5V
20
PULSE TEST
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
80
175 oC
60
40
20
PULSE DURATION = 80µs
TC = 25oC
0
0
-55oC
1
2
3
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
©2002 Fairchild Semiconductor Corporation
25 oC
5
0
0
VDD = 15V
1.5
3.0
4.5
6.0
VGS, GATE TO SOURCE VOLTAGE (V)
7.5
FIGURE 8. TRANSFER CHARACTERISTICS
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
Typical Performance Curves
(Continued)
1.2
80µs PULSE TEST
VGS = 10V, I D = 49A
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.5
2.0
1.5
1.0
0.5
-80
-40
0
40
80
120
160
1.0
0.8
0.6
0.4
-80
200
-40
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
40
80
120
160
200
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1800
ID = 250µA
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + C GD
1500
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
0
TJ, JUNCTION TEMPERATURE (oC)
1.1
1.0
0.9
1200
CISS
900
600
COSS
300
CRSS
0.8
-80
-40
0
40
80
120
160
0
200
0
TJ , JUNCTION TEMPERATURE (oC)
10
20
30
40
50
60
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VGS , GATE TO SOURCE VOLTAGE (V)
10
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 49A
ID = 36.75A
ID = 24.5A
ID = 12.25A
2
VDD = 30V
0
0
5
10
15
20
25
30
35
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
Test Circuits and Waveforms
VDS
BVDSS
tP
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
VDS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
-
VDD
VGS = 10V
VGS
DUT
VGS = 2V
IG(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
0
10%
DUT
RGS
VGS
90%
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
PSPICE Electrical Model
.SUBCKT HUFA75329P 2 1 3 ;
rev 6/18/02
CA 12 8 1.72e-9
CB 15 14 1.52e-9
CIN 6 8 9.61e-10
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
DRAIN
2
5
10
RLDRAIN
RSLC1
51
5
51
11
ESG
LGATE
GATE
1
+
17
EBREAK 18
RDRAIN
6
8
EVTHRES
+ 19 8
+
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
8
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20 1.52
RLDRAIN 2 5 10
RLGATE 1 9 26.9
RLSOURCE 3 7 28.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 13.85e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
ESLC
50
-
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 2.86e-9
LSOURCE 3 7 2.69e-9
DBREAK
+
RSLC2
EBREAK 11 7 17 18 58.13
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
12
S2A
14
13
13
8
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
EGS
19
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*135),3.5))}
.MODEL DBODYMOD D (IS = 7.50e-13 RS = 5.05e-3 TRS1 = 2.21e-3 TRS2 = 1.02e-6 CJO = 1.51e-9 TT = 4.05e-8 M = 0.5)
.MODEL DBREAKMOD D (RS = 2.14e-1 TRS1 = 9.62e-4 TRS2 = 1.23e-6)
.MODEL DPLCAPMOD D (CJO = 13.5e-10 IS = 1e-30 N = 10 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 2.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.52)
.MODEL MSTROMOD NMOS (VTO = 3.80 KP = 70.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.91 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 15.2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = 1.94e-7)
.MODEL RDRAINMOD RES (TC1 = 8.04e-2 TC2 = 1.37e-4)
.MODEL RSLCMOD RES (TC1 = 4.83e-3 TC2 = 1.16e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -3.43e-3 TC2 = -1.63e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.35e-3 TC2 = 1.16e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -7.90 VOFF= -4.90)
VON = -4.90 VOFF= -7.90)
VON = -0.50 VOFF= 2.50)
VON = 2.50 VOFF= -0.50)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
SABER Electrical Model
REV June 2002
template hufa75329p n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 7.50e-13, cjo = 1.51e-9, tt = 4.05e-8, m = 0.5)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 13.5e-10, is = 1e-30, n = 10, m = 0.85)
m..model mmedmod = (type=_n, vto = 3.25, kp = 2.50, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.80, kp = 70, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.91, kp = 0.06, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.90, voff = -4.90)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4.90, voff = -7.90)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.50, voff = 2.50)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2.50, voff = -0.50)
LDRAIN
DPLCAP
DRAIN
2
5
10
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
72
ISCL
c.ca n12 n8 = 1.72e-9
c.cb n15 n14 = 1.52e-9
c.cin n6 n8 = 9.61e-10
i.it n8 n17 = 1
RDRAIN
6
8
ESG
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
EVTHRES
+ 19 8
+
LGATE
GATE
1
DBREAK
50
-
EVTEMP
RGATE + 18 22
9
20
21
MWEAK
DBODY
EBREAK
+
17
18
MMED
MSTRO
RLGATE
71
11
16
6
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.86e-9
l.lsource n3 n7 = 2.69e-9
k.k1 i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085
RDBODY
CIN
-
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 1.94e-7
res.rdbody n71 n5 = 5.05e-3, tc1 = 2.21e-3, tc2 = 1.02e-6
res.rdbreak n72 n5 = 2.14e-1, tc1 = 9.62e-4, tc2 = 1.23e-6
res.rdrain n50 n16 = 1e-3, tc1 = 8.04e-2, tc2 = 1.37e-4
res.rgate n9 n20 = 1.52
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 26.9
res.rlsource n3 n7 = 28.6
res.rslc1 n5 n51 = 1e-6, tc1 = 4.83e-3, tc2 = 1.16e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 13.85e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.35e-3, tc2 = 1.16e-6
res.rvthres n22 n8 = 1, tc1 = -3.43e-3, tc2 = -1.63e-5
S1A
12
S2A
14
13
13
8
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
-
IT
14
+
+
EGS
19
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 58.13
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/135))** 3.5))
}
}
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
SPICE Thermal Model
th
JUNCTION
REV 18June2002
HUFA75329P
CTHERM1 th 6 2.80e-3
CTHERM2 6 5 1.00e-2
CTHERM3 5 4 6.80e-3
CTHERM4 4 3 7.00e-3
CTHERM5 3 2 2.2e-2
CTHERM6 2 tl 5.1e-2
RTHERM1
RTHERM1 th 6 7.94e-3
RTHERM2 6 5 1.98e-2
RTHERM3 5 4 5.57e-2
RTHERM4 4 3 3.13e-1
RTHERM5 3 2 4.61e-1
RTHERM6 2 tl 7.26e-2
RTHERM2
CTHERM1
6
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUFA75329P
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.80e-3
ctherm.ctherm2 6 5 = 1.00e-2
ctherm.ctherm3 5 4 = 6.80e-3
ctherm.ctherm4 4 3 = 7.00e-3
ctherm.ctherm5 3 2 = 2.2e-2
ctherm.ctherm6 2 tl = 5.1e-2
rtherm.rtherm1 th 6 = 7.94e-3
rtherm.rtherm2 6 5 = 1.98e-2
rtherm.rtherm3 5 4 = 5.57e-2
rtherm.rtherm4 4 3 = 3.13e-1
rtherm.rtherm5 3 2 = 4.61e-1
rtherm.rtherm6 2 tl = 7.26e-2
}
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2002 Fairchild Semiconductor Corporation
CASE
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
I2C™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
SPM™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H7