Preliminary Information H EE GEN FR ALO CAT34AC02 2K-Bit SMBus EEPROM for ACR Card Configuration LE A D F R E ETM FEATURES ■ 400 kHz (5V) and 100 kHz (1.8V) SMBus ■ Self-timed write cycle with auto-clear compatible ■ 1,000,000 program/erase cycles ■ 1.8 to 6.0 volt operation ■ 100 year data retention ■ Low power CMOS technology ■ 8-pin DIP, 8-pin SOIC and 8-pin TSSOP packages – zero standby current ■ 256 x 8 memory organization ■ 16-byte page write buffer ■ Hardware write protect ■ Industrial, automotive and extended temperature ranges DESCRIPTION The CAT34AC02 is a 2K-bit Serial CMOS EEPROM internally organized as 256 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT34AC02 features a 16-byte page write buffer. The device operates via the SMBus serial interface for ACR card configuration and is available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP packages. PIN CONFIGURATION BLOCK DIAGRAM DIP Package (P, L) SOIC Package (J, W) EXTERNAL LOAD A0 A1 A2 VSS 1 2 8 7 VCC WP A0 A1 1 2 8 7 VCC WP 3 4 6 5 SCL SDA A2 VSS 3 4 6 5 SCL SDA VCC VSS VSS 1 2 3 4 8 7 6 5 WORD ADDRESS BUFFERS COLUMN DECODERS MSOP Package (R, Z) TSSOP Package (U, Y) A0 A1 A2 SENSE AMPS SHIFT REGISTERS DOUT ACK VCC WP SCL SDA 1 2 8 7 3 4 6 5 SDA START/STOP LOGIC XDEC WP E2PROM CONTROL LOGIC PIN FUNCTIONS Pin Name Function A0, A1, A2 Device Address Inputs SDA Serial Data/Address SCL Serial Clock WP Write Protect VCC +1.8V to +6.0V Power Supply VSS Ground © 2003 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL SCL A0 A1 A2 1 STATE COUNTERS SLAVE ADDRESS COMPARATORS Doc No. 1025, Rev. E CAT34AC02 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol Parameter NEND(3) Endurance MIL-STD-883, Test Method 1033 1,000,000 Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH(3)(4) Latch-up JEDEC Standard 17 100 mA TDR (3) Reference Test Method Min Typ Max Units Cycles/Byte D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Units ICC Power Supply Current (Read) fSCL = 100 kHz 1 mA ICC Power Supply Current (Write) fSCL = 100 kHz 3 mA Standby Current (VCC = 5.0V) VIN = GND or VCC 0 µA ILI Input Leakage Current VIN = GND to VCC 10 µA ILO Output Leakage Current VOUT = GND to VCC 10 µA VIL Input Low Voltage –1 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V ISB (5) VOL1 Output Low Voltage (VCC = 3.0V) IOL = 3 mA 0.4 V VOL2 Output Low Voltage (VCC = 1.8V) IOL = 1.5 mA 0.5 V CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) CIN (3) Parameter Test Conditions Min Typ Max Units Input/Output Capacitance (SDA) VI/O = 0V 8 pF Input Capacitance (A0, A1, A2, SCL) VIN = 0V 6 pF Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Standby Current (ISB) = 0µA (<900nA). Doc. No. 1025, Rev. E 2 CAT34AC02 A.C. CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Read & Write Cycle Limits 1.8V-6.0V, 2.5V - 6.0V Symbol 4.5V - 5.5V Parameter Units Min Max Min Max FSCL Clock Frequency 100 400 kHz TI(1) Noise Suppression Time Constant at SCL, SDA Inputs 100 100 ns t AA SCL Low to SDA Data Out and ACK Out 3.5 1 µs tBUF(1) Time the Bus Must be Free Before a New Transmission Can Start tHD:STA Start Condition Hold Time 4.7 1.2 µs 4 0.6 µs tLOW Clock Low Period 4.7 1.2 µs tHIGH Clock High Period 4 0.6 µs 4.7 0.6 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 50 50 ns tR(1) SDA and SCL Rise Time 1 0.3 µs tF(1) SDA and SCL Fall Time 300 300 ns tSU:STO tDH Stop Condition Setup Time Data Out Hold Time 4 0.6 µs 100 100 ns Power-Up Timing(1)(2) Symbol Parameter Min Typ Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Typ Max Units 4 5 ms Write Cycle Limits Symbol tWR Parameter Min Write Cycle Time interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 3 Doc No. 1025, Rev. E CAT34AC02 FUNCTIONAL DESCRIPTION all data transfers into or out of the device. This is an input pin. The CAT34AC02 supports the SMBus data transmission protocol. This serial protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT34AC02 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. A maximum of 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2. SDA: Serial Data/Address The CAT34AC02 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These inputs set device address when cascading multiple devices. A maximum of eight devices can be cascaded when using the device. WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. For CAT34AC02 when this pin is tied to VCC, the entire array of memory is write protected. When left floating, memory is unprotected. PIN DESCRIPTIONS SCL: Serial Clock The CAT34AC02 serial clock input pin is used to clock Figure 1. Bus Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 2. Write Cycle Timing SCL SDA 8TH BIT BYTE n ACK tWR STOP CONDITION START CONDITION Figure 3. Start/Stop Timing SDA SCL START BIT Doc. No. 1025, Rev. E STOP BIT 4 ADDRESS CAT34AC02 eight CAT34AC02 may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. SERIAL BUS PROTOCOL The following defines the features of the ACR Serial bus protocol: (1) Data transfer may be initiated only when the bus is not busy. After the Master sends a START condition and the slave address byte, the CAT34AC02 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT34AC02 then performs a Read or a Write operation depending on the state of the R/W bit. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition Acknowledge The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT34AC02 monitor the SDA and SCL lines and will not respond until this condition is met. After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. STOP Condition The CAT34AC02 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each byte. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING When the CAT34AC02 begins a READ mode, it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT34AC02 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1011 for the CAT34AC02 (see Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to Figure 4. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 5. Slave Address Bits 1 0 1 1 A2 A1 A0 R/W DEVICE ADDRESS 5 Doc No. 1025, Rev. E CAT34AC02 WRITE OPERATIONS Byte Write Once all 16 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT34AC02 in a single write cycle. In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT34AC02. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT34AC02 acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT34AC02 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT34AC02 is still busy with the write operation, no ACK will be returned. If the CAT34AC02 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Page Write The CAT34AC02 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted the CAT34AC02 will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged. WRITE PROTECTION The write protection feature of CAT34AC02 allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to Vcc, the entire memory array is protected and becomes read only. If the WP pin is left floating or tied to Vss, the device can be written into. If the Master transmits more than 16 bytes prior to sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. Figure 6. Byte Write Timing S T A R T BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS S T O P DATA S P A C K A C K A C K Figure 7. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS (n) S DATA n DATA n+1 DATA n+P P * A C K A C K A C K NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0 Doc. No. 1025, Rev. E S T O P 6 A C K A C K CAT34AC02 READ OPERATIONS The READ operation for the CAT34AC02 is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. and the slave address, this time with the R/W bit set to one. The CAT34AC02 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Immediate Address Read Sequential Read The CAT34AC02’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N = 255 for the CAT34AC02, then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT34AC02 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT34AC02 sends the initial 8-bit data requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT34AC02 will continue to output a byte for each acknowledge sent by the Master. The operation will terminate operation when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from the CAT34AC02 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT34AC02 address bits so that the entire memory array can be read during one operation. If more than the 256 bytes are read out, the counter will “wrap around” and continue to clock out data bytes. Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT34AC02 acknowledge the word address, the Master device resends the START condition Figure 8. Immediate Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS S P A C K K SCL SDA 8 DATA N O A C K 9 8TH BIT DATA OUT NO ACK 7 STOP Doc No. 1025, Rev. E CAT34AC02 Figure 9. Memory Array FFH Hardware Write Protectable (by connecting WP pin to Vcc) 00H Figure 10. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS (n) S T O P SLAVE ADDRESS P S S A C K * A C K A C K DATA n N O A C K 5020 FHD F11 Figure 11. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K N O A C K 5020 FHD F12 Doc. No. 1025, Rev. E 8 CAT34AC02 ORDERING INFORMATION Prefix CAT Optional Company ID Device # 34AC02 Product Number Suffix J -1.8 I Temperature Range I = Industrial (-40ßC to 85ßC) A = Automotive (-40ßC to 105ßC) E = Extended (-40ßC to 125ßC) Package P: PDIP J: SOIC (JEDEC) U: TSSOP R: MSOP L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Z: MSOP (Lead free, Halogen free) TE13 Tape & Reel TE13: 2000/Reel Operating Voltage Blank: 2.5V - 6.0V 1.8: 1.8V - 6.0V Notes: (1) The device used in the above example is a 34AC02JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) 9 Doc No. 1025, Rev. E Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: Type: 1025 E 5/9/03 Preliminary