FQD3N25 / FQU3N25 November 2000 QFET TM FQD3N25 / FQU3N25 250V N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switching DC/DC converters, switch mode power supply. • • • • • • 2.4A, 250V, RDS(on) = 2.2Ω @VGS = 10 V Low gate charge ( typical 4.0 nC) Low Crss ( typical 4.7 pF) Fast switching 100% avalanche tested Improved dv/dt capability D ! D " ! " " " G! G S I-PAK D-PAK FQD Series G D S FQU Series ! S Absolute Maximum Ratings Symbol VDSS ID TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current FQD3N25 / FQU3N25 250 Units V 2.4 A - Continuous (TC = 100°C) IDM Drain Current - Pulsed (Note 1) 1.5 A 9.6 A VGSS Gate-Source Voltage ± 30 V EAS Single Pulsed Avalanche Energy (Note 2) 40 mJ IAR Avalanche Current (Note 1) 2.4 A EAR Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) * (Note 1) 3.0 5.5 2.5 mJ V/ns W 30 0.24 -55 to +150 W W/°C °C 300 °C dv/dt PD (Note 3) Power Dissipation (TC = 25°C) TJ, TSTG TL - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Characteristics Symbol RθJC Parameter Thermal Resistance, Junction-to-Case Typ -- Max 4.17 Units °C/W RθJA RθJA Thermal Resistance, Junction-to-Ambient * -- 50 °C/W Thermal Resistance, Junction-to-Ambient -- 110 °C/W * When mounted on the minimum pad size recommended (PCB Mount) ©2000 Fairchild Semiconductor International Rev. A, November 2000 Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units 250 -- -- V -- 0.24 -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C IDSS IGSSF IGSSR VDS = 250 V, VGS = 0 V -- -- 1 µA VDS = 200 V, TC = 125°C -- -- 10 µA Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA 3.0 -- 5.0 V -- 1.75 2.2 Ω -- 1.43 -- S -- 130 170 pF -- 30 40 pF -- 4.7 6.1 pF -- 6.6 23 ns -- 25 60 ns -- 5.5 21 ns Zero Gate Voltage Drain Current On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 1.2 A gFS Forward Transconductance VDS = 50 V, ID = 1.2 A (Note 4) Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 125 V, ID = 2.8 A, RG = 25 Ω (Note 4, 5) VDS = 200 V, ID = 2.8 A, VGS = 10 V (Note 4, 5) -- 20 50 ns -- 4.0 5.2 nC -- 1.1 -- nC -- 2.2 -- nC A Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- 2.4 ISM -- -- 9.6 A VSD Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 2.4 A Drain-Source Diode Forward Voltage -- -- 1.5 V trr Reverse Recovery Time -- 100 -- ns Qrr Reverse Recovery Charge -- 0.3 -- µC VGS = 0 V, IS = 2.8 A, dIF / dt = 100 A/µs (Note 4) Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 11mH, IAS = 2.4A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ 2.8A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 5. Essentially independent of operating temperature ©2000 Fairchild Semiconductor International Rev. A, November 2000 FQD3N25 / FQU3N25 Electrical Characteristics VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V ID, Drain Current [A] 0 10 ID , Drain Current [A] Top : -1 10 0 10 150℃ 25℃ -1 -55℃ 10 ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ ※ Notes : 1. VDS = 50V 2. 250μ s Pulse Test -2 -1 0 10 10 1 10 2 10 4 6 8 10 VGS , Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 8 IDR , Reverse Drain Current [A] RDS(on) [Ω], Drain-Source On-Resistance 10 VGS = 10V 6 VGS = 20V 4 2 0 0 10 150℃ ※ Notes : 25℃ 1. VGS = 0V 2. 250μ s Pulse Test -1 0 1 2 3 4 5 6 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ID , Drain Current [A] VSD, Source-Drain voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 12 300 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 200 Ciss 150 Coss ※ Notes : 1. VGS = 0 V 2. f = 1 MHz 100 Crss 50 VDS = 50V 10 VGS, Gate-Source Voltage [V] 250 Capacitance [pF] FQD3N25 / FQU3N25 Typical Characteristics VDS = 125V VDS = 200V 8 6 4 2 ※ Note : ID = 2.8 A 0 -1 10 0 0 10 1 10 VDS, Drain-Source Voltage [V] Figure 5. Capacitance Characteristics ©2000 Fairchild Semiconductor International 0 1 2 3 4 5 QG, Total Gate Charge [nC] Figure 6. Gate Charge Characteristics Rev. A, November 2000 FQD3N25 / FQU3N25 Typical Characteristics (Continued) 1.2 3.0 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.5 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.9 0.8 -100 -50 0 50 100 150 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 1.4 A 0.5 0.0 -100 200 -50 0 50 100 150 200 o o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 2.5 Operation in This Area is Limited by R DS(on) 2.0 1 10 ID, Drain Current [A] ID, Drain Current [A] 100 µs 1 ms 10 ms 0 10 DC -1 10 ※ Notes : 1.5 1.0 0.5 o 1. TC = 25 C o 2. TJ = 150 C 3. Single Pulse -2 10 0 1 10 0.0 25 2 10 10 50 JC ( t) , T h e r m a l R e s p o n s e Figure 9. Maximum Safe Operating Area 100 125 150 Figure 10. Maximum Drain Current vs. Case Temperature D = 0 .5 10 0 ※ N o te s : 1 . Z θ J C ( t ) = 4 . 1 7 ℃ /W M a x . 2 . D u ty F a c t o r , D = t 1 /t 2 3 . T JM - T C = P D M * Z θ JC(t) 0 .2 0 .1 0 .0 5 10 PDM 0 .0 2 0 .0 1 -1 t1 s in g le p u ls e Z θ 75 TC, Case Temperature [℃] VDS, Drain-Source Voltage [V] 10 -5 10 -4 10 t2 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ] Figure 11. Transient Thermal Response Curve ©2000 Fairchild Semiconductor International Rev. A, November 2000 FQD3N25 / FQU3N25 Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ Qg 200nF 12V 10V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL VDS 90% VDD VGS RG VGS DUT 10V 10% td(on) tr td(off) t on tf t off Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG VDD DUT 10V tp ©2000 Fairchild Semiconductor International ID (t) VDS (t) VDD tp Time Rev. A, November 2000 FQD3N25 / FQU3N25 Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2000 Fairchild Semiconductor International Rev. A, November 2000 DPAK MIN0.55 0.91 ±0.10 9.50 ±0.30 0.50 ±0.10 0.76 ±0.10 0.50 ±0.10 1.02 ±0.20 2.30TYP [2.30±0.20] (1.00) (3.05) (2XR0.25) (0.10) 2.70 ±0.20 6.10 ±0.20 9.50 ±0.30 6.60 ±0.20 (5.34) (5.04) (1.50) (0.90) 2.30 ±0.20 (0.70) 2.30TYP [2.30±0.20] (0.50) 2.30 ±0.10 0.89 ±0.10 MAX0.96 (4.34) 2.70 ±0.20 0.60 ±0.20 (0.50) 6.10 ±0.20 5.34 ±0.30 0.70 ±0.20 6.60 ±0.20 0.80 ±0.20 FQD3N25 / FQU3N25 Package Dimensions 0.76 ±0.10 ©2000 Fairchild Semiconductor International Rev. A, November 2000 (Continued) IPAK 2.30 ±0.20 6.60 ±0.20 5.34 ±0.20 0.76 ±0.10 2.30TYP [2.30±0.20] ©2000 Fairchild Semiconductor International 0.50 ±0.10 16.10 ±0.30 6.10 ±0.20 0.70 ±0.20 (0.50) 9.30 ±0.30 MAX0.96 (4.34) 1.80 ±0.20 0.80 ±0.10 0.60 ±0.20 (0.50) 2.30TYP [2.30±0.20] 0.50 ±0.10 Rev. A, November 2000 FQD3N25 / FQU3N25 Package Dimensions TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ PowerTrench QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER SMART START™ Star* Power™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. 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Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H1