Intel N80L188EB13 16-bit high-integration embedded processor Datasheet

80C186EB/80C188EB AND 80L186EB/80L188EB
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
X
Y
X Full Static Operation
True CMOS Inputs and Outputs
Integrated Feature Set
Ð Low-Power Static CPU Core
Ð Two Independent UARTs each with
an Integral Baud Rate Generator
Ð Two 8-Bit Multiplexed I/O Ports
Ð Programmable Interrupt Controller
Ð Three Programmable 16-Bit
Timer/Counters
Ð Clock Generator
Ð Ten Programmable Chip Selects with
Integral Wait-State Generator
Ð Memory Refresh Control Unit
Ð System Level Testing Support (ONCE
Mode)
Y
Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I/O
Y
Speed Versions Available (5V):
Ð 25 MHz (80C186EB25/80C188EB25)
Ð 20 MHz (80C186EB20/80C188EB20)
Ð 13 MHz (80C186EB13/80C188EB13)
Y
Available in Extended Temperature
Range ( b 40§ C to a 85§ C)
Y
Speed Versions Available (3V):
Ð 16 MHz (80L186EB16/80L188EB16)
Ð 13 MHz (80L186EB13/80L188EB13)
Ð 8 MHz (80L186EB8/80L188EB8)
Y
Low-Power Operating Modes:
Ð Idle Mode Freezes CPU Clocks but
keeps Peripherals Active
Ð Powerdown Mode Freezes All
Internal Clocks
Y
Supports 80C187 Numeric Coprocessor
Interface (80C186EB PLCC Only)
Y
Available In:
Ð 80-Pin Quad Flat Pack (QFP)
Ð 84-Pin Plastic Leaded Chip Carrier
(PLCC)
Ð 80-Pin Shrink Quad Flat Pack (SQFP)
The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new
to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent
Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes.
272433 – 1
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
October 1995
COPYRIGHT © INTEL CORPORATION, 1995
Order Number: 272433-004
1
80C186EB/80C188EB and 80L186EB/80L188EB
16-Bit High-Integration Embedded Processors
CONTENTS
PAGE
INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
CORE ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4
80C186EC PERIPHERAL
ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
Interrupt Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
Serial Communications Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Chip-Select Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
I/O Port Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
Power Management Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
80C187 Interface (80C186EB Only) ÀÀÀÀÀÀÀÀÀ 7
ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
Prefix Identification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
CONTENTS
PAGE
Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
ICC versus Frequency and Voltage ÀÀÀÀÀÀÀÀÀ 27
PDTMR Pin Delay Calculation ÀÀÀÀÀÀÀÀÀÀÀÀÀ 27
AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28
AC CharacteristicsÐ80C186EB25 ÀÀÀÀÀÀÀÀÀ 28
AC CharacteristicsÐ80C186EB20/13 ÀÀÀÀÀ 30
AC CharacteristicsÐ80L186EB16 ÀÀÀÀÀÀÀÀÀ 32
Relative Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
Serial Port Mode 0 Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37
AC TEST CONDITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38
AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38
DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41
RESET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42
BUS CYCLE WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45
EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 52
80C186EB PINOUT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 53
PACKAGE THERMAL
SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 59
REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 59
ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 23
Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
2
2
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 2
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB
Figure 1. 80C186EB/80C188EB Block Diagram
3
3
80C186EB/80C188EB, 80L186EB/80L188EB
INTRODUCTION
Unless specifically noted, all references to the
80C186EB apply to the 80C188EB, 80L186EB, and
80L188EB. References to pins that differ between
the 80C186EB/80L186EB and the 80C188EB/
80L188EB are given in parentheses. The ‘‘L’’ in the
part number denotes low voltage operation. Physically and functionally, the ‘‘C’’ and ‘‘L’’ devices are
identical.
The 80C186EB is the first product in a new generation of low-power, high-integration microprocessors.
It enhances the existing 186 family by offering new
features and new operating modes. The 80C186EB
is object code compatible with the 80C186XL/
80C188XL microprocessors.
The 80L186EB is the 3V version of the 80C186EB.
The 80L186EB is functionally identical to the
80C186EB
embedded
processor.
Current
80C186EB users can easily upgrade their designs to
use the 80L186EB and benefit from the reduced
power consumption inherent in 3V operation.
cept the queue status mode has been deleted and
buffer interface control has been changed to ease
system design timings. An independent internal bus
is used to allow communication between the BIU
and internal peripherals.
CORE ARCHITECTURE
Bus Interface Unit
The 80C186EB core incorporates a bus controller
that generates local bus control signals. In addition,
it employs a HOLD/HLDA protocol to share the local
bus with other bus masters.
The bus controller is responsible for generating 20
bits of address, read and write strobes, bus cycle
status information, and data (for write operations) information. It is also responsible for reading data off
the local bus during a read operation. A READY input pin is provided to extend a bus cycle beyond the
minimum four states (clocks).
The feature set of the 80C186EB meets the needs
of low power, space critical applications. Low-Power
applications benefit from the static design of the
CPU core and the integrated peripherals as well as
low voltage operation. Minimum current consumption is achieved by providing a Powerdown mode
that halts operation of the device, and freezes the
clock circuits. Peripheral design enhancements ensure that non-initialized peripherals consume little
current.
The local bus controller also generates two control
signals (DEN and DT/R) when interfacing to external transceiver chips. (Both DEN and DT/R are
available on the PLCC devices, only DEN is available on the QFP and SQFP devices.) This capability
allows the addition of transceivers for simple buffering of the multiplexed address/data bus.
Space critical applications benefit from the integration of commonly used system peripherals. Two
serial channels are provided for services such as
diagnostics, inter-processor communication, modem
interface, terminal display interface, and many others. A flexible chip select unit simplifies memory and
peripheral interfacing. The interrupt unit provides
sources for up to 129 external interrupts and will prioritize these interrupts with those generated from
the on-chip peripherals. Three general purpose timer/counters and sixteen multiplexed I/O port pins
round out the feature set of the 80C186EB.
The processor provides an on-chip clock generator
for both internal and external clock generation. The
clock generator features a crystal oscillator, a divideby-two counter, and two low-power operating
modes.
Figure 1 shows a block diagram of the 80C186EB/
80C188EB. The Execution Unit (EU) is an enhanced
8086 CPU core that includes: dedicated hardware to
speed up effective address calculations, enhance
execution speed for multiple-bit shift and rotate instructions and for multiply and divide instructions,
string move instructions that operate at full bus
bandwidth, ten new instruction, and fully static operation. The Bus Interface Unit (BIU) is the same as
that found on the original 186 family products, ex-
The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide-by-two counter. This counter is
used to drive all internal phase clocks and the external CLKOUT signal. CLKOUT is a 50% duty cycle
processor clock and can be used to drive other system components. All AC timings are referenced to
CLKOUT.
Clock Generator
The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-overtone mode crystal network. Alternatively, the oscillator circuit may be driven from an external clock
source. Figure 2 shows the various operating modes
of the oscillator circuit.
4
4
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 4
272433 – 3
(A) Crystal Connection
(B) Clock Connection
NOTE:
The L1C1 network is only required when using a thirdovertone crystal.
Figure 2. Clock Configurations
The following parameters are recommended when
choosing a crystal:
Temperature Range:
Application Specific
ESR (Equivalent Series Resistance):
40X max
C0 (Shunt Capacitance of Crystal):
7.0 pF max
CL (Load Capacitance):
20 pF g 2 pF
Drive Level:
1 mW max
80C186EB PERIPHERAL
ARCHITECTURE
The 80C186EB has integrated several common system peripherals with a CPU core to create a compact, yet powerful system. The integrated peripherals are designed to be flexible and provide logical
interconnections between supporting units (e.g., the
interrupt control unit supports interrupt requests
from the timer/counters or serial channels).
The list of integrated peripherals includes:
#
#
#
#
#
#
#
7-Input Interrupt Control Unit
3-Channel Timer/Counter Unit
2-Channel Serial Communications Unit
10-Output Chip-Select Unit
I/O Port Unit
Refresh Control Unit
Power Management Unit
The registers associated with each integrated periheral are contained within a 128 x 16 register file
called the Peripheral Control Block (PCB). The PCB
can be located in either memory or I/O space on
any 256 Byte address boundary.
Figure 3 provides a list of the registers associated
with the PCB. The Register Bit Summary at the end
of this specification individually lists all of the registers and identifies each of their programming attributes.
Interrupt Control Unit
The 80C186EB can receive interrupts from a number of sources, both internal and external. The interrupt control unit serves to merge these requests on
a priority basis, for individual service by the CPU.
Each interrupt source can be independently masked
by the Interrupt Control Unit (ICU) or all interrupts
can be globally masked by the CPU.
Internal interrupt sources include the Timers and Serial channel 0. External interrupt sources come from
the five input pins INT4:0. The NMI interrupt pin is
not controlled by the ICU and is passed directly to
the CPU. Although the Timer and Serial channel
each have only one request input to the ICU, separate vector types are generated to service individual
interrupts within the Timer and Serial channel units.
Timer/Counter Unit
The 80C186EB Timer/Counter Unit (TCU) provides
three 16-bit programmable timers. Two of these are
highly flexible and are connected to external pins for
control or clocking. A third timer is not connected to
any external pins and can only be clocked internally.
However, it can be used to clock the other two timer
channels. The TCU can be used to count external
events, time external events, generate non-repetitive waveforms, generate timed interrupts. etc.
5
5
80C186EB/80C188EB, 80L186EB/80L188EB
PCB
Offset
Function
PCB
Offset
Function
PCB
Offset
Function
PCB
Offset
Function
00H
Reserved
40H
Timer2 Count
80H
GCS0 Start
C0H
Reserved
02H
End Of Interrupt
42H
Timer2 Compare
82H
GCS0 Stop
C2H
Reserved
04H
Poll
44H
Reserved
84H
GCS1 Start
C4H
Reserved
06H
Poll Status
46H
Timer2 Control
86H
GCS1 Stop
C6H
Reserved
08H
Interrupt Mask
48H
Reserved
88H
GCS2 Start
C8H
Reserved
0AH
Priority Mask
4AH
Reserved
8AH
GCS2 Stop
CAH
Reserved
0CH
In-Service
4CH
Reserved
8CH
GCS3 Start
CCH
Reserved
0EH
Interrupt Request
4EH
Reserved
8EH
GCS3 Stop
CEH
Reserved
10H
Interrupt Status
50H
Port 1 Direction
90H
GCS4 Start
D0H
Reserved
12H
Timer Control
52H
Port 1 Pin
92H
GCS4 Stop
D2H
Reserved
14H
Serial Control
54H
Port 1 Control
94H
GCS5 Start
D4H
Reserved
16H
INT4 Control
56H
Port 1 Latch
96H
GCS5 Stop
D6H
Reserved
18H
INT0 Control
58H
Port 2 Direction
98H
GCS6 Start
D8H
Reserved
1AH
INT1 Control
5AH
Port 2 Pin
9AH
GCS6 Stop
DAH
Reserved
1CH
INT2 Control
5CH
Port 2 Control
9CH
GCS7 Start
DCH
Reserved
1EH
INT3 Control
5EH
Port 2 Latch
9EH
GCS7 Stop
DEH
Reserved
20H
Reserved
60H
Serial0 Baud
A0H
LCS Start
E0H
Reserved
22H
Reserved
62H
Serial0 Count
A2H
LCS Stop
E2H
Reserved
24H
Reserved
64H
Serial0 Control
A4H
UCS Start
E4H
Reserved
26H
Reserved
66H
Serial0 Status
A6H
UCS Stop
E6H
Reserved
28H
Reserved
68H
Serial0 RBUF
A8H
Relocation
E8H
Reserved
2AH
Reserved
6AH
Serial0 TBUF
AAH
Reserved
EAH
Reserved
2CH
Reserved
6CH
Reserved
ACH
Reserved
ECH
Reserved
2EH
Reserved
6EH
Reserved
AEH
Reserved
EEH
Reserved
30H
Timer0 Count
70H
Serial1 Baud
B0H
Refresh Base
F0H
Reserved
32H Timer0 Compare A
72H
Serial1 Count
B2H
Refresh Time
F2H
Reserved
34H Timer0 Compare B
74H
Serial1 Control
B4H
Refresh Control
F4H
Reserved
36H
Timer0 Control
76H
Serial1 Status
B6H
Reserved
F6H
Reserved
38H
Timer1 Count
78H
Serial1 RBUF
B8H
Power Control
F8H
Reserved
3AH Timer1 Compare A
7AH
Serial1 TBUF
BAH
Reserved
FAH
Reserved
3CH Timer1 Compare B
7CH
Reserved
BCH
Step ID
FCH
Reserved
3EH
7EH
Reserved
BEH
Reserved
FEH
Reserved
Timer1 Control
Figure 3. Peripheral Control Block Registers
6
6
80C186EB/80C188EB, 80L186EB/80L188EB
Serial Communications Unit
The Serial Control Unit (SCU) of the 80C186EB contains two independent channels. Each channel is
identical in operation except that only channel 0 is
supported by the integrated interrupt controller
(channel 1 has an external interrupt pin). Each
channel has its own baud rate generator that is independent of the Timer/Counter Unit, and can be
internally or externally clocked at up to one half the
80C186EB operating frequency.
Independent baud rate generators are provided for
each of the serial channels. For the asynchronous
modes, the generator supplies an 8x baud clock to
both the receive and transmit register logic. A 1x
baud clock is provided in the synchronous mode.
Chip-Select Unit
The 80C186EB Chip-Select Unit (CSU) integrates
logic which provides up to ten programmable chipselects to access both memories and peripherals. In
addition, each chip-select can be programmed to
automatically insert additional clocks (wait-states)
into the current bus cycle and automatically terminate a bus cycle independent of the condition of the
READY input pin.
I/O Port Unit
The I/O Port Unit (IPU) on the 80C186EB supports
two 8-bit channels of input, output, or input/output
operation. Port 1 is multiplexed with the chip select
pins and is output only. Most of Port 2 is multiplexed
with the serial channel pins. Port 2 pins are limited to
either an output or input function depending on the
operation of the serial pin it is multiplexed with.
Refresh Control Unit
The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to keep
dynamic or pseudo-static memory refreshed. A 9-bit
counter controls the number of clocks between refresh requests.
A 12-bit address generator is maintained by the RCU
and is presented on the A12:1 address lines during
the refresh bus cycle. Address bits A19:13 are programmable to allow the refresh address block to be
located on any 8 Kbyte boundary.
Power Management Unit
The 80C186EB Power Management Unit (PMU) is
provided to control the power consumption of the
device. The PMU provides three power modes: Active, Idle, and Powerdown.
Active Mode indicates that all units on the
80C186EB are functional and the device consumes
maximum power (depending on the level of peripheral operation). Idle Mode freezes the clocks of the
Execution and Bus units at a logic zero state (all
peripherals continue to operate normally).
The Powerdown mode freezes all internal clocks at
a logic zero level and disables the crystal oscillator.
All internal registers hold their values provided VCC
is maintained. Current consumption is reduced to
just transistor junction leakage.
80C187 Interface (80C186EB Only)
The 80C186EB (PLCC package only) supports the
direct connection of the 80C187 Numerics Coprocessor.
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system, the 80C186EB has a test
mode available which forces all output and input/
output pins to be placed in the high-impedance
state. ONCE stands for ‘‘ON Circuit Emulation’’. The
ONCE mode is selected by forcing the A19/ONCE
pin LOW (0) during a processor reset (this pin is
weakly held to a HIGH (1) level) while RESIN is active.
7
7
80C186EB/80C188EB, 80L186EB/80L188EB
PACKAGE INFORMATION
This section describes the pins, pinouts, and thermal
characteristics for the 80C186EB in the Plastic
Leaded Chip Carrier (PLCC) package, Shrink Quad
Flat Pack (SQFP), and Quad Flat Pack (QFP) package. For complete package specifications and information, see the Intel Packaging Outlines and Dimensions Guide (Order Number: 231369).
Prefix Identification
With the extended temperature range, operational
characteristics are guaranteed over the temperature
range corresponding to b 40§ C to a 85§ C ambient.
Package types are identified by a two-letter prefix to
the part number. The prefixes are listed in Table 1.
Table 1. Prefix Identification
Prefix Note
TN
Package
Type
PLCC
TS
Temperature
Type
Extended
QFP (EIAJ) Extended
SB
1
SQFP
Extended/Commercial
N
1
PLCC
Commercial
S
1
QFP (EIAJ) Commercial
NOTE:
1. The 5V 25 MHz and 3V 16 MHz versions are only available in commercial temperature range corresponding to
0§ C to a 70§ C ambient.
Pin Descriptions
Each pin or logical set of pins is described in Table
3. There are three columns for each entry in the Pin
Description Table.
The Pin Type column contains two kinds of information. The first symbol indicates whether a pin is power (P), ground (G), input only (I), output only (O) or
input/output (I/O). Some pins have multiplexed
functions (for example, A19/S6). Additional symbols
indicate additional characteristics for each pin. Table
2 lists all the possible symbols for this column.
The Input Type column indicates the type of input
(Asynchronous or Synchronous).
Asynchronous pins require that setup and hold times
be met only in order to guarantee recognition at a
particular clock edge. Synchronous pins require that
setup and hold times be met to guarantee proper
operation. For example, missing the setup or hold
time for the SRDY pin (a synchronous input) will result in a system failure or lockup. Input pins may also
be edge- or level-sensitive. The possible characteristics for input pins are S(E), S(L), A(E) and A(L).
The Output States column indicates the output
state as a function of the device operating mode.
Output states are dependent upon the current activity of the processor. There are four operational
states that are different from regular operation: bus
hold, reset, Idle Mode and Powerdown Mode. Appropriate characteristics for these states are also indicated in this column, with the legend for all possible characteristics in Table 2.
The Pin Description column contains a text description of each pin.
As an example, consider AD15:0. I/O signifies the
pins are bidirectional. S(L) signifies that the input
function is synchronous and level-sensitive. H(Z)
signifies that, as outputs, the pins are high-impedance upon acknowledgement of bus hold. R(Z) signifies that the pins float during reset. P(X) signifies
that the pins retain their states during Powerdown
Mode.
The Pin Name column contains a mnemonic that
describes the pin function. Negation of the signal
name (for example, RESIN) denotes a signal that is
active low.
8
8
80C186EB/80C188EB, 80L186EB/80L188EB
Table 2. Pin Description Nomenclature
Symbol
Description
P
G
I
O
I/O
Power Pin (Apply a VCC Voltage)
Ground (Connect to VSS)
Input Only Pin
Output Only Pin
Input/Output Pin
S(E)
S(L)
A(E)
A(L)
Synchronous, Edge Sensitive
Synchronous, Level Sensitive
Asynchronous, Edge Sensitive
Asynchronous, Level Sensitive
H(1)
H(0)
H(Z)
H(Q)
H(X)
Output Driven to VCC during Bus Hold
Output Driven to VSS during Bus Hold
Output Floats during Bus Hold
Output Remains Active during Bus Hold
Output Retains Current State during Bus Hold
R(WH)
R(1)
R(0)
R(Z)
R(Q)
R(X)
Output Weakly Held at VCC during Reset
Output Driven to VCC during Reset
Output Driven to VSS during Reset
Output Floats during Reset
Output Remains Active during Reset
Output Retains Current State during Reset
I(1)
I(0)
I(Z)
I(Q)
I(X)
Output Driven to VCC during Idle Mode
Output Driven to VSS during Idle Mode
Output Floats during Idle Mode
Output Remains Active during Idle Mode
Output Retains Current State during Idle Mode
P(1)
P(0)
P(Z)
P(Q)
P(X)
Output Driven to VCC during Powerdown Mode
Output Driven to VSS during Powerdown Mode
Output Floats during Powerdown Mode
Output Remains Active during Powerdown Mode
Output Retains Current State during Powerdown Mode
9
9
80C186EB/80C188EB, 80L186EB/80L188EB
Table 3. Pin Descriptions
Pin
Name
Pin
Type
Input
Type
Output
States
VCC
P
Ð
Ð
POWER connections consist of four pins which must be
shorted externally to a VCC board plane.
VSS
G
Ð
Ð
GROUND connections consist of six pins which must be
shorted externally to a VSS board plane.
CLKIN
I
A(E)
Ð
CLocK INput is an input for an external clock. An external
oscillator operating at two times the required processor
operating frequency can be connected to CLKIN. For crystal
operation, CLKIN (along with OSCOUT) are the crystal
connections to an internal Pierce oscillator.
OSCOUT
O
Ð
H(Q)
R(Q)
P(Q)
OSCillator OUTput is only used when using a crystal to
generate the external clock. OSCOUT (along with CLKIN)
are the crystal connections to an internal Pierce oscillator.
This pin is not to be used as 2X clock output for non-crystal
applications (i.e., this pin is N.C. for non-crystal applications).
OSCOUT does not float in ONCE mode.
CLKOUT
O
Ð
H(Q)
R(Q)
P(Q)
CLocK OUTput provides a timing reference for inputs and
outputs of the processor, and is one-half the input clock
(CLKIN) frequency. CLKOUT has a 50% duty cycle and
transistions every falling edge of CLKIN.
RESIN
I
A(L)
Ð
RESet IN causes the processor to immediately terminate
any bus cycle in progress and assume an initialized state. All
pins will be driven to a known state, and RESOUT will also
be driven active. The rising edge (low-to-high) transition
synchronizes CLKOUT with CLKIN before the processor
begins fetching opcodes at memory location 0FFFF0H.
RESOUT
O
Ð
H(0)
R(1)
P(0)
RESet OUTput that indicates the processor is currently in
the reset state. RESOUT will remain active as long as RESIN
remains active.
PDTMR
I/O
A(L)
H(WH)
R(Z)
P(1)
Power-Down TiMeR pin (normally connected to an external
capacitor) that determines the amount of time the processor
waits after an exit from power down before resuming normal
operation. The duration of time required will depend on the
startup characteristics of the crystal oscillator.
NMI
I
A(E)
Ð
Non-Maskable Interrupt input causes a TYPE-2 interrupt to
be serviced by the CPU. NMI is latched internally.
TEST/BUSY
(TEST)
I
A(E)
Ð
TEST is used during the execution of the WAIT instruction to
suspend CPU operation until the pin is sampled active
(LOW). TEST is alternately known as BUSY when interfacing
with an 80C187 numerics coprocessor (80C186EB only).
I/O
S(L)
H(Z)
R(Z)
P(X)
These pins provide a multiplexed Address and Data bus.
During the address phase of the bus cycle, address bits 0
through 15 (0 through 7 on the 80C188EB) are presented on
the bus and can be latched using ALE. 8- or 16-bit data
information is transferred during the data phase of the bus
cycle.
AD15:0
(AD7:0)
Description
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
10
10
80C186EB/80C188EB, 80L186EB/80L188EB
Table 3. Pin Descriptions (Continued)
Pin
Name
Pin
Type
Input
Type
Output
States
A18:16
A19/ONCE
(A15:A8)
(A18:16)
(A19/ONCE)
I/O
A(L)
H(Z)
R(WH)
P(X)
O
Ð
H(Z)
R(Z)
P(1)
S2:0
Description
These pins provide multiplexed Address during the address
phase of the bus cycle. Address bits 16 through 19 are presented
on these pins and can be latched using ALE. These pins are
driven to a logic 0 during the data phase of the bus cycle. On the
80C188EB, A15 – A8 provide valid address information for the
entire bus cycle. During a processor reset (RESIN active), A19/
ONCE is used to enable ONCE mode. A18:16 must not be driven
low during reset or improper operation may result.
Bus cycle Status are encoded on these pins to provide bus
transaction information. S2:0 are encoded as follows:
S2
S1
S0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bus Cycle Initiated
Interrupt Acknowledge
Read I/O
Write I/O
Processor HALT
Queue Instruction Fetch
Read Memory
Write Memory
Passive (no bus activity)
ALE
O
Ð
H(0)
R(0)
P(0)
Address Latch Enable output is used to strobe address
information into a transparent type latch during the address phase
of the bus cycle.
BHE
(RFSH)
O
Ð
H(Z)
R(Z)
P(X)
Byte High Enable output to indicate that the bus cycle in progress
is transferring data over the upper half of the data bus. BHE and
A0 have the following logical encoding
A0
BHE
0
0
1
1
0
1
0
1
Encoding (for the 80C186EB/80L186EB only)
Word Transfer
Even Byte Transfer
Odd Byte Transfer
Refresh Operation
On the 80C188EB/80L188EB, RFSH is asserted low to indicate a
refresh bus cycle.
RD
O
Ð
H(Z)
R(Z)
P(1)
ReaD output signals that the accessed memory or I/O device
must drive data information onto the data bus.
WR
O
Ð
H(Z)
R(Z)
P(1)
WRite output signals that data available on the data bus are to be
written into the accessed memory or I/O device.
READY
I
A(L)
S(L)
Ð
DEN
O
Ð
H(Z)
R(Z)
P(1)
READY input to signal the completion of a bus cycle. READY
must be active to terminate any bus cycle, unless it is ignored by
correctly programming the Chip-Select Unit.
Data ENable output to control the enable of bi-directional
transceivers in a buffered system. DEN is active only when data is
to be transferred on the bus.
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
11
11
80C186EB/80C188EB, 80L186EB/80L188EB
Table 3. Pin Descriptions (Continued)
Pin
Name
Pin
Type
Input
Type
Output
States
DT/R
O
Ð
H(Z)
R(Z)
P(X)
Data Transmit/Receive output controls the direction of a
bi-directional buffer in a buffered system. DT/R is only
available for the PLCC package.
LOCK
O
Ð
H(Z)
R(WH)
P(1)
LOCK output indicates that the bus cycle in progress is not
to be interrupted. The processor will not service other bus
requests (such as HOLD) while LOCK is active. This pin is
configured as a weakly held high input while RESIN is
active and must not be driven low.
HOLD
I
A(L)
Ð
HLDA
O
Ð
H(1)
R(0)
P(0)
HoLD Acknowledge output to indicate that the processor
has relinquished control of the local bus. When HLDA is
asserted, the processor will (or has) floated its data bus
and control signals allowing another bus master to drive the
signals directly.
NCS
(N.C.)
O
Ð
H(1)
R(1)
P(1)
Numerics Coprocessor Select output is generated when
accessing a numerics coprocessor. NCS is not provided on
the QFP or SQFP packages. This signal does not exist on
the 80C188EB/80L188EB.
ERROR
(N.C.)
I
A(L)
Ð
ERROR input that indicates the last numerics coprocessor
operation resulted in an exception condition. An interrupt
TYPE 16 is generated if ERROR is sampled active at the
beginning of a numerics operation. ERROR is not provided
on the QFP or SQFP packages. This signal does not exist
on the 80C188EB/80L188EB.
PEREQ
(N.C.)
I
A(L)
Ð
CoProcessor REQuest signals that a data transfer
between an External Numerics Coprocessor and Memory is
pending. PEREQ is not provided on the QFP or SQFP
packages. This signal does not exist on the 80C188EB/
80L188EB.
UCS
O
Ð
H(1)
R(1)
P(1)
Upper Chip Select will go active whenever the address of
a memory or I/O bus cycle is within the address limitations
programmed by the user. After reset, UCS is configured to
be active for memory accesses between 0FFC00H and
0FFFFFH.
LCS
O
Ð
H(1)
R(1)
P(1)
Lower Chip Select will go active whenever the address of
a memory bus cycle is within the address limitations
programmed by the user. LCS is inactive after a reset.
P1.0/GCS0
P1.1/GCS1
P1.2/GCS2
P1.3/GCS3
P1.4/GCS4
P1.5/GCS5
P1.6/GCS6
P1.7/GCS7
O
Ð
H(X)/H(1)
R(1)
P(X)/P(1)
These pins provide a multiplexed function. If enabled, each
pin can provide a Generic Chip Select output which will go
active whenever the address of a memory or I/O bus cycle
is within the address limitations programmed by the user.
When not programmed as a Chip-Select, each pin may be
used as a general purpose output Port. As an output port
pin, the value of the pin can be read internally.
Description
HOLD request input to signal that an external bus master
wishes to gain control of the local bus. The processor will
relinquish control of the local bus between instruction
boundaries not conditioned by a LOCK prefix.
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
12
12
80C186EB/80C188EB, 80L186EB/80L188EB
Table 3. Pin Descriptions (Continued)
Pin
Name
Pin
Type
Input
Type
Output
States
Description
T0OUT
T1OUT
O
Ð
H(Q)
R(1)
P(Q)
Timer OUTput pins can be programmed to provide a
single clock or continuous waveform generation,
depending on the timer mode selected.
T0IN
T1IN
I
A(L)
A(E)
Ð
Timer INput is used either as clock or control signals,
depending on the timer mode selected.
INT0
INT1
INT4
I
A(E,L)
Ð
Maskable INTerrupt input will cause a vector to a
specific Type interrupt routine. To allow interrupt
expansion, INT0 and/or INT1 can be used with
INTA0 and INTA1 to interface with an external slave
controller.
INT2/INTA0
INT3/INTA1
I/O
A(E,L)
H(1)
R(Z)
P(1)
These pins provide a multiplexed function. As inputs,
they provide a maskable INTerrupt that will cause
the CPU to vector to a specific Type interrupt routine.
As outputs, each is programmatically controlled to
provide an INTERRUPT ACKNOWLEDGE
handshake signal to allow interrupt expansion.
P2.7
P2.6
I/O
A(L)
H(X)
R(Z)
P(X)
BI-DIRECTIONAL, open-drain Port pins.
CTSO
P2.4/CTS1
I
A(L)
Ð
Clear-To-Send input is used to prevent the
transmission of serial data on their respective TXD
signal pin. CTS1 is multiplexed with an input only port
function.
TXD0
P2.1/TXD1
O
Ð
H(X)/H(Q)
R(1)
P(X)/P(Q)
Transmit Data output provides serial data
information. TXD1 is multiplexed with an output only
Port function. During synchronous serial
communications, TXD will function as a clock output.
RXD0
P2.0/RXD1
I/O
A(L)
R(Z)
H(Q)
P(X)
Receive Data input accepts serial data information.
RXD1 is multiplexed with an input only Port function.
During synchronous serial communications, RXD is
bi-directional and will become an output for
transmission or data (TXD becomes the clock).
P2.5/BCLK0
P2.2/BCLK1
I
A(L)/A(E)
Ð
Baud CLocK input can be used as an alternate clock
source for each of the integrated serial channels.
BCLKx is multiplexed with an input only Port function,
and cannot exceed a clock rate greater than one-half
the operating frequency of the processor.
P2.3/SINT1
O
Ð
H(X)/H(Q)
R(0)
P(X)/P(X)
Serial INTerrupt output will go active to indicate
serial channel 1 requires service. SINT1 is
multiplexed with an output only Port function.
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
13
13
80C186EB/80C188EB, 80L186EB/80L188EB
80C186EB PINOUT
Tables 4 and 5 list the 80C186EB/80C188EB pin
names with package location for the 84-pin Plastic
Leaded Chip Carrier (PLCC) component. Figure 5
depicts the complete 80C186EB/80C188EB pinout
(PLCC package) as viewed from the top side of the
component (i.e., contacts facing down).
Tables 6 and 7 list the 80C186EB/80C188EB pin
names with package location for the 80-pin Quad
Flat Pack (QFP) component. Figure 6 depicts the
complete 80C186EB/80C188EB (QFP package) as
viewed from the top side of the component (i.e., contacts facing down).
Tables 8 and 9 list the 80186EB/80188EB pin
names with package location for the 80-pin Shrink
Quad Flat Pack (SQFP) component. Figure 7 depicts
the complete 80C186EB/80C188EB (SQFP package) as viewed from the top side of the component
(i.e., contacts facing down).
Table 4. PLCC Pin Names with Package Location
Address/Data Bus
Bus Control
Processor Control
Name
Location
Name
Location
Location
Name
Location
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8 (A8)
AD9 (A9)
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13 (A13)
AD14 (A14)
AD15 (A15)
A16
A17
A18
A19/ONCE
61
66
68
70
72
74
76
78
62
67
69
71
73
75
77
79
80
81
82
83
ALE
BHE (RFSH)
6
7
RESIN
RESOUT
37
38
S0
S1
S2
10
9
8
CLKIN
OSCOUT
CLKOUT
41
40
44
RD
WR
4
5
READY
18
DEN
DT/R
11
16
UCS
LCS
P1.0/GCS0
P1.1/GCS1
P1.2/GCS2
P1.3/GCS3
P1.4/GCS4
P1.5/GCS5
P1.6/GCS6
P1.7/GCS7
30
29
28
27
26
25
24
21
20
19
LOCK
15
HOLD
HLDA
13
12
T0OUT
T0IN
T1OUT
T1IN
45
46
47
48
RXD0
TXD0
P2.5/BCLK0
CTS0
53
52
54
51
P2.0/RXD1
P2.1/TXD1
P2.2/BCLK1
P2.3/SINT1
P2.4/CTS1
57
58
59
55
56
P2.6
P2.7
50
49
Power
Name
Location
VSS
2, 22, 43
63, 65, 84
VCC
1, 23
42, 64
Name
I/O
TEST/BUSY
14
NCS (N.C.)
PEREQ (N.C.)
ERROR (N.C.)
60
39
3
PDTMR
36
NMI
INT0
INT1
INT2/INTA0
INT3/INTA1
INT4
17
31
32
33
34
35
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
14
14
80C186EB/80C188EB, 80L186EB/80L188EB
Table 5. PLCC Package Locations with Pin Name
Location
Name
Location
Name
Location
Name
Location
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VCC
VSS
ERROR (N.C.)
RD
WR
ALE
BHE (RFSH)
S2
S1
S0
DEN
HLDA
HOLD
TEST/BUSY
LOCK
DT/R
NMI
READY
P1.7/GCS7
P1.6/GCS6
P1.5/GCS5
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VSS
VCC
P1.4/GCS4
P1.3/GCS3
P1.2/GCS2
P1.1/GCS1
P1.0/GCS0
LCS
UCS
INT0
INT1
INT2/INTA0
INT3/INTA1
INT4
PDTMR
RESIN
RESOUT
PEREQ (N.C.)
OSCOUT
CLKIN
VCC
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
VSS
CLKOUT
T0OUT
T0IN
T1OUT
T1IN
P2.7
P2.6
CTS0
TXD0
RXD0
P2.5/BCLK0
P2.3/SINT1
P2.4/CTS1
P2.0/RXD1
P2.1/TXD1
P2.2/BCLK1
NCS (N.C.)
AD0
AD8 (A8)
VSS
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VCC
VSS
AD1
AD9 (A9)
AD2
AD10 (A10)
AD3
AD11 (A11)
AD4
AD12 (A12)
AD5
AD13 (A13)
AD6
AD14 (A14)
AD7
AD15 (A15)
A16
A17
A18
A19/ONCE
VSS
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
15
15
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 5
NOTE:
This is the FPO number location (indicated by X’s).
Pin names in parentheses apply to the 80C188EB/80L188EB.
Figure 4. 84-Pin Plastic Leaded Chip Carrier Pinout Diagram
16
16
80C186EB/80C188EB, 80L186EB/80L188EB
Table 6. QFP Pin Name with Package Location
Address/Data Bus
Bus Control
Processor Control
I/O
Name
Location
Name
Location
Name
Location
Name
Location
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8 (A8)
AD9 (A9)
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13 (A13)
AD14 (A14)
AD15 (A15)
A16
A17
A18
A19/ONCE
10
15
17
19
21
23
25
27
11
16
18
20
22
24
26
28
29
30
31
32
ALE
BHE (RFSH)
38
39
S0
S1
S2
42
41
40
RD
WR
READY
36
37
49
DEN
43
LOCK
47
HOLD
HLDA
45
44
RESIN
RESOUT
CLKIN
OSCOUT
CLKOUT
TEST
PDTMR
NMI
INT0
INT1
INT2/INTA0
INT3/INTA1
INT4
68
69
71
70
74
46
67
48
62
63
64
65
66
UCS
LCS
P1.0/GCS0
P1.1/GCS1
P1.2/GCS2
P1.3/GCS3
P1.4/GCS4
P1.5/GCS5
P1.6/GCS6
P1.7/GCS7
T0OUT
T0IN
T1OUT
T1IN
RXD0
TXD0
P2.5/BCLK0
CTS0
P2.0/RXD1
P2.1/TXD1
P2.2/BCLK1
P2.3/SINT1
P2.4/CTS1
61
60
59
58
57
56
55
52
51
50
75
76
77
78
3
2
4
1
7
8
9
5
6
P2.6
P2.7
80
79
Power
Name
Location
VSS
12, 14, 33
35, 53, 73
13, 34
54, 72
VCC
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
17
17
80C186EB/80C188EB, 80L186EB/80L188EB
Table 7. QFP Package Location with Pin Names
Location
Name
Location
Name
Location
Name
Location
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CTS0
TXD0
RXD0
P2.5/BCLK0
P2.3/SINT1
P2.4/CTS1
P2.0/RXD1
P2.1/TXD1
P2.2/BCLK1
AD0
AD8 (A8)
VSS
VCC
VSS
AD1
AD9 (A9)
AD2
AD10 (A10)
AD3
AD11 (A11)
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AD4
AD12 (A12)
AD5
AD13 (A13)
AD6
AD14 (A14)
AD7
AD15 (A15)
A16
A17
A18
A19/ONCE
VSS
VCC
VSS
RD
WR
ALE
BHE (RFSH)
S2
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
S1
S0
DEN
HLDA
HOLD
TEST
LOCK
NMI
READY
P1.7/GCS7
P1.6/GCS6
P1.5/GCS5
VSS
VCC
P1.4/GCS4
P1.3/GCS3
P1.2/GCS2
P1.1/GCS1
P1.0/GCS0
LCS
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
UCS
INT0
INT1
INT2/INTA0
INT3/INTA1
INT4
PDTMR
RESIN
RESOUT
OSCOUT
CLKIN
VCC
VSS
CLKOUT
T0OUT
T0IN
T1OUT
T1IN
P2.7
P2.6
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
18
18
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 6
NOTE:
This is the FPO number location (indicated by X’s).
Pin names in parentheses apply to the 80C188EB/80L188EB.
Figure 5. Quad Flat Pack Pinout Diagram
19
19
80C186EB/80C188EB, 80L186EB/80L188EB
Table 8. SQFP Pin Functions with Location
AD Bus
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8 (A8)
AD9 (A9)
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13 (A13)
AD14 (A14)
AD15 (A15)
A16
A17
A18
A19/ONCE
Bus Control
47
52
54
56
58
60
62
64
48
53
55
57
59
61
63
65
66
67
68
69
ALE
BHEÝ (RFSHÝ)
S0Ý
S1Ý
S2Ý
RDÝ
WRÝ
READY
DENÝ
LOCKÝ
HOLD
HLDA
Processor Control
75
76
79
78
77
73
74
6
80
4
2
1
RESINÝ
RESOUT
CLKIN
OSCOUT
CLKOUT
TESTÝ/BUSY
NMI
INT0
INT1
INT2/INTA0Ý
INT3/INTA1Ý
INT4
PDTMR
25
26
28
27
31
3
5
19
20
21
22
23
24
Power and Ground
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
11
29
50
71
10
30
49
51
70
72
I/O
UCSÝ
LCSÝ
18
17
P1.0/GCS0Ý
P1.1/GCS1Ý
P1.2/GCS2Ý
P1.3/GCS3Ý
P1.4/GCS4Ý
P1.5/GCS5Ý
P1.6/GCS6Ý
P1.7/GCS7Ý
16
15
14
13
12
9
8
7
P2.0/RXD1
P2.1/TXD1
P2.2/BCLK1
P2.3/SINT1
P2.4/CTS1Ý
P2.5/BCLK0
P2.6
P2.7
44
45
46
42
43
41
37
36
CTS0Ý
TXD0
RXD0
38
39
40
T0IN
T1IN
T0OUT
T1OUT
33
35
32
34
Table 9. SQFP Pin Locations with Pin Names
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
HLDA
HOLD
TESTÝ
LOCKÝ
NMI
READY
P1.7/GCS7Ý
P1.6/GCS6Ý
P1.5/GCS5Ý
VSS
VCC
P1.4/GCS4Ý
P1.3/GCS3Ý
P1.2/GCS2Ý
P1.1/GCS1Ý
P1.0/GCS0Ý
LCSÝ
UCSÝ
INT0
INT1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
INT1/INTA0Ý
INT3/INTA1Ý
INT4
PDTMR
RESINÝ
RESOUT
OSCOUT
CLKIN
VCC
VSS
CLKOUT
T0OUT
T0IN
T1OUT
T1IN
P2.7
P2.6
CTS0Ý
TXD0
RXD0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P2.5/BCLK0
P2.3/SINT1
P2.4/CTS1Ý
P2.0/RXD1
P2.1/TXD1
P2.2/BCLK1
AD0
AD8 (A8)
VSS
VCC
VSS
AD1
AD9 (A9)
AD2
AD10 (A10)
AD3
AD11 (A11)
AD4
AD12 (A12)
AD5
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
AD13 (A13)
AD6
AD14 (A14)
AD7
AD15 (A15)
A16
A17
A18
A19/ONCE
VSS
VCC
VSS
RDÝ
WRÝ
ALE
BHEÝ (RFSHÝ)
S2Ý
S1Ý
S0Ý
DENÝ
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
20
20
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 7
NOTE:
XXXXXXXXC indicates Intel FPO number.
Pin names in parentheses apply to the 80C188EB/80L188EB.
Figure 6. SQFP Package
21
21
80C186EB/80C188EB, 80L186EB/80L188EB
TA (the ambient temperature) can be calculated
from iCA (thermal resistance from the case to ambient) with the following equation:
PACKAGE THERMAL
SPECIFICATIONS
The 80C186EB/80L186EB is specified for operation
when TC (the case temperature) is within the range
of b 40§ C to a 100§ C (PLCC package) or b 40§ C to
a 114§ C (QFP package). TC may be measured in
any environment to determine whether the processor is within the specified operating range. The case
temperature must be measured at the center of the
top surface.
TA e TC b P*iCA
Typical values for iCA at various airflows are given
in Table 10. P (the maximum power consumption,
specified in watts) is calculated by using the maximum ICC as tabulated in the DC specifications and
VCC of 5.5V.
Table 10. Thermal Resistance (iCA) at Various Airflows (in § C/Watt)
Airflow Linear ft/min (m/sec)
0 200
400
600
800 1000
(0) (1.01) (2.03) (3.04) (4.06) (5.07)
iCA (PLCC)
30
24
21
19
17
16.5
iCA (QFP)
58
47
43
40
38
36
iCA (SQFP)
70
TBD
TBD
TBD
TBD
TBD
22
22
80C186EB/80C188EB, 80L186EB/80L188EB
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C
Case Temp under Bias ÀÀÀÀÀÀÀÀÀ b 65§ C to a 120§ C
Supply Voltage
with Respect to VSSÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to a 6.5V
Voltage on other Pins
with Respect to VSS ÀÀÀÀÀÀ b 0.5V to VCC a 0.5V
Recommended Connections
Power and ground connections must be made to
multiple VCC and VSS pins. Every 80C186EB-based
circuit board should include separate power (VCC)
and ground (VSS) planes. Every VCC pin must be
connected to the power plane, and every VSS pin
must be connected to the ground plane. Pins identified as ‘‘NC’’ must not be connected in the system.
Liberal decoupling capacitance should be placed
near the processor. The processor can cause transient power surges when its output buffers transition, particularly when connected to large capacitive loads.
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Low inductance capacitors and interconnects are
recommended for best high frequency electrical performance. Inductance is reduced by placing the decoupling capacitors as close as possible to the processor VCC and VSS package pins.
Always connect any unused input to an appropriate
signal level. In particular, unused interrupt inputs
(INT0:4) should be connected to VCC through a pullup resistor (in the range of 50 KX). Leave any unused output pin or any NC pin unconnected.
23
23
80C186EB/80C188EB, 80L186EB/80L188EB
DC SPECIFICATIONS (80C186EB/80C188EB)
Symbol
Parameter
Min
Max
Units
Notes
VCC
Supply Voltage
4.5
5.5
V
VIL
Input Low Voltage
b 0.5
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC a 0.5
V
VOL
Output Low Voltage
0.45
V
IOL e 3 mA (Min)
VOH
Output High Voltage
VCC b 0.5
V
IOH e b 2 mA (MIn)
VHYR
Input Hysterisis on RESIN
0.50
V
ILI1
Input Leakage Current for Pins:
AD15:0 (AD7:0), READY, HOLD,
RESIN, CLKIN, TEST, NMI, INT4:0,
T0IN, T1IN, RXD0, BCLK0, CTS0,
RXD1, BCLK1, CTS1, P2.6, P2.7
ILI2
Input Leakage Current for Pins:
ERROR, PEREQ
ILI3
Input Leakage Current for Pins:
A19/ONCE, A18:16, LOCK
ILO
ICC
IID
IPD
g 15
mA
0V s VIN s VCC
g 0.275
g7
mA
0V s VIN k VCC
b 0.275
b 5.0
mA
VIN e 0.7 VCC (Note 1)
Output Leakage Current
g 15
mA
0.45 s VOUT s VCC
(Note 2)
Supply Current Cold (RESET)
80C186EB25
115
mA
(Notes 3, 7)
80C186EB20
108
mA
(Note 3)
80C186EB13
73
mA
(Note 3)
Supply Current Idle
80C186EB25
91
mA
(Notes 4, 7)
80C186EB20
76
mA
(Note 4)
80C186EB13
48
mA
(Note 4)
100
mA
(Notes 5, 7)
100
mA
(Note 5)
Supply Current Powerdown
80C186EB25
80C186EB20
100
mA
(Note 5)
CIN
Input Pin Capacitance
80C186EB13
0
15
pF
TF e 1 MHz
COUT
Output Pin Capacitance
0
15
pF
TF e 1 MHz (Note 6)
NOTES:
1. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more
current than specified (on any of these pins) may invoke a factory test mode.
2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.
3. Measured with the device in RESET and at worst case frequency, VCC, and temperature with ALL outputs loaded as
specified in AC Test Conditions, and all floating outputs driven to VCC or GND.
4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, VCC, and temperature with ALL
outputs loaded as specified in AC Test Conditions, and all floating outputs driven to VCC or GND.
5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, VCC, and temperature with
ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to VCC or GND.
6. Output Capacitance is the capacitive load of a floating output pin.
7. Operating temperature for 25 MHz is 0§ C to 70§ C, VCC e 5.0 g 10%.
24
24
80C186EB/80C188EB, 80L186EB/80L188EB
DC SPECIFICATIONS (80L186EB16)
Symbol
Parameter
(operating temperature, 0§ C to 70§ C)
Min
Max
Units
Notes
VCC
Supply Voltage
3.0
5.5
V
VIL
Input Low Voltage
b 0.5
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC a 0.5
V
VOL
Output Low Voltage
0.45
V
IOL e 1.6 mA (Min) (Note 1)
VOH
Output High Voltage
VCC b 0.5
V
IOH e b 1 mA (Min) (Note 1)
VHYR
Input Hysterisis on RESIN
0.50
V
ILI1
Input Leakage Current for pins:
AD15:0 (AD7:0), READY, HOLD,
RESIN, CLKIN, TEST, NMI,
INT4:0, T0IN, T1IN, RXD0,
BCLK0, CTS0, RXD1, BCLK1,
CTS1, SINT1, P2.6, P2.7
ILI2
Input Leakage Current for Pins:
A19/ONCE, A18:16, LOCK
ILO
Output Leakage Current
ICC3
g 15
mA
0V s VIN s VCC
b2
mA
VIN e 0.7 VCC (Note 2)
g 15
mA
0.45 s VOUT s VCC (Note 3)
Supply Current (RESET, 3.3V)
80L186EB16
54
mA
(Note 4)
IID3
Supply Current Idle (3.3V)
80L186EB16
38
mA
(Note 5)
IPD3
Supply Current Powerdown (3.3V)
80L186EB16
40
mA
(Note 6)
CIN
Input Pin Capacitance
0
15
pF
TF e 1 MHz
COUT
Output Pin Capacitance
0
15
pF
TF e 1 MHz (Note 7)
b 0.275
NOTES:
1. IOL and IOH measured at VCC e 3.0V.
2. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more
current than specified (on any of these pins) may invoke a factory test mode.
3. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.
4. Measured with the device in RESET and at worst case frequency, VCC, and temperature with ALL outputs loaded as
specified in AC Test Conditions, and all floating outputs driven to VCC or GND.
5. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, VCC, and temperature with ALL
outputs loaded as specified in AC Test Conditions, and all floating outputs driven to VCC or GND.
6. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, VCC, and temperature with
ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to VCC or GND.
7. Output Capacitance is the capacitive load of a floating output pin.
25
25
80C186EB/80C188EB, 80L186EB/80L188EB
DC SPECIFICATIONS (80L186EB13/80L188EB13, 80L186EB8/80L188EB8)
Symbol
Parameter
Min
Max
Units
Notes
VCC
Supply Voltage
2.7
5.5
V
VIL
Input Low Voltage
b 0.5
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC a 0.5
V
VOL
Output Low Voltage
0.45
V
IOL e 1.6 mA (Min) (Note 1)
VOH
Output High Voltage
VCC b 0.5
V
IOH e b 1 mA (Min) (Note 1)
VHYR
Input Hysterisis on RESIN
0.50
V
ILI1
Input Leakage Current for pins:
AD15:0 (AD7:0), READY, HOLD,
RESIN, CLKIN, TEST, NMI,
INT4:0, T0IN, T1IN, RXD0,
BCLK0, CTS0, RXD1, BCLK1,
CTS1, SINT1, P2.6, P2.7
ILI2
Input Leakage Current for Pins:
A19/ONCE, A18:16, LOCK
ILO
Output Leakage Current
ICC5
ICC3
IID5
IID3
IPD5
IPD3
g 15
mA
0V s VIN s VCC
b2
mA
VIN e 0.7 VCC (Note 2)
g 15
mA
0.45 s VOUT s VCC (Note 3)
Supply Current (RESET, 5.5V)
80L186EB13
80L186EB8
73
45
mA
mA
(Note 4)
(Note 4)
Supply Current (RESET, 2.7V)
80L186EB13
80L186EB8
36
22
mA
mA
(Note 4)
(Note 4)
Supply Current Idle (5.5V)
80L186EB13
80L186EB8
48
31
mA
mA
(Note 5)
(Note 5)
Supply Current Idle (2.7V)
80L186EB13
80L186EB8
24
15
mA
mA
(Note 5)
(Note 5)
Supply Current Powerdown (5.5V)
80L186EB13
80L186EB8
100
100
mA
mA
(Note 6)
(Note 6)
Supply Current Powerdown (2.7V)
80L186EB13
80L186EB8
30
30
mA
mA
(Note 6)
(Note 6)
b 0.275
CIN
Input Pin Capacitance
0
15
pF
TF e 1 MHz
COUT
Output Pin Capacitance
0
15
pF
TF e 1 MHz (Note 7)
NOTES:
1. IOL and IOH measured at VCC e 2.7V.
2. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more
current than specified (on any of these pins) may invoke a factory test mode.
3. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.
4. Measured with the device in RESET and at worst case frequency, VCC, and temperature with ALL outputs loaded as
specified in AC Test Conditions, and all floating outputs driven to VCC or GND.
5. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, VCC, and temperature with ALL
outputs loaded as specified in AC Test Conditions, and all floating outputs driven to VCC or GND.
6. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, VCC, and temperature with
ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to VCC or GND.
7. Output Capacitance is the capacitive load of a floating output pin.
26
26
80C186EB/80C188EB, 80L186EB/80L188EB
ICC VERSUS FREQUENCY AND VOLTAGE
PDTMR PIN DELAY CALCULATION
The current (ICC) consumption of the processor is
essentially composed of two components; IPD and
ICCS.
The PDTMR pin provides a delay between the assertion of NMI and the enabling of the internal
clocks when exiting Powerdown. A delay is required
only when using the on-chip oscillator to allow the
crystal or resonator circuit time to stabilize.
IPD is the quiescent current that represents internal
device leakage, and is measured with all inputs or
floating outputs at GND or VCC (no clock applied to
the device). IPD is equal to the Powerdown current
and is typically less than 50 mA.
ICCS is the switching current used to charge and
discharge parasitic device capacitance when changing logic levels. Since ICCS is typically much greater
than IPD, IPD can often be ignored when calculating
ICC.
ICCS is related to the voltage and frequency at which
the device is operating. It is given by the formula:
Power e V c I e V2 c CDEV c f
.
. . I e ICC e ICCS e V c CDEV c f
Where: V e Device operating voltage (VCC)
NOTE:
The PDTMR pin function does not apply when
RESIN is asserted (i.e., a device reset during Powerdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabilized).
To calculate the value of capacitor required to provide a desired delay, use the equation:
440 c t e CPD (5V, 25§ C)
Where: t e desired delay in seconds
CPD e capacitive load on PDTMR in microfarads
EXAMPLE: To get a delay of 300 ms, a capacitor
value of CPD e 440 c (300 c 10b6) e 0.132 mF is
required. Round up to standard (available) capacitive values.
CDEV e Device capacitance
f e Device operating frequency
ICCS e ICC e Device current
Measuring CDEV on a device like the 80C186EB
would be difficult. Instead, CDEV is calculated using
the above formula by measuring ICC at a known VCC
and frequency (see Table 11). Using this CDEV value, ICC can be calculated at any voltage and frequency within the specified operating range.
EXAMPLE: Calculate the typical ICC when operating
at 10 MHz, 4.8V.
NOTE:
The above equation applies to delay times greater
than 10 ms and will compute the TYPICAL capacitance needed to achieve the desired delay. A delay
variance of a 50% or b 25% can occur due to
temperature, voltage, and device process extremes. In general, higher VCC and/or lower temperature will decrease delay time, while lower VCC
and/or higher temperature will increase delay time.
ICC e ICCS e 4.8 c 0.583 c 10 & 28 mA
Table 11. Device Capacitance (CDEV) Values
Parameter
Typ
Max
Units
Notes
CDEV (Device in Reset)
CDEV (Device in Idle)
0.583
1.02
mA/V*MHz
1, 2
0.408
0.682
mA/V*MHz
1, 2
1. Max CDEV is calculated at b40§ C, all floating outputs driven to VCC or GND, and all
outputs loaded to 50 pF (including CLKOUT and OSCOUT).
2. Typical CDEV is calculated at 25§ C with all outputs loaded to 50 pF except CLKOUT and
OSCOUT, which are not loaded.
27
27
80C186EB/80C188EB, 80L186EB/80L188EB
AC SPECIFICATIONS
AC CharacteristicsÐ80C186EB25
Symbol
Parameter
25 MHz
Units
Notes
50
%
%
%
7
7
MHz
ns
ns
ns
ns
ns
1
1
1, 2
1, 2
1, 3
1, 3
(T/2) b 5
(T/2) b 5
1
1
16
2*TC
(T/2) a 5
(T/2) a 5
6
6
ns
ns
ns
ns
ns
ns
1, 4
1
1
1
1, 5
1, 5
3
17
ns
1, 4, 6, 7
Min
Max
0
20
8
8
1
1
0
INPUT CLOCK
TF
TC
TCH
TCL
TCR
TCF
CLKIN Frequency
CLKIN Period
CLKIN High Time
CLKIN Low Time
CLKIN Rise Time
CLKIN Fall Time
OUTPUT CLOCK
TCD
T
TPH
TPL
TPR
TPF
CLKIN to CLKOUT Delay
CLKOUT Period
CLKOUT High Time
CLKOUT Low Time
CLKOUT Rise Time
CLKOUT Fall Time
OUTPUT DELAYS
TCHOV1
ALE, S2:0, DEN, DT/R, BHE (RFSH), LOCK, A19:16
TCHOV2
GCS0:7, LCS, UCS, NCS, RD, WR
3
20
ns
1, 4, 6, 8
TCLOV1
BHE (RFSH), DEN, LOCK, RESOUT, HLDA, T0OUT,
T1OUT, A19:16
3
17
ns
1, 4, 6
TCLOV2
RD, WR, GCS7:0, LCS, UCS, AD15:0 (AD7:0, A15:8),
NCS, INTA1:0, S2:0
3
20
ns
1, 4, 6
TCHOF
RD, WR, BHE (RFSH), DT/R, LOCK, S2:0, A19:16
0
20
ns
1
TCLOF
DEN, AD15:0 (AD7:0, A15:8)
0
20
ns
1
28
28
80C186EB/80C188EB, 80L186EB/80L188EB
AC SPECIFICATIONS
AC CharacteristicsÐ80C186EB25 (Continued)
Symbol
Parameter
25 MHz
Min
Max
Units
Notes
ns
1, 9
SYNCHRONOUS INPUTS
TCHIS
TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0, P2.6, P2.7
10
TCHIH
TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0
3
ns
1, 9
TCLIS
AD15:0 (AD7:0), READY
10
ns
1, 10
TCLIH
READY, AD15:0 (AD7:0)
3
ns
1, 10
TCLIS
HOLD, PEREQ, ERROR
10
ns
1, 9
TCLIH
HOLD, PEREQ, ERROR
3
ns
1, 9
NOTES:
1. See AC Timing Waveforms, for waveforms and definition.
2. Measure at VIH for high time, VIL for low time.
3. Only required to guarantee ICC. Maximum limits are bounded by TC, TCH and TCL.
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.
6. See Figure 14 for rise and fall times.
7. TCHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.
8. TCHOV2 applies to RD and WR only after a HOLD release.
9. Setup and Hold are required to guarantee recognition.
10. Setup and Hold are required for proper operation.
29
29
80C186EB/80C188EB, 80L186EB/80L188EB
AC SPECIFICATIONS
AC CharacteristicsÐ80C186EB20/80C186EB13
Symbol
Parameter
20 MHz
13 MHz
Units
Notes
26
%
%
%
8
8
MHz
ns
ns
ns
ns
ns
1
1
1, 2
1, 2
1, 3
1, 3
(T/2) b 5
(T/2) b 5
1
1
23
2*TC
(T/2) a 5
(T/2) a 5
6
6
ns
ns
ns
ns
ns
ns
1, 4
1
1
1
1, 5
1, 5
Min
Max
Min
Max
0
25
10
10
1
1
40
%
%
%
8
8
0
38.5
12
12
1
1
0
0
(T/2) b 5
(T/2) b 5
1
1
17
2*TC
(T/2) a 5
(T/2) a 5
6
6
INPUT CLOCK
TF
TC
TCH
TCL
TCR
TCF
CLKIN Frequency
CLKIN Period
CLKIN High Time
CLKIN Low Time
CLKIN Rise Time
CLKIN Fall Time
OUTPUT CLOCK
TCD
T
TPH
TPL
TPR
TPF
CLKIN to CLKOUT Delay
CLKOUT Period
CLKOUT High Time
CLKOUT Low Time
CLKOUT Rise Time
CLKOUT Fall Time
OUTPUT DELAYS
TCHOV1
ALE, S2:0, DEN, DT/R,
BHE (RFSH), LOCK,
A19:16
3
22
3
25
ns
1, 4, 6, 7
TCHOV2
GCS0:7, LCS, UCS, NCS,
RD, WR
3
27
3
30
ns
1, 4, 6, 8
TCLOV1
BHE (RFSH), DEN, LOCK,
RESOUT, HLDA, T0OUT,
T1OUT, A19:16
3
22
3
25
ns
1, 4, 6
TCLOV2
RD, WR, GCS7:0, LCS,
UCS, AD15:0 (AD7:0,
A15:8), NCS, INTA1:0, S2:0
3
27
3
30
ns
1, 4, 6
TCHOF
RD, WR, BHE (RFSH),
DT/R, LOCK, S2:0, A19:16
0
25
0
25
ns
1
TCLOF
DEN, AD15:0 (AD7:0,
A15:8)
0
25
0
25
ns
1
30
30
80C186EB/80C188EB, 80L186EB/80L188EB
AC SPECIFICATIONS
AC CharacteristicsÐ80C186EB20/80C186EB13 (Continued)
Symbol
Parameter
20 MHz
Min
Max
13 MHz
Min
Max
Units
Notes
SYNCHRONOUS INPUTS
TCHIS
TEST, NMI, INT4:0, BCLK1:0, T1:0IN,
READY, CTS1:0, P2.6, P2.7
10
10
ns
1, 9
TCHIH
TEST, NMI, INT4:0, BCLK1:0, T1:0IN,
READY, CTS1:0
3
3
ns
1, 9
TCLIS
AD15:0 (AD7:0), READY
10
10
ns
1, 10
TCLIH
READY, AD15:0 (AD7:0)
3
3
ns
1, 10
TCLIS
HOLD, PEREQ, ERROR
10
10
ns
1, 9
TCLIH
HOLD, PEREQ, ERROR
3
3
ns
1, 9
NOTES:
1. See AC Timing Waveforms, for waveforms and definition.
2. Measure at VIH for high time, VIL for low time.
3. Only required to guarantee ICC. Maximum limits are bounded by TC, TCH and TCL.
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.
6. See Figure 14 for rise and fall times.
7. TCHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.
8. TCHOV2 applies to RD and WR only after a HOLD release.
9. Setup and Hold are required to guarantee recognition.
10. Setup and Hold are required for proper operation.
31
31
80C186EB/80C188EB, 80L186EB/80L188EB
AC SPECIFICATIONS
AC CharacteristicsÐ80L186EB16
Symbol
Parameter
16 MHz
Units
Notes
32
%
%
%
8
8
MHz
ns
ns
ns
ns
ns
1
1
1, 2
1, 2
1, 3
1, 3
(T/2) b 5
(T/2) b 5
1
1
30
2*TC
(T/2) a 5
(T/2) a 5
9
9
ns
ns
ns
ns
ns
ns
1, 4
1
1
1
1, 5
1, 5
Min
Max
0
31.25
13
13
1
1
0
INPUT CLOCK
TF
TC
TCH
TCL
TCR
TCF
CLKIN Frequency
CLKIN Period
CLKIN High Time
CLKIN Low Time
CLKIN Rise Time
CLKIN Fall Time
OUTPUT CLOCK
TCD
T
TPH
TPL
TPR
TPF
CLKIN to CLKOUT Delay
CLKOUT Period
CLKOUT High Time
CLKOUT Low Time
CLKOUT Rise Time
CLKOUT Fall Time
OUTPUT DELAYS
TCHOV1
DT/R, LOCK, A19:16, RFSH
3
22
ns
1, 4, 6, 7
TCHOV2
GCS0:7, LCS, UCS, NCS, RD, WR
3
27
ns
1, 4, 6, 8
TCHOV3
BHE, DEN
3
25
ns
1, 4
TCHOV4
ALE
3
30
ns
1, 4
TCHOV5
S2:0
3
33
ns
1, 4
TCLOV1
LOCK, RESOUT, HLDA, T0OUT, T1OUT, A19:16
3
22
ns
1, 4, 6
TCLOV2
RD, WR, GCS7:0, LCS, UCS, NCS, INTA1:0, AD15:0
(AD7:0, A15:8)
3
27
ns
1, 4, 6
TCHOF
RD, WR, BHE (RFSH), DT/R, LOCK, S2:0, A19:16
0
25
ns
1
TCLOF
DEN, AD15:0 (AD7:0, A15:8)
0
25
ns
1
TCLOV3
BHE, DEN
3
25
ns
1, 4, 6
TCLOV5
S2:0
3
33
ns
1, 4, 6
32
32
80C186EB/80C188EB, 80L186EB/80L188EB
AC SPECIFICATIONS
AC CharacteristicsÐ80L186EB16 (Continued)
Symbol
Parameter
16 MHz
Min
Max
Units
Notes
ns
1, 9
SYNCHRONOUS INPUTS
TCHIS
TEST, NMI, INT4:0, BCLK1:0, T1:0IN, READY, CTS1:0, P2.6, P2.7
15
TCHIH
TEST, NMI, INT4:0, T1:0IN, BCLK1:0, READY, CTS1:0
3
ns
1, 9
TCLIS
AD15:0 (AD7:0), READY
15
ns
1, 10
TCLIH
READY, AD15:0 (AD7:0)
3
ns
1, 10
TCLIS
HOLD
15
ns
1, 9
TCLIH
HOLD
3
ns
1, 9
NOTES:
1. See AC Timing Waveforms, for waveforms and definition.
2. Measure at VIH for high time, VIL for low time.
3. Only required to guarantee ICC. Maximum limits are bounded by TC, TCH and TCL.
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.
6. See Figure 14 for rise and fall times.
7. TCHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.
8. TCHOV2 applies to RD and WR only after a HOLD release.
9. Setup and Hold are required to guarantee recognition.
10. Setup and Hold are required for proper operation.
33
33
80C186EB/80C188EB, 80L186EB/80L188EB
AC SPECIFICATIONS
AC CharacteristicsÐ80L186EB13/80L186EB8
Symbol
13 MHz
Parameter
8 MHz
Units
Notes
16
%
%
%
8
8
MHz
ns
ns
ns
ns
ns
1
1
1, 2
1, 2
1, 3
1, 3
(T/2) b 5
(T/2) b 5
1
1
50
2*TC
(T/2) a 5
(T/2) a 5
15
15
ns
ns
ns
ns
ns
ns
1, 4
1
1
1
1, 5
1, 5
Min
Max
Min
Max
0
38.5
15
15
1
1
26
%
%
%
8
8
0
62.5
15
15
1
1
0
0
(T/2) b 5
(T/2) b 5
1
1
10
2*TC
(T/2) a 5
(T/2) a 5
10
10
INPUT CLOCK
Tr
TC
TCH
TCL
TCR
TCF
CLKIN Frequency
CLKIN Period
CLKIN High Time
CLKIN Low Time
CLKIN Rise Time
CLKIN Fall Time
OUTPUT CLOCK
TCD
T
TPH
TPL
TPR
TPF
CLKIN to CLKOUT Delay
CLKOUT Period
CLKOUT High Time
CLKOUT Low Time
CLKOUT Rise Time
CLKOUT Fall Time
OUTPUT DELAYS
TCHOV1
ALE, S2-0, DEN, DT/R,
BHE (RFSH), LOCK,
A19:16
3
25
3
30
ns
1, 4, 6, 7
TCHOV2
GCS0:7, LCS, UCS,
NCS, RD, WR
3
30
3
35
ns
1, 4,6, 8
TCLOV1
BHE (RFSH), DEN,
LOCK, RESOUT, HLDA,
T0OUT, T1OUT, A19:16
3
25
3
30
ns
1, 4, 6
TCLOV2
S2:0, RD, WR, GCS7:0,
LCS, UCS, NCS,
INTA1:0, AD15:0 (AD7:0,
A15:8)
3
30
3
35
ns
1, 4, 6
TCHOF
RD, WR, BHE (RFSH),
DT/R, LOCK, S2:0,
A19:16
0
30
0
30
ns
1
TCLOF
DEN, AD15:0
(AD7:0, A15:8)
0
30
0
35
ns
1
34
34
80C186EB/80C188EB, 80L186EB/80L188EB
AC SPECIFICATIONS
AC CharacteristicsÐ80L186EB13/80L186EB8 (Continued)
Symbol
13 MHz
Parameter
Min
Max
8 MHz
Min
Units
Notes
Max
SYNCHRONOUS INPUTS
TCHIS
TEST, NMI, INT4:0,
BCLK1:0, T1:0IN, READY
CTS1:0, P2.6, P2.7
20
25
ns
1, 9
TCHIH
TEST, NMI, INT4:0, T1:0IN,
BCLK1:0, READY, CTS1:0
3
3
ns
1, 9
TCLIS
AD15:0 (AD7:0), READY
20
25
ns
1, 10
TCLIH
READY, AD15:0 (AD7:0)
3
3
ns
1, 10
TCLIS
HOLD
20
25
ns
1, 9
TCLIH
HOLD
3
3
ns
1, 9
NOTES:
1. See AC Timing Waveforms, for waveforms and definition.
2. Measured at VIH for high time, VIL for low time.
3. Only required to guarantee ICC. Maximum limits are bounded by TC, TCH and TCL.
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.
6. See Figure 14 for rise and fall times.
7. TCHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.
8. TCHOV2 applies to RD and WR only after a HOLD release.
9. Setup and Hold are required to guarantee recognition.
10. Setup and Hold are required for proper operation.
35
35
80C186EB/80C188EB, 80L186EB/80L188EB
AC SPECIFICATIONS (Continued)
Relative Timings (80C186EB25, 20, 13/80L186EB16, 13, 8)
Symbol
Parameter
Min
Max
Units
Notes
RELATIVE TIMINGS
TLHLL
ALE Rising to ALE Falling
T b 15
ns
TAVLL
Address Valid to ALE Falling
(/2T b 10
ns
TPLLL
Chip Selects Valid to ALE Falling
(/2T b 10
ns
TLLAX
Address Hold from ALE Falling
(/2T b 10
ns
TLLWL
ALE Falling to WR Falling
(/2T b 15
ns
1
TLLRL
ALE Falling to RD Falling
(/2T b 15
ns
1
TWHLH
WR Rising to ALE Rising
(/2T b 10
ns
1
TAFRL
Address Float to RD Falling
0
ns
TRLRH
RD Falling to RD Rising
(2*T) b 5
ns
2
TWLWH
WR Falling to WR Rising
(2*T) b 5
ns
2
ns
TRHAV
RD Rising to Address Active
T b 15
TWHDX
Output Data Hold after WR Rising
T b 15
ns
1
TWHPH
WR Rising to Chip Select Rising
(/2T b 10
ns
1
TRHPH
RD Rising to Chip Select Rising
(/2T b 10
ns
1
TPHPL
CS Inactive to CS Active
(/2T b 10
ns
1
TOVRH
ONCE Active to RESIN Rising
T
ns
3
TRHOX
ONCE Hold from RESIN Rising
T
ns
3
NOTES:
1. Assumes equal loading on both pins.
2. Can be extended using wait states.
3. Not tested
36
36
80C186EB/80C188EB, 80L186EB/80L188EB
AC SPECIFICATIONS (Continued)
Serial Port Mode 0 Timings (80C186EB25, 20, 13/80L186EB16, 13, 8)
Symbol
Parameter
Min
TXLXL
TXD Clock Period
T (n a 1)
TXLXH
TXD Clock Low to Clock High (n l 1)
2T b 35
TXLXH
TXD Clock Low to Clock High (n e 1)
T b 35
TXHXL
TXD Clock High to Clock Low (n l 1)
TXHXL
TXD Clock High to Clock Low (n e 1)
TQVXH
RXD Output Data Setup to TXD Clock High (n l 1)
TQVXH
RXD Output Data Setup to TXD Clock High (n e 1)
Max
Unit Notes
ns
1, 2
2T a 35
ns
1
T a 35
ns
1
ns
1, 2
ns
1
(n b 1) T b 35
ns
1, 2
T b 35
ns
1
TXHQX
RXD Output Data Hold after TXD Clock High (n l 1)
2T b 35
ns
1
TXHQX
RXD Output Data Hold after TXD Clock High (n e 1)
T b 35
ns
1
TXHQZ
RXD Output Data Float after Last TXD Clock High
TDVXH
RXD Input Data Setup to TXD Clock High
TXHDX
RXD Input Data Hold after TXD Clock High
(n b 1) T b 35 (n b 1) T a 35
T b 35
T a 35
T a 20
ns
1
T a 20
ns
1
0
ns
1
NOTES:
1. See Figure 12 for waveforms.
2. n is the value of the BxCMP register ignoring the ICLK Bit (i.e., ICLK e 0).
37
37
80C186EB/80C188EB, 80L186EB/80L188EB
AC TEST CONDITIONS
The AC specifications are tested with the 50 pF load
shown in Figure 7. See the Derating Curves section
to see how timings vary with load capacitance.
Specifications are measured at the VCC/2 crossing
point, unless otherwise specified. See AC Timing
Waveforms, for AC specification definitions, test
pins, and illustrations.
272433 – 8
CL e 50 pF for all signals.
Figure 7. AC Test Load
AC TIMING WAVEFORMS
272433 – 9
Figure 8. Input and Output Clock Waveform
38
38
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 10
NOTE:
20% VCC k Float k 80% VCC
Figure 9. Output Delay and Float Waveform
272433 – 11
Figure 10. Input Setup and Hold
39
39
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 12
NOTE:
Pin names in parentheses apply to 80C188EB/80L188EB
Figure 11. Relative Signal Waveform
272433 – 13
Figure 12. Serial Port Mode 0 Waveform
40
40
80C186EB/80C188EB, 80L186EB/80L188EB
DERATING CURVES
TYPICAL OUTPUT DELAY VARIATIONS VERSUS LOAD CAPACITANCE
272433 – 14
Figure 13
TYPICAL RISE AND FALL VARIATIONS VERSUS LOAD CAPACITANCE
272433 – 15
Figure 14
41
41
80C186EB/80C188EB, 80L186EB/80L188EB
RESET
The processor will perform a reset operation any
time the RESIN pin active. The RESIN pin is actually
synchronized before it is presented internally, which
means that the clock must be operating before a
reset can take effect. From a power-on state, RESIN
must be held active (low) in order to guarantee correct initialization of the processor. Failure to provide RESIN while the device is powering up will
result in unspecified operation of the device.
Figure 14 shows the correct reset sequence when
first applying power to the processor. An external
clock connected to CLKIN must not exceed the VCC
threshold being applied to the processor. This is normally not a problem if the clock driver is supplied
with the same VCC that supplies the processor.
When attaching a crystal to the device, RESIN must
remain active until both VCC and CLKOUT are stable
(the length of time is application specific and depends on the startup characteristics of the crystal
circuit). The RESIN pin is designed to operate correctly using an RC reset circuit, but the designer
must ensure that the ramp time for VCC is not so
long that RESIN is never really sampled at a logic
low level when VCC reaches minimum operating
conditions.
Figure 16 shows the timing sequence when RESIN
is applied after VCC is stable and the device has
been operating. Note that a reset will terminate all
activity and return the processor to a known operating state. Any bus operation that is in progress at the
time RESIN is asserted will terminate immediately
(note that most control signals will be driven to their
inactive state first before floating).
While RESIN is active, bus signals LOCK, A19/
ONCE, and A18:16 are configured as inputs and
weakly held high by internal pullup transistors. Only
19/ONCE can be overdriven to a low and is used to
enable ONCE Mode. Forcing LOCK or A18:16 low at
any time while RESIN is low is prohibited and will
cause unspecified device operation.
42
42
NOTE:
CLKOUT synchronization occurs on the rising edge of RESIN. If RESIN is sampled high while CLKOUT is high (solid line), then CLKOUT will remain
low for two CLKIN periods. If RESIN is sampled high while CLKOUT is low (dashed line), then CLKOUT will not be affected.
Pin names in parentheses apply to 80C188EB/80L188EB
272433– 16
80C186EB/80C188EB, 80L186EB/80L188EB
Figure 15. Cold Reset Waveforms
43
43
NOTE:
CLKOUT synchronization occurs on the rising edge of RESIN. If RESIN is sampled high while CLKOUT is high (solid line), then CLKOUT will remain
low for two CLKIN periods. If RESIN is sampled high while CLKOUT is low (dashed line), then CLKOUT will not be affected.
Pin names in parentheses apply to 80C188EB/80L188EB
272433– 17
80C186EB/80C188EB, 80L186EB/80L188EB
Figure 16. Warm Reset Waveforms
44
44
80C186EB/80C188EB, 80L186EB/80L188EB
BUS CYCLE WAVEFORMS
Figures 17 through 23 present the various bus cycles that are generated by the processor. What is
shown in the figure is the relationship of the various
bus signals to CLKOUT. These figures along with
the information present in AC Specifications allow
the user to determine all the critical timing analysis
needed for a given application.
272433 – 18
NOTE:
Pin names in parentheses apply to 80C188EB/80L188EB
Figure 17. Read, Fetch, and Refresh Cycle Waveforms
45
45
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 19
NOTE:
Pin names in parentheses apply to 80C188EB/80L188EB
Figure 18. Write Cycle Waveforms
46
46
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 20
NOTE:
The address driven is typically the location of the next instruction prefetch. Under a majority of instruction sequences the
AD15:0 (AD7:0) bus will float, while the A19:16 (A19:8) bus remains driven and all bus control signals are driven to their
inactive state.
Pin names in parentheses apply to 80C188EB/80L188EB
Figure 19. Halt Cycle Waveforms
47
47
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 21
NOTE:
Pin names in parentheses apply to 80C188EB/80L188EB
Figure 20. Interrupt Acknowledge Cycle Waveform
48
48
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 22
NOTE:
Pin names in parentheses apply to 80C188EB/80L188EB
Figure 21. HOLD/HLDA Waveforms
49
49
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 23
NOTES:
1. READY must be low by either edge to cause a wait state.
2. Lighter lines indicate READ cycles, darker lines indicate WRITE cycles.
Pin names in parentheses apply to 80C188EB/80L188EB
Figure 22. Refresh during Hold Acknowledge
50
50
80C186EB/80C188EB, 80L186EB/80L188EB
272433 – 24
NOTES:
1. READY must be low by either edge to cause a wait state.
2. Lighter lines indicate READ cycles, darker lines indicate WRITE cycles.
Pin names in parentheses apply to 80C188EB/80L188EB
Figure 23. Ready Waveforms
51
51
80C186EB/80C188EB, 80L186EB/80L188EB
EXECUTION TIMINGS
A determination of program execution timing must
consider the bus cycles necessary to prefetch instructions as well as the number of execution unit
cycles necessary to execute instructions. The following instruction timings represent the minimum
execution time in clock cycles for each instruction.
The timings given are based on the following assumptions:
# The opcode, along with any data or displacement
required for execution of a particular instruction,
has been prefetched and resides in the queue at
the time it is needed.
# No wait states or bus HOLDs occur.
# All word-data is located on even-address boundaries (80C186EB only).
All jumps and calls include the time required to fetch
the opcode of the next instruction at the destination
address.
All instructions which involve memory accesses can
require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU) and execution unit.
With a 16-bit BIU, the 80C186EB has sufficient bus
performance to ensure that an adequate number of
prefetched bytes will reside in the queue (6 bytes)
most of the time. Therefore, actual program execution time will not be substantially greater than that
derived from adding the instruction timings shown.
The 80C188EB 8-bit BIU is limited in its performance
relative to the execution unit. A sufficient number of
prefetched bytes may not reside in the prefetch
queue (4 bytes) much of the time. Therefore, actual
program execution time will be substantially greater
than that derived from adding the instruction timings
shown.
52
52
80C186EB/80C188EB, 80L186EB/80L188EB
INSTRUCTION SET SUMMARY
Function
Format
80C186EB
Clock
Cycles
80C188EB
Clock
Cycles
2/12
2/12*
Comments
DATA TRANSFER
MOV e Move:
Register to Register/Memory
1000100w
mod reg r/m
Register/memory to register
1000101w
mod reg r/m
Immediate to register/memory
1100011w
mod 000 r/m
data
Immediate to register
1 0 1 1 w reg
data
Memory to accumulator
1010000w
Accumulator to memory
Register/memory to segment register
Segment register to register/memory
2/9
2/9*
12/13
12/13
8/16-bit
data if w e 1
3/4
3/4
8/16-bit
addr-low
addr-high
8
8*
1010001w
addr-low
addr-high
9
9*
10001110
mod 0 reg r/m
2/9
2/13
10001100
mod 0 reg r/m
2/11
2/15
Memory
11111111
mod 1 1 0 r/m
16
20
Register
0 1 0 1 0 reg
10
14
Segment register
0 0 0 reg 1 1 0
9
13
Immediate
011010s0
10
14
PUSHA e Push All
01100000
36
68
20
24
10
14
8
12
51
83
4/17
4/17*
3
3
10
10*
8
8*
data if w e 1
PUSH e Push:
data
data if s e 0
POP e Pop:
Memory
10001111
Register
0 1 0 1 1 reg
Segment register
0 0 0 reg 1 1 1
POPA e Pop All
01100001
mod 0 0 0 r/m
(reg i 01)
XCHG e Exchange:
Register/memory with register
1000011w
Register with accumulator
1 0 0 1 0 reg
mod reg r/m
IN e Input from:
Fixed port
1110010w
Variable port
1110110w
port
OUT e Output to:
Fixed port
1110011w
Variable port
1110111w
XLAT e Translate byte to AL
11010111
LEA e Load EA to register
10001101
port
mod reg r/m
9
9*
7
7*
11
15
6
6
18
26
18
26
LDS e Load pointer to DS
11000101
mod reg r/m
(mod i 11)
LES e Load pointer to ES
11000100
mod reg r/m
(mod i 11)
LAHF e Load AH with flags
10011111
2
2
SAHF e Store AH into flags
10011110
3
3
PUSHF e Push flags
10011100
9
13
POPF e Pop flags
10011101
8
12
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
53
53
80C186EB/80C188EB, 80L186EB/80L188EB
INSTRUCTION SET SUMMARY (Continued)
Function
Format
80C186EB
Clock
Cycles
80C188EB
Clock
Cycles
Comments
DATA TRANSFER (Continued)
SEGMENT e Segment Override:
CS
00101110
2
2
SS
00110110
2
2
DS
00111110
2
2
ES
00100110
2
2
3/10
3/10*
4/16
4/16*
3/4
3/4
3/10
3/10*
4/16
4/16*
3/4
3/4
3/15
3/15*
3
3
3/10
3/10*
4/16
4/16*
3/4
3/4
3/10
3/10*
4/16
4/16*
3/4
3/4*
3/15
3/15*
3
3
ARITHMETIC
ADD e Add:
Reg/memory with register to either
000000dw
mod reg r/m
Immediate to register/memory
100000sw
mod 0 0 0 r/m
data
Immediate to accumulator
0000010w
data
data if w e 1
data if s w e 01
8/16-bit
ADC e Add with carry:
Reg/memory with register to either
000100dw
mod reg r/m
Immediate to register/memory
100000sw
mod 0 1 0 r/m
data
0001010w
data
data if w e 1
Register/memory
1111111w
mod 0 0 0 r/m
Register
0 1 0 0 0 reg
Immediate to accumulator
data if s w e 01
8/16-bit
INC e Increment:
SUB e Subtract:
Reg/memory and register to either
001010dw
mod reg r/m
Immediate from register/memory
100000sw
mod 1 0 1 r/m
data
Immediate from accumulator
0010110w
data
data if w e 1
data if s w e 01
8/16-bit
SBB e Subtract with borrow:
Reg/memory and register to either
000110dw
mod reg r/m
Immediate from register/memory
100000sw
mod 0 1 1 r/m
data
Immediate from accumulator
0001110w
data
data if w e 1
Register/memory
1111111w
mod 0 0 1 r/m
Register
0 1 0 0 1 reg
data if s w e 01
8/16-bit
DEC e Decrement
CMP e Compare:
Register/memory with register
0011101w
mod reg r/m
3/10
3/10*
Register with register/memory
0011100w
mod reg r/m
3/10
3/10*
Immediate with register/memory
100000sw
mod 1 1 1 r/m
data
3/10
3/10*
Immediate with accumulator
0011110w
data
data if w e 1
NEG e Change sign register/memory
1111011w
mod 0 1 1 r/m
AAA e ASCII adjust for add
DAA e Decimal adjust for add
data if s w e 01
3/4
3/4
3/10
3/10*
00110111
8
8
00100111
4
4
AAS e ASCII adjust for subtract
00111111
7
7
DAS e Decimal adjust for subtract
00101111
4
4
MUL e Multiply (unsigned):
1111011w
26–28
35–37
32–34
41–43
26–28
35–37
32–34
41–43*
8/16-bit
mod 100 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
54
54
80C186EB/80C188EB, 80L186EB/80L188EB
INSTRUCTION SET SUMMARY (Continued)
Function
Format
80C186EB
Clock
Cycles
80C188EB
Clock
Cycles
25–28
34–37
31–34
40–43
25–28
34–37
31–34
40–43*
22–25/
29–32
22–25/
29–32
29
38
35
44
29
38
35
44*
44–52
53–61
50–58
59–67
44–52
53–61
50–58
59–67*
Comments
ARITHMETIC (Continued)
IMUL e Integer multiply (signed):
1111011w
mod 1 0 1 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
IMUL e Integer Immediate multiply
(signed)
011010s1
mod reg r/m
DIV e Divide (unsigned):
1111011w
mod 1 1 0 r/m
data
data if s e 0
Register-Byte
Register-Word
Memory-Byte
Memory-Word
IDIV e Integer divide (signed):
1111011w
mod 1 1 1 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
AAM e ASCII adjust for multiply
11010100
00001010
19
19
AAD e ASCII adjust for divide
11010101
00001010
15
15
CBW e Convert byte to word
10011000
2
2
CWD e Convert word to double word
10011001
4
4
2/15
2/15
LOGIC
Shift/Rotate Instructions:
Register/Memory by 1
1101000w
mod TTT r/m
Register/Memory by CL
1101001w
mod TTT r/m
Register/Memory by Count
1100000w
mod TTT r/m
5 a n/17 a n 5 a n/17 a n
count
5 a n/17 a n 5 a n/17 a n
TTT Instruction
000
ROL
001
ROR
010
RCL
011
RCR
1 0 0 SHL/SAL
101
SHR
111
SAR
AND e And:
Reg/memory and register to either
001000dw
mod reg r/m
Immediate to register/memory
1000000w
mod 1 0 0 r/m
data
Immediate to accumulator
0010010w
data
data if w e 1
data if w e 1
3/10
3/10*
4/16
4/16*
3/4
3/4*
3/10
3/10*
4/10
4/10*
3/4
3/4
3/10
3/10*
4/16
4/16*
3/4
3/4*
8/16-bit
TEST e And function to flags, no result:
Register/memory and register
1000010w
mod reg r/m
Immediate data and register/memory
1111011w
mod 0 0 0 r/m
data
Immediate data and accumulator
1010100w
data
data if w e 1
data if w e 1
8/16-bit
OR e Or:
Reg/memory and register to either
000010dw
mod reg r/m
Immediate to register/memory
1000000w
mod 0 0 1 r/m
data
Immediate to accumulator
0000110w
data
data if w e 1
data if w e 1
8/16-bit
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
55
55
80C186EB/80C188EB, 80L186EB/80L188EB
INSTRUCTION SET SUMMARY (Continued)
Function
Format
80C186EB
Clock
Cycles
80C188EB
Clock
Cycles
3/10
3/10*
4/16
4/16*
3/4
3/4
3/10
3/10*
Comments
LOGIC (Continued)
XOR e Exclusive or:
Reg/memory and register to either
001100dw
mod reg r/m
Immediate to register/memory
1000000w
mod 1 1 0 r/m
data
Immediate to accumulator
0011010w
data
data if w e 1
NOT e Invert register/memory
1111011w
mod 0 1 0 r/m
data if w e 1
8/16-bit
STRING MANIPULATION
MOVS e Move byte/word
1010010w
14
14*
CMPS e Compare byte/word
1010011w
22
22*
SCAS e Scan byte/word
1010111w
15
15*
LODS e Load byte/wd to AL/AX
1010110w
12
12*
STOS e Store byte/wd from AL/AX
1010101w
10
10*
INS e Input byte/wd from DX port
0110110w
14
14
OUTS e Output byte/wd to DX port
0110111w
14
14
8 a 8n
8 a 8n*
Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ)
MOVS e Move string
11110010
1010010w
CMPS e Compare string
1111001z
1010011w
5 a 22n
5 a 22n*
SCAS e Scan string
1111001z
1010111w
5 a 15n
5 a 15n*
LODS e Load string
11110010
1010110w
6 a 11n
6 a 11n*
STOS e Store string
11110010
1010101w
6 a 9n
6 a 9n*
INS e Input string
11110010
0110110w
8 a 8n
8 a 8n*
OUTS e Output string
11110010
0110111w
8 a 8n
8 a 8n*
CONTROL TRANSFER
CALL e Call:
Direct within segment
11101000
disp-low
Register/memory
indirect within segment
11111111
mod 0 1 0 r/m
Direct intersegment
10011010
disp-high
segment offset
15
19
13/19
17/27
23
31
38
54
14
14
segment selector
Indirect intersegment
11111111
mod 0 1 1 r/m
Short/long
11101011
disp-low
Direct within segment
11101001
disp-low
Register/memory
indirect within segment
11111111
mod 1 0 0 r/m
Direct intersegment
11101010
(mod
i
11)
JMP e Unconditional jump:
disp-high
segment offset
14
14
11/17
11/21
14
14
26
34
segment selector
Indirect intersegment
11111111
mod 1 0 1 r/m
(mod
i
11)
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
56
56
80C186EB/80C188EB, 80L186EB/80L188EB
INSTRUCTION SET SUMMARY (Continued)
Function
Format
80C186EB
Clock
Cycles
80C188EB
Clock
Cycles
16
20
Comments
CONTROL TRANSFER (Continued)
RET e Return from CALL:
Within segment
11000011
Within seg adding immed to SP
11000010
Intersegment
11001011
Intersegment adding immediate to SP
11001010
data-low
25
33
JE/JZ e Jump on equal/zero
01110100
disp
4/13
4/13
JL/JNGE e Jump on less/not greater or equal
01111100
disp
4/13
4/13
JLE/JNG e Jump on less or equal/not greater
01111110
disp
4/13
4/13
JB/JNAE e Jump on below/not above or equal
01110010
disp
4/13
4/13
JBE/JNA e Jump on below or equal/not above
01110110
disp
4/13
4/13
JP/JPE e Jump on parity/parity even
01111010
disp
4/13
4/13
JO e Jump on overflow
01110 000
disp
4/13
4/13
JS e Jump on sign
01111000
disp
4/13
4/13
JNE/JNZ e Jump on not equal/not zero
01110101
disp
4/13
4/13
JNL/JGE e Jump on not less/greater or equal
01111101
disp
4/13
4/13
JNLE/JG e Jump on not less or equal/greater
01111111
disp
4/13
4/13
JNB/JAE e Jump on not below/above or equal
01110011
disp
4/13
4/13
data-low
data-high
data-high
18
22
22
30
JNBE/JA e Jump on not below or equal/above
01110111
disp
4/13
4/13
JNP/JPO e Jump on not par/par odd
01111011
disp
4/13
4/13
JNO e Jump on not overflow
01110001
disp
4/13
4/13
JNS e Jump on not sign
01111001
disp
4/13
4/13
JCXZ e Jump on CX zero
11100011
disp
5/15
5/15
LOOP e Loop CX times
11100010
disp
6/16
6/16
LOOPZ/LOOPE e Loop while zero/equal
11100001
disp
6/16
6/16
LOOPNZ/LOOPNE e Loop while not zero/equal
11100000
disp
6/16
6/16
ENTER e Enter Procedure
11001000
data-low
15
25
22 a 16(n b 1)
19
29
26 a 20(n b 1)
8
8
data-high
Le0
Le1
Ll1
LEAVE e Leave Procedure
11001001
JMP not
taken/JMP
taken
LOOP not
taken/LOOP
taken
L
INT e Interrupt:
Type specified
11001101
47
47
Type 3
11001100
type
45
45
if INT. taken/
INTO e Interrupt on overflow
11001110
48/4
48/4
if INT. not
taken
IRET e Interrupt return
11001111
BOUND e Detect value out of range
01100010
mod reg r/m
28
28
33–35
33–35
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
57
57
80C186EB/80C188EB, 80L186EB/80L188EB
INSTRUCTION SET SUMMARY (Continued)
Function
Format
80C186EB
Clock
Cycles
80C188EB
Clock
Cycles
Comments
PROCESSOR CONTROL
CLC e Clear carry
11111000
2
2
CMC e Complement carry
11110101
2
2
STC e Set carry
11111001
2
2
CLD e Clear direction
11111100
2
2
STD e Set direction
11111101
2
2
CLI e Clear interrupt
11111010
2
2
STI e Set interrupt
11111011
2
2
HLT e Halt
11110100
2
2
WAIT e Wait
10011011
6
6
LOCK e Bus lock prefix
11110000
2
2
10010000
3
3
NOP e No Operation
if TEST e 0
(TTT LLL are opcode to processor extension)
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
FOOTNOTES
The Effective Address (EA) of the memory operand
is computed according to the mod and r/m fields:
if mod e 11 then r/m is treated as a REG field
if mod e 00 then DISP e 0*, disp-low and disphigh are absent
if mod e 01 then DISP e disp-low sign-extended to 16-bits, disp-high is absent
if mod e 10 then DISP e disp-high: disp-low
e 000 then EA e (BX) a (SI) a DISP
if r/m
e 001 then EA e (BX) a (DI) a DISP
if r/m
e 010 then EA e (BP) a (SI) a DISP
if r/m
e 011 then EA e (BP) a (DI) a DISP
if r/m
e 100 then EA e (SI) a DISP
if r/m
e 101 then EA e (DI) a DISP
if r/m
e 110 then EA e (BP) a DISP*
if r/m
e 111 then EA e (BX) a DISP
if r/m
DISP follows 2nd byte of instruction (before data if
required)
*except if mod e 00 and r/m e 110 then EA e
disp-high: disp-low.
EA calculation time is 4 clock cycles for all modes,
and is included in the execution times given whenever appropriate.
Segment Override Prefix
0
0
1
reg
1
1
reg is assigned according to the following:
Segment
reg
Register
00
ES
01
CS
10
SS
11
DS
REG is assigned according to the following table:
16-Bit (w e 1)
8-Bit (w e 0)
000 AX
000 AL
001 CX
001 CL
010 DX
010 DL
011 BX
011 BL
100 SP
100 AH
101 BP
101 CH
110 SI
110 DH
111 DI
111 BH
The physical addresses of all operands addressed
by the BP register are computed using the SS segment register. The physical addresses of the destination operands of the string primitive operations
(those addressed by the DI register) are computed
using the ES segment, which may not be overridden.
0
58
58
80C186EB/80C188EB, 80L186EB/80L188EB
ERRATA
An 80C186EB/80L186EB with a STEPID value of
0001H has the following known errata. A device with
a STEPID of 0001H can be visually identified by the
presence of an ‘‘A’’ alpha character next to the
FPO number. The FPO number location is shown in
Figures 4, 5 and 6.
1. A19/ONCE is not latched by the rising edge of
RESIN. A19/ONCE must remain active (LOW) at
all times to remain in the ONCE Mode. Removing
A19/ONCE after RESIN is high will return all output pins to a driving state, however, the
80C186EB will remain in a reset state.
2. During interrupt acknowledge (INTA) bus cycles,
the bus controller will ignore the state of the
READY pin if the previous bus cycle ignored the
state of the READY pin. This errata can only occur if the Chip-Select Unit is being used. All active
chip-selects must be programmed to use READY
(RDY bit must be programmed to a 1) if waitstates are required for INTA bus cycles.
3. CLKOUT will transition off the rising edge of
CLKIN rather than the falling edge of CLKIN. This
does not affect any bus timings other than TCD.
4. RESIN has a hysterisis of only 130 mV. It is recommended that RESIN be driven by a Schmitt
triggered device to avoid processor lockup during
reset using an RC circuit.
5. SINT1 will only go active for one clock period
when a receive or transmit interrupt is pending
(i.e., it does not remain active until the S1STS
register is read). If SINT1 is to be connected to
any of the processor interrupt lines (INT0 – INT4),
then it must be latched by user logic.
An 80C186EB/80L186EB with a STEPID value of
0001H or 0002H has the following known errata. A
device with a STEPID of 0002H can be visually identified by noting the presence of a ‘‘B’’, ‘‘C’’, ‘‘D’’, or
‘‘E’’ alpha character next to the FPO number. The
FPO number location is shown in Figures 4, 5 and 6.
1. An internal condition with the interrupt controller
can cause no acknowledge cycle on the INTA1
line in response to INT1. This errata only occurs
when Interrupt 1 is configured in cascade mode
and a higher priority interrupt exists. This errata
will not occur consistantly, it is dependent on interrupt timing.
REVISION HISTORY
This data sheet replaces the following data sheets:
270803-004 80C186EB
270885-003 80C188EB
270921-003 80L186EB
270920-003 80L188EB
272311-001 SB80C188EB/SB80L188EB
272312-001 SB80C186EB/SB80L186EB
59
59