MOSA MS6720SSGTR 3 stereo inputs and 4-channel outputs volume, balance, fader and selectable input gain Datasheet

MS6720
MOSA
3 Stereo Inputs / 4-Channel Outputs Audio Processor
3 Stereo Inputs and 4-Channel Outputs
Volume, Balance, Fader and Selectable Input
Gain
FEATURES
APPLICATIONS
•Operation range : 2.7V~5V
•3 stereo inputs with selectable input gain
•4 independent speaker controls for fader and balance
•Independent mute function
•Volume control in 1.25 dB/step
•I2C interface
•Components less and good PSRR
•Housed in SOP20, SSOP20 packages
•Portable audio device
•Car stereo audio
•Hi-Fi audio system
•Cross-reference:
PT2313L-20
DESCRIPTION
The MS6720 is a 3 stereo inputs/4-channel outputs digital control audio processor for the low voltage operation.
Volume, balance (left/right), and fader (front/rear) processor are incorporated into a single chip. The MS6720 also has
selectable input gain. All functions are programmable via the serial I2C bus. The default states of the chip as the power
is on are: the volume is -78.75dB, the stereo 4 is selected, all the speakers are mute and the gains of the input stage are
0dB. The stereo 4 is connected internally, but not available on pins.
BLOCK DIAGRAM
LOUT
13
LIN
12
Speaker
ATT
17
OUT_LF
Mute
LIN1
LIN2
LIN3
11
10
9
Volume
15
OUT_LR
Mute
Input
Selector
&Gain
Control
RIN3
RIN2
RIN1
Speaker
ATT
20
SCL
19
SDA
18
DGND
Serial Bus Decoder and Latches
6
7
8
Speaker
ATT
Volume
16
OUT_RF
Mute
Speaker
ATT
Supply
2
3
1
5
AVDD AGND REF ROUT
REV1.0
14
OUT_RR
Mute
4
RIN
1
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MS6720
MOSA
3 Stereo Inputs / 4-Channel Outputs Audio Processor
PIN CONFIGURATION
Symbol
REF
Pin
1
VDD
AGND
2
3
Description
Analog Reference Voltage(1/2VDD)
Supply Input Voltage
Analog Ground
RIN
4
Audio Processor Right Channel Input
ROUT
RIN3
5
6
Gain Output and Input Selector for Right Channel
Right Channel Input 3
RIN2
RIN1
7
8
Right Channel Input 2
Right Channel Input 1
LIN3
LIN2
9
10
Left Channel Input 3
Left Channel Input 2
LIN1
11
LIN
LOUT
REF 1
20 SCL
VDD 2
19 SDA
AGND 3
18 DGND
17 OUT_LF
RIN 4
ROUT 5
16 OUT_RF
MS6720
RIN3 6
15 OUT_LR
Left Channel Input 1
RIN2 7
14 OUT_RR
12
13
Audio Processor Left Channel Input
Gain Output and Input Selector for Left Channel
RIN1 8
13 LOUT
LIN3 9
12 LIN
OUT_RR
OUT_LR
14
15
Right Rear Speaker Output
Left Rear Speaker Output
LIN2 10
11 LIN1
OUT_RF
16
Right Front Speaker Output
OUT_LF
DGND
17
18
Left Front Speaker Output
Digital Ground
SDA
SCL
19
20
I2C Data Input
I2C Clock Input
SOP20 / SSOP20
ORDERING INFORMATION
Package
Part number
Packaging Marking
Transport Media
20-Pin SOP (lead free)
MS6720GTR
MS6720G
1k Units Tape and Reel
20-Pin SOP (lead free)
MS6720GU
MS6720G
36 Units Tube
20-Pin SSOP (lead free)
MS6720SSGTR
MS6720G
2.5k Units Tape and Reel
20-Pin SSOP (lead free)
RoHS Compliance
MS6720SSGU
MS6720G
56 Units Tube
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Supply Voltage
Rating
Unit
6
V
VESD
Electrostatic Handling
-3000 to 3000
V
TSTG
Storage Temperature Range
-65 to 150
℃
TA
Operating Ambient Temperature Range
-40 to 85
℃
TJ
Maximum Junction Temperature
150
℃
TS
Soldering Temperature, 10 seconds
260
℃
RTHJA
Thermal Resistance from Junction to Ambient in Free Air
SOP20
SSOP20
210
210
℃/W
REV1.0
2
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MS6720
MOSA
3 Stereo Inputs / 4-Channel Outputs Audio Processor
OPERATING RATINGS
Symbol
VDD
Parameter
Supply Voltage
Min
Typ
Max
Unit
2.7
-
5.5
V
5V ELECTRICAL CHARACTERISTICS
(Ta=25℃, All stages 0dB, f=1kHz, CREF =22uF, refer to the application circuit; unless otherwise specified)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
12.2
12.5
mA
Supply
IQ
Quiescent Current
VIN=0V
PSRR
Power Supply Rejection Ratio
CREF = 22uF, f = 100Hz
55
60
-
dB
Input Selectors
RIN
Input Resistance
Input 1,2,3
35
50
70
kΩ
GIN
Input Gain Range
Gain
0
-
11.25
dB
GSTEP
Step Resolution
-
3.75
-
dB
ERRG
Gain Setting error
-0.2
0
0.2
dB
-78.75
-
0
dB
-
1.25
-
dB
-0.5
0
1
dB
-1
0
5
dB
-37.5
-
0
dB
-
1.25
-
dB
-0.2
0
0.1
dB
-
-65
-60
dB
4.3
-
-
Vpp
-75
0.0177
-
dB
%
Volume control
CRVOL
Volume Control Range
RESVOL
Volume Step Resolution
ERRVOL
Volume Setting Error
Attenuation
Av = 0 to -40dB
Av = -40 to -60dB
Speaker Attenuators
CRSPK
Speaker Control Range
RESSPK
Speaker Step Resolution
ERRSPK
Speaker Setting Error
MUTE
Output Mute Attenuation
Attenuation
General
VOMAX
Maximum Output Voltage Swing
(THD+N)/S <0.3%
THD+N
Total Harmonic Distortion Plus
Noise
VOUT=2Vpp
-
S/N
Signal-to-Noise Ratio
VOUT=4Vpp
-
97
-
dB
CS
Channel Separation Left/Right
93
97
-
dB
VIH
Bus High Input Level
2
-
-
V
VIL
Bus Low Input Level
-
-
0.8
V
Bus Input
REV1.0
3
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MS6720
MOSA
3 Stereo Inputs / 4-Channel Outputs Audio Processor
2.7V ELECTRICAL CHARACTERISTICS
(Ta=25℃, All stages 0dB, f=1kHz, CREF =22uF, refer to the application circuit; unless otherwise specified)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Supply
IQ
Quiescent Current
VIN=0V
PSRR
Power Supply Rejection Ratio
CREF = 22uF, f = 100Hz
VOMAX
Maximum Output Voltage Swing
(THD+N)/S <0.3%
THD+N
Total Harmonic Distortion Plus
Noise
VOUT=2Vpp
S/N
Signal-to-Noise Ratio
VOUT=2.5Vpp
CS
Channel Separation Left/Right
-
8.7
9
mA
53
58
-
dB
-
2.5
-
Vpp
-
-50
-
dB
General
-
0.3
-
%
90
94
-
dB
90
94
-
dB
TYPICAL PERFORMANCE CHARACTERISTICS
(Ta=25℃, All stages 0dB, f=1kHz, CREF =22uF, refer to the application circuit; unless otherwise specified)
VDD=2.7V
VO=2Vpp
THD+N (%)
THD+N (%)
THD+N (%)
f=1kHz
f=20kHz
f=20Hz
VDD=5V
VO=2Vpp
f=20kHz
f=1kHz
VDD=5V
VDD=2.7V
OUTPUT VOLTAGE (dBV)
OUTPUT VOLTAGE (dBV)
THD+N vs. Frequency
THD+N vs. Output Voltage
THD+N vs. Output Voltage
CAP=10uF
VDD=5V
VRR=-20dBV
PSRR (dB)
PSRR (dB)
CAP=22uF
CAP=10uF
VDD=2.7V
VRR=-20dBV
CHANNEL SEPARATION (dB)
VOLUME (dB)
CAP=22uF
REV1.0
f=20Hz
VDD=2.7V
VIN=-3dBV
VDD=5V
VIN=0dBV
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
PSRR vs. Frequency
PSRR vs. Frequency
Channel Separation vs. Frequency
4
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MS6720
MOSA
QUIESCENT CURRENT (mA)
3 Stereo Inputs / 4-Channel Outputs Audio Processor
SUPPLY VOLTAGE (V)
Quiescent Current vs. Supply Voltage
I2C BUS DESCRIPTION
Start and Stop Conditions
A start condition is activated when the SCL is set to HIGH and SDA shifts from HIGH to LOW state. The stop
condition is activated when SCL is set to HIGH and SDA shifts from LOW to HIGH state. Please refer to the timing
diagram below.
SCL
SDA
Start
Stop
SCL : Serial Clock Line, SDA : Serial Data Line
Data Validity
A data on the SDA line is considered valid and stable only when the SCL signal is in HIGH state. The HIGH and
LOW states of the SDA line can only change when the SCL signal is LOW. Please refer to the figure below.
SDA
SCL
Data line
stable,
Data valid
Data
change
allowed
Byte Format
Every byte transmitted to the SDA line consists of 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transmitted first.
REV1.0
5
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MS6720
MOSA
3 Stereo Inputs / 4-Channel Outputs Audio Processor
Acknowledge
During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral
(audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that
the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below.
SCL
1
2
3
7
8
9
SDA
MSB
Acknowledge
Start
The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise,
the SDA line will remain at the HIGH level during the ninth (9th) clock pulse. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
Timing of SDA and SCL Bus Lines
SDA
tf
tLOW
SCL
S
tHD;STA
tSU;DAT
tr
tHD;DAT
Standard Mode
Symbol
fSCL
tHD;STA
tf
tHIGH
tSU;STA
Parameter
Sr
tSP
tBUF
tr
tSU;STO
P
S
Min
Max
Unit
0
100
kHz
4.0
-
us
tLOW
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
LOW period of the SCL clock
4.7
-
us
tHIGH
HIGH period of the SCL clock
4.0
-
us
tSU:STA
4.7
-
us
0
3.45
us
tSU:DAT
Set-up time for a repeated START condition
Data hold time:
For I2C-bus devices
Data-set-up time
250
-
ns
tr
Rise time of both SDA and SCL signals
-
1000
ns
tf
Fall time of both SDA and SCL signals
-
300
ns
tSU:STO
Set-up time for STOP condition
4.0
-
us
tBUF
Bus free time between a STOP and START condition
4.7
-
us
Cb
Capacitive load for each bus line
-
400
pF
VnL
Noise margin at the LOW level for each connected device (including
0.1VDD
hysteresis)
-
V
VnH
Noise margin at the HIGH level for each connected device (including
0.2VDD
hysteresis)
-
V
tHD:STA
tHD:DAT
REV1.0
6
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MS6720
MOSA
3 Stereo Inputs / 4-Channel Outputs Audio Processor
BUS INTERFACE
Data are transmitted to and from the MCU to the MS6720 via the SDA and SCL. The SDA and SCL make up the
BUS interface. It should be noted that pull-up resistors must be connected to the positive supply voltage.
VDD
Rp
Rp
Pull up resistors
SDA (Serial Data Line)
SCL (Serial Clock Line)
MCU
MS6720
Interface Protocol
The format consists of the following
•A START condition
•A chip address byte including the MS6720 address. (7bits)
•The 8th bit of the byte must be “0”.(write=0, read=1)
•MS6720 must always acknowledge the end of each transmitted byte.
•A data sequence (N-bytes + Acknowledge)
•A STOP condition
SDA
SCL
1-7
8
ADDRESS
W
R / --
9
1-7
8
9
1-7
8
9
S
P
START
CONDITION
ACK
DATA
ACK
DATA
ACK
STOP
CONDITION
Address Code
The chip address of the MS6720 is 88H.
1
0
0
0
1
0
7 bits address
0
0
W
MS6720 address
REV1.0
7
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MS6720
MOSA
3 Stereo Inputs / 4-Channel Outputs Audio Processor
Data Bytes Description
The default states of the chip as the power is on are: the volume is -78.75dB, the stereo 4 is selected, all the speakers are
mute and the gains of the input stage are 0dB.
MSB
LSB
Function
0
0
B2
B1
B0
A2
A1
A0
Volume Control
1
1
0
B1
B0
A2
A1
A0
Speaker ATT LR
1
1
1
B1
B0
A2
A1
A0
Speaker ATT RR
1
0
0
B1
B0
A2
A1
A0
Speaker ATT LF
1
0
1
B1
B0
A2
A1
A0
Speaker ATT RF
0
1
0
G1
G0
1
S1
S0
Audio Switch
Where Ax = 1.25dB/step; Bx = 10dB/step; Cx = 2dB/step; Gx = 3.75dB/step
Volume
MSB
0
0
0
0
B2
B1
B0
LSB
Function
A2
A1
A0
Volume 1.25 dB steps
0
0
0
0
0
0
1
-1.25
0
1
0
-2.5
0
1
1
-3.75
1
0
0
-5
1
0
1
-6.25
1
1
0
-7.5
1
1
1
-8.75
A2
A1
A0
Volume 10dB steps
B2
B1
B0
0
0
0
0
0
0
1
-10
0
1
0
-20
0
1
1
-30
1
0
0
-40
1
0
1
-50
1
1
0
-60
1
1
1
-70
The default volume is –78.75dB.
REV1.0
8
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MS6720
MOSA
3 Stereo Inputs / 4-Channel Outputs Audio Processor
Speaker Attenuator
MSB
LSB
Function(
(dB)
)
1
0
0
B1
B0
A2
A1
A0
Speaker LF
1
0
1
B1
B0
A2
A1
A0
Speaker RF
1
1
0
B1
B0
A2
A1
A0
Speaker LR
1
1
1
B1
B0
A2
A1
A0
Speaker RR
0
0
0
0
0
0
1
-1.25
0
1
0
-2.5
0
1
1
-3.75
1
0
0
-5
1
0
1
-6.25
1
1
0
-7.5
1
1
1
-8.75
0
0
0
0
1
-10
1
0
-20
1
1
-30
1
1
1
1
1
Mute
LSB
Function
S1
S0
Audio Switch
0
0
Stereo 1
0
1
Stereo 2
1
0
Stereo 3
1
1
*Stereo 4
LF: Left Front, RF: Right Front, LR: Left Rear, RR: Right Rear
The default state is mute.
Audio Switch
MSB
0
1
0
G1
G0
1
0
0
+11.25dB
0
1
+7.5dB
1
0
+3.75dB
1
1
0dB
* The stereo 4 is connected internally, but not available on pins.
The default state is stereo 4 and gain 0dB.
REV1.0
9
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MS6720
MOSA
3 Stereo Inputs / 4-Channel Outputs Audio Processor
Examples
Set Volume at –37.5dB.
MSB
Start
Data byte
LSB
MS6720 Address
ACK
0
0
0
1
1
1
-30dB
0
ACK
Stop
0
ACK
Stop
1
1
ACK
Stop
0
1
ACK
Stop
1
-7.5dB
Volume
Set Speaker RF at –30dB.
MSB
Start
Data byte
LSB
MS6720 Address
ACK
1
0
1
Speaker
RF
1
1
0
-30dB
0
0dB
Set Speaker RR in mute-on.
MSB
Start
Data byte
LSB
MS6720 Address
ACK
1
1
1
1
1
Speaker
RR
1
Mute
Set Stereo 2 Input with gain of +7.5dB
MSB
Start
MS6720 Address
Data byte
LSB
ACK
0
1
0
0
1
1
+7.5dB
Stereo 2
REV1.0
10
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MS6720
MOSA
3 Stereo Inputs / 4-Channel Outputs Audio Processor
APPLICATION INFORMATION
Basic Application Example
2.2u
MCU
18
19
13
20
12
LIN
LOUT
SCL
SDA
DGND
10u
2.2u
11
8
10
INPUT
7
9
6
OUT_LF
LIN1
RIN1
17
10u
OUT_LR
LIN2
RIN2
15
MS6720
OUTPUT
10u
OUT_RF
LIN3
RIN3
16
10u
2.2u
OUT_RR
1
RIN
ROUT
3
REF
AGND
AVDD
2
14
5
4
22u
AVDD
REV1.0
2.2u
11
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MS6720
MOSA
3 Stereo Inputs / 4-Channel Outputs Audio Processor
EXTERNAL DIMENSIONS
SOP20 (300mil)
D
Detail A
Symbol
E
A
A1
B
C
e
D
E
H
L
h
θ
H
h x 45
C
Dimension in mm
Min
Max
2.35
2.65
0.10
0.30
0.33
0.51
0.23
0.32
1.27 BSC
12.6
13
7.4
7.60
10.00
10.65
0.40
1.27
0.25
0.75
o
o
8
0
Dimension in inch
Min
Max
0.0926 0.1043
0.004 0.0118
0.013
0.020
0.0091 0.0125
0.050 BSC
0.4961 0.5118
0.2914 0.2992
0.394
0.419
0.016
0.050
0.010
0.029
o
o
0
8
A
A1
0.25mm
B
e
θ
L
Detail A
SSOP20
D
Detail A
Symbol
E1
A
A1
A2
b
c
e
D
E
E1
L
h
L1
ZD
R1
R
θ
θ1
θ2
E
H x 45
c
ZD
A2
A
θ2
e
b
A1
θ1
Dimension in mm Dimension in inch
Min
Max
Min
Max
1.35
1.75
0.053
0.069
0.10
0.25
0.004
0.010
1.50
0.059
0.20
0.30
0.008
0.012
0.18
0.25
0.007
0.010
0.635 BASIC
0.025 BASIC
8.56
8.74
0.337
0.344
5.79
6.20
0.228
0.244
3.81
3.99
0.150
0.157
0.41
1.27
0.016
0.050
0.25
0.50
0.010
0.020
0.254 BASIC
0.010 BASIC
1.4732 REF
0.058 REF
0.20
0.33
0.008
0.013
0.20
0.008
o
o
o
o
0
8
0
8
o
o
0
0
o
o
o
o
15
5
15
5
R1
L1
R
θ
L
Detail A
REV1.0
12
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