IDT IDT72V7230L15BB 3.3 volt high-density supersync ii 72-bit fifo Datasheet

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 72-BIT FIFO
512 x 72, 1,024 x 72
2,048 x 72, 4,096 x 72
8,192 x 72, 16,384 x 72
32,768 x 72, 65,536 x 72
•
•
•
FEATURES:
•
•
•
•
•
•
•
Choose among the following memory organizations:
IDT72V7230  512 x 72
IDT72V7240  1,024 x 72
IDT72V7250  2,048 x 72
IDT72V7260  4,096 x 72
IDT72V7270  8,192 x 72
IDT72V7280  16,384 x 72
IDT72V7290  32,768 x 72
IDT72V72100  65,536 x 72
100 MHz operation (10 ns read/write cycle time)
User selectable input and output port bus-sizing
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
Big-Endian/Little-Endian user selectable word representation
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
•
•
•
•
•
•
•
•
•
•
•
•
•
IDT72V7230, IDT72V7240
IDT72V7250, IDT72V7260
IDT72V7270, IDT72V7280
IDT72V7290, IDT72V72100
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Asynchronous operation of Output Enable, OE
Read Chip Select ( RCS ) on Read Side
Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)
Features JTAG (Boundary Scan)
High-performance submicron CMOS technology
Industrial temperature range (–40°°C to +85°°C) is available
FUNCTIONAL BLOCK DIAGRAM
D0 -Dn (x72, x36 or x18)
WEN
INPUT REGISTER
WRITE CONTROL
LOGIC
RAM ARRAY
512 x 72
1,024 x 72
2,048 x 72
4,096 x 72
8,192 x 72
16,384 x 72
32,768 x 72
65,536 x 72
WRITE POINTER
BE
IP
CONTROL
LOGIC
BM
IW
OW
BUS
CONFIGURATION
MRS
PRS
RESET
LOGIC
TCK
TRST
TMS
TDO
TDI
LD
WCLK
JTAG
CONTROL
(BOUNDARY SCAN)
OUTPUT REGISTER
SEN SCLK
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
FLAG
LOGIC
READ POINTER
READ
CONTROL
LOGIC
RT
RM
RCLK
REN
RCS
OE
Q0 -Qn (x72, x36 or x18)
4680 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
DECEMBER 2003
COMMERCIAL TEMPERATURE RANGE
1
 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4680/9
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
Bus-Matching Sync FIFOs are particularly appropriate for network, video,
telecommunications, data communications and other applications that need to
buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either a 72-bit, 36-bit or a 18-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and BusMatching (BM) pin during the Master Reset cycle.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(WEN) input. Data is written into the FIFO on every rising edge of WCLK when
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
DESCRIPTION:
The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100 are exceptionally deep, high speed, CMOS First-In-FirstOut (FIFO) memories with clocked read and write controls and a flexible BusMatching x72/x36/x18 data flow. These FIFOs offer several key user benefits:
• Flexible x72/x36/x18 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 4 Mbit
PIN CONFIGURATION
A1 BALL PAD CORNER
A
Q33
Q35
Q47
Q50
Q53
Q65
Q68
Q71
D71
D68
D65
D53
D50
D47
D35
D33
Q32
Q34
Q46
Q49
Q52
Q64
Q67
Q70
D70
D67
D64
D52
D49
D46
D34
D32
Q31
Q30
Q45
Q48
Q51
Q63
Q66
Q69
D69
D66
D63
D51
D48
D45
D30
D31
Q29
Q28
Q27
VCC
GND
VCC GND
TCK
TDI
TRST TDO
TMS
GND
D27
D28
D29
Q17
Q16
Q15
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
D15
D16
D17
Q14
Q13
Q12
VCC
GND
VCC
GND
VCC
GND VCC
GND
VCC
GND
D12
D13
D14
Q11
Q10
Q9
VCC
GND VCC
GND
VCC
GND
VCC
GND
VCC
GND
D9
D10
D11
Q62
Q61
Q60
VCC
GND VCC
GND
VCC
GND
VCC
GND
VCC
GND
D60
D61
D62
Q59
Q58
Q57
VCC
GND VCC
GND
VCC
GND
VCC
GND
VCC
GND
D57
D58
D59
Q56
Q55
Q54
VCC
GND
VCC
GND
VCC
GND VCC
GND
VCC
GND
D54
D55
D56
Q44
Q43
Q42
VCC
GND
VCC
GND VCC
GND
VCC
GND
GND
IW
D42
D43
D44
Q41
Q40
Q39
VCC
GND
VCC
GND
GND
FS1
FS0
OW
GND SCLK D39
D40
D41
Q38
Q37
Q36
RT
RM
PFM
BM
IP
BE
HF
FWFT/ LD
SI
Q26
Q25
Q18
Q6
Q3
Q0
RCS
PAE
MRS
PRS
D0
Q24
Q21
Q19
Q7
Q4
Q1
OE
EF
PAF
WEN
Q23
Q22
Q20
Q8
Q5
Q2
REN RCLK
FF
1
2
3
4
5
6
9
B
C
D
E
F
G
H
J
K
L
M
N
SEN
D36
D37
D38
D3
D6
D18
D25
D26
D1
D4
D7
D19
D21
D24
WCLK
D2
D5
D8
D20
D22
D23
10
11
12
13
14
15
16
P
R
T
7
8
4680 drw02
PBGA (BB256-1, order code: BB)
TOP VIEW
2
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that PAE can be set to switch at a predefined number of locations
from the empty boundary and the PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
SCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via Dn. REN together with LD on each rising edge
of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.
DESCRIPTION (CONTINUED)
and Read Enable (REN) input. Data is read from the FIFO on every rising edge
of RCLK when REN is asserted. An Output Enable (OE) input is provided for
three-state control of the outputs.
A Read Chip Select (RCS) input is also provided for synchronous enable
and disable of the read port control input, REN. The RCS input is synchronized
to the read clock, and also provides three-state control of the Qn outputs. When
RCS is disable, REN will be disabled internally and data outputs will be in
High-Impedance state.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
PARTIAL RESET (PRS)
MASTER RESET (MRS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
(x72, x36, x18) DATA IN (D0 - Dn)
SERIAL IN CLOCK(SCLK)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
COMMERCIAL TEMPERATURE RANGE
IDT
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
READ CLOCK (RCLK)
READ ENABLE (REN)
READ CHIP SELECT (RCS)
OUTPUT ENABLE (OE)
(x72, x36, x18) DATA OUT (Q0 - Qn)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
JTAG CLOCK (TCLK)
JTAG RESET (TRST)
JTAG MODE (TMS)
(TDO)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
(TDI)
OUTPUT WIDTH (OW)
BUSMATCHING
(BM)
INPUT WIDTH (IW)
Figure 1. Single Device Configuration Signal Flow Diagram
3
4680 drw03
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
During Master Reset (MRS) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect. PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.
If asynchronous PAE/PAF configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOWto-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOWto-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The
mode desired is configured during master reset by the state of the Programmable
Flag Mode (PFM) pin.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the RT input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
A zero-latency retransmit timing mode can be selected using the Retransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero latency retransmit operation is selected, the first data word to be
retransmitted will be placed on the output register with respect to the same RCLK
edge that initiated the retransmit based on RT being LOW.
Refer to Figure 16 and 17 for Retransmit Timing with normal latency. Refer
to Figure 18 and 19 for Zero Latency Retransmit Timing.
COMMERCIAL TEMPERATURE RANGE
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when the FIFO is used in Bus-Matching mode, to determine order of the
words. As an example, if Big-Endian mode is selected, then the most significant
word of the long word written into the FIFO will be read out of the FIFO first,
followed by the least significant word. If Little-Endian format is selected, then the
least significant word of the long word written into the FIFO will be read out first,
followed by the most significant word. The mode desired is configured during
master reset by the state of the Big-Endian (BE) pin.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit position D8 during the parallel
programming of the flag offsets. If Non-Interspersed Parity mode is selected,
then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode
is selected during Master Reset by the state of the IP input pin.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read
Chip Select is synchronized to the RCLK. Both the output enable and read chip
select control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
JTAG test pins are also provided, the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100 are fabricated using IDT’s high speed submicron CMOS
technology.
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
BM
IW
OW
Write Port Width
Read Port Width
L
X
X
x72
x72
H
H
L
x36
x72
H
H
H
x18
x72
H
L
L
x72
x36
H
L
H
x72
x18
4
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
Name
I/O
Description
D0–D71
Data Inputs
I
Data inputs for a 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused input pins should be tied
LOW.
MRS
Master Reset
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset,
the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight
programmable flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian
format, zero latency timing mode, interspersed parity, and synchronous versus asynchronous programmable
flag timing modes.
PRS
Partial Reset
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
RT
Retransmit
I
FWFT/SI
I
OW
First Word Fall
Through/Serial In
Output Width
I
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to
HIGH in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or
programmable flag settings. RT is useful to reread data from the first physical location of the FIFO.
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions
as a serial input for loading offset registers.
This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
IW
BM
Input Width
Bus-Matching
I
I
This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration.
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
configuration.
BE
Big-Endian/
Little-Endian
I
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
will select Little-Endian format.
RM
Retransmit Timing
Mode
I
During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
normal latency mode.
PFM
I
IP
Programmable
Flag Mode
Interspersed Parity
I
FSEL0
Flag Select Bit 0
I
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
PFM will select Synchronous Programmable flag timing mode.
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
Parity mode.
During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
FSEL1
Flag Select Bit 1
I
WCLK
Write Clock
I
WEN
Write Enable
I
RCLK
Read Clock
I
REN
Read Enable
I
OE
Output Enable
I
RCS
Read Chip Select
I
SCLK
Serial Input Clock
I
SEN
Serial Enable
I
LD
Load
I
This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
determines one of eight default offset values for the PAE and PAF flags, along with the method by which these
offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing
to and reading from the offset registers.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full.
In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing
to the FIFO memory.
During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the programmable
registers for parallel programming.
WEN enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the
programmable registers. (RCS must be active).
REN enables RCLK for reading data from the FIFO memory and offset registers. (RCS must be active).
OE provides asynchronous control of the output impedance of Qn. During a Master or Partial Reset the OE
input is the only input that provide High-Impedance control of the data outputs.
RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During
a Master or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance
regardless of RCS.
when enabled by SEN, the rising edge of SCLK writes one bit of data (present on the SI input), into the
programmable register for serial programming.
SEN enables serial loading of programmable flag offsets.
5
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol
EF/OR
PAF
Name
Empty Flag/
Output Ready
Programmable
Almost-Full Flag
I/O
O
O
Description
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs.
PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in
the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or
equal to m.
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty
Offset register. PAE goes HIGH if the number of Flag words in the FIFO memory is greater than or equal to
offset n.
PAE
Programmable
Almost-Empty
O
HF
Q0–Q71
Half-Full Flag
Data Outputs
O
O
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for an 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused output pins should not
be connected. Data Outputs are not 5V tolerant regardless of the state of the OE and RCS.
TCK(1)
JTAG Clock
I
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations
of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and
outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI(1)
JTAG Test Data Input
I
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO(1)
JTAG Test Data Output
O
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID
Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and
SHIFT-IR controller states.
TMS(1)
JTAG Mode Select
I
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST(1)
JTAG Reset
I
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper
FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.
NOTE:
1. These pins are for the JTAG port. Please refer to pages 22-25 and Figures 5-7.
6
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
Rating
Terminal Voltage
with respect to GND
Commercial
–0.5 to +4.5
Unit
V
TSTG
Storage
Temperature
–55 to +125
°C
IOUT
DC Output Current
–50 to +50
mA
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Supply Voltage
VCC
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Min.
3.15
Typ.
3.3
Max.
3.45
Unit
V
0
0
0
V
GND
Supply Voltage
VIH
Input High Voltage
2.0
—
VCC+0.3
V
VIL(1)
Input Low Voltage
—
—
0.8
V
TA
Operating Temperature
Commercial
0
—
70
°C
NOTES:
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; JEDEC JESD8-A compliant)
IDT72V7230L
IDT72V7240L
IDT72V7250L
IDT72V7260L
IDT72V7270L
IDT72V7280L
IDT72V7290L
IDT72V72100L
Commercial
tCLK = 10, 15 ns
Symbol
(1)
Parameter
Min.
Max.
Unit
ILI
ILO(2)
Input Leakage Current
Output Leakage Current
–10
–10
10
10
µA
µA
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 4 mA
2.4
—
—
0.4
V
V
ICC1(3,4,5)
Active Power Supply Current
—
75
mA
Standby Current
—
15
mA
(3,6)
ICC2
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 15.5 + 2.275*fS + 0.002*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at
fS/2, CL = capacitive load (in pF).
6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
Capacitance
VIN = 0V
10
pF
COUT(1,2)
Output
Capacitance
VOUT = 0V
10
pF
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
7
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; JEDEC JESD8-A compliant)
Symbol
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tLDS
tLDH
tRS
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
tOHZ
tWFF
tREF
tPAFA
tPAFS
tPAEA
tPAES
tHF
tRCSS
tRCSH
tRCSLZ
tRCSHZ
tSKEW1
tSKEW2
Commercial
IDT72V7230L10
IDT72V7240L10
IDT72V7250L10
IDT72V7260L10
IDT72V7270L10
IDT72V7280L10
IDT72V7290L10
IDT72V72100L10
Min.
Max.
—
100
1
6.5
10
—
4.5
—
4.5
—
3.5
—
0.5
—
3.5
—
0.5
—
3.5
—
0.5
—
10
—
10
—
10
—
—
15
0
—
3.5
—
1
—
1
6
1
6
—
6.5
—
6.5
—
16
—
6.5
—
16
—
6.5
—
16
3.5
—
0.5
—
1
6.5
1
6.5
7
—
10
—
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Load Setup Time
Load Hold Time
Reset Pulse Width(2)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Mode Select Time
Retransmit Setup Time
Output Enable to Output in Low Z(3)
Output Enable to Output Valid
Output Enable to Output in High Z(3)
Write Clock to FF or IR
Read Clock to EF or OR
Clock to Asynchronous Programmable Almost-Full Flag
Write Clock to Synchronous Programmable Almost-Full Flag
Clock to Asynchronous Programmable Almost-Empty Flag
Read Clock to Synchronous Programmable Almost-Empty Flag
Clock to HF
RCS Setup Time
RCS Hold Time
RCLK to Active from High-Z(3)
RCLK to High-Z(3)
Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK and WCLK for PAE and PAF
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Data Sheet slow conditions: 85°c, 3.0V. Data Sheet fast conditions: -40°c, 3.6V.
3.3V
330Ω
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
IDT72V7230L15
IDT72V7240L15
IDT72V7250L15
IDT72V7260L15
IDT72V7270L15
IDT72V7280L15
IDT72V7290L15
IDT72V72100L15
Min.
Max.
—
66.7
1
10
15
—
6
—
6
—
4
—
1
—
4
—
1
—
4
—
1
—
15
—
15
—
15
—
—
15
0
—
4
—
1
—
1
8
1
8
—
10
—
10
—
20
—
10
—
20
—
10
—
20
5
—
1
—
1
10
1
10
9
—
14
—
D.U.T.
GND to 3.0V
3ns
1.5V
1.5V
See Figure 2
510Ω
30pF*
4680 drw04
Figure 2. Output Load
* Includes jig and scope capacitances
8
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
FUNCTIONAL DESCRIPTION
COMMERCIAL TEMPERATURE RANGE
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
10,11,12,16 and 18.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100 support two different timing modes of operation: IDT
Standard mode or First Word Fall Through (FWFT) mode. The selection of
which mode will operate is determined during Master Reset, by the state of the
FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
the first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depending
on which timing mode is in effect.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will
go HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of Table
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 258th word
for the IDT72V7230, 514th word for the IDT72V7240, 1,026th word for the
IDT72V7250, 2,050th word for the IDT72V7260, 4,098th word for the
IDT72V7270, 8,194th word for the IDT72V7280, 16,386th word for the
IDT72V7290 and 32,770th word for the IDT72V72100, respectively was
written into the FIFO. Continuing to write data into the FIFO will cause the PAF
to go LOW. Again, if no reads are performed, the PAF will go LOW after (513-m)
writes for the IDT72V7230, (1,025-m) writes for the IDT72V7240, (2,049-m)
writes for the IDT72V7250, (4,097-m) writes for the IDT72V7260 and (8,193-m)
writes for the IDT72V7270, 16,385 writes for the IDT72V7280, 32,769 writes
for the IDT72V7290 and 65,537 writes for the IDT72V72100, where m is the
full offset value. The default setting for these values are stated in the footnote
of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. D = 513 writes for the IDT72V7230, 1,025 writes for the
IDT72V7240, 2,049 writes for the IDT72V7250, 4,097 writes for the IDT72V7260
and 8,193 writes for the IDT72V7270, 16,385 writes for the IDT72V7280,
32,769 writes for the IDT72V7290, 65,537 writes for the IDT72V72100,
respectively. Note that the additional word in FWFT mode is due to the capacity
of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is
empty.
When configured in FWFT mode, the OR flag output is triple registerbuffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 13, 14,15,
17, and 19.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
the 257th word for IDT72V7230, 513rd word for IDT72V7240, 1,025th word
for IDT72V7250, 2,049th word for IDT72V7260, 4,097th word for IDT72V7270,
8,193th word for the IDT72V7280, 16,385th word for the IDT72V7290 and
32,769th word for the IDT72V72100, respectively was written into the FIFO.
Continuing to write data into the FIFO will cause the Programmable Almost-Full
flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW
after (512-m) writes for the IDT72V7230, (1,024-m) writes for the IDT72V7240,
(2,048-m) writes for the IDT72V7250, (4,096-m) writes for the IDT72V7260,
(8,192-m) writes for the IDT72V7270, (16,384-m) writes for the IDT72V7280,
(32,768-m) writes for the IDT72V7290 and (65,536-m) writes for the
IDT72V72100. The offset “m” is the full offset value. The default setting for these
values are stated in the footnote of Table 2. This parameter is also user
programmable. See section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. D = 512 writes for the IDT72V7230, 1,024 writes for the
IDT72V7240, 2,048 writes for the IDT72V7250, 4,096 writes for the IDT72V7260,
8,192 writes for the IDT72V7270, 16,384 writes for the IDT72V7280, 32,768
writes for the IDT72V7290, 65,536 writes for the IDT72V72100, respectively.
9
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
IDT72V7230, 72V7240
LD
L
L
L
L
H
H
H
H
FSEL1
H
L
L
H
L
H
L
H
FSEL0
L
H
L
H
L
L
H
H
Offsets n,m
511
255
127
63
31
15
7
3
LD
H
FSEL1
X
FSEL0
X
Program Mode
Serial(3)
L
X
X
Parallel(4)
IDT72V7250, 72V7260, 72V7270, 72V7280
LD
H
L
L
L
L
H
H
H
FSEL1
L
H
L
L
H
H
L
H
FSEL0
L
L
H
L
H
L
H
H
Offsets n,m
1,023
511
255
127
63
31
15
7
LD
H
L
FSEL1
X
X
FSEL0
X
X
Program Mode
Serial(3)
Parallel(4)
IDT72V7290, 72V72100
LD
L
L
L
H
H
H
H
L
FSEL1
H
L
H
H
L
L
H
L
FSEL0
L
H
H
L
L
H
H
L
Offsets n,m
16,383
8,191
4,095
2,047
1,023
511
255
127
LD
H
L
FSEL1
X
X
FSEL0
X
X
Program Mode
Serial(3)
Parallel(4)
COMMERCIAL TEMPERATURE RANGE
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72V7230/
72V7240/72V7250/72V7260/72V7270/72V7280/72V7290/72V72100 have
internal registers for these offsets. There are eight default offset values selectable
during Master Reset. These offset values are shown in Table 2. Offset values
can also be programmed into the FIFO in one of two ways; serial or parallel
loading method. The selection of the loading method is done using the LD (Load)
pin. During Master Reset, the state of the LD input determines whether serial
or parallel flag offset programming is enabled. A HIGH on LD during Master
Reset selects serial loading of offset values. A LOW on LD during Master Reset
selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time after
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100 can be configured during the Master Reset cycle with
either synchronous or asynchronous timing for PAF and PAE flags by use of
the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous
PAF timing and Figure 24 for synchronous PAE timing.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure
25 for asynchronous PAF timing and Figure 26 for asynchronous PAE timing.
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
10
11
1,024
512
1 to n
(n+1) to 8,192
8,193 to (16,384-(m+1))
(16,384-m) to 16,383
16,384
4,097 to (8,192-(m+1))
(8,192-m) to 8,191
8,192
(1)
(n+1) to 4,096
0
1 to n (1)
0
IDT72V7280
(1024-m) to 1,023
(512-m) to 511
IDT72V7270
(n+1) to 512
(1)
513 to (1,024-(m+1))
1,025
513
to 8,192
8,193
(8,193-m)
4,098 to (8,193-(m+1))
(n+2) to 4,097
1 to n+1
16,385
(16,385-m) to 16,384
8,194 to (16,385-(m+1))
(n+2) to 8,193
1 to n+1
0
IDT72V7280
(1,025-m) to 1,024
(513-m) to 512
32,769
(32,769-m) to 32,768
16,386 to (32,769-(m+1))
(n+2) to 16,385
1 to n+1
0
65,537
(65,537-m) to 65,536
32,770 to (65,537-(m+1))
(n+2) to 32,769
1 to n+1
0
IDT72V72100
IDT72V7290
to 4,096
4,097
(4,097-m)
2,049
(2,049-m) to 2,048
(n+2) to 2,049
2,050 to (4,097-(m+1))
(n+2) to 513
(n+2) to 1,025
0
IDT72V7260
65,536
(65,536-m) to 65,535
32,769 to (65,536-(m+1))
1,026 to (2,049-(m+1))
0
IDT72V7250
32,768
(32,768-m) to 32,767
16,385 to (32,768-(m+1))
(1)
(n+1) to 32,768
1 to n
0
1 to n+1
514 to (1,025-(m+1))
0
(1)
(n+1) to 16,384
1 to n
0
IDT72V72100
IDT72V7290
(4,096-m) to 4,095
4,096
to 2,047
2,049 to (4,096-(m+1))
(n+1) to 2,048
(1)
2,048
(2048-m)
1,025 to (2048-(m+1))
1 to n
0
IDT72V7260
1 to n+1
(n+2) to 257
IDT72V7270
(1)
(n+1) to 1,024
1 to n
0
IDT72V7250
1 to n+1
0
IDT72V7240
258 to (513-(m+1))
1 to n+1
0
IDT72V7230
STATUS FLAGS FOR FWFT MODE
NOTE:
1. See table 2 for values for n, m.
Number of
Words in
FIFO
Number of
Words in
FIFO
TABLE 4
0
1 to n
(n+1) to 256
(1)
IDT72V7240
257 to (512-(m+1))
1 to n
0
IDT72V7230
STATUS FLAGS FOR IDT STANDARD MODE
NOTE:
1. See table 2 for values for n, m.
Number of
Words in
FIFO
Number of
Words in
FIFO
TABLE 3
H
L
L
H
H
L
H
L
L
L
L
H
L
L
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
L
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
4680 drw 05
L
L
L
L
L
H
PAE OR
H
L
H
H
L
L
H
H
H
H
H
H
PAE OR
H
H
L
L
H
H
H
PAF HF
H
L
IR
H
H
PAF HF
L
L
IR
L
L
L
L
L
H
H
H
L
H
H
H
H
H
L
L
H
H
H
H
L
H
PAE EF
H
L
H
H
H
H
H
L
L
PAE EF
L
L
H
H
H
PAF HF
H
H
FF
H
H
PAF HF
H
H
FF
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
LD
WEN
REN
SEN
0
0
1
1
0
1
0
1
X
0
1
1
0
X
X
1
1
1
X
1
0
X
X
1
X
0
X
X
1
1
1
X
X
WCLK
COMMERCIAL TEMPERATURE RANGE
IDT72V7230
IDT72V7240
IDT72V7250
IDT72V7260
IDT72V7270
IDT72V7280
IDT72V7290
IDT72V72100
RCLK
SCLK
X
X
Parallel write to registers:
Empty Offset
Full Offset
X
Parallel read from registers:
Empty Offset
Full Offset
Serial shift into registers:
18 bits for the IDT72V7230
20 bits for the IDT72V7240
22 bits for the IDT72V7250
24 bits for the IDT72V7260
26 bits for the IDT72V7270
28 bits for the IDT72V7280
30 bits for the IDT72V7290
32 bits for the IDT72V72100
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
No Operation
X
X
Write Memory
X
Read Memory
X
No Operation
X
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence
12
4680 drw06
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
1st Parallel Offset Write/Read Cycle
D/Q71
D/Q19
D/Q17
D/Q0
D/Q8
EMPTY OFFSET REGISTER (PAE)
16 15 14 13 12 11 10 9 8 7 6
16 15 14 13 12 11 10 9
5 4 3 2 1
8 7 6 5 4 3 2 1
Non-Interspersed
Parity
Interspersed
Parity
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q71
D/Q19
D/Q0
D/Q8
FULL OFFSET REGISTER (PAF)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
D/Q17
Non-Interspersed
Parity
Interspersed
Parity
# of Bits Used
x72 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q35
D/Q19
D/Q17
D/Q0
D/Q8
EMPTY OFFSET REGISTER (PAE)
16 15 14 13 12 11 10 9 8 7 6
16 15 14 13 12 11 10 9
5 4 3 2 1
8 7 6 5 4 3 2 1
Non-Interspersed
Parity
Interspersed
Parity
# of Bits Used
D/Q35
D/Q19
2nd Parallel Offset Write/Read Cycle
D/Q17
D/Q8
D/Q0
FULL OFFSET REGISTER (PAF)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
Non-Interspersed
Parity
Interspersed
Parity
# of Bits Used
x36 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q16
D/Q0
EMPTY OFFSET (LSB) REGISTER (PAE)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
D/Q8
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q0
D/Q16
FULL OFFSET (LSB) REGISTER (PAF)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
D/Q8
x18 Bus Width
Non-Interspersed
Parity
Interspersed
Parity
# of Bits Used:
09 bits for the IDT72V7230
10 bits for the IDT72V7240
11 bits for the IDT72V7250
12 bits for the IDT72V7260
13 bits for the IDT72V7270
14 bits for the IDT72V7280
15 bits for the IDT72V7290
16 bits for the IDT72V72100
Note: All unused input bits
are don’t care.
4680 drw07
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
13
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
FUNCTIONAL DESCRIPTION
(CONTINUED)
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, SEN, SCLK and SI input pins. Programming PAE and PAF proceeds
as follows: when LD and SEN are set LOW, data on the SI input are written, one
bit for each SCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. A total of 18 bits for the IDT72V7230, 20 bits for the
IDT72V7240, 22 bits for the IDT72V7250, 24 bits for the IDT72V7260, 26 bits
for the IDT72V7270, 28 bits for the IDT72V7280, 30 bits for the IDT72V7290
and 32 bits for the IDT72V72100. See Figure 20, Serial Loading of
Programmable Flag Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does not
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing LD and SEN HIGH, data can be written to FIFO memory via
Dn by toggling WEN. When WEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruption of serial programming is desired, it is sufficient either to set LD LOW
and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising SCLK edge that achieves the above criteria;
PAF will be valid after three more rising WCLK edges plus tPAF, PAE will be valid
after the next three rising RCLK edges plus tPAE.
It is only possible to read the flag offset values via the parallel output port Qn.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, WCLK, WEN and Dn input pins. Programming PAE and PAF
proceeds as follows: LD and WEN must be set LOW. For x72, x36 or x18 bit
input bus widths, data on the inputs Dn are written into the Empty Offset Register
on the first LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH
transition of WCLK, data are written into the Full Offset Register. The third
transition of WCLK writes, once again, to the Empty Offset Register. See Figure
3, Programmable Flag Offset Programming Sequence. See Figure 21,
Parallel Loading of Programmable Flag Registers, for the timing diagram for
this mode.
The act of writing offsets in parallel employs a dedicated write offset register
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset register. A Partial Reset has no effect
on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers does
not have to occur at one time. One offset register can be written and then by
bringing LD HIGH, write operations can be redirected to the FIFO memory.
COMMERCIAL TEMPERATURE RANGE
When LD is set LOW again, and WEN is LOW, the next offset register in sequence
is written to. As an alternative to holding WEN LOW and toggling LD, parallel
programming can also be interrupted by setting LD LOW and toggling WEN.
Note that the status of a programmable flag (PAE or PAF) output is invalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register pertaining to that flag. Measuring from the
rising WCLK edge that achieves the above criteria; PAF will be valid after two
more rising WCLK edges plus tPAF, PAE will be valid after the next two rising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Q16
pins when LD is set LOW and REN is set LOW. For x72, x36 or x18 output bus
width, data are read via Q0-Q16 from the Empty Offset Register on the first
LOW-to-HIGH transition of RCLK. Upon the second LOW-to-HIGH transition
of RCLK, data are read from the Full Offset Register. The third transition of RCLK
reads, once again, from the Empty Offset Register. See Figure 3, Programmable Flag Offset Programming Sequence. See Figure 22, Parallel Read of
Programmable Flag Registers, for the timing diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting REN, LD,
or both together. When REN and LD are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK edge.
REN and WEN must be HIGH before bringing RT LOW. When zero latency is
utilized, REN does not need to be HIGH before bringing RT LOW. At least two words,
but no more than D - 2 words should have been written into the FIFO, and read
from the FIFO, between Reset (Master or Partial) and the time of Retransmit
setup. D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the
IDT72V7250, 4,096 for the IDT72V7260, 8,192 for the IDT72V7270, 16,384
for the IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the
IDT72V72100. In FWFT mode, D = 513 for the IDT72V7230, 1,025 for the
IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for
the IDT72V7270, 16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and
65,537 for the IDT72V72100.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting EF LOW. The change in level will only be noticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 16,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
14
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup,
the PAE flag will be updated. HF is asynchronous, thus the rising edge of RCLK
that RT is setup will update HF. PAF is synchronized to WCLK, thus the second
rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that RT
is setup will update PAF. RT is synchronized to RCLK.
The Retransmit function has the option of two modes of operation, either
“normal latency” or “zero latency”. Figure 16 and Figure 17 mentioned
previously, relate to “normal latency”. Figure 18 and Figure 19 show “zero
latency” retransmit operation. Zero latency basically means that the first data
word to be retransmitted, is placed onto the output register with respect to the
RCLK pulse that initiated the retransmit.
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is selected,
the first word appears on the outputs, no LOW on REN is necessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. See Figure 17, Retransmit Timing (FWFT Mode), for the relevant timing
diagram.
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
15
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 - Dn)
Data inputs for 72-bit wide data (D0 - D71), data inputs for 36-bit wide data
(D0 - D35) or data inputs for 18-bit wide data (D0 - D17).
CONTROLS:
MASTER RESET ( MRS )
A Master Reset is accomplished whenever the MRS input is taken to a LOW
state. This operation sets the internal read and write pointers to the first location
of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
All control settings such as OW, IW, BM, BE, RM, PFM and IP are defined
during the Master Reset cycle.
During a Master Reset, the output register is initialized to all zeroes. A Master
Reset is required after power up, before a write operation can take place. MRS
is asynchronous.
See Figure 8, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET ( PRS )
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH,
and HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active at
the time of Partial Reset is also retained. The output register is initialized to all
zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming programmable flag offset settings may not be
convenient.
See Figure 9, Partial Reset Timing, for the relevant timing diagram.
RETRANSMIT ( RT )
The Retransmit operation allows data that has already been read to be
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of the memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK edge.
REN and WEN must be HIGH before bringing RT LOW. When zero latency is
utilized, REN does not need to be HIGH before bringing RT LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting EF LOW. The change in level will only be noticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard mode
COMMERCIAL TEMPERATURE RANGE
is selected, every word read including the first word following Retransmit setup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 16,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is selected,
the first word appears on the outputs, no LOW on REN is necessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. See Figure 17, Retransmit Timing (FWFT Mode), for the relevant timing
diagram.
In Retransmit operation, zero latency mode can be selected using the
Retransmit Mode (RM) pin during a Master Reset. This can be applied to both
IDT Standard mode and FWFT mode.
Note, the Read Chip Select (RCS) input must be LOW during Retransmit.
The RCS input enables/disables the REN input.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determines whether the device will operate in IDT Standard mode or
First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO memory. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to Qn after three RCLK
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAE and PAF
offsets into the programmable registers. The serial input function can only be
used when the serial loading method has been selected during Master Reset.
Serial programming using the FWFT/SI pin functions the same way in both IDT
Standard and FWFT modes.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/
IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating HF flag to LOW.) The Write and Read Clocks can either be
independent or coincident.
WRITE ENABLE ( WEN )
When the WEN input is LOW, data may be loaded into the FIFO RAM array
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When WEN is HIGH, no new data is written in the RAM array on each WCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
16
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
READ CHIP SELECT ( RCS )
The Read Chip Select input provides synchronous control of the Read
output port. When RCS goes LOW, the next rising edge of RCLK causes the
Qn outputs to go to the LOW Z state. When RCS goes HIGH, the next RCLK
rising edge causes the Qn outputs to return to HIGH Z. During a Master or Partial
Reset the RCS input can be HIGH or LOW. OE provides High-Impedance
control of the data outputs. If OE is LOW the data outputs will be Low-Impedance
regardless of RCS until the first rising edge of RCLK after reset is complete. Then
if RCS is HIGH the data outputs will go to High-Impedance.
During the time while RCS is HIGH (disabled) all read operations are
ignored. That is, the REN input is disabled and data is not clocked from the RAM
array to the output register.
The RCS input does not effect the operation of the flags. For example, when
the first word is written to an empty FIFO, the EF will still go from LOW to HIGH
based on a rising edge of RCLK, regardless of the state of the RCS input.
Also, when operating the FIFO in FWFT mode the first word written to an
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of RCS. The RCS pin must also be active (LOW) in order
to perform a Retransmit. See figure 12 for Read Cycle and Read Chip Select
Timing (IDT Standard Mode). See figure 15 for Read Cycle and Read Chip
Select Timing (First Word Fall Through Mode).
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle, IR will go
LOW allowing a write to occur. The IR flag is updated by two WCLK cycles +
tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can be
read on the outputs, on the rising edge of the RCLK input. It is permissible to
stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and HF flags will
not be updated. (Note that RCLK is only capable of updating the HF flag to
HIGH.) The Write and Read Clocks can be independent or coincident.
READ ENABLE ( REN )
When Read Enable is LOW, data is loaded from the RAM array into the output
register on the rising edge of every RCLK cycle if the device is not empty.
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using REN provided that RCS
is LOW. When the last word has been read from the FIFO, the Empty Flag (EF)
will go LOW, inhibiting further read operations. REN is ignored when the FIFO
is empty. Once a write is performed, EF will go HIGH allowing a read to occur.
The EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle.
In the FWFT mode, the first word written to an empty FIFO automatically goes
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW
after the first write. REN and RCS do not need to be asserted LOW. In order
to access all other words, a read must be executed using REN and RCS must
be enabled LOW. The RCLK LOW-to-HIGH transition after the last word has
been read from the FIFO, Output Ready (OR) will go HIGH with a true read
(RCLK with REN = LOW; RCS = LOW), inhibiting further read operations. REN
is ignored when the FIFO is empty.
LOAD ( LD )
This is a dual purpose pin. During Master Reset, the state of the LD input,
along with FSEL0 and FSEL1, determines one of eight default offset values for
the PAE and PAF flags, along with the method by which these offset registers
can be programmed, parallel or serial (see Table 2). After Master Reset, LD
enables write operations to and read operations from the offset registers. Only
the offset loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel.
After Master Reset, the LD pin is used to activate the programming process
of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading
or parallel load or read of these offset values.
BUS-MATCHING (BM, IW, OW)
The pins BM, IW and OW are used to define the input and output bus widths.
During Master Reset, the state of these pins is used to configure the device bus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 4 for BusMatching Byte Arrangement.
SERIAL CLOCK ( SCLK )
During serial loading of the programmable flag offset registers, a rising edge
on the SCLK input is used to load serial data present on the SI input provided
that the SEN input is LOW.
BIG-ENDIAN/LITTLE-ENDIAN ( BE )
During Master Reset, a LOW on BE will select Big-Endian operation. A
HIGH on BE during Master Reset will select Little-Endian format. This function
is useful when the following input to output bus widths are implemented: x72 to
x36, x72 to x18, x36 to x72 and x18 to x72. If Big-Endian mode is selected,
then the most significant byte (word) of the long word written into the FIFO will
be read out of the FIFO first, followed by the least significant long word. If LittleEndian format is selected, then the least significant word of the long word written
into the FIFO will be read out first, followed by the most significant word. The
mode desired is configured during master reset by the state of the Big-Endian
(BE) pin. See Figure 4 for Bus-Matching Byte Arrangement.
SERIAL ENABLE ( SEN )
The SEN input is an enable used only for serial programming of the offset
registers. The serial programming method must be selected during Master
Reset. SEN is always used in conjunction with LD. When these lines are both
LOW, data at the SI input can be loaded into the program register one bit for each
LOW-to-HIGH transition of SCLK.
When SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded. SEN functions the same way in both IDT
Standard and FWFT modes.
OUTPUT ENABLE ( OE )
When Output Enable is enabled (LOW), the parallel output buffers receive
data from the output register. When OE is HIGH, the output data bus (Qn) goes
into a high impedance state. Note, during a Master or Partial Reset RCS can
be HIGH or LOW, OE is the only input that can place the output bus into HighImpedance.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM will select Synchronous Programmable
17
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM,
LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition
of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by
the state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode.
A HIGH will select Interspersed Parity mode. The IP bit function allows the user
to select the parity bit in the long word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bits are located in bit position D8, D17, D26, D35,
D44, D53, D62 and D71 during the parallel programming of the flag offsets. If
Non-Interspersed Parity mode is selected, then D8, D17 and D28 are is assumed
to be valid bits and D64, D65, D66, D67, D68, D69, D70 and D71 are ignored.
IP mode is selected during Master Reset by the state of the IP input pin.
OUTPUTS:
FULL FLAG ( FF/IR )
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. When FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the
IDT72V7250, 4,096 for the IDT72V7260, 8,192 for the IDT72V7270, 16,384
for the IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the
IDT72V72100). See Figure10, Write Cycle and Full Flag Timing (IDT
Standard Mode), for the relevant timing information.
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
any free space left, IR goes HIGH, inhibiting further write operations. If no reads
are performed after a reset (either MRS or PRS), IR will go HIGH after D writes
to the FIFO (D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049
for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270,
16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the
IDT72V72100). See Figure 13, Write Timing (FWFT Mode), for the relevant
timing information.
The IR status not only measures the contents of the FIFO memory, but also
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert IR is one greater than needed to
assert FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
double register-buffered outputs.
EMPTY FLAG ( EF/OR )
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)
function is selected. When the FIFO is empty, EF will go LOW, inhibiting further
read operations. When EF is HIGH, the FIFO is not empty. See Figure 11,
Read Cycle, Output Enable, Empty Flag and First Word Latency Timing (IDT
Standard Mode), for the relevant timing information.
In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW
at the same time that the first word written to an empty FIFO appears valid on
COMMERCIAL TEMPERATURE RANGE
the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts
the last word from the FIFO memory to the outputs. OR goes HIGH only with
a true read (RCLK with REN = LOW). The previous data stays at the outputs,
indicating the last word was read. Further data reads are inhibited until OR goes
LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG ( PAF )
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are written
to the FIFO. The PAF will go LOW after (512-m) writes for the IDT72V7230,
(1,024-m) writes for the IDT72V7240, (2,048-m) writes for the IDT72V7250,
(4,096-m) writes for the IDT72V7260, (8,192-m) writes for the IDT72V7270,
(16,384-m) writes for the IDT72V7280, (32,768-m) writes for the IDT72V7290,
and (65,536-m) writes for the IDT72V72100. The offset “m” is the full offset value.
The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the PAF will go LOW after (513-m) writes for the IDT72V7230,
(1,025-m) writes for the IDT72V7240, (2,049-m) writes for the IDT72V7250,
(4,097-m) writes for the IDT72V7260 and (8,193-m) writes for the IDT72V7270,
(16,385-m) writes for the IDT72V7280, (32,769-m) writes for the IDT72V7290
and (65,537-m) writes for the IDT72V72100, where “m” is the full offset value.
The default setting for this value is stated in Table 2.
See Figure 23, Synchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Modes), for the relevant timing information.
If asynchronous PAF configuration is selected, the PAF is asserted LOW
on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF
configuration is selected, the PAF is updated on the rising edge of WCLK. See
Figure 25, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT
Modes).
PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE )
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 24, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Modes), for the relevant timing information.
If asynchronous PAE configuration is selected, the PAE is asserted LOW
on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Modes).
HALF-FULL FLAG ( HF )
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
18
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 512 for the
IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the IDT72V7250, 4,096 for
the IDT72V7260, 8,192 for the IDT72V7270, 16,384 for the IDT72V7280,
32,768 for the IDT72V7290 and 65,536 for the IDT72V72100.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 513 for the
IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for
the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280,
COMMERCIAL TEMPERATURE RANGE
32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q0-Qn)
(Q0-Q71) are data outputs for 72-bit wide data, (Q0 - Q35) are data outputs
for 36-bit wide data or (Q0-Q17) are data outputs for 18-bit wide data.
19
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
BYTE ORDER ON INPUT PORT:
BYTE ORDER ON OUTPUT PORT:
BE
BM
IW
OW
X
L
X
X
COMMERCIAL TEMPERATURE RANGE
D71-D54
D53-D36
D35-D18
D17-D0
A
B
C
D
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
A
B
C
D
Write to FIFO
Read from FIFO
(a) x72 INPUT to x72 OUTPUT
Q71-Q54
BE
BM
IW
OW
L
H
L
L
Q53-Q36
Q35-Q18
Q17-Q0
B
A
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
C
D
1st: Read from FIFO
2nd: Read from FIFO
(b) x72 INPUT to x36 OUTPUT - BIG-ENDIAN
Q71-Q54
BE
BM
IW
OW
H
H
L
L
Q53-Q36
Q35-Q18
Q17-Q0
C
Q71-Q54
Q53-Q36
D
Q35-Q18
Q17-Q0
A
B
1st: Read from FIFO
2nd: Read from FIFO
(c) x72 INPUT to x36 OUTPUT - LITTLE-ENDIAN
Q71-Q54
BE
BM
IW
OW
L
H
L
H
Q53-Q36
Q35-Q18
Q17-Q0
A
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
B
Q71-Q54
Q53-Q36
Q35-Q18
Q53-Q36
2nd: Read from FIFO
Q17-Q0
C
Q71-Q54
1st: Read from FIFO
Q35-Q18
3rd: Read from FIFO
Q17-Q0
D
4th: Read from FIFO
(d) x72 INPUT to x18 OUTPUT - BIG-ENDIAN
Q71-Q54
BE
BM
IW
OW
H
H
L
H
Q53-Q36
Q35-Q18
Q17-Q0
D
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
C
Q71-Q54
Q53-Q36
Q35-Q18
Q53-Q36
Q35-Q18
(e) x72 INPUT to x18 OUTPUT - LITTLE-ENDIAN
20
3rd: Read from FIFO
Q17-Q0
A
Figure 4. Bus-Matching Byte Arrangement
2nd: Read from FIFO
Q17-Q0
B
Q71-Q54
1st: Read from FIFO
4th: Read from FIFO
4680 drw08
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
BYTE ORDER ON INPUT PORT:
D71-D54
D71-D54
BYTE ORDER ON OUTPUT PORT:
BE
BM
IW
OW
L
H
H
L
D53-D36
D53-D36
Q71-Q54
Q53-Q36
A
B
COMMERCIAL TEMPERATURE RANGE
D35-D18
D17-D0
A
B
D35-D18
D17-D0
C
D
Q35-Q18
1st: Write to FIFO
2nd: Write to FIFO
Q17-Q0
D
C
Read from FIFO
(a) x36 INPUT to x72 OUTPUT - BIG-ENDIAN
BE
BM
IW
OW
H
H
H
L
Q71-Q54
Q53-Q36
C
D
Q35-Q18
Q17-Q0
B
A
Read from FIFO
(b) x36 INPUT to x72 OUTPUT - LITTLE-ENDIAN
BYTE ORDER ON INPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
A
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
B
Q71-Q54
Q53-Q36
Q35-Q18
Q53-Q36
Q35-Q18
BE
BM
L
H
IW
OW
H
H
Q71-Q54
Q53-Q36
A
B
Q35-Q18
3rd: Write to FIFO
Q17-Q0
D
BYTE ORDER ON OUTPUT PORT:
2nd: Write to FIFO
Q17-Q0
C
Q71-Q54
1st: Write to FIFO
4th: Write to FIFO
Q17-Q0
C
D
Read from FIFO
(a) x18 INPUT to x72 OUTPUT - BIG-ENDIAN
BE
BM
IW
OW
H
H
H
H
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
D
C
B
A
Read from FIFO
(b) x18 INPUT to x72 OUTPUT - LITTLE-ENDIAN
4680 drw09
Figure 4. Bus-Matching Byte Arrangement (Continued)
21
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
JTAG TIMING SPECIFICATION
tTCK
t3
t4
t1
t2
TCK
TDI/
TMS
tDS
tDH
TDO
TDO
t6
tDO
TRST
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t3 = tTCKFALL
t4 = tTCKRise
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
t5
4680 drw10
Figure 5. Standard JTAG Timing
JTAG AC ELECTRICAL
CHARACTERISTICS
SYSTEM INTERFACE PARAMETERS
(vcc = 3.3V ± 5%; Tcase = 0°C to +85°C)
IDT72V7230
IDT72V7240
IDT72V7250
IDT72V7260
IDT72V7270
IDT72V7280
IDT72V7290
IDT72V72100
Parameter
Symbol
Test Conditions
Min.
Parameter
Test
Conditions
Min.
Max. Units
Data Output
tDO = Max
–
20
ns
Data Output Hold
tDOH(1)
0
–
ns
Data Input
tDS
tDH
10
–
ns
10
–
trise=3ns
tfall=3ns
Symbol
NOTE:
1. 50pf loading on external output signals.
JTAG Clock Input Period tTCK
-
100
-
ns
JTAG Clock HIGH
tTCKHIGH
-
40
-
ns
JTAG Clock Low
tTCKLOW
-
40
-
ns
(1)
JTAG Clock Rise Time
tTCKRise
-
-
5
ns
JTAG Clock Fall Time
tTCKFall
-
-
5(1)
ns
JTAG Reset
tRST
-
50
-
ns
JTAG Reset Recovery
tRSR
-
50
-
ns
NOTE:
1. Guaranteed by design.
22
Max. Units
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
The Standard JTAG interface consists of four basic elements:
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
JTAG INTERFACE
•
•
•
•
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72V7230/72V7240/
72V7250/72V7260/72V7270/72V7280/72V7290/72V72100 incorporates
the necessary tap controller and modified pad cells to implement the JTAG facility.
Note that IDT provides appropriate Boundary Scan Description Language
program files for these devices.
The following sections provide a brief description of each element. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
TMS
TCLK
TRST
P
TAP
Controller
clkDR, ShiftDR
UpdateDR
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
4680 drw11
Figure 6. Boundary Scan Architecture
THE TAP CONTROLLER
The Tap controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
TEST ACCESS PORT (TAP)
The Tap interface is a general-purpose port that provides access to the
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
23
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
1
Test-Logic
Reset
0
0
COMMERCIAL TEMPERATURE RANGE
Run-Test/
Idle
1
SelectDR-Scan
1
SelectIR-Scan
1
0
1
0
Capture-IR
1
Capture-DR
0
0 0
Shift-DR
1
Input = TMS
EXit1-DR
1
1
0
1
Exit2-DR
Exit2-IR
0
1
1
Update-DR
0
0
Pause-IR
1
1
1
Exit1-IR
0 0
Pause-DR
0
0
Shift-IR
Update-IR
1
0
4680 drw12
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Figure 7. TAP Controller State Diagram
UPDATE-DR
The shifting process has been completed. The data is latched into their
parallel outputs in this state to be accessed through the internal bus.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
EXIT1-DR / EXIT2-DR
This is a temporary controller state. If TMS is held high, a rising edge applied
to TCK while in this state causes the controller to enter the Update-DR state. This
terminates the scanning process. All test data registers selected by the current
instruction retain their previous state unchanged.
CAPTURE-DR
Data is loaded from the parallel input pins or core outputs into the Data
Register.
PAUSE-DR
This controller state allows shifting of the test data register in the serial path
between TDI and TDO to be temporarily halted. All test data registers selected
by the current instruction retain their previous state unchanged.
SHIFT-DR
The previously captured data is shifted in serially, LSB first at the rising edge
of TCLK in the TDI/TDO path and shifted out serially, LSB first at the falling edge
of TCLK towards the output.
Capture-IR, Shift-IR and Update-IR, Exit-IR and Pause-IR are
similar to Data registers. These instructions operate on the instruction registers.
24
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
THE INSTRUCTION REGISTER
The Instruction register allows an instruction to be shifted in serially into the
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at UpdateIR state.
The instruction register must contain 4 bit instruction register-based cells
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
IDT72V7230/40/50/60/70/80/90/100
JTAG DEVICE IDENTIFICATION REGISTER
JTAG INSTRUCTION REGISTER
The Instruction register allows instruction to be serially input into the device
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
•
Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
•
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e.IR3, IR2, IR1, IR0) to decode 16
different possible instructions. Instructions are decoded as follows.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
Hex
Value
0x00
0x02
0x01
0x03
0x0F
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
Instruction
Function
EXTEST
IDCODE
SAMPLE/PRELOAD
HI-Z
BYPASS
Select Boundary Scan Register
Select Chip Identification data register
Select Boundary Scan Register
JTAG
Select Bypass Register
JTAG INSTRUCTION REGISTER DECODING
The following sections provide a brief description of each instruction. For
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
THE BOUNDARY-SCAN REGISTER
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
EXTEST
The mandatory EXTEST instruction is provided for external circuity and
board level interconnection check.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is dropped in the 11-bit Manufacturer ID field.
For the IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100, the Part Number field contains the following values:
Device
IDT72V7230
IDT72V7240
IDT72V7250
IDT72V7260
IDT72V7270
IDT72V7280
IDT72V7290
IDT72V72100
COMMERCIAL TEMPERATURE RANGE
IDCODE
This instruction is provided to select Device Identification Register to read
out manufacture’s identity, part number and version number.
SAMPLE/PRELOAD
The mandatory SAMPLE/PRELOAD instruction allows data values to be
loaded onto the latched parallel outputs of the boundary-scan shift register prior
to selection of the boundary-scan test instruction. The SAMPLE instruction
allows a snapshot of data flowing from the system pins to the on-chip logic or
vice versa.
Part# Field
0x57
0x51
0x52
0x53
0x54
0x55
0x56
0x50
HIGH Z
This instruction places all the output pins on the device into a high impedance
state.
BYPASS
The Bypass instruction contains a single shift-register stage and is set to
provide a minimum-length serial path between the TDI and the TDO pins of the
device when no test operation of the device is required.
25
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
tRS
MRS
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
REN
WEN
FWFT/SI
LD
tRSS
FSEL0,
FSEL1
tRSS
BM,
OW, IW
tRSS
BE
tRSS
RM
tRSS
PFM
tRSS
IP
tRSS
RT
tRSS
SEN
If FWFT = HIGH, OR = HIGH
tRSF
EF/OR
If FWFT = LOW, EF = LOW
tRSF
If FWFT = LOW, FF = HIGH
FF/IR
If FWFT = HIGH, IR = LOW
tRSF
PAE
tRSF
PAF, HF
tRSF
Q0 - Qn
OE = HIGH
(1)
OE = LOW
4680 drw13
NOTE:
1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
Figure 8. Master Reset Timing
26
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
tRS
PRS
tRSS
tRSR
REN
tRSS
tRSR
WEN
tRSS
RT
tRSS
SEN
If FWFT = HIGH, OR = HIGH
tRSF
EF/OR
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
tRSF
FF/IR
If FWFT = HIGH, IR = LOW
tRSF
PAE
tRSF
PAF, HF
tRSF
OE = HIGH
Q0 - Qn(1)
OE = LOW
4680 drw 14
NOTE:
1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Partial Reset
is complete.
Figure 9. Partial Reset Timing
27
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
WCLK
NO WRITE
2
1
(1)
tSKEW1
tCLK
tCLKL
tCLKH
NO WRITE
COMMERCIAL TEMPERATURE RANGE
tDS
1
(1)
tSKEW1
tDH
2
tDH
tDS
DX+1
DX
D0 - Dn
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
tENH
tENH
REN
tRCSS
RCS
tA
tA
Q0 - Qn
NEXT DATA READ
DATA READ
4680 drw15
tRCSLZ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 10. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
1
RCLK
tENS
tCLKL
2
tENH
tENS
REN
tENH
tENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
LAST WORD
Q0 - Qn
tOLZ
OE
LAST WORD
tOHZ
tA
D0
D1
t OLZ
tOE
(1)
tSKEW1
WCLK
tENS
tENH
tENS
tDH
tDS
tENH
WEN
tDS
D0 - Dn
D0
tDH
D1
4680 drw16
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. RCS is LOW.
Figure 11. Read Cycle, Output Enable, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
28
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
2
1
RCLK
tENS
REN
tRCSH
tRCSS
tRCSS
tRCSS
RCS
tREF
EF
tRCSLZ
Q0 - Qn
tRCSHZ
tA
tRCSLZ
tREF
tRCSHZ
tA
LAST DATA-1
LAST DATA
tSKEW1(1)
WCLK
tENS
tENH
WEN
tDS
Dn
tDH
Dx
4680 drw 17
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. OE is LOW.
Figure 12. Read Cycle and Read Chip Select Timing (IDT Standard Mode)
29
30
W1
W2
tRCSS
1
tSKEW1(1)
tDH
2
tRCSLZ
W3
PREVIOUS DATA IN OUTPUT REGISTER
tDS
tENS
3
tREF
tA
W4
tDS
W[n +2]
W[n+3]
1
tPAES
tSKEW2(2)
2
W[n+4]
W[
D-1
]
tDS
W[
D-1
]
tHF
W[
D-1
]
W1
W[D-m-2]
tDS
W[D-m-1]
W[D-m]
1
tPAFS
W[D-m+1]
W[D-m+2]
W[D-1]
WD
4680 drw 18
tWFF
tENH
Figure 13. Write Timing (First Word Fall Through Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than tSKEW1, then OR assertion may be delayed one extra RCLK cycle.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 513 for IDT72V7230, 1,025 for IDT72V7240, 2,049 for IDT72V7250, 4,097 for IDT72V7260, 8,193 for IDT72V7270, 16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
6. First data word latency = tSKEW1 + 2*TRCLK + tREF.
IR
PAF
HF
PAE
OR
Q0 - Qn
REN
RCS
RCLK
D0 - Dn
WEN
WCLK
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
31
tDS
tENS
W1
tOHZ
WD
tENS
tWFF
tDH
tENH
W1
tOE
tA
W2
1
(1)
tSKEW1
tA
2
tWFF
W3
(2)
Wm+2
tSKEW2
W[m+3]
tA
tPAFS
W[m+4]
W[
D-1
]
tHF
W[
tA
D-1
]
W[D-n-1]
tA
W[D-n]
1
tPAES
W[D-n+1]
W[D-n+2]
W[D-1]
tA
tENS
WD
4680 drw 19
tREF
Figure 14. Read Timing (First Word Fall Through Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH.
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 513 for IDT72V7230, 1,025 for IDT72V7240, 2,049 for IDT72V7250, 4,097 for IDT72V7260, 8,193 for IDT72V7270, 16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
6. RCS = LOW.
IR
PAF
HF
PAE
OR
Q0 - Qn
OE
REN
RCLK
D0 - Dn
WEN
WCLK
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
32
tDS
tENS
W1
tRCSS
WD
tRCSHZ
tRCSH
tENS
tWFF
tDH
tENH
W2
tRCSLZ
1
(1)
tSKEW1
tA
2
tWFF
W3
(2)
Wm+2
tSKEW2
W[m+3]
tA
tPAFS
W[m+4]
W[
D-1
]
tHF
W[
tA
D-1
]
W[D-n-1]
tA
W[D-n]
1
tPAES
W[D-n+1]
W[D-n+2]
W[D-1]
tA
tENS
WD
4680 drw 20
tREF
Figure 15. Read Cycle and Read Chip Select Timing (First Word Fall Through Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH.
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 513 for IDT72V7230, 1,025 for IDT72V7240, 2,049 for IDT72V7250, 4,097 for IDT72V7260, 8,193 for IDT72V7270, 16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
6. OE = LOW.
IR
PAF
HF
PAE
OR
Q0 - Qn
RCS
REN
RCLK
D0 - Dn
WEN
WCLK
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
RCLK
2
1
tENH
tENS
COMMERCIAL TEMPERATURE RANGE
tENS
tRTS
tENH
REN
tA
Q0 - Q n
tA
tA
Wx
W x+1
W1(3)
W2
(3)
tSKEW2
1
WCLK
2
tRTS
WEN
tENS
tENH
RT
tREF
tREF
EF
tPAES
PAE
tHF
HF
tPAFS
PAF
4680 drw21
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW; RCS = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 512 for IDT72V7230, 1,024 for IDT72V7240, 2,048 for IDT72V7250, 4,096 for IDT72V7260, 8,192 for IDT72V7270, 16,384 for the IDT72V7280, 32,768 for the IDT72V7290
and 65,536 for the IDT72V72100.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 16. Retransmit Timing (IDT Standard Mode)
33
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
RCLK
tENH
tENS
1
COMMERCIAL TEMPERATURE RANGE
3
2
4
tENS
tRTS
tENH
REN
tA
Q0 - Qn
tA
Wx+1
Wx
W1
tA
(4)
W2
(4)
tA
W3
(4)
W4
tSKEW2
1
WCLK
2
tRTS
WEN
tENS
tENH
RT
tREF
tREF
OR
tPAES
PAE
tHF
HF
tPAFS
PAF
4680 drw22
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280, 32,769 for
the IDT72V7290 and 65,537 for the IDT72V72100.
3. OE = LOW; RCS = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 17. Retransmit Timing (FWFT Mode)
34
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
RCLK
1
2
COMMERCIAL TEMPERATURE RANGE
3
tENH
tENS
REN
tA
Q0 - Qn
tA
tA
Wx
W0(3)
Wx+1
tA
tA
W2(3)
W1(3)
W3
tSKEW2
1
WCLK
2
tRTS
WEN
tENS
tENH
RT
EF
tPAES
PAE
tHF
HF
tPAFS
PAF
4680 drw23
NOTES:
1. If the part is empty at the point of Retransmit, the empty flag (EF) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. OE = LOW; RSC = LOW.
3. W0 = first word written to the FIFO after Master Reset, W1 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 512 for IDT72V7230, 1,024 for IDT72V7240, 2,048 for IDT72V7250, 4,096 for IDT72V7260, 8,192 for IDT72V7270, 16,384 for the IDT72V7280, 32,768 for the IDT72V7290
and 65,536 for the IDT72V72100.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 18. Zero Latency Retransmit Timing (IDT Standard Mode)
35
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
1
RCLK
2
COMMERCIAL TEMPERATURE RANGE
4
3
5
tENH
tENS
REN
tA
Q0 - Qn
Wx
tA
Wx+1
tA
tA
W1
W2
(4)
W3
(4)
tA
W4
(4)
W5
tSKEW2
1
WCLK
2
tRTS
WEN
tENS
tENH
RT
OR
tPAES
PAE
tHF
HF
tPAFS
PAF
4680 drw24
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280, 32,769 for
the IDT72V7290 and 65,537 for the IDT72V72100.
3. OE = LOW; RCS = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 19. Zero Latency Retransmit Timing (FWFT Mode)
SCLK
t ENS
tENH
t ENH
SEN
tLDS
tLDH
tLDH
LD
tDH
tDS
SI
BIT 0
BIT X
(1)
BIT 0
BIT X
FULL OFFSET
EMPTY OFFSET
(1)
4680 drw25
NOTE:
1. X = 9 for the IDT72V7230, X= 10 for the IDT72V7240, X = 11 for the IDT72V7250, X = 12 for the IDT72V7260, X = 13 for the IDT72V7270, X = 14 for the IDT72V7280,
X = 15 for the IDT72V7290 and X = 16 for the IDT72V72100.
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
36
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
t CLK
t CLKH
t CLKL
WCLK
t LDS
t LDH
t LDH
t ENS
t ENH
t ENH
LD
WEN
t DS
t DH
t DH
PAF
OFFSET
PAE
OFFSET
D0 - Dn
4680 drw26
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t CLK
t CLKH
t CLKL
RCLK
t LDS
t LDH
t LDH
LD
t ENS
t ENH
t ENH
REN
tA
tA
PAE OFFSET
DATA IN OUTPUT REGISTER
Q0 - Q16
PAF OFFSET
4680 drw27
NOTES:
1. OE = LOW; RCS = LOW.
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLKL
tCLKL
WCLK
1
tENS
1
2
2
tENH
WEN
tPAFS
PAF
tPAFS
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
tSKEW2
(3)
D-(m+1) words
in FIFO(2)
RCLK
tENS
tENH
REN
4680 drw 28
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the IDT72V7250, 4,096 for the IDT72V7260 and 8,192 for the IDT72V7270, 16,384 for
the IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the IDT72V72100.
In FWFT mode: D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280,
32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
37
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
tCLKH
COMMERCIAL TEMPERATURE RANGE
tCLKL
WCLK
tENS
tENH
WEN
PAE
n words in FIFO (2),
n+1 words in FIFO (3)
tSKEW2 (4)
RCLK
n+1 words in FIFO
n+2 words in FIFO
tPAES
1
2
n words in FIFO (2),
n+1 words in FIFO (3)
(2)
,
(3)
tPAES
1
tENS
2
tENH
REN
4680 drw29
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS is LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAFA
PAF
D - m words
in FIFO
D - (m + 1) words in FIFO
D - (m + 1) words
in FIFO
tPAFA
RCLK
tENS
REN
4680 drw30
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the IDT72V7250, 4,096 for the IDT72V7260, 8,192 for the IDT72V7270, 16,384 for the
IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the IDT72V72100.
In FWFT Mode: D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280,
32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
38
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
tCLKH
COMMERCIAL TEMPERATURE RANGE
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
n words in FIFO(2),
n + 1 words in FIFO(3)
PAE
n + 1 words in FIFO(2),
n + 2 words in FIFO(3)
n words in FIFO(2),
n + 1 words in FIFO(3)
tPAEA
RCLK
tENS
REN
4680 drw 31
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
tHF
HF
[
D/2 words in FIFO(1),
D-1
(2)
2 + 1 words in FIFO
[
]
D/2 + 1 words in FIFO(1),
D-1
(2)
2 + 2 words in FIFO
]
D/2 words in FIFO(1),
(2)
[ D-1
2 + 1] words in FIFO
tHF
RCLK
tENS
REN
4680 drw32
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the IDT72V7250, 4,096 for the IDT72V7260, 8,192 for the
IDT72V7270, 16,384 for the IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the IDT72V72100.
2. In FWFT mode: D = maximum FIFO depth. D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270,
16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
Figure 27. Half-Full Flag Timing (IDT Standard and FWFT Modes)
39
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every FIFO.
Figure 28 demonstrates a width expansion using two IDT72V7230/
72V7240/72V7250/72V7260/72V7270/72V7280/72V7290/72V72100 devices. D0 - D71 from each device form a 144-bit wide input bus and Q0-Q71
from each device form a 144-bit wide output bus. Any word width can be attained
by adding additional IDT72V7230/72V7240/72V7250/72V7260/72V7270/
72V7280/72V7290/72V72100 devices.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m+n
DATA IN
D0 - Dm
m
n
READ CLOCK (RCLK)
READ SHIP SELECT (RCS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
IDT
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
FIFO
#1
IDT
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
FIFO
#2
m
Q0 - Qm
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
n
Qm+1 - Qn
GATE
m+n
DATA OUT
4680 drw 33
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 28. Block Diagram of 512 x 144, 1,024 x 144, 2,048 x 144, 4,096 x 144, 8,192 x 144, 16,384 x 144, 32,768 x 144 and 65,536 x 144 Width Expansion
40
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIAL TEMPERATURE RANGE
FWFT/SI
TRANSFER CLOCK
WRITE CLOCK
WRITE ENABLE
INPUT READY
DATA IN
FWFT/SI
WCLK
WEN
IR
n
Dn
IDT
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
WCLK
RCLK
OR
WEN
REN
RCS
OE
IR
GND
n
Qn
Dn
FWFT/SI
RCLK
IDT
RCS
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
READ CLOCK
READ CIP SELECT
REN
READ ENABLE
OR
OUTPUT READY
OE
OUTPUT ENABLE
n
DATA OUT
Qn
4680 drw34
Figure 29. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72, 32,768 x 72, 65,572 x 72 and 131,072 x 72 Depth Expansion
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
The "ripple down" delay is only noticeable for the first word written to an empty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the first
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72V7230 can easily be adapted to applications requiring depths
greater than 512, 1,024 for the IDT72V7240, , 2,048 for the IDT72V7250,
4,096 for the IDT72V7260, 8,192 for the IDT72V7270, 16,384 for the
IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the IDT72V72100
with an 72-bit bus width. In FWFT mode, the FIFOs can be connected in series
(the data outputs of one FIFO connected to the data inputs of the next) with no
external logic necessary. The resulting configuration provides a total depth
equivalent to the sum of the depths associated with each single FIFO. Figure
29 shows a depth expansion using two IDT72V7230/72V7240/72V7250/
72V7260/72V7270/72V7280/72V7290/72V72100 devices.
Care should be taken to select FWFT mode during Master Reset for all FIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain – no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the
data word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR of
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the tSKEW1
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. Note that extra cycles should be added for the possibility that the tSKEW1
41
ORDERING INFORMATION
IDT
XXXXX
X
XX
X
Device Type
Power
Speed
Package
X
Process /
Temperature
Range
NOTE:
1. Industrial temperature range is available by special order.
BLANK
Commercial (0°C to +70°C)
BB
Fine Pitch Ball Grid Array (PBGA, BB256−1)
10
15
Commercial
L
Low Power
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
512 x 72

1,024 x 72 
2,048 x 72 
4,096 x 72 
8,192 x 72 
16,384 x 72 
32,768 x 72 
65,536 x 72 
Clock Cycle Time (tCLK)
Speed in Nanoseconds
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
4680 drw35
DATASHEET DOCUMENT HISTORY
06/01/2000
11/01/2000
01/10/2001
04/12/2001
05/01/2001
10/04/2001
12/16/2002
02/11/2003
09/29/2003
12/17/2003
pgs.
pgs.
pg.
pgs.
pg.
pg.
pgs.
pgs.
pg.
pg.
1, 2, 3, 7, 33, 34, 34, 35, 38, 41, and 42.
1, 2, and 42.
7.
3, 4, 5, 17, 26, and 27.
23.
36.
1, 4, 6, 22, 24, and 41.
6, and 24.
7.
35.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
42
for Tech Support:
408-330-1753
email: [email protected]