HUF75631SK8
Data Sheet
December 2001
5.5A, 100V, 0.039 Ohm, N-Channel,
UltraFET® Power MOSFET
Packaging
JEDEC MS-012AA
Features
BRANDING DASH
5
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
1
2
3
• Ultra Low On-Resistance
- rDS(ON) = 0.039Ω, VGS = 10V
4
Symbol
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
SOURCE (1)
DRAIN (8)
SOURCE (2)
DRAIN (7)
SOURCE (3)
DRAIN (6)
GATE (4)
DRAIN (5)
Ordering Information
PART NUMBER
HUF75631SK8
PACKAGE
MS-012AA
BRAND
75631SK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF75631SK8T.
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
HUF75631SK8
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
100
V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
100
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
Drain Current
Continuous (TA= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
5.5
3.5
Figure 4
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
20
W
mW/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 150
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
NOTES:
1. TJ = 25oC to 150oC.
2. 50oC/W measured using FR-4 board with 0.76 in 2 (490.3 mm2) copper pad at 10 second.
3. 152oC/W measured using FR-4 board with 0.054 in 2 (34.8 mm2) copper pad at 1000 seconds
4. 189oC/W measured using FR-4 board with 0.0115 in 2 (7.42 mm2) copper pad at 1000 seconds
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75631SK8 Rev. B
HUF75631SK8
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
100
-
-
V
VDS = 95V, VGS = 0V
-
-
1
µA
VDS = 90V, VGS = 0V, TA = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 11)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
Drain to Source On Resistance
rDS(ON)
ID = 5.5A, V GS = 10V (Figure 9)
-
0.033
0.039
Ω
Pad Area = 0.76 in2 (490.3 mm2) (Note 2)
(Figures 20, 21)
-
-
50
oC/W
Pad Area = 0.054 in2 (34.8 mm2) (Note 3)
(Figures 20, 21)
-
-
152
oC/W
Pad Area = 0.0115 in2 (7.42 mm2)(Note 4)
(Figures 20, 21)
-
-
189
oC/W
VDD = 50V, ID = 5.5A
VGS = 10V, RGS = 6.8Ω
(Figures 18, 19)
-
-
50
ns
-
11
-
ns
tr
-
23
-
ns
td(OFF)
-
39
-
ns
tf
-
31
-
ns
tOFF
-
-
105
ns
-
66
79
nC
-
35
43
nC
-
2.4
2.9
nC
THERMAL SPECIFICATIONS
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
tON
td(ON)
GATE CHARGE SPECIFICATIONS
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Total Gate Charge
VDD = 50V, ID = 5.5A,
Ig(REF) = 1.0mA
(Figures 13, 16, 17)
Gate to Source Gate Charge
Qgs
-
4.75
-
nC
Gate to Drain “Miller” Charge
Qgd
-
12
-
nC
-
1225
-
pF
-
330
-
pF
-
105
-
pF
MIN
TYP
MAX
UNITS
ISD = 5.5 A
-
-
1.25
V
ISD = 2.5 A
-
-
1.00
V
trr
ISD = 5.5 A, dISD/dt = 100A/µs
-
-
96
ns
QRR
ISD = 5.5 A, dISD/dt = 100A/µs
-
-
310
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2001 Fairchild Semiconductor Corporation
SYMBOL
VSD
TEST CONDITIONS
HUF75631SK8 Rev. B
HUF75631SK8
1.2
6
1.0
5
VGS = 10V, RθJA = 50oC/W
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
0.2
4
3
2
1
0
0
25
50
75
125
100
0
150
25
50
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
ZθJA, NORMALIZED
THERMAL IMPEDANCE
10
1
75
100
150
125
TA, AMBIENT TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 50oC/W
PDM
0.1
t1
t2
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
RθJA = 50oC/W
100
VGS = 10V
I = I25
150 - TA
125
10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF75631SK8 Rev. B
HUF75631SK8
Typical Performance Curves
(Continued)
100
200
RθJA
= 50oC/W
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
10ms
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
0.1
100
10
1
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10
STARTING TJ = 25oC
STARTING TJ = 150oC
1
0.01
200
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
40
VGS = 20V
VGS = 10V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
50
30
20
TJ = 150oC
10
TJ = 25oC
TJ = -55oC
0
2
3
4
5
VGS, GATE TO SOURCE VOLTAGE (V)
40
VGS =5V
30
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
10
0
0
6
FIGURE 7. TRANSFER CHARACTERISTICS
4
1
2
3
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 8. SATURATION CHARACTERISTICS
2.5
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
VGS = 7V
VGS = 6V
2.0
1.5
1.0
1.0
0.8
VGS = 10V, ID = 5.5A
0.5
0.6
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
160
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
HUF75631SK8 Rev. B
HUF75631SK8
Typical Performance Curves
(Continued)
3000
ID = 250µA
CISS = CGS + CGD
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
1.1
1.0
1000
CRSS = CGD
COSS ≅ CDS + CGD
100
VGS = 0V, f = 1MHz
0.9
-80
-40
0
40
80
120
30
0.1
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VGS , GATE TO SOURCE VOLTAGE (V)
10
1.0
10
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VDD = 50V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 5.5A
ID = 2A
2
0
0
10
20
30
Qg, GATE CHARGE (nC)
40
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
©2001 Fairchild Semiconductor Corporation
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
HUF75631SK8 Rev. B
HUF75631SK8
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
VGS = 10V
VGS
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
VDD
10%
0
-
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
10%
50%
50%
PULSE WIDTH
FIGURE 19. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal resistance RθJA (oC/W) must be reviewed
to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as the
basis for establishing the rating of the part.
( T JM – TA )
P
= ------------------------------DM
Z θJA
(EQ. 1)
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
©2001 Fairchild Semiconductor Corporation
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 20
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
HUF75631SK8 Rev. B
HUF75631SK8
Displayed on the curve are RθJA values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, PDM.
Thermal resistances corresponding to other copper areas can
be obtained from Figure 23 or by calculation using Equation 2.
RθJA is defined as the natural log of the area times a coefficient
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
R θJA = 83.2 – 23.6 ×
ln ( Area )
(EQ. 2)
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
240
RθJA = 83.2 - 23.6*ln(AREA)
200
RθJA (oC/W)
junction temperature or power dissipation. Pulse applications
can be evaluated using the Fairchild device Spice thermal
model or manually utilizing the normalized maximum
transient thermal impedance curve.
189oC/W - 0.0115in2
152oC/W - 0.054in2
160
120
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
80
0.1
0.01
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
150
ZθJA, THERMAL
IMPEDANCE (oC/W)
120
90
COPPER BOARD AREA - DESCENDING ORDER
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.00 in2
60
30
0
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA
©2001 Fairchild Semiconductor Corporation
HUF75631SK8 Rev. B
HUF75631SK8
PSPICE Electrical Model
.SUBCKT HUF75631SK8 2 1 3 ;
rev 29 July 1999
CA 12 8 1.88e-9
CB 15 14 1.88e-9
CIN 6 8 1.12e-9
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
DBREAK
+
RSLC2
5
51
ESLC
11
-
RDRAIN
6
8
ESG
IT 8 17 1
LGATE
GATE
1
+
50
EVTHRES
+ 19 8
+
EVTEMP
RGATE + 18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
8
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.86e-2
RGATE 9 20 1.88
RLDRAIN 2 5 10
RLGATE 1 9 11.2
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 7.55e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 114.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 1.12e-9
LSOURCE 3 7 1.29e-10
DRAIN
2
5
12
S2A
13
8
14
13
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*76),2))}
.MODEL DBODYMOD D (IS = 1.02e-12 RS = 5.39e-3 TRS1 = 1.01e-3 TRS2 = 9.97e-7 CJO = 1.49e-9 TT = 9.98e-8 M = 0.58)
.MODEL DBREAKMOD D (RS = 3.03e- 1TRS1 = 2.37e- 3TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 1.44e- 9IS = 1e-3 0M = 0.80)
.MODEL MMEDMOD NMOS (VTO = 3.04 KP = 1.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.88)
.MODEL MSTROMOD NMOS (VTO = 3.47 KP = 40 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.71 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 18.8 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.09e- 3TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 9.09e-3 TC2 = 2.74e-5)
.MODEL RSLCMOD RES (TC1 = 5.00e-3 TC2 = 0)
.MODEL RSOURCEMOD RES (TC1 = 1.00e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.66e-3 TC2 = -1.01e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.38e- 3TC2 = 1.39e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -5.5 VOFF= -4.0)
VON = -4.0 VOFF= -5.5)
VON = -1.0 VOFF= 0.0)
VON = 0.0 VOFF= -1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF75631SK8 Rev. B
HUF75631SK8
SABER Electrical Model
REV 29 July 1999
template huf75631sk8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.02e-12, cjo = 1.49e-9, tt = 9.98e-8, m = 0.58)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.44e-9, is = 1e-30, m = 0.80 )
m..model mmedmod = (type=_n, vto = 3.04, kp = 1.75, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.47, kp = 40, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.71, kp = 0.08, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -4)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -4, voff = -5.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -1)
LDRAIN
DPLCAP
10
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
72
ISCL
c.ca n12 n8 = 1.88e-9
c.cb n15 n14 = 1.88e-9
c.cin n6 n8 = 1.12e-9
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.12e-9
l.lsource n3 n7 = 1.29e-10
EVTEMP
RGATE + 18 22
9
20
MWEAK
DBODY
EBREAK
+
17
18
MMED
MSTRO
CIN
71
11
16
6
RLGATE
-
8
LSOURCE
7
SOURCE
3
RSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.09e-3, tc2 = 0
res.rdbody n71 n5 = 5.39e-3, tc1 = 1.01e-3, tc2 = 9.97e-7
res.rdbreak n72 n5 = 3.03e-1, tc1 = 2.37e-3, tc2 = 0
res.rdrain n50 n16 = 1.86e-2, tc1 = 9.09e-3, tc2 = 2.74e-5
res.rgate n9 n20 = 1.88
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 11.2
res.rlsource n3 n7 = 1.29
res.rslc1 n5 n51 = 1e-6, tc1 = 5.00e-3, tc2 = 0
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 7.55e-3, tc1 = 1.00e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -2.38e-3, tc2 = 1.39e-6
res.rvthres n22 n8 = 1, tc1 = -2.66e-3, tc2 = -1.01e-5
21
RDBODY
DBREAK
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
DRAIN
2
5
RLSOURCE
S1A
12
S2A
14
13
13
8
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
+
6
8
EGS
19
CB
+
-
-
IT
14
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 114.8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/76))** 2))
}
}
©2001 Fairchild Semiconductor Corporation
HUF75631SK8 Rev. B
HUF75631SK8
SPICE Thermal Model
th
JUNCTION
REV 28 July 1999
HUF75631SK8
Copper Area = 0.04 in2
RTHERM1
CTHERM1 th 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 1.2e-1
CTHERM7 3 2 0.5
CTHERM8 2 tl 1.3
CTHERM1
8
RTHERM2
CTHERM2
7
RTHERM3
RTHERM1 th 8 0.1
RTHERM2 8 7 0.5
RTHERM3 7 6 1.0
RTHERM4 6 5 5.0
RTHERM5 5 4 8.0
RTHERM6 4 3 26
RTHERM7 3 2 39
RTHERM8 2 tl 55
CTHERM3
6
RTHERM4
CTHERM4
5
RTHERM5
SABER Thermal Model
CTHERM5
4
Copper Area = 0.04 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 2.0e-3
ctherm.ctherm2 8 7 = 5.0e-3
ctherm.ctherm3 7 6 = 1.0e-2
ctherm.ctherm4 6 5 = 4.0e-2
ctherm.ctherm5 5 4 = 9.0e-2
ctherm.ctherm6 4 3 = 1.2e-1
ctherm.ctherm7 3 2 = 0.5
ctherm.ctherm8 2 tl = 1.3
RTHERM6
CTHERM6
3
RTHERM7
CTHERM7
2
RTHERM8
rtherm.rtherm1 th 8 = 0.1
rtherm.rtherm2 8 7 = 0.5
rtherm.rtherm3 7 6 = 1.0
rtherm.rtherm4 6 5 = 5.0
rtherm.rtherm5 5 4 = 8.0
rtherm.rtherm6 4 3 = 26
rtherm.rtherm7 3 2 = 39
CTHERM8
tl
CASE
rtherm.rtherm8 2 tl = 55
}
TABLE 1. THERMAL MODELS
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.0 in2
CTHERM6
1.2e-1
1.5e-1
2.0e-1
2.0e-1
2.0e-1
CTHERM7
0.5
1.0
1.0
1.0
1.0
CTHERM8
1.3
2.8
3.0
3.0
3.0
RTHERM6
26
20
15
13
12
RTHERM7
39
24
21
19
18
RTHERM8
55
38.7
31.3
29.7
25
COMPONENT
©2001 Fairchild Semiconductor Corporation
HUF75631SK8 Rev. B
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Definition
Advance Information
Formative or
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Rev. H4