CD74AC153, CD74ACT153 Data sheet acquired from Harris Semiconductor SCHS237 Dual 4-Input Multiplexer September 1998 Features Description • Buffered Inputs The CD74AC153 and CD74ACT153 are dual 4-input multiplexers that utilize the Harris Advanced CMOS Logic technology. One of the four sources for each section is selected by the common Select inputs, S0 and S1. When the Enable inputs (1E, 2E) are HIGH, the outputs are in the low state. • Typical Propagation Delay - 6.3ns at VCC = 5V, TA = 25oC, CL = 50pF • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 [ /Title (CD74 AC153 , CD74 ACT15 3) /Subject (Dual 4-Input Multiplexer) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS ) /Creator () /DOCI NFO pdfmark Ordering Information • SCR-Latchup-Resistant CMOS Process and Circuit Design PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption CD74AC153E 0 to 70oC, -40 to 85, 16 Ld PDIP -55 to 125 E16.3 • Balanced Propagation Delays CD74ACT153E E16.3 • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply 0 to 70oC, -40 to 85, 16 Ld PDIP -55 to 125 CD74AC153M96 0 to 70oC, -40 to 85, 16 Ld SOIC -55 to 125 M16.15 CD74ACT153M 0 to 70oC, -40 to 85, 16 Ld SOIC -55 to 125 M16.15 • ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinout CD74AC153, CD74ACT153 (PDIP, SOIC) TOP VIEW 1E 1 16 VCC S1 2 15 2E 1I3 3 14 S0 1I2 4 13 2I3 1I1 5 12 2I2 1I0 6 11 2I1 1Y 7 10 2I0 GND 8 9 2Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. Copyright © Harris Corporation 1998 1 File Number 1966.1 CD74AC153, CD74ACT153 Functional Diagram 1 1E 6 1I0 5 1I1 7 SEL/MUX 4 1Y 1I2 3 1I3 S0 S1 2I0 2I1 2I2 2I3 2E 14 2 10 11 9 SEL/MUX 12 2Y 13 15 GND = 8 VCC = 16 TRUTH TABLE SELECT INPUTS DATA INPUTS ENABLE INPUTS OUTPUT S1 S0 nI0 nI1 nI2 nI3 nE nY X X X X X X H L L L L X X X L L L L H X X X L H L H X L X X L L L H X H X X L H H L X X L X L L H L X X H X L H H H X X X L L L H H X X X H L H Select inputs S1 and S0 are common to both sections. H = High Level, L = Low Level, X = Don’t Care, Z = High Impedance. 2 CD74AC153, CD74ACT153 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA Thermal Resistance (Typical, Note 5) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 4) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. For up to 4 outputs per device, add ±25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VIH - - 1.5 1.2 - 1.2 - 1.2 - V AC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH - VIH or VIL 3 2.1 - 2.1 - 2.1 - V 5.5 3.85 - 3.85 - 3.85 - V 1.5 - 0.3 - 0.3 - 0.3 V 3 - 0.9 - 0.9 - 0.9 V 5.5 - 1.65 - 1.65 - 1.65 V -0.05 1.5 1.4 - 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - 4.4 - V -4 3 2.58 - 2.48 - 2.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V - 3 CD74AC153, CD74ACT153 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V Input Leakage Current Quiescent Supply Current MSI ACT TYPES Low Level Output Voltage Input Leakage Current Quiescent Supply Current MSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 - 0.1 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 2.4 - 2.8 - 3 mA NOTES: 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC. ACT Input Load Table INPUT UNIT LOAD S0, S1, nI0, nI1 1 nE 0.47 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. 4 CD74AC153, CD74ACT153 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 227 - - 250 ns 3.3 (Note 9) 7.2 - 25.5 7 - 28 ns 5 (Note 10) 5.2 - 18.2 5 - 20 ns 1.5 - - 151 - - 166 ns 3.3 4.8 - 16.9 4.7 - 18.6 ns 5 3.4 - 12.1 3.3 - 13.3 ns 1.5 - - 134 - - 148 ns 3.3 4.3 - 15 4.1 - 16.5 ns 5 3.1 - 10.7 3 - 11.8 ns CI - - - 10 - - 10 pF CPD (Note 11) - - 93 - - 93 - pF Propagation Delay, S0, S1, to Y tPLH, tPHL 5 (Note 10) 5.7 - 20 5.5 - 22 ns Propagation Delay, nI to Y tPLH, tPHL 5 4.6 - 16.4 4.5 - 18 ns Propagation Delay, nE to Y tPLH, tPHL 5 3.2 - 11.5 3.2 - 12.6 ns CI - - - 10 - - 10 pF CPD (Note 11) - - 93 - - 93 - pF PARAMETER AC TYPES Propagation Delay, S0, S1, to Y Propagation Delay, nI to Y Propagation Delay, nE to Y Input Capacitance Power Dissipation Capacitance tPLH, tPHL tPLH, tPHL ACT TYPES Input Capacitance Power Dissipation Capacitance NOTES: 8. Limits tested at 100%. 9. 3.3V Min at 3.6V, Max at 3V. 10. 5V Min at 5.5V, Max at 4.5V. 11. CPD is used to determine the dynamic power consumption per multiplexer. AC: PD = VCC2 fi (CPD + CL) ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. 5 CD74AC153, CD74ACT153 tr = 3ns tf = 3ns INPUT LEVEL 90% OUTPUT DISABLE VS 10% GND tPZL tPLZ VS 0.2VCC OUTPUT: LOW TO OFF TO LOW tPHZ tPZH VOH (≠ VCC) 0.8 VCC VS OUTPUT: HIGH TO OFF TO HIGH OUTPUTS ENABLED OUTPUTS DISABLED OTHER INPUTS (TIED HIGH OR LOW) OUTPUT DISABLE OUTPUTS ENABLED GND (tPHZ, tPZH) OPEN (tPHL, tPLH) 2 VCC (tPLZ, tPZL) (OPEN DRAIN) 500Ω† RL DUT WITH THREESTATE OUTPUT CL 50pF VOL (≠ GND) OUT 500Ω† RL †FOR AC SERIES ONLY: WHEN VCC = 1.5V, RL = 1kΩ FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT tr = 3ns tf = 3ns E 90% VS 10% I OR S VS OUTPUT Y tPHL tPLH FIGURE 2. PROPAGATION DELAY TIMES AND TEST CIRCUIT OUTPUT RL (NOTE) 500Ω DUT OUTPUT LOAD CL 50pF NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. CD74AC CD74ACT VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC Input Level FIGURE 3. PROPAGATION DELAY TIMES 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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