Revised March 2000 DM74LS390 Dual 4-Bit Decade Counter General Description Features Each of these monolithic circuits contains eight masterslave flip-flops and additional gating to implement two individual four-bit counters in a single package. The DM74LS390 incorporates dual divide-by-two and divideby-five counters, which can be used to implement cycle lengths equal to any whole and/or cumulative multiples of 2 and/or 5 up to divide-by-100. When connected as a bi-quinary counter, the separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final output stage. The DM74LS390 has parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system-timing signals. ■ Dual version of the popular DM74LS90 ■ DM74LS390...individual clocks for A and B flip-flops provide dual ÷ 2 and ÷ 5 counters ■ Direct clear for each 4-bit counter ■ Dual 4-bit version can significantly improve system densities by reducing counter package count by 50% ■ Typical maximum count frequency...35 MHz ■ Buffered outputs reduce possibility of collector commutation Ordering Code: Order Number Package Number Package Description DM74LS390M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS390N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation DS006433 www.fairchildsemi.com DM74LS390 Dual 4-Bit Decade Counter August 1986 DM74LS390 Function Tables Bi-Quinary (5-2) BCD Count Sequence (Each Counter) (Note 1) Count (Each Counter) (Note 2) Outputs QD QC QB QA 0 L L L L 1 L L L 2 L L 3 L L 4 L H 5 L H 6 L H 7 L H 8 H 9 H Count QD QC 0 L L L L H 1 L L L H H L 2 L L H L H H 3 L L H H L L 4 L H L L L H 5 H L L L H L 6 H L L H H H 7 H L H L L L L 8 H L H H L L H 9 H H L L H = HIGH Level L = LOW Level Note 1: Output QA is connected to input B for BCD count. Note 2: Output QD is connected to input A for Bi-quinary count. Logic Diagram www.fairchildsemi.com Outputs QA 2 QB Supply Voltage 7V Note 3: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Input Voltage Clear 7V A or B 5.5V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 4) fCLK tW Clock Frequency (Note 5) Pulse Width (Note 4) V 2 V A to QA 0 25 B to QB 0 20 A to QA 0 20 B to QB 0 15 A 20 B 25 Clear HIGH 20 tREL Clear Release Time (Note 6)(Note 7) TA Free Air Operating Temperature MHz MHz ns 25↓ ns 0 °C 70 Note 4: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 5: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 6: The symbol (↓) indicates the falling edge of the clear pulse is used for reference. Note 7: TA = 25°C and VCC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Min 2.7 IOL = 4 mA, VCC = Min II IIH IIL Typ (Note 8) Max Units −1.5 V 3.4 V 0.35 0.5 0.25 0.4 Input Current @ Max VCC = Max, VI = 7V Clear Input Voltage VCC = Max A 0.2 VI = 5.5V B 0.4 0.1 HIGH Level VCC = Max Clear 20 Input Current VI = 2.7V A 40 B 80 LOW Level VCC = Max, VI = 0.4V Input Current IOS Short Circuit Output Current VCC = Max (Note 9) ICC Supply Current VCC = Max (Note 10) V Clear −0.4 A −1.6 B −2.4 −20 15 mA µA mA −100 mA 26 mA Note 8: All typicals are at VCC = 5V, TA = 25°C. Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 10: ICC is measured with all outputs OPEN, both CLEAR inputs grounded following momentary connection to 4.5 and all other inputs grounded. 3 www.fairchildsemi.com DM74LS390 Absolute Maximum Ratings(Note 3) DM74LS390 Switching Characteristics at VCC = 5V and TA = 25°C RL = 2 kΩ Symbol fMAX tPLH Parameter Min Maximum Clock A to QA 25 20 Frequency B to QB 20 15 Propagation Delay Time Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output www.fairchildsemi.com Max CL = 50 pF To (Output) LOW-to-HIGH Level Output tPHL CL = 15 pF From (Input) Min Units Max MHz A to QA 20 24 ns A to QA 20 30 ns A to QC 60 81 ns A to QC 60 81 ns B to QB 21 27 ns B to QB 21 33 ns B to QC 39 51 ns B to QC 39 54 ns B to QD 21 27 ns B to QD 21 33 ns Clear to Any Q 39 45 ns 4 DM74LS390 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com DM74LS390 Dual 4-Bit Decade Counter 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 www.fairchildsemi.com