LINER LTC1276BCN 12-bit, 300ksps sampling a/d converters with reference Datasheet

LTC1273
LTC1275/LTC1276
12-Bit, 300ksps Sampling
A/D Converters with Reference
U
DESCRIPTIO
FEATURES
■
■
■
■
■
■
■
■
■
■
■
Single Supply 5V or ±5V Operation
300ksps Sample Rate
75mW (Typ) Power Dissipation
On-Chip 25ppm/°C Reference
Internal Synchronized Clock; No Clock Required
High Impedance Analog Input
70dB S/(N + D) and 77dB THD at Nyquist
±1/2LSB INL and ±3/4LSB DNL Max (A Grade)
ESD Protected On All Pins
24-Pin Narrow DIP and SOL Packages
Variety of Input Ranges:
0V to 5V (LTC1273)
±2.5V (LTC1275)
±5V (LTC1276)
The LTC1273/LTC1275/LTC1276 are 300ksps, sampling
12-bit A/D converters that draw only 75mW from single
5V or ±5V supplies. These easy-to-use devices come
complete with 600ns sample-and-holds, precision references and internally trimmed clocks. Unipolar and bipolar conversion modes provide flexibility for various applications. They are built with LTBiCMOSTM switched capacitor technology.
These devices have 25ppm/°C (max) internal references.
The LTC1273 converts 0V to 5V unipolar inputs from a
single 5V supply. The LTC1275/LTC1276 convert ±2.5V
and ±5V respectively from ±5V supplies. Maximum DC
specifications include ±1/2LSB INL, ±3/4LSB DNL and
25ppm/°C full scale drift over temperature. Outstanding
AC performance includes 70dB S/(N + D) and 77dB THD
at the Nyquist input frequency of 150kHz.
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APPLICATI
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■
S
The internal clock is trimmed for 2.7µs maximum conversion time. The clock automatically synchronizes to each
sample command eliminating problems with asynchronous clock noise found in competitive devices. A high
speed parallel interface eases connections to FIFOs, DSPs
and microprocessors.
High Speed Data Acquisition
Digital Signal Processing
Multiplexed Data Acquisition Systems
Audio and Telecom Processing
Spectrum Analysis
LTBiCMOSTM is a trademark of Linear Technology Corporation
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TYPICAL APPLICATI
Effective Bits and Signal to (Noise + Distortion)
vs Input Frequency
Single 5V Supply, 300ksps, 12-Bit Sampling A/D Converter
+
10µF
5V
24
12
23
11
22
21
10µF
0.1µF
10
9
µP CONTROL
LINES
19
18
17
16
68
62
NYQUIST
FREQUENCY
56
50
8
7
6
5
4
15
3
14
2
1
13
74
S/(N + D) (dB)
20
+
EFFECTIVE BITS
2.42V
VREF
OUTPUT
LTC1273
ANALOG INPUT 1 A
VDD
(0V TO 5V) 2 IN
VREF
NC
3
BUSY
AGND
0.1µF
4
CS
D11
5
RD
D10
6
HBEN
D9
7
NC
D8
8
NC
D7
9
D0/8
D6
10
8- OR 12-BIT
D1/9
D5
PARALLEL BUS
11
D2/10
D4
12
D3/11
DGND
0
10k
fSAMPLE = 300kHz
100k
INPUT FREQUENCY (Hz)
1M
2M
LTC1273/75/76 • TA02
LTC1273/75/76 • TA01
1
LTC1273
LTC1275/LTC1276
W W
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AXI U
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ABSOLUTE
RATI GS
(Notes 1 and 2)
Supply Voltage (VDD) .............................................. 12V
Negative Supply Voltage (VSS)
LTC1275/LTC1276.................................. – 6V to GND
Total Supply Voltage (VDD to VSS)
LTC1275/LTC1276............................................... 12V
Analog Input Voltage (Note 3)
LTC1273 .................................... – 0.3V to VDD + 0.3V
LTC1275/LTC1276.............. VSS – 0.3V to VDD + 0.3V
Digital Input Voltage (Note 4)
LTC1273 ................................................ – 0.3V to 12V
LTC1275/LTC1276......................... VSS – 0.3V to 12V
Digital Output Voltage (Note 3)
LTC1273 .................................... – 0.3V to VDD + 0.3V
LTC1275/LTC1276 .............. VSS – 0.3V to VDD + 0.3V
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1273AC, LTC1273BC, LTC1275AC
LTC1275BC, LTC1276AC, LTC1276BC .... 0°C to 70°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
W
U
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PACKAGE/ORDER I FOR ATIO
ORDER
PART NUMBER
TOP VIEW
AIN
1
24 VDD
VREF
2
23 NC
AGND
3
22 BUSY
D11
4
21 CS
D10
5
20 RD
D9
6
19 HBEN
D8
7
18 NC
D7
8
17 NC
D6
9
16 D0/8
D5 10
15 D1/9
D4 11
14 D2/10
DGND 12
13 D3/11
LTC1273ACN
LTC1273BCN
LTC1273ACS
LTC1273BCS
(For MIL Grade:
Contact Factory)
AIN
1
24 VDD
VREF
2
23 VSS
AGND
3
22 BUSY
D11
4
21 CS
D10
5
20 RD
D9
6
19 HBEN
D8
7
18 NC
D7
8
17 NC
D6
9
16 D0/8
D5 10
15 D1/9
D4 11
14 D2/10
DGND 12
13 D3/11
N PACKAGE
S PACKAGE
24-LEAD PLASTIC DIP 24-LEAD PLASTIC SOL
N PACKAGE
S PACKAGE
24-LEAD PLASTIC DIP 24-LEAD PLASTIC SOL
TJMAX = 110°C, θJA = 100°C/W (N)
TJMAX = 110°C, θJA = 130°C/W (S)
TJMAX = 110°C, θJA = 100°C/W (N)
TJMAX = 110°C, θJA = 130°C/W (S)
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CO VERTER CHARACTERISTICS
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
(Note 7)
Commercial
Military
Commercial
Military
12
2
LTC1273B/LTC1275B/LTC1276B
MIN
TYP
MAX
12
UNITS
Bits
●
●
±1
±1
±1
LSB
LSB
LSB
●
●
±3/4
±1
±1
±1
LSB
LSB
●
±3
±4
±4
±6
LSB
LSB
±10
±15
LSB
±45
ppm/°C
(Note 8)
IOUT(REFERENCE) = 0
(For MIL Grade:
Contact Factory)
±1/2
±1/2
±3/4
Full Scale Error
Full Scale Tempco
LTC1275ACN
LTC1275BCN
LTC1275ACS
LTC1275BCS
LTC1276ACN
LTC1276BCN
LTC1276ACS
LTC1276BCS
With Internal Reference (Notes 5 and 6)
LTC1273A/LTC1275A/LTC1276A
MIN
TYP
MAX
CONDITIONS
ORDER
PART NUMBER
TOP VIEW
●
±5
±25
±10
LTC1273
LTC1275/LTC1276
W U
DY A IC ACCURACY (Note 5)
SYMBOL
PARAMETER
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
MIN
TYP
MAX
CONDITIONS
UNITS
S/(N + D) Signal-to-Noise Plus Distortion Ratio
50kHz/150kHz Input Signal
72/70
dB
THD
Total Harmonic Distortion
Up to 5th Harmonic
50kHz/150kHz Input Signal
– 83/– 74
dB
Peak Harmonic or Spurious Noise
50kHz/150kHz Input Signal
– 85/– 76
dB
IMD
Intermodulation Distortion
fIN1 = 29.37kHz, fIN2 = 32.446kHz
– 80
dB
Full Power Bandwidth
4.5
MHz
Full Linear Bandwidth (S/(N + D) ≥ 68dB)
200
kHz
U
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A ALOG I PUT (Note 5)
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
MIN
TYP
MAX
UNITS
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 9)
4.95V ≤ VDD ≤ 5.25V (LTC1273)
4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 2.45V (LTC1275)
4.95V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.95V (LTC1276)
●
●
●
IIN
Analog Input Leakage Current
CS = High
●
CIN
Analog Input Capacitance
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
tACQ
Sample-and-Hold
Acquisition Time
Commercial
Military
0 to 5
±2.5
±5
V
V
V
±1
50
5
pF
pF
600
1000
●
●
µA
ns
ns
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U
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I TER AL REFERE CE CHARACTERISTICS (Note 5)
PARAMETER
CONDITIONS
LTC1273A/LTC1275A/LTC1276A
MIN
TYP
MAX
LTC1273B/LTC1275B/LTC1276B
MIN
TYP
MAX
VREF Output Voltage
IOUT = 0
2.400
2.400
VREF Output Tempco
IOUT = 0
VREF Line Regulation
4.95V ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ – 4.95V
VREF Load Regulation
0V ≤ |IOUT| ≤ 1mA
●
2.420
2.440
±5
±25
UNITS
2.420
2.440
V
±10
±45
ppm/°C
0.01
0.01
0.01
0.01
2
2
LSB/V
LSB/V
LSB/mA
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DIGITAL I PUTS A D DIGITAL OUTPUTS (Note 5)
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
MIN
TYP
MAX
UNITS
SYMBOL PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.95V
●
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
●
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VDD = 4.95V
IO = – 10µA
IO = – 200µA
●
2.4
4.0
V
5
pF
4.7
V
V
3
LTC1273
LTC1275/LTC1276
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DIGITAL I PUTS A D DIGITAL OUTPUTS (Note 5)
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
MIN
TYP
MAX
UNITS
SYMBOL PARAMETER
CONDITIONS
VOL
VDD = 4.95V
IO = 160µA
IO = 1.6mA
●
Low Level Output Voltage
0.05
0.10
0.4
V
V
±10
µA
IOZ
High Z Output Leakage D11-D0/8
VOUT = 0V to VDD, CS High
●
COZ
High Z Output Capacitance D11-D0/8
CS High (Note 9 )
●
ISOURCE
Output Source Current
VOUT = 0V
– 10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
15
pF
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POWER REQUIRE E TS (Note 5)
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
MIN
TYP
MAX
UNITS
SYMBOL PARAMETER
CONDITIONS
VDD
Positive Supply Voltage
LTC1273/LTC1276 (Notes 10, 11)
LTC1275 (Note 10)
4.95
4.75
5.25
5.25
V
V
VSS
Negative Supply Voltage
LTC1275 (Note 10)
LTC1276 (Notes 10, 11)
– 2.45
– 4.95
– 5.25
– 5.25
V
V
IDD
Positive Supply Current
ISS
Negative Supply Current
PD
Power Dissipation
LTC1275/LTC1276
●
15
25
mA
●
0.065
0.200
mA
75
mW
WU
TI I G CHARACTERISTICS See Timing Characteristics Figures (Note 5)
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
MIN
TYP
MAX
UNITS
SYMBOL
PARAMETER
CONDITIONS
fSAMPLE(MAX)
Maximum Sampling Frequency
(Note 10)
Commercial
Military
●
●
Commercial
Military
●
●
tCONV
Conversion Time
t1
CS to RD Setup Time
t2
RD to BUSY Delay
t3
Data Access Time After RD↓
●
CL = 50pF
Commercial
Military
●
●
CL = 20pF
Commercial
Military
●
●
CL = 100pF
Commercial
Military
●
●
300
250
kHz
kHz
2.7
3.0
µs
µs
80
190
230
270
ns
ns
ns
40
90
110
120
ns
ns
ns
50
125
150
170
ns
ns
ns
0
ns
t4
RD Pulse Width
●
t3
ns
t5
CS to RD Hold Time
●
0
ns
t6
Data Setup Time After BUSY↑
40
Commercial
Military
4
●
●
70
90
100
ns
ns
ns
LTC1273
LTC1275/LTC1276
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TI I G CHARACTERISTICS See Timing Characteristics Figures (Note 5)
SYMBOL PARAMETER
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
MIN
TYP
MAX
UNITS
CONDITIONS
Bus Relinquish Time
t7
Commercial
Military
●
●
20
20
20
30
75
85
90
ns
ns
ns
t8
HBEN to RD Setup Time
●
0
ns
t9
HBEN to RD Hold Time
●
0
ns
t10
Delay Between RD Operations
●
40
ns
t11
Delay Between Conversions
●
●
500
600
1000
ns
ns
ns
t12
(Note 10)
Commercial
Military
Aperture Delay of Sample-and-Hold
25
The ● indicates specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS (ground for
LTC1273) or above VDD, they will be clamped by internal diodes. This
product can handle input currents greater than 60mA below VSS (ground
for LTC1273) or above VDD without latch-up.
Note 4: When these pin voltages are taken below VSS (ground for
LTC1273) they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below VSS (ground for LTC1273)
without latch-up. These pins are not clamped to VDD.
Note 5: VDD = 5V (VSS = – 5V for LTC1275/LTC1276), 300kHz at 70°C and
250kHz at 125°C, tr = tf = 5ns unless otherwise specified.
ns
Note 6: Linearity, offset and full scale specifications apply for unipolar and
bipolar modes.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset (LTC1275/LTC1276) is the different voltage
measured from – 0.5LSB when the LTC1275/LTC1276 output code flickers
between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note11: AIN must not exceed VDD or fall below VSS by more than 50mV for
specified accuracy. Therefore the minimum supply voltage for the
LTC1273 is + 4.95V. The minimum supplies for the LTC1275 are +4.75V
and – 2.45V and the minimum supplies for the LTC1276 are ±4.95V.
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TI I G CHARACTERISTICS (Note 5)
ROM Mode, Parallel Read Timing Diagram
Slow Memory Mode, Parallel Read Timing Diagram
CS
CS
t1
t5
t2
t11
tCONV
t10
t2
t1
t4
t5
t11
tCONV
t2
tCONV
BUSY
BUSY
t3
t6
OLD DATA
DB11 TO DB0
DATA
TRACK
t5
t4
RD
RD
HOLD
t1
t1
t7
t3
NEW DATA
DB11 TO DB0
DATA
t12
HOLD
LTC1273/75/76 • TA03
TRACK
t7
t3
OLD DATA
DB11 TO DB0
t12
t7
NEW DATA
DB11 TO DB0
t12
LTC1273/75/76 • TA04
5
LTC1273
LTC1275/LTC1276
WU
TI I G CHARACTERISTICS (Note 5)
Slow Memory Mode, Two Byte Read Timing Diagram
HBEN
t8
t9
t8
t9
CS
t1
t5
t1
t5
t4
RD
t10
t2
tCONV
t10
t11
BUSY
t3
t6
OLD DATA
DB7 TO DB0
DATA
t3
t7
NEW DATA
DB7 TO DB0
t7
NEW DATA
DB11 TO DB8
t12
HOLD
t12
TRACK
LTC1273/75/76 • TA05
ROM Mode, Two Byte Read Timing Diagram
HBEN
t8
t9
t9
t8
t9
t8
CS
t1
t4
t5
t1
t4
t5
t1
t4
t5
RD
t2
t10
t11
tCONV
t2
BUSY
t3
DATA
HOLD
TRACK
6
t7
OLD DATA
DB7 TO DB0
t12
t3
t7
t3
NEW DATA
DB11 TO DB8
t7
NEW DATA
DB7 TO DB0
t12
LTC1273/75/76 • TA06
LTC1273
LTC1275/LTC1276
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Differential Nonlinearity
0.5
0.5
0
–0.5
Supply Current vs Temperature
25
20
SUPPLY CURRENT (mA)
1.0
DNL ERROR (LSB)
INL ERROR (LSB)
Integral Nonlinearity
1.0
0
–0.5
15
10
5
–1.0
–1.0
512 1024 1536 2048 2560 3072 3584 4096
CODE
0
0
LTC1273/75/76 • TPC01
62
9
56
8
50
7
6
5
4
3
2
60
50
40
30
20
10
fSAMPLE = 300kHz
fSAMPLE = 300kHz
1M
2M
1k
100k
10k
INPUT FREQUENCY (Hz)
Power Supply Feedthrough
vs Ripple Frequency (LTC1273)
0
fSAMPLE = 300kHz
–20
–40
VDD
(VRIPPLE = 1mV)
–80
DGND
(VRIPPLE = 0.1V)
–100
–120
1k
fSAMPLE = 300kHz
–10
THD
2nd HARMONIC
3rd HARMONIC
–20
–30
–40
–50
–60
–70
–80
–90
1k
1M
100k
1M
10k
INPUT FREQUENCY (Hz)
10k
100k
RIPPLE FREQUENCY (Hz)
1M
LTC1273/75/76 • TPC07
10M
LTC1273/75/76 • TPC06
LTC1273/75/76 • TPC05
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
LTC1273/75/76 • TPC04
–60
0
–100
0
100k
INPUT FREQUENCY (Hz)
Distortion vs Input Frequency
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
10
70
SIGNAL-TO-NOISE RATIO (dB)
68
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
EFFECTIVE NUMBER OF BITS
11
80
S/(N + D) (dB)
74
125
100
LTC1273/75/76 • TPC03
Signal-to-Noise Ratio (Without
Harmonics) vs Input Frequency
12
0
10k
50
25
0
75
TEMPERATURE (°C)
LTC1273/75/76 • TPC02
ENOBs and S/(N + D)
vs Input Frequency
1
0
–50 –25
512 1024 1536 2048 2560 3072 3584 4096
CODE
Power Supply Feedthrough
vs Ripple Frequency (LTC1275/76)
0
fSAMPLE = 300kHz
–20
VDD (VRIPPLE = 1mV)
DGND (VRIPPLE = 0.1V)
VSS (VRIPPLE = 10mV)
–40
–60
–80
–100
–120
1k
10k
100k
RIPPLE FREQUENCY (Hz)
1M
LTC1273/75/76 • TPC08
7
LTC1273
LTC1275/LTC1276
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Acquisition Time
vs Source Impedance
Intermodulation Distortion Plot
fSAMPLE = 300kHz
fIN1 = 29.37kHz
fIN2 = 32.446kHz
ACQUISITION TIME (ns)
AMPLITUDE (dB)
–20
–40
–60
–80
4500
80
4000
70
SIGNAL/(NOISE + DISTORTION) (dB)
0
S/(N + D) vs Input Frequency and
Amplitude
3500
3000
2500
2000
1500
1000
–100
500
–120
0
20
40
100
1k
RSOURCE (Ω)
10
10k
Spurious Free Dynamic Range
vs Input Frequency
40
30
20
VIN = –60dB
10
1k
1M
10k
100k
INPUT FREQUENCY (Hz)
10M
LTC1273/75/76 • TPC11
Reference Voltage
vs Load Current
2.435
0
fSAMPLE = 300kHz
2.430
–20
REFERENCE VOLTAGE (V)
SPURIOUS FREE DYNAMIC RANGE (dB)
VIN = –20dB
50
LTC1273/75/76 • TPC10
LTC1273/75/76 • F05
–10
VIN = 0dB
60
0
0
60 80 100 120 140 160
FREQUENCY (kHz)
fSAMPLE = 300kHz
–30
–40
–50
–60
–70
–80
2.425
2.420
2.415
2.410
–90
–100
10k
2.405
100k
1M
INPUT FREQUENCY (Hz)
10M
LTC1273/75/76 • TPC12
–5
–4
–3
0
–2
–1
LOAD CURRENT (mA)
1
2
LTC1273/75/76 • TPC13
U U
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PI FU CTIO S
AIN (Pin 1): Analog Input. 0V to 5V (LTC1273), ±2.5V
(LTC1275) or ±5V (LTC1276).
VREF (Pin 2): +2.42V Reference Output. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
AGND (Pin 3): Analog Ground.
D11-D4 (Pins 4 to 11): Three-State Data Outputs.
DGND (Pin 12): Digital Ground.
D3/11-D0/8 (Pins 13 to 16): Three-State Data Outputs.
NC (Pins 17 and 18): No Connection.
8
HBEN (Pin 19): High Byte Enable Input. This pin is used to
multiplex the internal 12-bit conversion result into the
lower bit outputs (D7-D0/8). See Table 1. HBEN also
disables conversion start when HIGH.
RD (Pin 20): READ Input. This active low signal starts a
conversion when CS and HBEN are low. RD also enables
the output drivers when CS is low.
CS (Pin 21): The CHIP SELECT Input must be low for the
ADC to recognize RD and HBEN inputs.
BUSY (Pin 22): The BUSY Output shows the converter
status. It is low when a conversion is in progress.
LTC1273
LTC1275/LTC1276
UO
U
U
PI FU CTI
S
VSS (Pin 23): Negative Supply. – 5V for LTC1275/LTC1276.
Bypass to AGND with 0.1µF ceramic.
VDD (Pin 24): Positive Supply, 5V. Bypass to AGND (10µF
tantalum in parallel with 0.1µF ceramic).
NC (Pin 23): No Connection for LTC1273.
Table 1. Data Bus Output, CS and RD = LOW
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
Pin 11
Pin 13
Pin 14
Pin 15
Pin 16
MNEMONIC*
D11
D10
D9
D8
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
HBEN = LOW
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
HBEN = HIGH
DB11
DB10
DB9
DB8
LOW
LOW
LOW
LOW
DB11
DB10
DB9
DB8
*D11...D0/8 are the ADC data output pins.
DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
U U
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FU TIO AL BLOCK DIAGRA
SAMPLE
VSS (NC ON LTC1273)
VDD
SAMPLE
CSAMPLE
COMPARATOR
–
AIN
HOLD
+
D11
12
12-BIT
CAPACITIVE
DAC
VREF(OUT)
SUCCESSIVE
APPROXIMATION
REGISTER
12
•
•
•
OUTPUT
LATCHES
D0/8
BUSY
2.42V
REFERENCE
INTERNAL
CLOCK
AGND
CS
RD
HBEN
CONTROL
LOGIC
DGND
LTC1273/75/76 • FBD
TEST CIRCUITS
Load Circuits for Output Float Delay
Load Circuits for Access Time
5V
5V
3k
3k
DBN
DBN
DBN
3k
CL
DGND
A) HIGH-Z TO VOH (t3)
AND VOL TO VOH (t6)
CL
DGND
B) HIGH-Z TO VOL (t3)
AND VOH TO VOL (t6)
DBN
3k
10pF
DGND
A) VOH TO HIGH-Z
10pF
DGND
B) VOL TO HIGH-Z
1273/75/76 • TA08
1273/75/76 • TA07
9
LTC1273
LTC1275/LTC1276
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CONVERSION DETAILS
The LTC1273/LTC1275/LTC1276 use a successive approximation algorithm and an internal sample-and-hold
circuit to convert an analog signal to a 12-bit parallel or
2-byte output. The ADCs are complete with a precision
reference and an internal clock. The control logic provides
easy interface to microprocessors and DSPs. (Please refer
to the Digital Interface section for the data format.)
Conversion start is controlled by the CS, RD and HBEN
inputs. At the start of conversion the successive approximation register (SAR) is reset and the three-state data
outputs are enabled. Once a conversion cycle has begun
it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN input connects to the sample-and-hold
capacitor during the acquire phase, and the comparator
offset is nulled by the feedback switch. In this acquire
phase, a minimum delay of 600ns will provide enough
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
compare mode. The input switch switches CSAMPLE to
ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the AIN input charge. The SAR contents (a 12-bit
data word) which represent the AIN are loaded into the
12-bit output latches.
DYNAMIC PERFORMANCE
The LTC1273/LTC1275/LTC1276 have an exceptionally
high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to characterize the ADC’s
frequency response, distortion and noise at the rated
throughput. By applying a low distortion sine wave and
analyzing the digital output using an FFT algorithm, the
ADC’s spectral content can be examined for frequencies
outside the fundamental. Figure 2 shows a typical LTC1275
FFT plot.
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with
a 300kHz sampling rate and a 29kHz input. The dynamic
performance is excellent for input frequencies up to the
Nyquist limit of 150kHz.
0
fSAMPLE = 300kHz
fIN = 29.37kHz
SAMPLE
–20
AMPLITUDE (dB)
SAMPLE
SI
CSAMPLE
–
AIN
HOLD
+
CDAC
COMPARATOR
–40
–60
–80
DAC
VDAC
S
A
R
–100
–120
0
LTC1273/75/76 • F01
Figure 1. AIN Input
10
12-BIT
LATCH
20
40
60 80 100 120 140 160
FREQUENCY (kHz)
LTC1273/75/76 • F02
Figure 2. LTC1275 Nonaveraged, 1024 Point FFT Plot
LTC1273
LTC1275/LTC1276
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Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
12
74
11
68
10
62
9
56
8
50
7
6
5
fSAMPLE = 300kHz
–10
THD
2nd HARMONIC
3rd HARMONIC
–20
–30
–40
–50
–60
–70
–80
–90
1k
4
10k
100k
1M
INPUT FREQUENCY (Hz)
10M
LTC1273/75/76 • F04
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
3
2
1
0
–100
S/(N + D) (dB)
EFFECTIVE BITS
where N is the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 300kHz the LTC1273/LTC1275/LTC1276 maintain
very good ENOBs up to the Nyquist input frequency of
150kHz. Refer to Figure 3.
quency is shown in Figure 4. The LTC1273/LTC1275/
LTC1276 have good distortion performance up to Nyquist
and beyond.
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
APPLICATI
fSAMPLE = 300kHz
0
10k
100k
INPUT FREQUENCY (Hz)
1M
2M
LTC1273/75/76 • F03
Figure 3. Effective Bits and Signal to (Noise + Distortion)
vs Input Frequency
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD = 20log
√V22 + V32 + V42 ... + VN2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the
second through Nth harmonics. THD versus input fre-
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while the 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
waves are equal in magnitude, the value (in decibels) of the
2nd order IMD products can be expressed by the following
formula:
IMD (fa ± fb) = 20log
Amplitude at (fa ± fb)
Amplitude at fa
11
LTC1273
LTC1275/LTC1276
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Figure 5 shows the IMD performance at a 30kHz input.
0
fSAMPLE = 300kHz
fIN1 = 29.37kHz
fIN2 = 32.446kHz
AMPLITUDE (dB)
–20
–40
–60
–80
–100
–120
0
20
40
60 80 100 120 140 160
FREQUENCY (kHz)
LTC1273/75/76 • F05
Figure 5. Intermodulation Distortion Plot
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full scale input signal.
Full Power and Full Linear Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1273/LTC1275/LTC1276 have been designed to optimize input bandwidth, allowing ADCs to undersample
input signals with frequencies above the converters’ Nyquist
Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at
frequencies far beyond Nyquist.
Driving the Analog Input
the analog input must settle after the small current spike
before the next conversion starts. Any op amp that settles
in 600ns to small current transients will allow maximum
speed operation. If slower op amps are used, more settling
time can be provided by increasing the time between
conversions. Suitable devices capable of driving the ADCs’
AIN input include the LT1190/LT1191, LT1007, LT1220,
LT1223 and LT1224 op amps.
The analog input tolerates source resistance very well.
Here again, the only requirement is that the analog input
must settle before the next conversion starts. For larger
source resistance, full DC accuracy can be obtained if
more time is allowed between conversions. For more
information, see the Acquisition Time vs Source Resistance curve in the Typical Performance Characteristics
section. For optimum frequency domain performance
[e.g., S/(N + D)], keep the source resistance below 100Ω.
Internal Reference
The LTC1273/LTC1275/LTC1276 have an on-chip, temperature compensated, curvature corrected, bandgap reference which is factory trimmed to 2.42V. It is internally
connected to the DAC and is available at pin 2 to provide
up to 1mA current to an external load.
For minimum code transition noise the reference output
should be decoupled with a capacitor to filter wideband
noise from the reference (10µF tantalum in parallel with a
0.1µF ceramic).
In the LTC1275, the VREF pin can be driven above its
normal value with a DAC or other means to provide input
span adjustment or to improve the reference temperature
drift. Figure 6 shows an LT1006 op amp driving the
INPUT RANGE
±1.033VREF(OUT)
+
VREF(OUT) ≥ 2.45V
LT1006
The analog inputs of the LTC1273/LTC1275/LTC1276 are
easy to drive. They draw only one small current spike while
charging the sample-and-hold capacitor at the end of
conversion. During conversion the analog input draws no
current. The only requirement is that the amplifier driving
12
–
LTC1275
AIN
VREF
3Ω
10µF
AGND
LTC1273/75/76 • F06
Figure 6. Driving the VREF with the LT1006 Op Amp
LTC1273
LTC1275/LTC1276
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reference pin. The VREF pin must be driven to at least
2.45V to prevent conflict with the internal reference. The
reference should be driven to no more than 4.8V to keep
the input span within the ±5V supplies. In the LTC1273/
LT1276, the input spans are 0V to 5V and ±5V respectively with the internal reference. Driving the reference is
not recommended on the LTC1273/LTC1276 since the
input spans will exceed the supplies and codes will be lost
at full scale.
1LSB = FS = 5V
4096 4096
111...111
111...110
111...101
OUTPUT CODE
APPLICATI
111...100
UNIPOLAR
ZERO
000...011
000...010
000...001
000...000
Figure 7 shows a typical reference, the LT1019A-2.5
connected to the LTC1275. This will provide an improved
drift (equal to the maximum 5ppm/°C of the LT1019A-2.5)
and a ±2.582V full scale.
0V
FS – 1LSB
1
LSB
INPUT VOLTAGE (V)
LTC1273/75/76 • F08
Figure 8. LTC1273 Unipolar Transfer Characteristic
INPUT RANGE
±2.58V
5V
VIN
GND
BIPOLAR
ZERO
011...110
VREF
3Ω
10µF
AGND
LTC1273/75/76 • F07
OUTPUT CODE
VOUT
LT1019A-2.5
011...111
LTC1275
AIN
000...101
000...000
111...111
111...110
Figure 7. Supplying a 2.5V Reference Voltage
to the LTC1275 with the LT1019A-2.5
FS = 5V (LTC1275)
FS = 10V (LTC1276)
1LSB = FS/4096
100...001
100...000
–FS/2
UNIPOLAR/BIPOLAR OPERATION AND ADJUSTMENT
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
LTC1273/75/76 • F09
Figure 8 shows the ideal input/output characteristics for
the LTC1273. The code transitions occur midway between
successive integer LSB values (i.e., 1/2LSB, 1 1/2LSBs,
2 1/2LSBs, ... FS – 1 1/2LSBs). The output code is natural
binary with 1LSB = FS/4096 = 5V/4096 = 1.22mV. Figure
9 shows the input/output transfer characteristics for the
LTC1275/LTC1276 in 2’s complement format. As stated in
the figure, 1LSB for LTC1275/LTC1276 are 1.22mV and
2.44mV respectively.
Unipolar Offset and Full Scale Adjustment (LTC1273)
Figure 9. LTC1275/LTC1276 Bipolar Transfer Characteristic
R1
50Ω
+
V1
A1
–
R2
10k
R3
10k
AIN
R4
100Ω
LTC1273
LTC1275
LTC1276
FULL SCALE
ADJUST
AGND
In applications where absolute accuracy is important,
offset and full scale errors can be adjusted to zero. Figure
10a shows the extra components required for full scale
error adjustment. If both offset and full scale adjustments
are needed, the circuit in Figure 10b can be used. Offset
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
LTC1273/75/76 • F10a
Figure 10a. Full Scale Adjust Circuit
13
LTC1273
LTC1275/LTC1276
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U
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10k
W
ANALOG
INPUT
0V TO 5V
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APPLICATI
S I FOR ATIO
+
R2
10k
AIN
–
5V
R9
20Ω
R4
100k
R5
4.3k
FULL SCALE
5V
ADJUST
R3
100k R7
100k
R6
400Ω
LTC1273
R8
LTC1273/75/76 • F10b
10k
OFFSET
ADJUST
ANALOG
INPUT
±2.5V (LTC1275)
±5V (LTC1276)
R1
10k
+
R2
10k
AIN
–
R4
100k
R5
4.3k
FULL SCALE
5V
ADJUST
R3
100k R7
100k
R6
200Ω
LTC1275
LTC1276
R8
LTC1273/75/76 • F10c
20k
OFFSET
ADJUST
–5V
Figure 10b. LTC1273 Offset and Full Scale Adjust Circuit
should be adjusted before full scale. To adjust offset, apply
0.61mV (i.e., 1/2LSB) at the input and adjust the offset trim
until the LTC1273 output code flickers between 0000 0000
0000 and 0000 0000 0001. To adjust full scale, apply an
analog input of 4.99817V (i.e., FS – 1 1/2LSBs or last code
transition) at the input and adjust the full scale trim until
the LTC1273 output code flickers between 1111 1111
1110 and 1111 1111 1111. It should be noted that if
negative ADC offsets need to be adjusted or if an output
swing to ground is required, the op amp in Figure 10b
requires a negative power supply.
Bipolar Offset and Full Scale Adjustment
(LTC1275/LTC1276)
Bipolar offset and full scale errors are adjusted in a similar
fashion to the unipolar case. Figure 10a shows the extra
components required for full scale error adjustment. If both
offset and full scale adjustments are needed, the circuit in
Figure 10c can be used. Again, bipolar offset must be
adjusted before full scale error. Bipolar offset adjustment is
achieved by trimming the offset adjustment of Figure 10c
while the input voltage is 1/2LSB below ground. This is done
by applying an input voltage of – 0.61mV or – 1.22mV
(– 0.5LSB for LTC1275 or LTC1276) to the input in Figure
10c and adjusting R8 until the ADC output code flickers
between 0000 0000 0000 and 1111 1111 1111. For full
scale adjustment, an input voltage of 2.49817V or 4.99636V
(FS – 1 1/2LSBs for LTC1275 or LTC1276) is applied to the
14
Figure 10c. LTC1275/LTC1276 Offset and
Full Scale Adjust Circuit
input and R5 is adjusted until the output code flickers
between 0111 1111 1110 and 0111 1111 1111.
BOARD LAYOUT AND BYPASSING
The LTC1273/LTC1275/LTC1276 are easy to use. To obtain the best performance from the devices a printed
circuit board is required. Layout for the printed circuit
board should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track. The analog input should be screened by
AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in Figure
11. For the LTC1275/LTC1276 a 0.1µF ceramic provides
adequate bypassing for the VSS pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
Noise: Input signal leads to AIN and signal return leads
from AGND (Pin 3) should be kept as short as possible to
minimize input noise coupling. In applications where this
is not possible, a shielded cable between source and ADC
is recommended. Also, since any potential difference in
grounds between the signal source and ADC appears as an
LTC1273
LTC1275/LTC1276
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1
ANALOG
INPUT
CIRCUITRY
+
–
DIGITAL
SYSTEM
LTC1273
AIN
AGND
VREF
3
2
10µF
VDD
DGND
24
0.1µF
10µF
12
0.1µF
GROUND CONNECTION
TO DIGITAL CIRCUITRY
ANALOG GROUND PLANE
LTC1273/75/76 • F11
Figure 11. Power Supply Grounding Practice
error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedances
as much as possible.
A single point analog ground plane separate from the logic
system ground should be established at Pin 3 (AGND) or
as close as possible to the ADC, as shown in Figure 11. Pin
12 (DGND) and all other analog grounds should be connected to this single analog ground point. No other digital
grounds should be connected to this analog ground point.
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC and
the width for these traces should be as wide as possible.
In applications where the ADC data outputs and control
signals are connected to a continuously active microprocessor bus, it is possible to get errors in conversion
results. These errors are due to feedthrough from the
microprocessor to the ADC. The problem can be eliminated by forcing the microprocessor into a WAIT state
during conversion or by using three-state buffers to isolate the ADC data bus.
DIGITAL INTERFACE
The ADCs are designed to interface with microprocessors
as a memory mapped device. The CS and RD control
inputs are common to all peripheral memory interfacing.
The HBEN input serves as a data byte select for 8-bit
processors and is normally either connected to the microprocessor address bus or grounded.
Internal Clock
These ADCs have an internal clock that eliminates the need
for synchronization between an external clock and the CS
and RD signals found in other ADCs. The internal clock is
factory trimmed to achieve a typical conversion time of
2.45µs, and a maximum conversion time over the full
operating temperature range of 2.7µs. No external adjustments are required and, with the guaranteed maximum
acquisition time of 600ns, throughput performance of
300ksps is assured.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: HBEN, CS and RD. Figure 12 shows
the logic structure associated with these inputs. The three
signals are internally gated so that a logic “0” is required
LTC1273/75/76
HBEN 19
CS
21
BUSY
D
Q
CONVERSION
START (RISING
EDGE TRIGGER)
FLIP
FLOP
RD 20
CLEAR
ACTIVE HIGH
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
D11....D0/8 = DB11....DB0
ENABLE THREE-STATE OUTPUTS
D11....D8 = DB11....DB8
D7....D4 = LOW
D3/11....D0/8 = DB11....DB8
* D11....D0/8 ARE THE ADC DATA OUTPUT PINS
DB11....DB0 ARE THE 12-BIT CONVERSION RESULTS
LTC1273/75/76 • F12
Figure 12. Internal Logic for Control Inputs CS, RD and HBEN
15
LTC1273
LTC1275/LTC1276
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on all three inputs to initiate a conversion. Once initiated it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output, and this
is low while conversion is in progress.
There are two modes of operation as outlined by the timing
diagrams of Figures 13 to 16. Slow Memory Mode is
designed for microprocessors which can be driven into a
WAIT state. A READ operation brings CS and RD low which
initiates a conversion and data is read when conversion is
complete. The second is the ROM Mode which does not
require microprocessor WAIT states. A READ operation
brings CS and RD low which initiates a conversion and
reads the previous conversion result.
8MSBs) where it can be read in two read cycles. The
4MSBs always appear on D11...D8 whenever the threestate output drivers are turned on.
Slow Memory Mode, Parallel Read (HBEN = LOW)
Figure 13 and Table 2 show the timing diagram and data
bus status for Slow Memory Mode, Parallel Read. CS and
RD going low trigger a conversion and the ADC acknowledges by taking BUSY low. Data from the previous conversion appears on the three-state data outputs. BUSY returns high at the end of conversion when the output
latches have been updated and the conversion result is
placed on data outputs D11...D0/8.
Data Format
Slow Memory Mode, Two Byte Read
The output format can be either a complete parallel load for
16-bit microprocessors or a two byte load for 8-bit microprocessors. Data is always right justified (i.e., LSB is the
most right-hand bit in a 16-bit word). For a two byte read,
only data outputs D7...D0/8 are used. Byte selection is
governed by the HBEN input which controls an internal
digital multiplexer. This multiplexes the 12-bits of conversion data onto the lower D7...D0/8 outputs (4MSBs or
For a two byte read, only 8 data outputs D7...D0/8 are used.
Conversion start procedure and data output status for the
first read operation are identical to Slow Memory Mode,
Parallel Read. See Figure 14 timing diagram and Table 3
data bus status. At the end of the conversion, the low data
byte (D7...D0/8) is read from the ADC. A second READ
operation, with the HBEN high, places the high byte on data
outputs D3/11...D0/8 and disables conversion start. Note
CS
t1
t5
t1
RD
t2
t11
tCONV
t10
BUSY
OLD DATA
DB11-DB0
DATA
HOLD
t7
t6
t3
NEW DATA
DB11-DB0
t12
TRACK
LTC1273/75/76 • F13
Figure 13. Slow Memory Mode, Parallel Read Timing Diagram
Table 2. Slow Memory Mode, Parallel Read Data Bus Status
Data Outputs
D11
D10
D9
D8
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
Read
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
16
LTC1273
LTC1275/LTC1276
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HBEN
t8
t9
t8
t9
CS
t1
t5
t1
t4
t5
RD
t10
t2
t10
t11
t CONV
BUSY
t3
t6
OLD DATA
DB7-DB0
DATA
t7
t3
t7
NEW DATA
DB11-DB8
NEW DATA
DB7-DB0
t12
HOLD
t12
TRACK
LTC1273/75/76 • F14
Figure 14. Slow Memory Mode, Two Byte Read Timing Diagram
Table 3. Slow Memory Mode, Two Byte Read Data Bus Status
Data Outputs
D7
D6
D5
D4
First Read
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Second Read
Low
Low
Low
Low
DB11
DB10
DB9
DB8
that the 4MSBs appear on data output D11...D8 during
both READ operations.
ROM Mode, Parallel Read (HBEN = LOW)
The ROM Mode avoids placing a microprocessor into a
WAIT state. A conversion is started with a READ operation, and the 12 bits of data from the previous conversion
are available on data outputs D11...D0/8 (see Figure 15
and Table 4). This data may be disregarded if not required. A second READ operation reads the new data
(DB11...DB0) and starts another conversion. A delay at
least as long as the ADC’s conversion time plus the 600ns
minimum delay between conversions must be allowed
between READ operations.
ROM Mode, Two Byte Read
As previously mentioned for a two byte read, only data
outputs D7...D0/8 are used. Conversion is started in the
D3/11
D2/10
D1/9
D0/8
normal way with a READ operation and the data output
status is the same as the ROM mode, Parallel Read (see
Figure 16 timing diagram and Table 5 data bus status).
Two more READ operations are required to access the new
conversion result. A delay equal at the ADCs’ conversion
time must be allowed between conversion start and the
third data READ operation. The second READ operation
with HBEN high disables conversion start and places the
high byte (4MSBs) on data outputs D3/11...D0/8. A third
read operation accesses the low data byte (DB7...DB0)
and starts another conversion. The 4MSBs appear on data
outputs D11...D8 during all three read operations.
MICROPROCESSOR INTERFACING
The LTC1273/LTC1275/LTC1276 allow easy interfacing to digital signal processors as well as modern high
speed, 8-bit or 16-bit microprocessors. Here are several examples.
17
LTC1273
LTC1275/LTC1276
W
U
U
UO
APPLICATI
S I FOR ATIO
CS
t1
t5
t4
t1
t5
t4
RD
t11
t2
t2
t CONV
t CONV
BUSY
t3
t7
t3
OLD DATA
DB11-DB0
DATA
t7
NEW DATA
DB11-DB0
t12
HOLD
t12
TRACK
LTC1273/75/76 • F15
Figure 15. ROM Mode, Parallel Read Timing Diagram (HBEN = LOW)
Table 4. ROM Mode, Parallel Read Data Bus Status
Data Outputs
D11
D10
D9
D8
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
First Read (Old Data)
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Second Read
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
HBEN
t8
t9
t8
t9
t9
t8
CS
t1
t5
t4
t1
t4
t5
t1
RD
t11
t2
t4
t5
t10
t2
tCONV
BUSY
t3
DATA
HOLD
t7
t3
OLD DATA
DB7-DB0
t7
t3
NEW DATA
DB11-DB8
t7
NEW DATA
DB7-DB0
t12
t12
LTC1272 • TA16
TRACK
Figure 16. ROM Mode Two Byte Read Timing Diagram
Table 5. ROM Mode, Two Byte Read Data Bus Status
Data Outputs
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
First Read (Old Data)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Second Read (New Data)
Low
Low
Low
Low
DB11
DB10
DB9
DB8
Third Read (New Data)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
18
LTC1273
LTC1275/LTC1276
W
U
U
UO
APPLICATI
S I FOR ATIO
TMS320C25
Figure 17 shows an interface between the LTC1273 and
the TMS320C25.
The W/R signal of the DSP initiates a conversion and
conversion results are read from the LTC1273 using the
following instruction:
IN
D, PA
A23
A1
ADDRESS BUS
AS
EN
LTC1273/75/76
MC68000
CS
BUSY
DTACK
R/W
RD
D11
where D is Data Memory Address and PA is the PORT
ADDRESS.
ADDRESS
DECODE
D11
DATA BUS
D0
D0/8
HBEN
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1273/75/76 • F18
A16
A1
IS
Figure 18. MC68000 Interface
ADDRESS BUS
EN
ADDRESS
DECODE
8085A/Z80 Microprocessor
LTC1273/75/76
TMS320C25
CS
BUSY
READY
RD
R/W
D16
D0
DATA BUS
D11
D0/8
HBEN
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1273/75/76 • F17
Figure 17. TMS320C25 Interface
MC68000 Microprocessor
Figure 18 shows a typical interface for the MC68000. The
LTC1273 is operating in the Slow Memory Mode. Assuming the LTC1273 is located at address C000, then the
following single 16-bit MOVE instruction both starts a
conversion and reads the conversion result:
Move.W $C000,D0
At the beginning of the instruction cycle when the ADC
address is selected, BUSY and CS assert DTACK so that
the MC68000 is forced into a WAIT state. At the end of
conversion, BUSY returns high and the conversion result
is placed in the D0 register of the microprocessor.
Figure 19 shows an LTC1273 interface for the Z80/8085A.
The LTC1273 is operating in the Slow Memory Mode and
a two byte read is required. Not shown in the figure is the
8-bit latch required to demultiplex the 8085A common
address/data bus. A0 is used to assert HBEN so that an
even address (HBEN = LOW) to the LTC1273 will start a
conversion and read the low data byte. An odd address
(HBEN = HIGH) will read the high data byte. This is
accomplished with the single 16-bit LOAD instruction
below.
For the 8085A
For the Z80
A15
A0
MREQ
LHLD (B000)
LDHL, (B000)
ADDRESS BUS
EN
ADDRESS
DECODE
Z80
8085A
WAIT
D0
HBEN
CS
BUSY
LTC1273/75/76
RD
RD
D7
A0
DATA BUS
D7
D0/8
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1273/75/76 • F19
Figure 19. 8085A and Z80 Interface
19
LTC1273
LTC1275/LTC1276
W
U
U
UO
APPLICATI
S I FOR ATIO
This is a two byte read instruction which loads the ADC
data (address B000) into the HL register pair. During the
first read operation, BUSY forces the microprocessor to
WAIT for the LTC1273 conversion. No WAIT states are
inserted during the second read operation when the microprocessor is reading the high data byte.
TMS32010 Microcomputer
current so it can be accurately driven by the unbuffered
MUX. The CD4520 counter increments the MUX channel
after each sample is taken. Figure 22 shows the acquisition time of LTC1275 vs the source resistance. For a
500Ω maximum “on” resistance of the CD4051, the
acquisition time of the ADC is not greatly affected. For
larger source resistances, modest increases in acquisition time must be allowed.
Figure 20 shows an LTC1273/TMS32010 interface. The
LTC1273 is operating in the ROM Mode.
The LTC1273 is mapped at a port address. The following
I/O instruction starts a conversion and reads the previous
conversion result into data memory.
IN A,PA
(PA = PORT ADDRESS)
When conversion is complete, a second I/O instruction
reads the up-to-date data into memory and starts another
conversion. A delay at least as long as the ADC conversion
time must be allowed between I/O instructions.
PA2
PA0
5V
CD4051
EN
D11
•
•
•
AIN
µP
OR
DSP
D0
LTC1275
CS
8 INPUT
CHANNELS
±2.8V
INPUT
VARIES
RD
BUSY
LTC1273/75/76 • F21
VSS
VEE A
5V
B C
ENABLE
CD4520
COUNTER
Q0 RESET
Q2
–5V
PORT ADDRESS BUS
DEN
NO
BUFFER
REQUIRED
VDD
Q1
ADDRESS
DECODE
LTC1273/75/76
TMS32010
Figure 21. MUXing the LTC1275 with CD4051
CS
RD
DATA BUS
D0
4
D11
D0/8
HBEN
LINEAR CIRCUITRY OMITTED FOR CLARITY
LTC1273/75/76 • F20
Figure 20. TMS32010 Interface
MUXing with CD4051
The high input impedance of the LTC1273/LTC1275/
LTC1276 provides an easy, cheap, fast, and accurate way
to multiplex many channels of data through one converter. Figure 21 shows a low cost CD4051 connected to
the LTC1275. The LTC1275’s input draws no DC input
20
ACQUISITION TIME (µs)
D11
RSOURCE
3
AIN
LTC1275
VIN
2
1
500Ω
0
10
100
1k
SOURCE RESISTANCE (Ω)
10k
LTC1273/75/76 • F22
Figure 22. Acqusition Time of LTC1275 vs Source Resistance
LTC1273
LTC1275/LTC1276
W
U
U
UO
APPLICATI
S I FOR ATIO
Demodulating a Signal by Undersampling
with LTC1275
Figure 23 shows a 455kHz amplitude modulated input
undersampled by the LTC1275. With a 227.5kHz sample
rate, the converter provides a 100dB noise floor and 68dB
distortion when digitizing the 455kHz AM input.
A time domain view of the demodulation is shown in Figure
25. The top trace shows the 455kHz waveform modulated
by a – 6dB, 5kHz signal. The bottom trace shows the
demodulated signal produced by the LTC1275 reconstructed through a 12-bit DAC. The resultant frequency is
5kHz with a sample rate of 227.5kHz. There are roughly 45
points per cycle.
Figure 24 shows an FFT of the AM signal digitized at
212.5kHz.
5V
RD
455kHz
AMPLITUDE
MODULATED
INPUT
AIN
227.5kHz
SAMPLE RATE
RD
455kHz
AM SIGNAL
1V/DIV
DEMODULATED
5kHz OUTPUT
1V/DIV
LTC1275
D11
D0
DATA OUTPUT
–5V
LTC1273/75/76 • F23
Figure 23. A 455kHz Amplitude Modulated Input
Undersampled by the LTC1275
50µs/DIV
LTC1273/75/76 • F27
Figure 25. 455kHz AM Signal Demodulated to 10.5 ENOBs
0
fSAMPLE = 212.5kHz
fIN = 454.8kHz
fMOD = 5.03kHz
–10
–20
AMPLITUDE (dB)
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
20
40
60
80
FREQUENCY (kHz)
100
120
100ps Resolution ∆Time Measurement with LTC1273
Figure 26 shows a circuit that precisely measures the
difference in time between two events. It has a 400ns full
scale and 100ps resolution. The start signal releases the
ramp generator made up of the PNP current source and
the 250pF capacitor. The circuit ramps until the stop
signal shuts off the current source. The final value of the
ramp represents the time between the start and stop
events. The LTC1273 digitizes this final value and outputs
the digital data.
LTC1273/75/76 • F24
Figure 24. 455kHz Input Voltage Modulated by a 5kHz Signal
21
LTC1273
LTC1275/LTC1276
U
W
U
UO
APPLICATI
S I FOR ATIO
7V
65Ω
5V
2N2369
65Ω
10µF
2N2369
400k
10µF
1N457
2N5771
REFOUT
20k
620Ω
LM134
AIN
250pF
POLYSTYRENE
45.3Ω
VDD
LTC1273
12-BIT
DATA OUTPUT
CS VSS GND RD BUSY
74HC03
1N457
45.3Ω
74HC74
5V
D
START↑
Q
CLK
Q
CLR
1k
1N4148
10k
5V
D
5V
STOP↑
DATA LATCH
SIGNAL
Q
CLK
1N4148
100pF
Q
CLR
1k
100k
0.001µF
1k
5V
10k
10pF
LTC1273/75/76 • F26
Figure 26. ∆Time Measurement with the LTC1273
22
LTC1273
LTC1275/LTC1276
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N Package
24-Lead Plastic DIP
1.265
(32.131)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
0.260 ± 0.010
(6.604 ± 0.254)
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.015
(0.381)
MIN
0.009 – 0.015
(0.229 – 0.381)
(
0.125
(3.175)
MIN
+0.025
0.325 –0.015
+0.635
8.255
–0.381
0.065
(1.651)
TYP
)
0.050 – 0.085
(1.27 – 2.159)
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
S Package
24-Lead Plastic SOL
24
23
22
21
0.598 – 0.614
(15.190 – 15.600)
(NOTE 2)
20 19 18 17 16
15
14
13
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
1
0.005
(0.127)
RAD MIN
0.291 – 0.299
(7.391 – 7.595)
(NOTE 2)
0.010 – 0.029 × 45°
(0.254 – 0.737)
2
3
4
5
6
7
8
9
10
11
12
0.093 – 0.104
(2.362 – 2.642)
0.037 – 0.045
(0.940 – 1.143)
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.014 – 0.019
(0.356 – 0.482)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
2. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1273
LTC1275/LTC1276
U.S. Area Sales Offices
NORTHEAST REGION
Linear Technology Corporation
One Oxford Valley
2300 E. Lincoln Hwy.,Suite 306
Langhorne, PA 19047
Phone: (215) 757-8578
FAX: (215) 757-5631
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Linear Technology Corporation
17060 Dallas Parkway
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Phone: (214) 733-3071
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Phone: (818) 703-0835
FAX: (818) 703-0517
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266 Lowell St., Suite B-8
Wilmington, MA 01887
Phone: (508) 658-3881
FAX: (508) 658-2701
CENTRAL REGION
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Chesapeake Square
229 Mitchell Court, Suite A-25
Addison, IL 60101
Phone: (708) 620-6910
FAX: (708) 620-6977
NORTHWEST REGION
Linear Technology Corporation
782 Sycamore Dr.
Milpitas, CA 95035
Phone: (408) 428-2050
FAX: (408) 432-6331
International Sales Offices
FRANCE
Linear Technology S.A.R.L.
Immeuble "Le Quartz"
58 Chemin de la Justice
92290 Chatenay Malabry
France
Phone: 33-1-41079555
FAX: 33-1-46314613
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Linear Technology Korea Branch
Namsong Building, #505
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Phone: 82-2-792-1617
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D-85386 Eching
Germany
Phone: 49-89-3197410
FAX: 49-89-3194821
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Linear Technology Pte. Ltd.
101 Boon Keng Road
#02-15 Kallang Ind. Estates
Singapore 1233
Phone: 65-293-5322
FAX: 65-292-0398
TAIWAN
Linear Technology Corporation
Rm. 801, No. 46, Sec. 2
Chung Shan N. Rd.
Taipei, Taiwan, R.O.C.
Phone: 886-2-521-7575
FAX: 886-2-562-2285
UNITED KINGDOM
Linear Technology (UK) Ltd.
The Coliseum, Riverside Way
Camberley, Surrey GU15 3YL
United Kingdom
Phone: 44-276-677676
FAX: 44-276-64851
JAPAN
Linear Technology KK
5F YZ Bldg.
Iidabashi, Chiyoda-Ku
Tokyo, 102 Japan
Phone: 81-3-3237-7891
FAX: 81-3-3237-8010
World Headquarters
Linear Technology Corporation
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
Phone: (408) 432-1900
FAX: (408) 434-0507
06/24/93
24
Linear Technology Corporation
LT/GP 0893 10K REV 0
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
 LINEAR TECHNOLOGY CORPORATION 1993