ON MJD42C Complementary power transistor Datasheet

MJD41C (NPN)
MJD42C (PNP)
Preferred Device
Complementary Power
Transistors
DPAK For Surface Mount Applications
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Designed for general purpose amplifier and low speed switching
applications.
Features
• Lead Formed for Surface Mount Applications in Plastic Sleeves
•
•
•
•
•
•
(No Suffix)
Straight Lead Version in Plastic Sleeves (“1” Suffix)
Electrically Similar to Popular TIP41 and TIP42 Series
Monolithic Construction With Built−in Base − Emitter Resistors
Epoxy Meets UL 94 V−0 @ 0.125 in
ESD Ratings: Human Body Model, 3B u 8000 V
Machine Model, C u 400 V
Pb−Free Packages are Available
SILICON
POWER TRANSISTORS
6 AMPERES
100 VOLTS, 20 WATTS
MARKING
DIAGRAMS
4
YWW
J4xCG
1 2
3
DPAK
CASE 369C
STYLE 1
MAXIMUM RATINGS
Rating
Symbol
Max
Unit
VCEO
100
Vdc
Collector−Base Voltage
VCB
100
Vdc
Emitter−Base Voltage
VEB
5
Vdc
IC
6
10
Adc
Base Current
IB
2
Adc
Total Power Dissipation @ TC = 25°C
Derate above 25°C
PD
20
0.16
W
W/°C
Total Power Dissipation (Note 1)
@ TA = 25°C
Derate above 25°C
PD
Operating and Storage Junction
Temperature Range
TJ, Tstg
Collector−Emitter Voltage
Collector Current
− Continuous
− Peak
W
1.75
0.014
W/°C
−65 to +150
°C
YWW
J4xCG
1
2
3
DPAK−3
CASE 369D
STYLE 1
Y
= Year
WW = Work Week
J4xC = Device Code
x = 1 or 2
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
THERMAL CHARACTERISTICS
Characteristic
4
Symbol
Max
Unit
Thermal Resistance, Junction−to−Case
RqJC
6.25
°C/W
Thermal Resistance, Junction−to−Ambient
(Note 1)
RqJA
71.4
°C/W
Preferred devices are recommended choices for future use
and best overall value.
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. These ratings are applicable when surface mounted on the minimum pad
sizes recommended.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 6
1
Publication Order Number:
MJD41C/D
MJD41C (NPN) MJD42C (PNP)
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ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
VCEO(sus)
100
−
Vdc
Collector Cutoff Current
(VCE = 60 Vdc, IB = 0)
ICEO
−
50
mAdc
Collector Cutoff Current
(VCE = 100 Vdc, VEB = 0)
ICES
−
10
mAdc
Emitter Cutoff Current
(VBE = 5 Vdc, IC = 0)
IEBO
−
0.5
mAdc
30
15
−
75
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage (Note 2)
(IC = 30 mAdc, IB = 0)
ON CHARACTERISTICS (Note 2)
hFE
DC Current Gain
(IC = 0.3 Adc, VCE = 4 Vdc)
(IC = 3 Adc, VCE = 4 Vdc)
−
Collector−Emitter Saturation Voltage
(IC = 6 Adc, IB = 600 mAdc)
VCE(sat)
−
1.5
Vdc
Base−Emitter On Voltage
(IC = 6 Adc, VCE = 4 Vdc)
VBE(on)
−
2
Vdc
Current Gain − Bandwidth Product (Note 3)
(IC = 500 mAdc, VCE = 10 Vdc, ftest = 1 MHz)
fT
3
−
MHz
Small−Signal Current Gain
(IC = 0.5 Adc, VCE = 10 Vdc, f = 1 kHz)
hfe
20
−
−
DYNAMIC CHARACTERISTICS
2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
3. fT = ⎪hfe⎪• ftest.
ORDERING INFORMATION
Device
MJD41CRL
MJD41CRLG
MJD41CT4
MJD41CT4G
MJD42C
Package Type
DPAK
369C
DPAK
(Pb−Free)
2500 / Tape & Reel
DPAK
MJD42C1
DPAK−3
MJD42C1G
DPAK−3
(Pb−Free)
MJD42CRL
DPAK
MJD42CT4G
1800 / Tape & Reel
DPAK
(Pb−Free)
DPAK
(Pb−Free)
MJD42CT4
Shipping †
DPAK
MJD42CG
MJD42CRLG
Package
75 Units / Rail
369D
1800 / Tape & Reel
DPAK
(Pb−Free)
369C
DPAK
2500 / Tape & Reel
DPAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
2
MJD41C (NPN) MJD42C (PNP)
PD, POWER DISSIPATION (WATTS)
TYPICAL CHARACTERISTICS
TA
2.5
TC
25
2
20
VCC
+30 V
+11 V
1.5
15
TA SURFACE MOUNT
10
0.5
5
0
0
25
50
tr, tf ≤ 10 ns
DUTY CYCLE = 1%
75
100
125
150
Figure 2. Switching Time Test Circuit
2
500
300
200
VCE = 2 V
TJ = 150°C
100
70
50
0.7
0.5
25°C
30
20
TJ = 25°C
VCC = 30 V
IC/IB = 10
1
t, TIME (s)
μ
hFE , DC CURRENT GAIN
−4 V
RB and RC VARIED TO OBTAIN DESIRED CURRENT LEVELS
D1 MUST BE FAST RECOVERY TYPE, e.g.:
MSB5300 USED ABOVE IB ≈ 100 mA
MSD6100 USED BELOW IB ≈ 100 mA
REVERSE ALL POLARITIES FOR PNP.
Figure 1. Power Derating
10
7
5
0.06
0.3
0.2
tr
0.1
0.07
−55 °C
td @ VBE(off) ≈ 5 V
0.05
0.2
0.1
0.3 0.4
0.6
1
2
4
0.03
0.02
0.06 0.1
6
0.2
0.4
1
2
IC, COLLECTOR CURRENT (AMP)
Figure 3. DC Current Gain
Figure 4. Turn−On Time
4
6
5
TJ = 25°C
TJ = 25°C
VCC = 30 V
IC/IB = 10
IB1 = IB2
3
2
1.6
t, TIME (s)
μ
ts
1.2
VCE(sat) @ IC/IB = 10
VBE @ VCE = 4 V
0.2 0.3 0.4
0.3
0.2
0.1
0.07
0.05
0.06 0.1
VBE(sat) @ IC/IB = 10
0.1
1
0.7
0.5
tf
0.4
0
0.06
0.6
IC, COLLECTOR CURRENT (AMP)
2
0.8
D1
51
−9 V
1
SCOPE
RB
0
TC
T, TEMPERATURE (°C)
V, VOLTAGE (VOLTS)
RC
25 ms
0.6
1
2
3
4
6
IC, COLLECTOR CURRENT (AMP)
0.2
0.4 0.6
1
2
IC, COLLECTOR CURRENT (AMP)
Figure 5. “On” Voltages
Figure 6. Turn−Off Time
http://onsemi.com
3
4
6
2
300
TJ = 25°C
TJ = 25°C
200
1.6
IC = 1 A
2.5 A
C, CAPACITANCE (pF)
VCE , COLLECTOR−EMITTER VOLTAGE (VOLTS)
MJD41C (NPN) MJD42C (PNP)
5A
1.2
0.8
Cib
100
70
Cob
50
0.4
0
10
20
30
50
100
200 300
IB, BASE CURRENT (mA)
500
1000
30
0.5
1
3
10
2
5
20
VR, REVERSE VOLTAGE (VOLTS)
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
50
Figure 8. Capacitance
Figure 7. Collector Saturation Region
1
0.7
0.5
30
D = 0.5
0.3
0.2
0.2
0.1
0.07
0.05
0.05
0.02
0.03
P(pk)
RqJC(t) = r(t) RqJC
RqJC = 6.25°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) qJC(t)
0.1
0.01
t1
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.02
0.01
0.01
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1
2 3
5
t, TIME (ms)
10
20
30
50
100
200 300
500
1000
Figure 9. Thermal Response
IC, COLLECTOR CURRENT (AMP)
10
500ms
5
3
2
1ms
dc
5ms
1
0.5
0.3
WIRE BOND LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
CURVES APPLY BELOW RATED VCEO
0.1
0.05
0.03
0.01
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 10 is based on TJ(pk) = 150_C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided
TJ(pk) v 150_C. TJ(pk) may be calculated from the data in
Figure 9. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
100ms
TC = 25°C SINGLE PULSE
TJ = 150°C
1
MJD41C, 42C
2
3
5 7 10
20 30
50 70 100
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
Figure 10. Maximum Forward Bias
Safe Operating Area
http://onsemi.com
4
MJD41C (NPN) MJD42C (PNP)
PACKAGE DIMENSIONS
DPAK
CASE 369C
ISSUE O
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
T
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
SOLDERING FOOTPRINT*
6.20
0.244
3.0
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
MJD41C (NPN) MJD42C (PNP)
PACKAGE DIMENSIONS
DPAK−3
CASE 369D−01
ISSUE B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
C
B
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
T
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MJD41C/D
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