LINER LTC1067-50 Rail-to-rail, very low noise universal dual filter building block Datasheet

LTC1067/LTC1067-50
Rail-to-Rail, Very Low Noise
Universal Dual Filter Building Block
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DESCRIPTION
FEATURES
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Rail-to-Rail Input and Output Operation
Operates from a Single 3V to ± 5V Supply
Dual 2nd Order Filter in a 16-Lead SSOP Package
> 80dB Dynamic Range on Single 3.3V Supply
Clock-to-Center Frequency Ratio of 100:1 for the
LTC1067 and 50:1 for the LTC1067-50
Internal Sampling-to-Center Frequency Ratio of
200:1 for the LTC1067 and 100:1 for the LTC1067-50
Center Frequency Error < ±0.2% Typ
Low Noise: < 40µVRMS, Q ≤ 5
Customizable with Internal Resistors
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APPLICATIONS
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Notch Filters
Narrowband Bandpass Filters
Tone Detection
Noise Reduction Systems
The LTC ®1067/LTC1067-50 consist of two identical railto-rail, high accuracy and very wide dynamic range 2nd
order switched-capacitor building blocks. Each building
block, together with three to five resistors, provides 2nd
order filter functions such as bandpass, highpass, lowpass,
notch and allpass. High precision 4th order filters are
easily designed.
The center frequency of each 2nd order section is tuned by
the external clock frequency. The internal clock-to-center
frequency ratio (100:1 for the LTC1067 and 50:1 for the
LTC1067-50) can be modified by the external resistors.
These devices have a double sampled architecture which
places aliasing and imaging components at twice the clock
frequency. The LTC1067-50 is a low power device consuming about one half the current of the LTC1067. The
LTC1067-50’s typical supply current is about 1mA from a
3.3V supply.
The LTC1067 and LTC1067-50 are available in 16-pin
narrow SSOP and SO packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Mask programmable versions of the LTC1067 and
LTC1067-50, with thin film resistors on-chip and custom
clock-to-cutoff frequency ratios, can be designed in an
SO-8 package to realize application specific monolithic
filters. Please contact LTC Marketing for more details.
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TYPICAL APPLICATION
Frequency Response
Single 3.3V Supply Rail-to-Rail,
4th Order, 10kHz Bandpass Filter
2
3
3.3V
4
0.1µF
R11
200k
IN
V+
NC
V+
SA
CLK
AGND
16
0
fCLK = 500kHz
15
14
V–
13
SB
–10
1µF
GAIN (dB)
1
5
LTC1067-50
12
LPA
LPB
R31, 200k
6
11
R32, 200k
R21, 10k
7
10
R22, 10k
8
BPA
HPA/NA
INV A
BPB
HPB/NB
INV B
–20
OUT
–30
9
–40
TOTAL OUTPUT NOISE: 90µVRMS
S/N RATIO: 80dB
RB1, 200k
1067 TA01
8
9
10
11
12
FREQUENCY (kHz)
1067 • TA02
1
LTC1067/LTC1067-50
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PACKAGE/ORDER INFORMATION
U
W W
V –)
W
to
.............................. 12V
Input Voltage ........................ (V + + 0.3V) to (V – – 0.3V)
Output Short-Circuit Duration .......................... Indefinite
Power Dissipation............................................... 500mV
Operating Temperature Range
LTC1067C................................................ 0°C to 70°C
LTC1067I............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
W
Total Voltage Supply (V +
U
ABSOLUTE MAXIMUM RATINGS
ORDER PART
NUMBER
TOP VIEW
V+
16 CLK
1
NC 2
15 AGND
V+ 3
14 V –
SA 4
13 SB
LPA 5
12 LPB
BPA 6
11 BPB
10 HPB/NB
HPA/NA 7
9
INV A 8
INV B
GN PACKAGE
S PACKAGE
16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO
LTC1067CGN
LTC1067-50CGN
LTC1067IGN
LTC1067-50IGN
LTC1067CS
LTC1067-50CS
LTC1067IS
LTC1067-50IS
TJMAX = 110°C, θJA = 135°C/ W (GN)
TJMAX = 110°C, θJA = 115°C/ W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Supply Range
Positive Output Voltage Swing
Negative Output Voltage Swing
Output Short-Circuit Current
(Source/Sink)
DC Open-Loop Gain
GBW Product
Slew Rate
LTC1067 (internal op amps) VS = 4.75V, TA = 25°C, unless otherwise noted.
CONDITIONS
VS = 3V, RL = 10k
VS = 4.75V, RL = 10k
VS = ±5V, RL = 10k
VS = 3V, RL = 10k
VS = 4.75V, RL = 10k
VS = ±5V, RL = 10k
VS = 3V
VS = 4.75V
VS = ±5V
RL = 10k
RL = 10k
RL = 10k
●
●
●
MIN
3
2.65
4.25
4.15
●
●
●
TYP
2.80
4.50
4.50
0.020
0.025
– 4.96
16/1.0
33/2.2
70/7.2
90
2.8
2.25
MAX
11
0.200
0.225
– 4.80
UNITS
V
V
V
V
V
V
V
mA
mA
mA
dB
MHz
V/µs
LTC1067 (complete filter) VS = 4.75V, fCLK = 250kHz, TA = 25°C, unless otherwise noted.
PARAMETER
Center Frequency Range, fO (Note 1)
Input Frequency Range
Clock-to-Center Frequency, fCLK/fO
Clock-to-Center Frequency Ratio,
Side-to-Side Matching
2
CONDITIONS
VS = 3V, fCLK = 250kHz, Mode 1, fO = 2.5kHz, Q = 5
R1 = R3 = 49.9k, R2 = 10k
VS = 4.75V, fCLK = 250kHz, Mode 1, fO = 2.5kHz, Q = 5
R1 = R3 = 49.9k, R2 = 10k
VS = ±5V, fCLK = 500kHz, Mode 1, fO = 5kHz, Q = 5
R1 = R3 = 49.9k, R2 = 10k
VS = 3V, fCLK = 250kHz, Q = 5
VS = 4.75V, fCLK = 250kHz, Q = 5
VS = ±5V, fCLK = 500kHz, Q = 5
MIN
TYP
0.001 to 20
0 to 1
100:1 ±0.2
●
100:1 ±0.2
●
100:1 ±0.2
●
●
●
●
±0.1
±0.1
±0.1
MAX
±0.70
±0.70
±0.70
±0.35
±0.35
±0.35
UNITS
kHz
MHz
%
%
%
%
%
%
%
%
%
LTC1067/LTC1067-50
ELECTRICAL CHARACTERISTICS
LTC1067 (complete filter) VS = 4.75V, fCLK = 250kHz, TA = 25°C, unless otherwise noted.
PARAMETER
Q Accuracy
fO Temperature Coefficient
Q Temperature Coefficient
DC Offset Voltage (See Table 2)
Clock Feedthrough
Maximum Clock Frequency
Power Supply Current
CONDITIONS
VS = 3V, fCLK = 250kHz, Q = 5
VS = 4.75V, fCLK = 250kHz, Q = 5
VS = ±5V, fCLK = 500kHz, Q = 5
MIN
●
●
●
VOS1 (DC Offset of Input Inverter)
VOS2 (DC Offset of First Integrator)
VOS3 (DC Offset of Second Integrator)
●
●
●
Q < 2.5, VS = ±5V
VS = 3V, fCLK = 250kHz
VS = 4.75V, fCLK = 250kHz
VS = ±5V, fCLK = 500kHz
●
●
●
TYP
±0.5
±0.5
±0.5
±1
±5
±3
±4
±4
150
2.0
2.50
3.00
4.35
MAX
±2
±2
±2
±12.5
±15.0
±15.0
4.5
5.5
7.5
UNITS
%
%
%
ppm/°C
ppm/°C
mV
mV
mV
µVRMS
MHz
mA
mA
mA
LTC1067-50 (internal op amps) VS = 4.75V, TA = 25°C, unless otherwise noted.
PARAMETER
Operating Supply Range
Positive Output Voltage Swing
Negative Output Voltage Swing
Output Short-Circuit Current
(Source/Sink)
DC Open-Loop Gain
GBW Product
Slew Rate
CONDITIONS
VS = 3V, RL = 10k
VS = 4.75V, RL = 10k
VS = ±5V, RL = 10k
VS = 3V, RL = 10k
VS = 4.75V, RL = 10k
VS = ±5V, RL = 10k
VS = 3V
VS = 4.75V
VS = ±5V
RL = 10k
RL = 10k
RL = 10k
●
●
●
MIN
2.7
2.65
4.25
4.15
●
●
●
TYP
2.80
4.50
4.50
0.020
0.025
– 4.96
16/0.6
33/1.2
70/5.7
90
1.9
0.8
MAX
11
0.200
0.225
– 4.80
UNITS
V
V
V
V
V
V
V
mA
mA
mA
dB
MHz
V/µs
LTC1067-50 (complete filter) VS = 4.75V, fCLK = 125kHz, TA = 25°C, unless otherwise noted.
PARAMETER
Center Frequency Range, fO (Note 1)
Input Frequency Range
Clock-to-Center Frequency, fCLK/fO
Clock-to-Center Frequency Ratio,
Side-to-Side Matching
Q Accuracy
CONDITIONS
VS = 3V, fCLK = 125kHz, Mode 1, fO = 2.5kHz, Q = 5
R1 = R3 = 49.9k, R2 = 10k
VS = 4.75V, fCLK = 125kHz, Mode 1, fO = 2.5kHz, Q = 5
R1 = R3 = 49.9k, R2 = 10k
VS = ±5V, fCLK = 250kHz, Mode 1, fO = 5kHz, Q = 5
R1 = R3 = 49.9k, R2 = 10k
VS = 3V, fCLK = 125kHz, Q = 5
VS = 4.75V, fCLK = 125kHz, Q = 5
VS = ±5V, fCLK = 250kHz, Q = 5
VS = 3V, fCLK = 125kHz, Q = 5
VS = 4.75V, fCLK = 125kHz, Q = 5
VS = ±5V, fCLK = 250kHz, Q = 5
MIN
TYP
0.001 to 40
0 to 1
50:1 ±0.2
●
50:1 ±0.2
●
50:1 ±0.3
●
●
●
●
●
●
●
±0.2
±0.2
±0.2
±0.5
±0.5
±0.5
MAX
±0.75
±0.75
±0.75
±0.55
±0.55
±0.55
±2
±2
±2
UNITS
kHz
MHz
%
%
%
%
%
%
%
%
%
%
%
%
3
LTC1067/LTC1067-50
ELECTRICAL CHARACTERISTICS
LTC1067-50 (complete filter) VS = 4.75V, fCLK = 125kHz, TA = 25°C, unless otherwise noted.
PARAMETER
fO Temperature Coefficient
Q Temperature Coefficient
DC Offset Voltage (See Table 2)
CONDITIONS
Clock Feedthrough
Maximum Clock Frequency
Power Supply Current
MIN
VOS1 (DC Offset of Input Inverter)
VOS2 (DC Offset of First Integrator)
VOS3 (DC Offset of Second Integrator)
●
●
●
Q < 2.5, VS = ±5V
VS = 3V, fCLK = 125kHz
VS = 4.75V, fCLK = 125kHz
VS = ±5V, fCLK = 250kHz
●
●
●
The ● denotes the specifications which apply over the full operating
temperature range.
TYP
±1
±5
±3
±4
±4
150
2.0
1.00
1.45
2.35
MAX
±12.5
±15.0
±15.0
2.5
3.0
4.0
UNITS
ppm/°C
ppm/°C
mV
mV
mV
µVRMS
MHz
mA
mA
mA
Note 1: See Typical Performance Characteristics.
U W
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1067 Maximum Q vs
Center Frequency
(Modes 1, 1B, 2 where R4 ≥ 10R2)
LTC1067 Maximum Q vs
Center Frequency
(Modes 2 where R4 < 10R2, 3)
50
VS = ±5V
fCLK(MAX) = 2MHz
40
–20
40
MAXIMUM Q
VS = 5V
fCLK(MAX) = 1.5MHz
30
VS = 3.3V
fCLK(MAX) = 1MHz
20
30
VS = 5V
fCLK(MAX) = 1.5MHz
20
VS = 3.3V
fCLK(MAX) = 1MHz
10
10
4TH ORDER BUTTERWORTH LPF
VS = SINGLE 3.3V, fIN = 1kHz
fCLK = 400kHz, f–3dB = 4kHz
RL = 20k
–30
VS = ±5V
fCLK(MAX) = 2MHz
(NOISE + THD)/SIGNAL (dB)
50
MAXIMUM Q
LTC1067
Noise + THD vs Input Voltage
–40
–50
–60
–70
MODE 1
–80
MODE 3
–90
0
0
0
10
5
15
CENTER FREQUENCY, fO (kHz)
20
0
10
5
15
CENTER FREQUENCY, fO (kHz)
20
LTC1067
Noise + THD vs Input Voltage
–50
–60
–70
–80
MODE 1
MODE 3
1
INPUT VOLTAGE (VRMS)
2
1067 G04
4
–40
–65
–50
–60
–70
–80
–90
–90
–100
0.1
–60
4TH ORDER BUTTERWORTH LPF
VS = ±5V, fIN = 1kHz
fCLK = 500kHz, f–3dB = 5kHz
RL = 20k
(NOISE + THD)/SIGNAL (dB)
–30
(NOISE + THD)/SIGNAL (dB)
(NOISE + THD)/SIGNAL (dB)
–40
LTC1067
Noise + THD vs Input Frequency
–20
–20
–100
0.1
2
1067 G03
LTC1067
Noise + THD vs Input Voltage
4TH ORDER BUTTERWORTH LPF
VS = SINGLE 5V, fIN = 1kHz
fCLK = 500kHz, f–3dB = 5kHz
RL = 20k
1
INPUT VOLTAGE (VRMS)
1067 G02
1067 G01
–30
–100
0.1
MODE 2
MODE 1
–70
–75
–80
MODE 3
–85
MODE 3
1
INPUT VOLTAGE (VRMS)
MODE 1
5
1067 G05
–90
1
4TH ORDER BUTTERWORTH LPF
VS = SINGLE 3.3V
fCLK = 400kHz, VIN = 0.36VRMS
f–3dB = 4kHz, RL = 20k
2
3
INPUT FREQUENCY (kHz)
4
5
1067 G06
LTC1067/LTC1067-50
U W
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1067
Noise + THD vs Input Frequency
LTC1067
Noise + THD vs Input Frequency
–75
MODE 1
–80
MODE 3
–85
4TH ORDER BUTTERWORTH LPF
VS = SINGLE 5V, fCLK = 500kHz
VIN = 0.5VRMS, f–3dB = 5kHz, RL = 20k
220
4TH ORDER LOWPASS
BUTTERWORTH
VS = ±5V, VIN = 1VRMS
fCLK = 1MHz, f–3dB = 10kHz
RL = 20k
–80
160
MODE 1
3
2
INPUT FREQUENCY (kHz)
4
5
9.2
9.0
8.8
8.6
8.4
8.0
4.5
4.5
VS = 5V
4.0
3.5
VS = 3.3V
3.0
2.5
2.0
0
4 6 8 10 12 14 16 18 20
LOAD RESISTANCE (kΩ TO GND)
2
4
6
8
3.0
–20°C
2.5
1.5
3
VS = ±5V
fCLK(MAX) = 2MHz
–20
VS = ±5V
fCLK(MAX) = 2MHz
40
MAXIMUM Q
10
LTC1067-50
Noise + THD vs Input Voltage
50
10
7
9
6
8
5
TOTAL POWER SUPPLY (V)
1067 G12
–30
VS = 5V
fCLK(MAX) = 1.5MHz
30
VS = 3.3V
fCLK(MAX) = 800kHz
20
VS = 3V
fCLK(MAX) = 600kHz
10
(NOISE + THD)/SIGNAL (dB)
50
VS = 3V
fCLK(MAX) = 600kHz
4
1067 G11
LTC1067-50
Maximum Q vs Center Frequency
(Modes 1, 1B, 2 Where R4 ≥ 10R2)
VS = 3.3V
fCLK(MAX) = 800kHz
25°C
2.0
LOAD RESISTANCE (kΩ TO V –)
LTC1067-50
Maximum Q vs Center Frequency
(Modes 2 Where R4 < 10R2, 3)
MAXIMUM Q
70°C
3.5
10 12 14 16 18 20
1067 G10
20
4.0
0
1.0
30
50
LTC1067
Power Supply Current
vs Power Supply
1.5
8.2
VS = 5V
fCLK(MAX) = 1.5MHz
40
1067 G09
POWER SUPPLY CURRENT (mA)
OUTPUT VOLTAGE SWING (VP-P)
9.4
30
20
1067 G08
LTC1067
Output Voltage Swing vs Load
Resistance, Single Supply Voltage
9.6
10
0
Q
5.0
40
3V
80
0
3
2
4 5 6 7 8 9 10
INPUT FREQUENCY (MHz)
1
VS = ±5V
2
100
20
10.0
0
5V
120
40
LTC1067
Output Voltage Swing vs Load
Resistance, ±5V Supply Voltage
9.8
140
60
MODE 3
–90
1
±5V
180
–85
1067 G07
OUTPUT VOLTAGE SWING (VP-P)
200
NOISE (µVRMS)
(NOISE + THD)/SIGNAL (dB)
(NOISE + THD)/SIGNAL (dB)
–75
–90
LTC1067
Noise vs Q
4TH ORDER BUTTERWORTH LPF
VS = SINGLE 3V, fIN = 1kHz
fCLK = 200kHz, f–3dB = 4kHz
–40
–50
–60
–70
–80
MODE 1
MODE 3
–90
0
0
20
10
30
CENTER FREQUENCY, fO (kHz)
0
40
1067 G13
0
20
10
30
CENTER FREQUENCY, fO (kHz)
40
1067 G14
–100
0.1
1
INPUT VOLTAGE (VRMS)
2
1067 G15
5
LTC1067/LTC1067-50
U W
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1067-50
Noise + THD vs Input Voltage
LTC1067-50
Noise + THD vs Input Voltage
–20
4TH ORDER BUTTERWORTH LPF
VS = SINGLE 5V, fIN = 1kHz
fCLK = 250kHz, f–3dB = 5kHz
RL = 20k
–40
–30
(NOISE + THD)/SIGNAL (dB)
–30
–50
–60
–70
MODE 1
–80
–90
–40
1
INPUT VOLTAGE (VRMS)
MODE 1
–65
–50
–60
MODE 3
MODE 2
–70
–80
MODE 1
–100
0.1
2
1
INPUT VOLTAGE (VRMS)
(NOISE + THD)/SIGNAL (dB)
–85
–90
3
2
INPUT FREQUENCY (kHz)
4
5
±5V
–70
MODE 1
–75
MODE 3
–80
–90
50
0
1
3
2
INPUT FREQUENCY (kHz)
4
OUTPUT VOLTAGE SWING (VP-P)
OUTPUT VOLTAGE SWING (VP-P)
9.0
8.8
8.6
8.4
8.0
2
4 6 8 10 12 14 16 18 20
LOAD RESISTANCE (kΩ TO GND)
1067 G22
10 15 20 25 30 35 40 45 50
1067 G21
LTC1067-50
Power Supply Current
vs Power Supply
2.2
VS = 5V
4.5
4.0
3.5
3.0
VS = 3V
2.5
2.0
2.0
1.8
70°C
1.6
1.4
20°C
1.2
25°C
1.0
0.8
1.0
0
5
Q
1.5
8.2
6
0
5
5.0
VS = ±5V
9.2
3V
150
LTC1067-50
Output Voltage Swing vs Load
Resistance, Single Supply Voltage
10.0
9.4
5V
200
1067 G20
LTC1067-50
Output Voltage Swing vs Load
Resistance, ±5V Supply Voltage
9.6
250
100
1067 G19
9.8
5
300
–85
1
4
350
POWER SUPPLY CURRENT (mA)
(NOISE + THD)/SIGNAL (dB)
MODE 3
–80
3
2
INPUT FREQUENCY (kHz)
400
4TH ORDER BUTTERWORTH LPF
VS = ±5V, fCLK = 250kHz
VIN = 1VRMS, f–3dB = 5kHz
RL = 20k
–65
MODE 1
1
LTC1067-50
Noise vs Q
–60
–70
4TH ORDER BUTTERWORTH LPF
VS = SINGLE 3V, fCLK = 200kHz
VIN = 0.34VRMS, f–3dB = 4kHz, RL = 20k
1067 G18
NOISE (µVRMS)
–60
–75
–80
LTC1067-50
Noise + THD vs Input Frequency
4TH ORDER BUTTERWORTH LPF
VS = SINGLE 5V, fCLK = 250kHz
VIN = 0.5VRMS, f–3dB = 5kHz, RL = 20k
MODE 3
1067 G17
LTC1067-50
Noise + THD vs Input Frequency
–65
–75
–90
5
1067 G16
–70
–85
–90
MODE 3
–100
0.1
–60
4TH ORDER BUTTERWORTH LPF
VS = ±5V, fIN = 1kHz
fCLK = 250kHz (225kHz FOR MODE 2)
f–3dB = 10kHz, RL = 20k
(NOISE + THD)/SIGNAL (dB)
–20
(NOISE + THD)/SIGNAL (dB)
LTC1067-50
Noise + THD vs Input Frequency
0
2
4
6
8
10 12 14 16 18 20
LOAD RESISTANCE (kΩ TO V –)
1067 G23
3
4
7
9
6
8
5
TOTAL POWER SUPPLY (V)
10
1067 G24
LTC1067/LTC1067-50
U W
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1067/LTC1067-50 Mode 3
Noise Increase vs R2/R4 Ratio
2.0
2.0
1.9
1.9
RELATIVE NOISE INCREASE
(REFERENCE NOISE WHEN R2/R4 = 1)
RELATIVE NOISE INCREASE
(REFERENCE NOISE WHEN R5/R6 = 0.02)
LTC1067/LTC1067-50 Mode 1B
Noise Increase vs R5/R6 Ratio
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
0.5
1.5 2.0 2.5
R5/R6 RATIO
1.0
3.0
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.2
1.0
0
1.8
3.5
0.3
0.4
0.5 0.6 0.7
R2/R4 RATIO
0.8
0.9
1.0
1067 G26
1067 G25
U
U
U
PIN FUNCTIONS
V +, V – (Pins 1, 3,14): The V + (Pins 1, 3) and the V – (Pin
14) should each be bypassed with a 0.1µF capacitor to an
adequate analog ground. The filter’s power supplies should
be isolated from other digital or high voltage analog
supplies. A low noise linear supply is recommended.
Using a switching power supply will lower the signal-to-
1
2
3
V+
4
0.1µF
5
6
7
8
STAR
SYSTEM
GROUND
V+
CLK
NC
AGND
V+
V–
SA
LTC1067
LTC1067-50
SB
LPA
LPB
BPA
BPB
HPA/NA
INV A
HPB/NB
INV B
DIGITAL
GROUND
PLANE
noise ratio of the filter. The supply’s power-up slew rate
should be less than 1V/µs. When V + is applied before V –, and
V – is allowed to go above ground, a diode should clamp V –
to prevent latch-up. Figures 1 and 2 show typical connections for dual and single supply operation.
16
1
15
2
14
13
3
V–
V+
0.1µF
0.1µF
4
12
5
11
6
10
7
9
8
STAR
SYSTEM
GROUND
200Ω
CLOCK
SOURCE
1067 F01
Figure 1. Dual Supply Ground Plane Connections
V+
CLK
NC
AGND
V+
V–
SA
LPA
LTC1067
LTC1067-50
BPA
HPA/NA
INV A
SB
LPB
BPB
HPB/NB
INV B
16
15
1µF
14
13
12
11
10
9
DIGITAL
GROUND
PLANE
200Ω
CLOCK
SOURCE
FOR MODE 3, THE SA AND SB SUMMING NODE PINS
ARE TIED TO THE AGND PIN
1067 F02
Figure 2. Single Supply Ground Plane Connections
7
LTC1067/LTC1067-50
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PIN FUNCTIONS
SA, SB (Pins 4, 13): Summing Inputs. The summing pins’
connection, along with the other resistor connections,
determine the circuit topology (mode) of each 2nd order
section. These pins should never be left floating.
LPA, BPA, HPA/NA, HPB/NB, BPB, LPB (Pins 5, 6, 7, 10,
11, 12): Output Pins. Each 2nd order section of the
LTC1067 has three outputs which typically source 33mA
and sink 2mA. Driving coaxial cable, capacitive loads or
resistive loads less than 10k will degrade the total harmonic distortion performance of any filter design. Refer to
Output Loading in the Applications Information section for
more details. When evaluating the distortion or noise
performance of a filter, the output should be buffered with
a wideband amplifier.
INV A, INV B (Pins 8, 9): Inverting Input. These pins are
the high impedance inverting inputs of internal op amps.
They are susceptible to stray capacitance coupling to low
impedance nodes such as signal outputs and power
supply lines. Resistors that are connected from a signal
output to the inverting input pin should be located as close
to the inverting input as possible.
AGND (Pin 15): Analog Ground. The filter performance
depends on the quality of the analog signal ground. For
either dual or single supply operation, an analog ground
plane surrounding the package is recommended. The
analog ground plane should be connected to any digital
ground at a single point. For dual supply operation Pin 15
is connected to the analog ground plane. For single supply
operation Pin 15 should be bypassed to the analog ground
plane with at least a 1µF capacitor. An on-chip resistive
voltage divider sets the bias at one-half of the supply.
CLK (Pin 16): Clock Input. Any CMOS logic clock source
with a square-wave output and a 50% duty cycle (±10%)
is an adequate clock source for the device. The power
supply for the clock source should not be the filter’s power
supply. The analog ground for the filter should be connected to the clock’s ground at a single point only. Table
1 shows the clock’s low and high level threshold values for
dual supply or single supply operation. Logic low level
signals must be greater than the negative supply voltage.
With a ±5V power supply, the clock levels may be either
±5V or 0V to 5V. Logic high level signals should be less
than the positive supply voltage. However, when the
positive supply voltage is either 3V or 3.3V, the clock
signal can be as high as 5.5V.
Table 1. Clock Source High and Low Threshold Levels
POWER SUPPLY
HIGH LEVEL
LOW LEVEL
±5V
≥ 2.2V
≤ 0.50V
Single 5V
≥ 2.2V
≤ 0.50V
Single 3V, 3.3V
≥ 2V
≤ 0.40V
Sine waves are not recommended for the clock input. The
clock signal should be routed from the right side of the IC
package to avoid coupling to any power supply lines or
input or output signal paths. A 200Ω resistor between the
clock source and Pin 16 will slow down the rise and fall
times of the clock to reduce charge coupling of the clock.
This will result in less clock feedthrough noise on the
output signal.
W
BLOCK DIAGRA
V+ 1
INV A
8
–
HPA/NA
BPA
LPA
7
6
5
HPB/NB
BPB
LPB
10
11
12
+
V+ 3
15k
SA
+
INV B
V – 14
4
AGND
15
15k
9
∑
–
+
–
+
∑
–
13
CLK
8
16
SB
1067 BD
LTC1067/LTC1067-50
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Linear Technology’s universal switched-capacitor filters
are designed with a fixed internal, nominal fCLK/fO ratio.
The LTC1067 has a 100:1 f CLK /f O ratio and the
LTC1067-50 has a 50:1 fCLK/fO ratio. Filter designs often
require the fCLK /fO ratio of each section to be different from
the nominal ratio and in most cases different from each
other. Ratios other than the nominal value are possible
with external resistors. Operating modes use external
resistors, connected in different arrangements to realize
different fCLK /fO ratios. By choosing the proper mode, the
fCLK /fO ratio can be increased or decreased from the part’s
nominal ratio.
The choice of operating mode also effects the transfer
function at the HP/N pins. The LP and BP pins always give
the lowpass and bandpass transfer functions respectively,
regardless of the mode utilized. The HP/N pins have a
different transfer function depending on the mode used.
Mode 1 yields a notch transfer function. Mode 3 yields a
highpass transfer function. Mode 2 yields a highpassnotch transfer function (i.e., a highpass with a stopband
notch). More complex transfer functions, such as lowpass-notch, allpass or complex zeros, are achieved by
summing two or more of the LP, BP or HP/N outputs. This
is illustrated in sections Mode 2n and Mode 3a.
Choosing the proper mode(s) for a particular application
is not trivial and involves much more than just adjusting
the fCLK/fO ratio. Listed here are six of the nearly twenty
modes available. To make the design process simpler and
quicker, Linear Technology has developed the FilterCADTM
for Windows® design software. FilterCAD is an easy-touse, powerful and interactive filter design program. The
designer can enter a few filter specifications and the
program produces a full schematic. FilterCAD allows the
designer to concentrate on the filter’s transfer function
and not get bogged down in the details of the design.
Alternatively, those who have experience with the Linear
Technology family of parts can control all of the details
themselves. For a complete listing of all the operating
modes, consult the appendices of the FilterCAD manual or
the Help files in FilterCAD. FilterCAD can be obtained free
of charge on the Linear Technology web site (http://
www.linear-tech.com) or you can order the FilterCAD
CD-ROM by contacting Linear Technology’s marketing
department.
Mode 1
In Mode 1, the ratio of the external clock frequency to the
center frequency of each 2nd order section is internally
fixed at the part’s nominal ratio. Figure 3 illustrates Mode
1 providing 2nd order notch, lowpass and bandpass
outputs. Mode 1 can be used to make high order Butterworth lowpass filters; it can also be used to make low Q
notches and for cascading 2nd order bandpass functions
tuned at the same center frequency. Mode 1 is faster than
Mode 3.
Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC.
CC
R3
R2
N
VIN
R1
–
+
AGND
S
+
Σ
–
LP
BP
∫
f
fO = CLK ; fn = fO
RATIO
R2
R3
Q = R3 ; HON = –
;H
=–
R1 OBP
R1
R2
HOLP = HON
∫
1067 F03
NOTE: RATIO = 100 FOR LTC1067
= 50 FOR LTC1067-50
Figure 3. Mode 1, 2nd Order Filter Providing Notch,
Bandpass and Lowpass Outputs
Mode 1b
Mode 1b is derived from Mode 1. In Mode 1b (Figure 4)
two additional resistors R5 and R6 are added to lower the
amount of voltage fed back from the lowpass output into
the input of the SA (or SB) switched-capacitor summer.
This allows the filter’s clock-to-center frequency ratio to
be adjusted beyond the part’s nominal ratio. Mode 1b
maintains the speed advantages of Mode 1 and should be
considered an optimum mode for high Q designs with fCLK
to fCUTOFF (or fCENTER) ratios greater than the part’s
nominal ratio.
FilterCAD is a trademark of Linear Technology Corporation.
Windows is a registered trademark of Microsoft Corporation.
9
LTC1067/LTC1067-50
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CC
R6
Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC.
R5
CC
R3
R4
R2
S
N
VIN
R1
–
+
Σ
+
AGND
NOTE: RATIO = 100 FOR LTC1067
= 50 FOR LTC1067-50
LP
BP
R2
–
∫
HP
∫
1067 F04
√
f
R6
fO = CLK
;f =f
RATIO (R6 + R5) n O
R3
R6 ; H = – R2 ; H
Q = R3
=–
R1 OBP
R1
R2 (R6 + R5) ON
R2 R6 + R5
HOLP = –
R6
R1
√
R3
(
VIN
R1
–
S
+
Σ
–
∫
+
)
fCLK
RATIO
1
R3 R2
R2
R3
√ R4 ; Q = 1.005 (R2) √ R4 (1 – (RATIO)(0.32)(R4)
)
R3
HOHP = – R2 ; HOBP = –
R1
R1
Figure 4. Mode 1b, 2nd Order Filter Providing Notch,
Bandpass and Lowpass Outputs
∫
1067 F05
fO =
AGND
LP
BP
1
R3
(1 – (RATIO)(0.32)(R4)
)
; HOLP = –
R4
R1
NOTE: RATIO = 100 FOR LTC1067
= 50 FOR LTC1067-50
The parallel combination of R5 and R6 should be kept
below 5k.
Figure 5. Mode 3, 2nd Order Section Providing
Highpass, Bandpass and Lowpass Outputs
Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC.
CC
Mode 3
In Mode 3, the ratio of the external clock frequency to the
center frequency of each 2nd order section can be adjusted above or below the part’s nominal ratio. Figure 5
illustrates Mode 3, the classical state variable configuration, providing highpass, bandpass and lowpass 2nd
order filter functions. Mode 3 is slower than Mode 1. Mode
3 can be used to make high order all-pole bandpass,
lowpass and highpass filters.
Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC.
Mode 2
Mode 2 is a combination of Mode 1 and Mode 3, shown in
Figure 6. With Mode 2, the clock-to-center frequency ratio,
fCLK/fO, is always less than the part’s nominal ratio. The
advantage of Mode 2 is that it provides less sensitivity to
resistor tolerances than does Mode 3. Mode 2 has a
highpass-notch output where the notch frequency
depends solely on the clock frequency and is therefore
less than the center frequency, fO.
10
R4
R3
R2
HPN
VIN
R1
–
+
S
Σ
+
–
LP
BP
∫
∫
1067 F06
AGND
√ 1 + R4 ; f = RATIO
R2
1
R3
Q = 1.005 ( ) 1 +
R2 √
R4
R3
(1 – (RATIO)(0.32)(R4)
)
fO =
fCLK
RATIO
HOHPN = –
HOBP = –
R2
n
fCLK
R2
R2
(AC GAIN, f >> fO); HOHPN = –
R1
R1
R3
R1
(
1
R3
1–
(RATIO)(0.32)(R4)
)
1
1 + R2
R4
(
; HOLP = – R2
R1
)
(DC GAIN)
1
1 + R2
R4
(
)
NOTE: RATIO = 100 FOR LTC1067
= 50 FOR LTC1067-50
Figure 6. Mode 2, 2nd Order Filter Providing Highpass
Notch, Bandpass and Lowpass Outputs
LTC1067/LTC1067-50
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Mode 3a
Mode 2n
This is an extension of Mode 3 where the highpass and
lowpass outputs are summed through two external resistors, RH and RL, to create a notch (see Figure 7). Mode 3a
is more versatile than Mode 2 because the notch frequency can be higher or lower than the center frequency
of the 2nd order section. The external op amp of Figure 7
is not always required. When cascading the sections of the
LTC1067, the highpass and lowpass outputs can be
summed directly into the inverting input of the next
section.
This mode extends the circuit topology of Mode 3a to
Mode 2 (Figure 8) where the highpass-notch and lowpass
outputs are summed through two external resistors, RH
and RL, to create a lowpass output with a notch higher in
frequency than the notch in Mode 2. This mode, shown in
Figure 8, is most useful in lowpass elliptic designs. When
cascading the sections of the LTC1067, the highpassnotch and lowpass outputs can be summed directly into
the inverting input of the next section.
Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC.
Please refer to the Operating Limits paragraph under Applications Information for a guide to the use of capacitor CC.
CC
√ R4 f = RATIO √ R
1
R2
Q = 1.005 (R3)
R2 √ R4
R3
(1 – (RATIO)(0.32)(R4)
)
R
R
(f = ∞) = ( ) ( R2 ) ; H
(f = 0) = ( ) ( R4 )
H
R R1
R R1
fO =
R4
R3
R2
HP
VIN
R1
–
+
S
Σ
–
+
LP
BP
fCLK
RATIO
R2
; n
fCLK
G
H
OHPn
RH
L
G
OLPn
L
NOTE: RATIO = 100 FOR LTC1067
= 50 FOR LTC1067-50
∫
∫
RL
RG
–
HIGHPASS
OR LOWPASS
NOTCH OUTPUT
RH
AGND
+
EXTERNAL OP AMP OR INPUT OP
AMP OF THE LTC1067, SIDES A OR B
1067 F07
Figure 7. Mode 3a, 2nd Order Filter Providing a Highpass Notch or Lowpass Notch Output
√
√
f
fO = CLK 1 + R2
RATIO
R4
f
R
fn = CLK
1+ H
RATIO
RL
RG RG
HOLPn (f = 0)=
+
RH RL
CC
R4
R3
Q = 1.005
R2
HP
VIN
R1
–
+
AGND
+
S
Σ
–
LP
BP
(
(R3R2) √ 1 + R2R4
)( ) (
R2
R1
1
1 + R2
R4
)
1
R3
(1 – (RATIO)(0.32)(R4)
)
NOTE: RATIO = 100 FOR LTC1067
= 50 FOR LTC1067-50
∫
∫
RL
RG
–
RH
+
LOWPASS
NOTCH
OUTPUT
EXTERNAL OP AMP OR INPUT OP AMP
OF THE LTC1067, SIDES A OR B
1067 F08
Figure 8. Mode 2n, 2nd Order Filter Providing a Lowpass Notch Output
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APPLICATIONS INFORMATION
A switched-capacitor integrator generally exhibits a higher
input offset than a discrete RC integrator. The larger offset
is mainly due to the charge injection from the CMOS
switches into the integrated capacitor. The integrator’s op
amp offset, typically a couple of millivolts, also adds to the
overall offset value. Figure 9 shows the input offsets from
a single 2nd order section. Table 2 lists the formula for the
output offset voltage for various modes and output pins.
HP/N
INV
VOS1
–
BP
+ ∑
–
+
VOS2
LP
VOS3
limits defined by the Typical Performance Characteristics
graphs, passband gain variations of 2dB or more should be
expected.
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics that are present at the filter’s
output pins. The clock feedthrough is tested with the
filter’s input grounded and depends on PC board layout
and on the value of the power supplies. With proper layout
techniques, the typical values of clock feedthrough are
listed under Electrical Characteristics.
1067 F09
S
Figure 9. Block Diagram of a 2nd Order Section
Showing the Input Offsets
Operating Limits
The Maximum Q vs Frequency (fO) graphs, under Typical
Performance Characteristics, define an upper limit of
operating Q for each LTC1067 (or LTC1067-50) 2nd order
section. These graphs indicate the power supply, fO and Q
value conditions under which a filter implemented with an
LTC1067 will remain stable when operated at temperatures of 70°C or less. For a 2nd order section, a bandpass
gain error of 3dB or less is arbitrarily defined as a condition
for stability.
When the passband gain error begins to exceed 1dB, the use
of capacitor CC will reduce the gain error (capacitor CC is
connected from the lowpass node to the inverting node of a
2nd order section). Please refer to Figures 3 through 8. The
value of CC can be best determined experimentally, and as a
guide it should be about 5pF for each 1dB of gain error and
not to exceed 15pF. When operating the LTC1067 near the
Any parasitic switching transients during the rising and
falling edges of the incoming clock are not part of the clock
feedthrough specifications. Switching transients have frequency contents much higher than the applied clock; their
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, can be greatly reduced by adding a
simple RC lowpass network at the final filter output. This
RC will completely eliminate any switching transients.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and is used to determine the operating signal-to-noise ratio. Most of its frequency contents lie within the filter passband and cannot
be reduced with post filtering. For a notch filter the noise
of the filter is centered at the notch frequency.
The total wideband noise (µVRMS) is nearly independent of
the value of the clock. The clock feedthrough specifications are not part of the wideband noise.
For a specific filter design, the total noise depends on the
Q of each section and the cascade sequence.
Table 2. Output DC Offsets for a Second Order Section
MODE
1
VOSHP/N
VOS1 [1 + (R2/R3) + (R2/R1)] – (VOS3)(R2/R3)
VOSBP
VOSLP
VOS3
VOSHP/N – VOS2
1b
VOS1 [1 + (R2/R3) + (R2/R1)] – (VOS3)(R2/R3)
VOS3
(VOSHP/N – VOS2)[1 + (R5/R6)]
2
VOS1 [1 + (R2/R3) + (R2/R1) + (R2/R4) – (VOS3)
(R2/R3)](R4/R2 + R4) + (VOS2)(R2/R2 + R4)
VOS3
VOSHP/N – VOS2
3
VOS2
VOS3
VOS1 [1 + (R4/R1) + (R4/R2) + (R4/R3)] – (VOS2)
(R4/R2) – (VOS3)(R4/R3)
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Aliasing
Aliasing is an inherent phenomenon of switched-capacitor
filters and occurs when the frequency of the input signals
that produce the strongest aliased components have a
frequency, fIN, such as (fSAMPLING – fIN) that falls into the
filter’s passband. For both the LTC1067 and the
LTC1067-50, the sampling frequency is twice fCLK. If the
input signal spectrum is not band limited, aliasing may
occur.
Output Loading
The op amps on the LTC1067/LTC1067-50 have a rail-torail output stage. The output loading issues can be divided
into resistive loading effects and capacitive loading effects.
Resistive loading effects the maximum output signal swing.
This effect is shown in the typical performance curves.
Note that the load on the output must include both the
feedback resistor and any external load resistor. For
example, consider the following situation: the part is
running on split power supplies, the section is configured
in Mode 3, the R4 resistor is 20k and an external 20k load
is connected from the LP node to ground. The load on the
LP output is 20k in parallel with 20k, or 10k. All testing on
the LTC1067/LTC1067-50 is done with a 10k load. For the
best results, the load resistance on all output pins should
be at least 10k.
Capacitive loading reduces the stability of the op amps.
The signal at the output of a switched-capacitor filter is
composed of a series of very small steps. The op amp
must respond to a step and fully settle before the next step.
As the stability of the op amp is decreased, the output step
response has increased ringing and a much longer settling
time. This longer settling time drastically lowers the maximum usable clock speed and introduces errors. If the
capacitive loading is sufficiently high, the stability will be
decreased to the point of oscillation at the output.
The LTC1067/LTC1067-50 are sensitive to capacitive loading. Capacitive loading should be kept below 20pF. Good,
tight layout techniques should be maintained at all times.
These parts should not drive long traces and never drive
a long coaxial cable. When probing the LTC1067 or
LTC1067-50, always use a 10× probe. Never use a 1×
probe. A standard 10× probe has a capacitance of 10pF to
15pF while a 1× probe’s capacitance can be as high as
150pF. The 1× probe will probably cause oscillation.
What to Do with an Unused Section
If the LTC1067 or LTC1067-50 is used as a single 2nd
order filter, the other 2nd order section is not used. Do not
leave this section unconnected. If the section is unconnected, inputs and outputs are left to float to undetermined
levels and oscillation may occur. The unused section
should be connected as shown in Figure 10.
V+
INV
–
∑
+
HP
BP
LP
1067 F10
Figure 10. Connections for an Unused Section
Output Voltage Swing on a Single Supply Voltage
The typical performance curves show the output voltage
swing limitations. The curves show the output signal
swing, in volts peak-to-peak, versus the output load resistance. The peak-to-peak swing is limited by the following
three considerations: the op amp’s output swings closer
to the negative supply than the positive supply, the AGND
pin is biased at the midpoint of the supplies and all
operating modes are inverting.
The op amps in the LTC1067/LTC1067-50 swing closer to
the negative supply rail than the positive supply rail. The
positive output voltage swing for single supply operation
is shown in Figures 11 and 12. The negative output voltage
swing is about 15mV for the LTC1067 and 10mV for the
LTC1067-50. The negative output voltage swing is nearly
independent of load resistance since the load in this case
is connected to the V – supply rail.
For single supply applications, the on-chip resistor divider
sets the voltage at the AGND pin to the midpoint of the V +
and V – potentials. The AGND voltage is the reference for
all internal op amps. If the input to the filter is at the V – rail,
13
LTC1067/LTC1067-50
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APPLICATIONS INFORMATION
POSITIVE OUTPUT VOLTAGE SWING (V)
5.0
4.5
LTC1067
4.0
LTC1067-50
3.5
3.0
2.5
0
2
4
6
8
10 12 14 16 18 20
LOAD RESISTANCE (kΩ TO V –)
1067 F11
Figure 11. LTC1067/LTC1067-50 Positive Output Voltage
Swing vs Load Resistance, 5V Supply
POSITIVE OUTPUT VOLTAGE SWING (V)
3.3
LTC1067
VS = 3.3V
3.0
2.7
LTC1067-50
VS = 3V
2.4
2.1
1.8
1.5
0
2
4
6
8
10 12 14 16 18 20
LOAD RESISTANCE (kΩ TO V –)
1067 F12
Figure 12. LTC1067/LTC1067-50 Positive Output Voltage
Swing vs Load Resistance, 3.3V/3V Supplies
Many applications are more concerned with the negative
output swing than the positive output swing. Interfacing to
an ADC running on a single 5V supply with a 4.096
reference voltage is a standard example. The LTC1067 or
LTC1067-50 will easily reach the 4.096V level for a fullscale reading. The issue is how close does the output go
to ground. The further the output is from ground, the more
codes that are essentially lost. The previous example
demonstrated that the lowest output voltage would be
about 250mV, although, as is shown below, 15mV is
achievable.
To achieve a lower negative output swing voltage, the
AGND voltage must be adjusted down below the midpoint.
The AGND voltage is determined by two equal, on-chip
resistors. These resistors are typically 15k each. While the
ratio of these two resistors is tightly matched, the absolute
value of the resistors is not tightly controlled. Adjusting
the AGND voltage by simply adding an external resistor
can be done, but caution must be exercised.
In Figure 13, a resistor is used to adjust the AGND voltage
for use with a 5V powered ADC with a full-scale input of
4.096V. The resistor value was chosen carefully to assure
that a 4.096V input signal to the filter yields a full-scale
reading from the ADC and a 0V input signal gives the
lowest possible value (15mV for the LTC1067 and 10mV
for the LTC1067-50). The circuit works well over temperature and part variations. For this application, the 5V supply
must be above 4.75V.
1
the output of the first section is near the positive rail
(operating modes invert the signal). The output of the first
stage will saturate at about 250mV (typical for 5V supply)
from positive supply. The output from the second stage
will be 250mV from the negative supply rail (assuming
inversion again) even though the op amp’s output is
capable of swinging to within 15mV.
2
3
5V
(4.75VMIN)
0.1µF
4
5
6
7
8
V+
CLK
NC
AGND
V+
V–
SA
LTC1067
LTC1067-50
SB
LPA
LPB
BPA
BPB
HPA/NA
INV A
HPB/NB
INV B
16
64.9k
1%
15
14
1µF
13
12
11
10
9
1067 F13
The positive output voltage swing being less than the
negative swing, coupled with the AGND potential set at the
midpoint of the supplies and inverting of the signal, yields
the following equation for peak-to-peak output swing:
VP-P Swing = (V + – V –) – 2(V+ – VPOSITIVE SWING)
14
Figure 13. Power and AGND Connections for
5V ADC with 4.096V Full Scale
LTC1067/LTC1067-50
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APPLICATIONS INFORMATION
Figure 14 illustrates how a resistor adjusts the AGND
voltage for use with a 3V/3.3V powered ADC with a fullscale input of 2.048V. As in the previous circuit, the
resistor value was chosen carefully to assure that a 2.048V
input signal to the filter yields a full-scale reading from the
ADC and a 0V input signal gives the lowest possible value.
For this application, the power supply must be above 2.7V
for an LTC1067-50 filter and above 3V for an LTC1067
filter.
1
2
3V TO 3.6V
(LTC1067)
2.7V TO 3.6V
(LTC1067-50)
0.1µF
3
4
5
6
7
8
V+
CLK
NC
AGND
V+
V–
SA
LTC1067
LTC1067-50
SB
LPA
LPB
BPA
BPB
HPA/NA
INV A
HPB/NB
INV B
16
33.2k
1%
15
14
1µF
13
12
11
10
9
1067 F14
Figure 14. Power and AGND Connections for
3V/3.3V ADC with 2.048V Full Scale
Semi-Custom Filter Program
Linear Technology has in place a program to deliver fully
integrated filters, custom designed for any specified application. These semi-custom filters are based on an existing
universal filter product with integrated, on-chip resistors.
The final filter is then tested to the exact parameters
defined for the application. The final result is a fully
integrated, accurately tested solution in a smaller package. For the LTC1067 or LTC1067-50 parts, a semicustom filter comes in the SO-8 package and requires only
a clock and a decoupling capacitor. For more details on the
semi-custom filter program, contact Linear Technology’s
marketing department.
Demonstration Board
There is a demonstration board available for the LTC1067/
LTC1067-50. Demonstration board 150A has the LTC1067
part installed and the board 150B has the LTC1067-50
installed. The schematic for the board is shown in Figure
15 and the assembly drawing is shown in Figure 16. To
obtain a demonstration board, call your local representative or Linear Technology’s marketing department.
The demonstration board has all integrated circuits, connectors and decoupling capacitors installed. The board is
ready to be configured with the appropriate resistors and
jumper connections.
There are two sets of power supply connections. One is for
the LTC1067/LTC1067-50 and the other is for the buffering op amp on the board. Having separate connections
gives the board the most flexibility. The two sets of
supplies can be connected together if a common supply is
desired.
When configuring the board for split supply operation, a
jumper wire must be installed in the JPAGND position.
This connects the AGND pin of the device to the ground
plane of the board. The JPVNEG jumper must be left open.
The power supply is then connected to V +, V – and GND
turrets (all of the GND turrets on the board are the same).
For single supply operation, insert a wire in the JPVNEG
jumper and leave the JPAGND jumper open. This connects
the V – pin to the board’s ground plane. The JPAGND
jumper must be left open so that the on-chip resistor
network can set the AGND potential at the midpoint of the
supply. Connect the power supply to V + and any GND
turret. The V – turret can be left open or shorted to the
adjacent GND turret. If the buffering op amp is run on the
same single voltage supply, the VOA + turret and the V +
turrets must be connected together and the VOA – turret
must be shorted to the adjacent GND turret.
The J1 BNC connector is the clock input. There is a 200Ω
series resistor connected between the connector and the
CLK pin of the part. This resistor, coupled with the CLK
pin’s input capacitance, slows down the rise and fall times
of the clock signal and decreases high frequency coupling.
The clock input is not terminated to 50Ω or 75Ω. An
external terminator should be used.
Jumpers JP51 and JP61 are connected in parallel with
R51 and R61 respectively. Jumper JP51 connects the LPA
pin of the part with the SA pin. This can be used for
operating modes 1 or 2. Alternatively, a 0Ω resistor in the
R51 position fulfills the same requirement. The JP61
jumper connects the SA pin of the part to the AGND pin.
15
LTC1067/LTC1067-50
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APPLICATIONS INFORMATION
This would be used for operating Mode 3. Here, a 0Ω
resistor in the R61 position also works. Jumpers JP52 and
JP62 perform the same functions on the B side of the part.
Several other jumpers should be connected as follows:
The buffering amplifier can be configured for inverting or
noninverting operation. For inverting applications, connect jumper JP2 positions 1 and 2. Additionally, connect
jumper JP4 for split supply applications or JP8 for a single
supply. For a noninverting application, connect jumper
JP2 positions 2 and 3.
JP5: Install a jumper wire if split supply, leave open if
single supply.
JP1: Install a jumper wire from position 1 to position 2,
leave the other positions open.
JP6: Leave open.
JP7: Install a jumper wire.
JP9: Install a jumper wire if single supply, leave open if
split supply.
CONNECT THIS JUMPER
FOR DUAL SUPPLIES
JPAGND
C1
10µF, 6.3V
CONNECT THIS JUMPER
FOR SINGLE SUPPLIES.
THE LTC1067 HAS ON-CHIP
RESISTORS TO GENERATE
1/2 SUPPLY FOR AGND
+
C2, 0.1µF
J1
CLOCK
IN
TP1
V+
JP61
C3 +
10µF
16V
C6, 0.1µF
1
D1
MBR0630T1
R61
2
JP51
3
TP9
4
R21
VIN
TP10
3
JP1
2 R11
4
NC
AGND
V+
V–
15
C7
0.1µF
RH1
RB1
RL1
C4
10µF
16V
+
R62
JP52
14
C5
R3
R2
TP8
JP8
R52
SA
JP3
TP2
V–
JP62
JPVNEG
RL2
5
R31
1
CLK
D2
MBR0630T1
LTC1067
13
OR
SB
LTC1067-50
12
LPA
LPB
6
11
BPA
BPB
7
10
HPA/NA
HPB/NB
8
9
INV A
INV B
R51
R41
TP4
V+
R1
200Ω
1%
16
RB2
RH2
+
C8
0.1µF
JP4
JP2
1 2 3
3 + 8
1/2
4 LT1498
C13
R32
R22
C10
0.1µF
TP3
VOA+
TP5
VOUT
1
2 –
R42
C9
10µF
36V
TP6
+
TP7
VOA–
C11
10µF
36V
TP11
JP9
JP6
JP5
R4
5 +
6 –
7
1/2
LT1498
JP7
C12
1067 F15
Figure 15. Schematic for the LTC1067/LTC1067-50 Demo Board
16
LTC1067/LTC1067-50
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APPLICATIONS INFORMATION
Figure 16. Silkscreen for the LTC1067/LTC1067-50 Demo Board
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TYPICAL APPLICATIONS
5th Order Lowpass with Input RC (Fixed Frequency)
1
5V
0.1µF
2
3
4
R41, 20k
R31, 47.5k
VIN
RIN1
16.9k
5
RIN2
22.6k
6
R21, 22.6k
7
8
CIN1
1500pF
5%
V+
CLK
NC
AGND
16
14
V–
V+
SA
SB
LTC1067
LPA
LPB
BPA
BPB
HPA/NA HPB/NB
INV A
INV B
fCLK
15
–5V
0.1µF
13
12
R42, 47.5k
11
R32, 29.4k
10
R22, 45.3k
VS
fCUTOFF
CIN1
fCLK
9
5V
10k
1500pF
1MHz
3V
5k
3000pF
500kHz
1067 TA05a
RH1, 118k
VOUT
RL1, 24.3k
Frequency Response (fCUTOFF = 10kHz)
Passband Gain Variation Due to CIN
10
1.00
0
0.75
–10
0.50
–20
0.25
–30
0
GAIN (dB)
GAIN (dB)
±5V
20k 15k
750pF 1000pF
2MHz 1.5MHz
–40
–50
–0.25
CIN1 = 1500pF + 5%
–0.50
–60
–0.75
–70
–1.00
–80
–1.25
–90
CIN1 = 1500pF – 5%
CIN1 = 1500pF
–1.50
1
10
FREQUENCY (kHz)
100
1067 TA05b
1
2
4
6 8 10
FREQUENCY (kHz)
20
1067 TA05c
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LTC1067/LTC1067-50
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TYPICAL APPLICATIONS
1kHz Linear Phase Bandpass Filter
1
5V
0.1µF
R61
40.2k
2
3
4
R51
4.99k
5
R31, 56.2k
6
R21, 10k
7
R11
60.4k
8
VIN
V+
CLK
NC
V
AGND
+
V
SA
100kHz
15
–5V
0.1µF
– 14
SB
LTC1067
LPA
LPB
BPA
BPB
HPA/NA HPB/NB
INV A
16
INV B
13
12
R42, 80.6k
11
R32, 53.6k
10
R22, 10k
VS
±5V
MAXIMUM
FREQUENCY 5kHz
CENTER
9
RB1, 36.5k
5V (OR ±2.5V) 3V (OR ±1.5V)
2.5kHz
2.2kHz
1067 TA06a
VOUT
Gain and Group Delay vs Frequency
Sine Burst Response
10
5
GAIN
0
INPUT
(500mV/DIV)
–10
3.0
DELAY
–15
2.5
–20
2.0
–25
1.5
–30
1.0
–35
0.5
–40
600
760
920
1080
FREQUENCY (Hz)
1240
DELAY (ms)
GAIN (dB)
–5
OUTPUT
(50mV/DIV)
0
1400
5ms/DIV
1067 TA06c
1067 TA06b
Single Supply, 4th Order Bandpass Filter
fCENTER = fCLK/64, – 3dB BW = fCENTER/20
1
5V
0.1µF
R61
7.32k
1µF
3
R51
4.99k
R31, 255k
R21, 4.99k
R11
267k
VIN
2
V+
CLK
NC
AGND
V+
V–
16
14
13
SB
LTC1067-50
12
5
LPA
LPB
4
6
7
8
SA
BPA
BPB
HPA/NA
INV A
HPB/NB
INV B
64kHz
15
VS
SINGLE 5V
SINGLE 3.3V
SINGLE 3V
R62
R52
4.99k 8.66k
11
R32, 255k
10
R22, 4.99k
VS
SINGLE 5V
SINGLE 3.3V
SINGLE 3V
9
RB1, 115k
VOUT
18
MAXIMUM fCENTER
12kHz
7.5kHz
5.5kHz
NOISE
(FILTER INPUT AT V +/2)
426 µVRMS
333 µVRMS
290 µVRMS
1067 TA07a
LTC1067/LTC1067-50
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TYPICAL APPLICATIONS
Single Supply, 4th Order Bandpass Filter
VS = 5V, fCLK = 64kHz
Gain vs Frequency
Gain vs Frequency
Sine Burst Response
1
0
0
5
–1
10
–2
15
–3
GAIN (dB)
GAIN (dB)
–5
20
25
–4
VOUT
(50mV/DIV)
–5
30
–6
35
–7
40
–8
45
500
VIN
(500mV/DIV)
–9
700
900
1100
1300
FREQUENCY (kHz)
1500
960
980
1000
1020
FREQUENCY (kHz)
1067 TA07b
5ms/DIV
1040
1067 TA07d
1067 TA07b
LTC1067 Dual Bandpass Filters
VS = ±5V, fCLK = 150kHz (fCENTER1 =1.3kHz, fCENTER2 = 2.1kHz)
5V
0.1µF
2
R61
15k
3
4
R51
4.99k
5
R31, 232k
6
R21, 4.99k
7
R11
232k
8
VIN1
V+
CLK
NC
V
AGND
+
V
SA
SB
LPA
LPB
BPA
BPB
HPA/NA HPB/NB
INV B
Frequency Response
5
150kHz
0
15
–5V
0.1µF
– 14
LTC1067
INV A
16
–5
13
12
R42, 5.23k
11
R32, 75k
10
R22, 4.99k
–15
–20
–25
–30
–35
9
–40
–45
R12,140k
VOUT1
VOUT1 VOUT2
–10
GAIN (dB)
1
1
VOUT2
VIN2
1067 TA08a
2
3
4
FREQUENCY (kHz)
5
1067 TA08b
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
16 15 14 13 12 11 10 9
0.004 – 0.0098
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.025
(0.635)
BSC
0.229 – 0.244
(5.817 – 6.198)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
0.150 – 0.157**
(3.810 – 3.988)
GN16 (SSOP) 1197
1
2 3
4
5 6
7
8
19
LTC1067/LTC1067-50
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
16
0.004 – 0.010
(0.101 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
15
14
13
12
11
10
9
0° – 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
S16 0695
3
2
1
4
5
6
7
8
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TYPICAL APPLICATION
1.02kHz Notch Filter for Telecom System
Frequency Response
0
0.1µF 2
3
R61, 9.88k*
4
R51, 4.99k* 5
R31, 61.9k
R21, 10k
C21, 300pF**
6
7
8
V+
CLK
NC
AGND
16
V+
SA
SB
LPA
LPB
BPA
BPB
HPA/NA
INV A
HPB/NB
INV B
fCLK = 125kHz
–20
1µF
–30
R62, 10k*
13
12 R52, 4.99k*
11
R32, 464k
10
R22, 75k
9
C22, 30pF**
–40
–50
–60
–70
VOUT
RH1, 40.2k
VIN***
–10
15
14
V–
LTC1067
200Ω
GAIN (dB)
1
5V
–80
–90
–100
800
R11, 18.7k
900
1000
1100
FREQUENCY (kHz)
* R51, R61, R52, R62 ARE 0.1% TOLERANCE RESISTORS
** C21 AND C22 IMPROVE THE NOTCH DEPTH WHERE
1
(30)(f NOTCH) <
< (75)(f NOTCH)
2π(R2x)(C2X)
WITHOUT C21 AND C22 THE NOTCH DEPTH IS LIMITED TO –35dB
1067 TA03
*** VIN ≤ 1.25VP-P
1200
1067 TA04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1068-25
High Speed Quad Universal Building Block Filter
25:1 Clock-to-fO Ratio
LTC1068-50
Low Power Quad Universal Building Block Filter
50:1 Clock-to-fO Ratio
LTC1068-200
Low Noise, Oversampled Quad Universal Building Block Filter
200:1 Clock-to-fO Ratio
LTC1068
Quad Universal Building Block Filter
100:1 Clock-to-fO Ratio
LTC1562
Quad, Universal, Continuous Time Building Block
10kHz < fC < 150kHz
20
Linear Technology Corporation
10675f LT/TP 0698 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1997