CMOS ST-BUSTM Family MT90820 Large Digital Switch Data Sheet Features August 2005 • 2,048 × 2,048 channel non-blocking switching at 8.192 Mb/s • Per-channel variable or constant throughput delay • Automatic identification of ST-BUS/GCI interfaces • Accept ST-BUS streams of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s • Automatic frame offset delay measurement • Per-stream frame delay offset programming • Per-channel high impedance output control Applications • Per-channel message mode • Medium and large switching platforms • Control interface compatible to Motorola nonmulitplexed CPUs • CTI application • Connection memory block programming • Voice/data multiplexer • IEEE-1149.1 (JTAG) Test Port • Digital cross connects • ST-BUS/GCI interface functions • Support IEEE 802.9a standard VDD VSS TMS TDI Ordering Information MT90820AP 84 Pin PLCC MT90820AL 100 Pin MQFP MT90820APR 84 Pin PLCC MT90820AL1 100 Pin MQFP* MT90820AP1 84 Pin PLCC* MT90820APR1 84 Pin PLCC* *Pb Free Matte Tin Tubes Trays Tape & Reel Trays Tubes Tape & Reel -40°C to +85°C TDO TCK TRST IC RESET ODE Test Port STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 Loopback Serial Parallel to Parallel Output MUX Multiple Buffer Data Memory Converter Timing Unit F0i Serial Converter Connection Memory Internal Registers CLK to FE/ WFPS HCLK Microprocessor Interface AS/ IM DS/ CS ALE RD R/W /WR A7-A0 DTA D15-D8/ CSTo AD7-AD0 Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2000-2005, Zarlink Semiconductor Inc. All Rights Reserved. STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15 MT90820 Data Sheet Description The MT90820 Large Digital Switch has a non-blocking switch capacity of 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s, 1,024 x 1,024 channels at 4.096 Mb/s and 512 x 512 channels at 2.048 Mb/s. The device has many features that are programmable on per stream or per channel basis, including message mode, input offset delay and high impedance output control. Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice channel and concatenated data channels. In addition, input stream can be individually calibrated for input frame offset using a dedicated pin. 2 Zarlink Semiconductor Inc. MT90820 VSS STo15 STo14 STo13 STo12 STo11 STo10 STo9 STo8 VDD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE VSS Data Sheet STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 F0i FE/HCLK VSS CLK VDD 8 10 6 4 2 84 82 80 78 76 13 73 15 71 17 69 19 67 84 PIN PLCC 21 CSTo DTA D15 D14 D13 D12 D11 D10 D9 D8 VSS VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VSS 65 23 63 25 61 27 59 29 57 31 55 36 38 40 42 44 46 48 50 52 NC NC NC NC VSS STo15 STo14 STo13 STo12 STo11 STo10 STo9 STo8 VDD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE VSS CSTo NC NC NC NC TMS TDI TDO TCK TRST IC RESET WFPS A0 A1 A2 A3 A4 A5 A6 A7 DS/RD R/W/RW CS AS/ALE IM 34 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 82 48 84 46 86 44 88 42 90 40 100 PIN MQFP 92 38 94 36 96 34 98 99 32 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 NC NC NC NC VDD TMS TDI TDO TCK TRST IC RESET WFPS A0 A1 A2 A3 A4 A5 A6 A7 DS/RD R/W/RW CS AS/ALE IM NC NC NC NC STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 F0i FE/HCLK VSS CLK Figure 2 - Pin Connections 3 Zarlink Semiconductor Inc. DTA D15 D14 D13 D12 D11 D10 D9 D8 VSS VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VSS MT90820 Data Sheet Pin Description Pin # Name Description 84 PLCC 100 MQFP 1, 11, 30, 54 64, 75 31, 41, 56, 66, 76, 99 VSS Ground. 2, 32, 63 5, 40, 67 VDD +5 Volt Power Supply. 3 - 10 68-75 STo8 - 15 ST-BUS Output 8 to 15 (Three-state Outputs): Serial data Output stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 - 1 in the IMS register. 12 - 27 81-96 STi0 - 15 ST-BUS Input 0 to 15 (Inputs): Serial data input stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 1 in the IMS register. 28 97 F0i Frame Pulse (Input): When the WFPS pin is low, this input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI specifications. When the WFPS pin is high, this pin accepts a negative frame pulse which conforms to WFPS formats. 29 98 FE/HCLK Frame Evaluation / HCLK Clock (Input): When the WFPS pin is low, this pin is the frame measurement input. When the WFPS pin is high, the HCLK (4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode. 31 100 CLK Clock (Input): Serial clock for shifting data in/out on the serial streams (STi/o 0 - 15). Depending upon the value programmed at bits DR0 - 1 in the IMS register, this input accepts a 4.096, 8.192 or 16.384 MHz clock. 33 6 TMS Test Mode Select (Input): JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. 34 7 TDI Test Serial Data In (Input): JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. 35 8 TDO Test Serial Data Out (Output): JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enable. 36 9 TCK Test Clock (Input): Provides the clock to the JTAG test logic. This pin is pulled high by an internal pull-up when not driven. 37 10 TRST Test Reset (Input): Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed low on power-up, or held low, to ensure that the MT90820 is in the normal functional mode. 38 11 IC Internal Connection (Input): Connect to VSS for normal operation. This pin must be low for the MT90820 to function normally and to comply with IEEE 1149 (JTAG) boundary scan requirements. This pin is pulled low internally when not driven. 4 Zarlink Semiconductor Inc. MT90820 Data Sheet Pin Description Pin # Name Description 12 RESET Device Reset (Schmitt Trigger Input): This input (active LOW) puts the MT90820 in its reset state that clears the device internal counters, registers and brings STo0 - 15 and microport data outputs to a high impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held low for a minimum of 100 nsec to reset the device. 40 13 WFPS Wide Frame Pulse Select (Input): When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in ST-BUS/GCI mode. 41 - 48 14-21 A0 - A7 Address 0 - 7 (Input): When non-multiplexed CPU bus operation is selected, these lines provide the A0 - A7 address lines to the internal memories. 49 22 DS/RD Data Strobe / Read (Input): For multiplexed bus operation, this input is DS. This active high DS input works in conjunction with CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This active low input works in conjunction with CS to enable the read and write operations. For multiplexed bus operation, this input is RD. This active low input sets the data bus lines (AD0-AD7, D8-D15) as outputs. 50 23 R/W / WR Read/Write / Write (Input): In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls the direction of the data bus lines (AD0 - AD7, D8-D15) during a microprocessor access. For multiplexed bus operation, this input is WR. This active low input is used with RD to control the data bus (AD0 - 7) lines as inputs. 51 24 CS 52 25 AS/ALE Address Strobe or Latch Enable (Input): This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed bus operation, connect this pin to ground. This pin is pulled low by an internal pull-down when not driven. 53 26 IM CPU Interface Mode (input): When IM is high, the microprocessor port is in the multiplexed mode. When IM is low, the microprocessor port is in non-multiplexed mode. This pin is pulled low by an internal pull-down when not driven. 55 - 62 32-39 AD0 - 7 Address/Data Bus 0 to 7 (Bidirectional): These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins are also the input address bits of the microprocessor port. 65 - 72 42-49 D8 - 15 Data Bus 8-15 (Bidirectional): These pins are the eight most significant data bits of the microprocessor port. 73 50 DTA Data Transfer Acknowledgement (Active Low Output): Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then tri-states, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is tri-stated. 74 55 CSTo Control Output (Output). This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1024 or 2048 bits per frame respectively. The level of each bit is determined by the CSTo bit in the connection memory. See External Drive Control Section. 84 PLCC 100 MQFP 39 Chip Select (Input): Active low input used by a microprocessor to activate the microprocessor port of MT90820. 5 Zarlink Semiconductor Inc. MT90820 Data Sheet Pin Description Pin # Name Description 57 ODE Output Drive Enable (Input): This is the output enable control for the STo0 to STo15 serial outputs. When ODE input is low and the OSB bit of the IMS register is low, STo015 are in a high impedance state. If this input is high, the STo0-15 output drivers are enabled. However, each channel may still be put into a high impedance state by using the per channel control bit in the connection memory. 77 - 84 58-65 STo0 - 7 - 1 - 4, 27 - 30, 51 - 54 77 - 80 NC 84 PLCC 100 MQFP 76 Data Stream Output 0 to 7 (Three-state Outputs): Serial data Output stream. These streams have selectable data rates of 2.048, 4.096 or 8.192 Mb/s. No connection. Device Overview The MT90820 Large Digital Switch is capable of switching up to 2,048 × 2,048 channels. The MT90820 is designed to switch 64 kbit/s PCM or N x 64 kbit/s data. The device maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis. The serial input streams of the MT90820 can have a bit rate of 2.048, 4.096 or 8.192 Mbit/s and are arranged in 125 µs wide frames, which contain 32, 64 or 128 channels, respectively. The data rates on input and output streams are identical. By using Zarlink’s message mode capability, the microprocessor can access input and output time-slots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other STBUS devices. The MT90820 automatically identifies the polarity of the frame synchronization input signal and configures its serial streams to be compatible to either ST-BUS or GCI formats. Two different microprocessor bus interfaces can be selected through the Input Mode pin (IM): Non-multiplexed or Multiplexed. These interfaces provide compatibility with multiplexed and Motorola non-multiplexed buses. The frame offset calibration function allows users to measure the frame offset delay using a frame evaluation pin (FE). The input offset delay can be programmed for individual streams using internal frame input offset registers, see Table 11. The internal loopback allows the ST-BUS output data to be looped around to the ST-BUS inputs for diagnostic purposes. Functional Description A functional Block Diagram of the MT90820 is shown in Figure 1. Data and Connection Memory For all data rates, the received serial data is converted to parallel format by internal serial-to-parallel converters and stored sequentially in the data memory. Depending upon the selected operation programmed in the interface mode select (IMS) register, the useable data memory may be as large as 2,048 bytes. The sequential addressing of the data memory is performed by an internal counter, which is reset by the input 8 kHz frame pulse (F0i) to mark the frame boundaries of the incoming serial data streams. 6 Zarlink Semiconductor Inc. MT90820 Data Sheet Data to be output on the serial streams may come from either the data memory or connection memory. Locations in the connection memory are associated with particular ST-BUS output channels. When a channel is due to be transmitted on an ST-BUS output, the data for this channel can be switched either from an ST-BUS input in connection mode, or from the lower half of the connection memory in message mode. Data destined for a particular channel on a serial output stream is read from the data memory or connection memory during the previous channel time-slot. This allows enough time for memory access and parallel-to-serial conversion. Connection and Message Modes In the connection mode, the addresses of the input source data for all output channels are stored in the connection memory. The connection memory is mapped in such a way that each location corresponds to an output channel on the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 13 and Table 14. Once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto an ST-BUS output stream. By having several output channels connected to the same input source channel, data can be broadcasted from one input channel to several output channels. In message mode, the microprocessor writes data to the connection memory locations corresponding to the output stream and channel number. The lower half (8 least significant bits) of the connection memory content is transferred directly to the parallel-to-serial converter. This data will be output on the ST-BUS streams in every frame until the data is changed by the microprocessor. The five most significant bits of the connection memory controls the following for an output channel: message or connection mode, constant or variable delay, enables/tristate the ST-BUS output drivers and enables/disable the loopback function. In addition, one of these bits allows the user to control the CSTo output. If an output channel is set to a high-impedance state through the connection memory, the ST-BUS output will be in a high impedance state for the duration of that channel. In addition to the per-channel control, all channels on the ST-BUS outputs can be placed in a high impedance state by either pulling the ODE input pin low or programming the output stand by (OSB) bit in the interface mode selection register to low. This action overrides the individual per-channel programming by the connection memory bits. The connection memory data can be accessed via the microprocessor interface through the D0 to D15 pins. The addressing of the device internal registers, data and connection memories is performed through the address input pins and the Memory Select (MS) bit of the control register. For details on device addressing, see Software Control and Control Register bits description (Table 4, Tables 6 and 7). Serial Data Interface Timing The master clock frequency must always be twice the data rate. The master clock (CLK) must be either at 4.096, 8.192 or 16.384 MHz for serial data rate of 2.048, 4.096 or 8.192 Mb/s respectively. The input and output stream data rates will always be identical. The MT90820 provides two different interface timing modes controlled by the WFPS pin. If the WFPS pin is low, the MT90820 is in ST-BUS/GCI mode. If the WFPS pin is high, the MT90820 is in the wide frame pulse (WFP) frame alignment mode. In ST-BUS/GCI mode, the input 8 kHz frame pulse can be in either ST-BUS or GCI format. The MT90820 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of CLK, three quarters of the way into the bit cell. In GCI format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell, see Figure 12. 7 Zarlink Semiconductor Inc. MT90820 Data Sheet Wide Frame Pulse (WFP) Frame Alignment Timing When the device is in WFP frame alignment mode, the CLK input must be at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 kHz frame pulse is in ST-BUS format. The timing relationship between CLK, HCLK and the frame pulse is defined in Figure 12. When WFPS pin is high, the frame alignment evaluation feature is disabled, but the frame input offset registers may still be programmed to compensate for the varying frame delays on the serial input streams. Switching Configurations The MT90820 maximum non-blocking switching configurations is determined by the data rates selected for the serial inputs and outputs. The switching configuration is selected by two DR bits in the IMS register. See Table 8 and Table 9. 2.048 Mb/s Serial Links (DR0=0, DR1=0) When the 2.048 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 32 64 Kbit/s channels each. This mode requires a CLK of 4.094 MHz and allows a maximum non-blocking capacity of 512 x 512 channels. 4.096 Mb/s Serial Links (DR0=1, DR1=0) When the 4.096 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 64 64 Kbit/s channels each. This mode requires a CLK of 8.192 MHz and allows a maximum non-blocking capacity of 1,024 x 1,024 channels. 8.192 Mb/s Serial Links (DR0=0, DR1=1) When the 8.192 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 128 64 Kbit/s channels each. This mode requires a CLK of 16.384 MHz and allows a maximum nonblocking capacity of 2,048 x 2,048 channels. Table 1 summarizes the switching configurations and the relationship between different serial data rates and the master clock frequencies. Serial Interface Data Rate Master Clock Required (MHz) Matrix Channel Capacity 2 Mb/s 4.096 512 x 512 4 Mb/s 8.192 1,024 x 1,024 8 Mb/s 16.384 2,048 x 2,048 Table 1 - Switching Configuration 8 Zarlink Semiconductor Inc. MT90820 Data Sheet Input Frame Offset Selection Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e., F0i). This feature is useful in compensating for variable path delays caused by serial backplanes of variable lengths, which may be implemented in large centralized and distributed switching systems. Each input stream can have its own delay offset value by programming the frame input offset (FOR) registers. Possible adjustment can range up to +4 master clock (CLK) periods forward with resolution of 1/2 clock period. The output frame offset cannot be offset or adjusted. See Figure 4, Table 11 and Table 12 for delay offset programming. Serial Input Frame Alignment Evaluation The MT90820 provides the frame evaluation (FE) input to determine different data input delays with respect to the frame pulse F0i. A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the evaluation starts when the SFE bit in the IMS register is changed from low to high. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register (FAR) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the FAR register. The SFE bit must be set to zero before a new measurement cycle started. In ST-BUS mode, the falling edge of the frame measurement signal (FE) is evaluated against the falling edge of the ST-BUS frame pulse. In GCI mode, the rising edge of FE is evaluated against the rising edge of the GCI frame pulse. See Table 10 & Figure 3 for the description of the frame alignment register. This feature is not available when the WFP Frame Alignment mode is enabled (i.e., when the WFPS pin is connected to VDD). Memory Block Programming The MT90820 provides users with the capability of initializing the entire connection memory block in two frames. Bits 11 to 15 of every connection memory location will be programmed with the pattern stored in bits 5 to 9 of the IMS register. The block programming mode is enabled by setting the memory block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data will be loaded into the bits 11 to 15 of every connection memory location. The other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero. Loopback Control The loopback control (LPBK) bit of each connection memory location allows the ST-BUS output data to be looped backed internally to the ST-BUS input for diagnostic purposes. If the LPBK bit is high, the associated ST-BUS output channel data is internally looped back to the ST-BUS input channel (i.e., data from STo n channel m will appear in STi n channel m). Note: when LPBK is activated in channel m STo n+1 (for n even) or STo n-1 (for n odd), the data from channel m of STi n will be switched to channel m STo n. The associated frame delay offset register must be set to zero for proper operation of the per-channel loopback function. If the LPBK bit is low, the per-channel loopback feature is disabled and the device will function normally. Delay Through the MT90820 The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on the per-channel basis. For voice application, select variable throughput delay to ensure minimum 9 Zarlink Semiconductor Inc. MT90820 Data Sheet delay between input and output data. In wideband data applications, select constant throughput delay to maintain the frame integrity of the information through the switch. The delay through the device varies according to the type of throughput delay selected in the V/C bit of the connection memory. Variable Delay Mode (V/C bit = 0) The delay in this mode is dependent only on the combination of source and destination channels and is independent of input and output streams. The minimum delay achievable in the MT90820 is three time-slots. When the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame (channel n, frame p+1). The same frame delay occurs if the input channel n is switched to output channel n+1 or n+2. When input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. Table 2 shows the possible delays for the MT90820 in the variable delay mode. Constant Delay Mode (V/C bit = 1) In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2. In the MT90820, the minimum throughput delay achievable in the constant delay mode will be one frame. For example, in 2 Mb/s mode, when input time-slot 31 is switched to output time-slot 0. The maximum delay of 94 timeslots of delay occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 3. Delay for Variable Throughput Delay Mode (m - output channel number) (n - input channel number)) Input Rate m<n m = n, n+1, n+2 m > n+2 2.048 Mb/s 32 - (n-m) time-slots m-n + 32 time-slots m-n time-slots 4.096 Mb/s 64 - (n-m) time-slots m-n + 64 time-slots m-n time-slots 8.192 Mb/s 128 - (n-m) time-slots m-n + 128 time-slots m-n time-slots Table 2 - Variable Throughput Delay Value Input Rate Delay for Constant Throughput Delay Mode (m - output channel number) (n - input channel number)) 2.048 Mb/s 32 + (32 - n) + (m - 1) time-slots 4.096 Mb/s 64 + (64 - n) + (m- 1) time-slots 8.192 Mb/s 128 + (128 - n) + (m- 1) time-slots Table 3 - Constant Throughput Delay Value Microprocessor Interface The MT90820 provides a parallel microprocessor interface for non-multiplexed or multiplexed bus structures. This interface is compatible with Motorola non-multiplexed and multiplexed buses. If the IM pin is low, the MT90820 microprocessor interface assumes Motorola non-multiplexed bus mode. If the IM pin is high, the device micro-processor interface accepts two different timing modes (mode1 and mode2) which allows direct connection to multiplexed microprocessors. 10 Zarlink Semiconductor Inc. MT90820 Data Sheet The microprocessor interface automatically identifies the type of micro-processor bus connected to the MT90820. This circuit uses the level of the DS/RD input pin at the rising edge of AS/ALE to identify the appropriate bus timing connected to the MT90820. If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the mode 2 multiplexed bus timing is selected. For multiplexed operation, the required signals are the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch enable (AS/ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR), Chip select (CS) and Data transfer acknowledge (DTA). See Figure 13 and Figure 14 for multiplexed parallel microport timing. For the Motorola non-multiplexed bus, the required signals are the 16-bit data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines (CS, DS, R/W and DTA). See Figure 15 for Motorola non-multiplexed microport timing. The MT90820 microport provides access to the internal registers, connection and data memories. All locations provide read/write access except for the data memory and the frame alignment register which are read only. Memory Mapping The address bus on the microprocessor interface selects the internal registers and memories of the MT90820. If the A7 address input is low, then the control (CR), interface mode selection (IMS), frame alignment (FAR) and frame input offset (FOR) registers are addressed by A6 to A0 according to Table 4. If the A7 is high, then the remaining address input lines are used to select memory subsections of up to 128 locations corresponding to the maximum number of channels per input or output stream. The address input lines and the stream address bits (STA) of the control register allow access to the entire data and connection memories. The control and IMS registers together control all the major functions of the device. The IMS register should be programmed immediately after system power-up to establish the desired switching configuration as explained in the Serial Data Interface Timing and Switching Configurations sections. The control register is used to control switching operations in the MT90820. It selects the internal memory locations that specify the input and output channels selected for switching. The data in the control register consists of the memory block programming bit (MBP), the memory select bit (MS) and the stream address bits (STA). The memory block programming bit allows users to program the entire connection memory block, (see Memory Block Programming section). The memory select bit controls the selection of the connection memory or the data Memory. The stream address bits define an internal memory subsections corresponding to input or output ST-BUS streams. The data in the IMS register consists of block programming bits (BPD0-BPD4), block programming enable bit (BPE), output stand by bit (OSB), start frame evaluation bit (SFE) and data rate selection bits (DR0, DR1). The block programming and the block programming enable bits allows users to program the entire connection memory, (see Memory Block Programming section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-BUS output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all ST-BUS output drivers are enabled. Connection Memory Control The contents of the CSTo bit of each connection memory location are output on the CSTo pin once every frame. The CSTo pin is a 4.096, 8.192 or 16.384 Mb/s output, which carries 512, 1,024 or 2,048 bits, respectively. If the CSTo bit is set high, the corresponding bit on the CSTo output is transmitted high. If the CSTo bit is low, the corresponding bit on the CSTo output is transmitted low. The contents of the CSTo bits of the connection memory are transmitted sequentially on to the CSTo pin and are synchronous with the data rates on the other ST-BUS streams. The CSTo bit is output one channel before the corresponding channel on the ST-BUS. For example, in 2 Mb/s mode, the contents of the CSTo bit in position 0 (STo0, CH0) of the connection memory is output on the first clock 11 Zarlink Semiconductor Inc. MT90820 Data Sheet cycle of channel 31 through CSTo pin. The contents of the CSTo bit in position 32 (STo1, CH0) of the connection memory is output on the second clock cycle of channel 31 via CSTo pin. If the ODE pin or the OSB bit is high, the OE bit of each connection memory location enables (if high) or disables (if low) the output drivers for an individual ST-BUS output stream and channel. See Table 5 for detail. The message channel (MC) bit of the connection memory enables (if high) an associated ST-BUS output channel in message mode. If the MC bit is low, the contents of the stream address bit (SAB) and the channel address bit (CAB) of the connection memory defines the source information (stream and channel) of the time-slot that will be switched to the output. When message mode is enabled, only the lower half (8 least significant bits) of the connection memory is transferred to the ST-BUS outputs. Bit V/C (Variable/Constant Delay) of each connection memory location allows the per-channel selection between variable and constant throughput delay modes. If the LPBK bit is high, the associated ST-BUS output channel data is internally looped back to the ST-BUS input channel (i.e., data from STo n channel m will appear in STi n channel m). Note: when LPBK is activated in channel m STo n+1 (for n even) or STo n-1 (for n odd), the data from channel m of STi n will be switched to channel m STo n. The associated frame delay offset register must be set to zero for proper operation of the per-channel loopback function. If the LPBK bit is low, the per-channel loopback feature is disabled and the device will function normally. Initialization of the MT90820 After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after power up to keep all ST-BUS outputs in a high impedance state until the microprocessor has initialized the switching matrix. During the microprocessor initialization routine, the microprocessor should program the desired active paths through the switch, and put all other channels into a high impedance state. This procedure prevents two ST-BUS outputs from driving the same stream simultaneously. When this process is complete, the microprocessor controlling the matrices can bring the ODE pin or OSB bit high to relinquish the high impedance state control to the OE bit in the connection memory. A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 Control Register, CR 0 0 0 0 0 0 0 1 Interface Mode Selection Register, IMS 0 0 0 0 0 0 1 0 Frame Alignment Register, FAR 0 0 0 0 0 0 1 1 Frame Input Offset Register 0, FOR0 0 0 0 0 0 1 0 0 Frame Input Offset Register 1, FOR1 0 0 0 0 0 1 0 1 Frame Input Offset Register 2, FOR2 0 0 0 0 0 1 1 0 Frame Input Offset Register 3, FOR3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 1 . 0 1 Ch 0 Ch 1 . Ch 30 Ch 31 (Note 1) 12 Zarlink Semiconductor Inc. Location (Note 2) MT90820 Data Sheet A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 1 . 0 1 Ch 32 Ch 33 . Ch 62 Ch 63 1 1 1 1 1 1 1 1 1 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 1 . 0 1 Ch 64 Ch 65 . Ch 126 Ch 127 (Note 1) Location (Note 3) (Note 4) Notes: 1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers. 2. Channels 0 to 31 are used when serial interface is at 2 Mb/s mode. 3. Channels 0 to 63 are used when serial interface is at 4 Mb/s mode. 4. Channels 0 to 127 are used when serial interface is at 8 Mb/s mode. Table 4 - Internal Register and Address Memory Mapping OE bit in Connection Memory ODE pin OSB bit in IMS register ST-BUS Output Driver Status 0 Don’t Care Don’t Care Per Channel High Impedance 1 0 0 High Impedance 1 0 1 Enable 1 1 0 Enable 1 1 1 Enable Table 5 - Output High Impedance Control Read/Write Address: Reset Value: 00H, 0000H. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 MBP MS STA3 STA2 STA1 STA0 Bit Name 15 - 6 Unused 5 MBP 4 MS Description Must be zero for normal operation. Memory Block Program. When 1, the connection memory block programming feature is ready for the programming of Connection Memory high bits, bit 11 to bit 15. When 0, this feature is disabled. Memory Select. When 0, connection memory is selected for read or write operations. When 1, the data memory is selected for read operations and connection memory is selected for write operations. (No microprocessor write operation is allowed for the data memory.) 13 Zarlink Semiconductor Inc. MT90820 Read/Write Address: Reset Value: Data Sheet 00H, 0000H. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 MBP MS STA3 STA2 STA1 STA0 Bit Name 3-0 STA3-0 Description Stream Address Bits. The binary value expressed by these bits refers to the input or output data stream, which corresponds to the subsection of memory made accessible for subsequent operations. (STA3 = MSB, STA0 = LSB) Table 6 - Control (CR) Register Bits Input/Output Data Rate Valid Address Lines 2.048 Mb/s A4, A3, A2, A1, A0 4.096 Mb/s A5, A4, A3, A2, A1, A0 8.192 Mb/s A6, A5, A4 A3, A2, A1, A0 Table 7 - Valid Address Lines for Different Bit Rates Read/Write Address: Reset Value: 01H, 0000H. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 BPD 4 BPD 3 BPD 2 BPD 1 BPD 0 BPE OSB SFE DR1 DR0 Bit Name Description 15-10 Unused Must be zero for normal operation. 9-5 BPD4-0 Block Programming Data. These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD4- 0 are loaded into bit 15 to bit 11 of the connection memory. Bit 10 to bit 0 of the connection memory are set to 0. 4 BPE Begin Block programming Enable. A zero to one transition of this bit enables the memory block programming function. The BPE and BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set high, the device requires two frames to complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort the programming operation. When BPE = 1, the other bits in the IMS register must not be changed for two frames to ensure proper operation. 14 Zarlink Semiconductor Inc. MT90820 Read/Write Address: Reset Value: Data Sheet 01H, 0000H. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 BPD 4 BPD 3 BPD 2 BPD 1 BPD 0 BPE OSB SFE DR1 DR0 Bit Name Description 3 OSB Output Stand By. When ODE = 0 and OSB = 0, the output drivers of STo0 to STo15 are in high impedance mode. When ODE = 0 and OSB = 1, the output driver of STo0 to STo15 function normally. When ODE = 1, STo0 to STo15 output drivers function normally. 2 SFE Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from zero to one, the evaluation procedure stops. To start another frame evaluation cycle, set this bit to zero for at least one frame. 1-0 DR1-0 Data Rate Select. Input/Output data rate selection. See Table 9 for detailed programming. Table 8 - Interface Mode Selection (IMS) Register Bits DR1 DR0 Data Rate Selected Master Clock Required 0 0 2.048 Mb/s 4.096 MHz 0 1 4.096 Mb/s 8.192 MHz 1 0 8.192 Mb/s 16.384 MHz 1 1 Reserved Reserved Table 9 - Serial Data Rate Selection (16 input x 16 output) Read Address: Reset Value: 02H, 0000H. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 Bit Name Description 15 - 13 Unused 12 CFE Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0. 11 FD11 Frame Delay Bit 11. The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to 1/2 CLK cycle. Must be zero for normal operation. 15 Zarlink Semiconductor Inc. MT90820 Read Address: Reset Value: Data Sheet 02H, 0000H. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 Bit Name 10 - 0 FD10-0 Description Frame Delay Bits. The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 = MSB, FD0 = LSB) Table 10 - Frame Alignment (FAR) Register Bits ST-BUS Frame CLK Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FE Input (FD[10:0] = 06H) (FD11 = 0, sample at CLK low phase) GCI Frame CLK Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FE Input (FD[10:0] = 09H) (FD11 = 1, sample at CLK high phase) Figure 3 - Example for Frame Alignment Measurement 16 Zarlink Semiconductor Inc. 16 MT90820 Read/Write Address: Data Sheet 03H for FOR0 register, 04H for FOR1 register, 05H for FOR2 register, 06H for FOR3 register, 0000H for all FOR registers. Reset value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0 FOR0 register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4 FOR1 register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8 FOR2 register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12 FOR3 register Name (Note 1) OFn2, OFn1, OFn0 DLEn Description Offset Bits 2,1 & 0. These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the STi input pin: i.e., to start a new frame. The input frame offset can be selected to +4 clock periods from the point where the external frame pulse input signal is applied to the F0i input of the device. See Figure 4. Data Latch Edge. ST-BUS mode: DLEn =0, if clock rising edge is at the 3/4 point of the bit cell. DLEn =1, if when clock falling edge is at the 3/4 of the bit cell. GCI mode: DLEn =0, if clock falling edge is at the 3/4 point of the bit cell. DLEn =1, if when clock rising edge is at the 3/4 of the bit cell. Note 1: n denotes an input stream number from 0 to 15. Table 11 - Frame Input Offset (FOR) Register Bits Input Stream Offset No clock period shift (Default) Measurement Result from Frame Delay Bits Corresponding Offset Bits FD11 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn 1 0 0 0 0 0 0 0 17 Zarlink Semiconductor Inc. MT90820 Data Sheet Measurement Result from Frame Delay Bits Input Stream Offset Corresponding Offset Bits FD11 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn + 0.5 clock period shift 0 0 0 0 0 0 0 1 +1.0 clock period shift 1 0 0 1 0 0 1 0 +1.5 clock period shift 0 0 0 1 0 0 1 1 +2.0 clock period shift 1 0 1 0 0 1 0 0 +2.5 clock period shift 0 0 1 0 0 1 0 1 +3.0 clock period shift 1 0 1 1 0 1 1 0 +3.5 clock period shift 0 0 1 1 0 1 1 1 +4.0 clock period shift 1 1 0 0 1 0 0 0 +4.5 clock period shift 0 1 0 0 1 0 0 1 Table 12 - Offset Bits (OFn2, OFn1, OFn0, DLEn) & Frame Delay Bits (FD11, FD2-0) ST-BUS F0i CLK STi Stream offset=0, DLE=0 Bit 7 STi Stream offset=1, DLE=0 Bit 7 STi Stream offset=0, DLE=1 Bit 7 STi Stream offset=1, DLE=1 Bit 7 denotes the 3/4 point of the bit cell GCI F0i CLK Input Stream offset=0, DLE=0 Bit 0 Input Stream Input Stream offset=1, DLE=0 Bit 0 Input Stream offset=0, DLE=1 Bit 0 offset=1, DLE=1 Bit 0 denotes the 3/4 point of the bit cell Figure 4 - Examples for Input Offset Delay Timing 18 Zarlink Semiconductor Inc. MT90820 15 LPBK 14 13 12 11 10 9 8 7 V/C MC CSTo OE SAB3 SAB2 SAB1 SAB0 Data Sheet 6 5 4 CAB6 CAB5 CAB4 3 2 1 0 CAB3 CAB2 CAB1 CAB0 Bit Name Description 15 LPBK 14 V/C Variable /Constant Throughput Delay. This bit is used to select between the variable (low) and the constant delay (high) modes on a per-channel basis. 13 MC Message Channel. When 1, the contents of the connection memory are output on the corresponding output channel and stream. Only the lower byte (bit 7 - bit 0) will be output to the ST-BUS output pins. When 0, the contents of the connection memory are the data memory address of the switched input channel and stream. 12 CSTo Control ST-BUS output. This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output first. 11 OE Output Enable. This bit enables the ST-BUS output drivers on a per-channel basis. When 1, the output driver functions normally. When 0, the output driver is in a highimpedance state. 10 - 8, 7 (Note 1) SAB3-0 Source Stream Address Bits. The binary value is the number of the data stream for the source of the connection. 6-0 (Note 1) CAB6-0 Source Channel Address Bits. The binary value is the number of the channel for the source of the connection. Per Channel Loopback. When 1, the STi n channel m data comes from the STo n channel m. For proper per channel loopback operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode. Refer to the section Loopback Control or Connection Memory Control for more details. Note 1: If bit 13 (MC) of the corresponding connection memory location is 1 (device in message mode), then these entire 8 bits (SAB0, CAB6 - CAB0) are output on the output channel and stream associated with this location. Table 13 - Connection Memory Bits Data Rate CAB Bits Used to Determine the Source Channel of the Connection 2.048 Mb/s CAB4 to CAB0 (32 channel/input stream) 4.096 Mb/s CAB5 to CAB0 (64 channel/input stream) 8.192 Mb/s CAB6 to CAB0 (128 channel/input stream) Table 14 - CAB Bits Programming for Different Data Rates JTAG Support The MT90820 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. 19 Zarlink Semiconductor Inc. MT90820 Data Sheet Test Access Port (TAP) The Test Access Port (TAP) provides access to the many test functions of the MT90820. It consists of three input pins and one output pin. The following pins are from the TAP. • Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. • Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to Vdd when it is not driven from an external source. • Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to Vdd when it is not driven from an external source. • Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high impedance state. • Test Reset (TRST) Reset the JTAG scan structure. This pin is internally pulled to VDD. Instruction Register In accordance with the IEEE 1149.1 standard, the MT90820 uses public instructions. The MT90820 JTAG Interface contains a two-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and DO during data register scanning. Test Data Register As specified in IEEE 1149.1, the MT90820 JTAG Interface contains two test data registers: • The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the MT90820 core logic. • The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO. The MT90820 boundary scan register contains 118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit clocked out. All tristate enable bits are active high. 20 Zarlink Semiconductor Inc. MT90820 Data Sheet Boundary Scan Bit 0 to Bit 117 Device Pin STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 Tristate Control Output Scan Cell 0 2 4 6 8 10 12 14 1 3 5 7 9 11 13 15 ODE CSTo Input Scan Cell 16 17 18 19 DTA D15 D14 D13 D12 D11 D10 D9 D8 20 23 26 29 32 35 38 41 21 24 27 30 33 36 39 42 22 25 28 31 34 37 40 43 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 44 47 50 53 56 59 62 65 45 48 51 54 57 60 63 66 46 49 52 55 58 61 64 67 IM 68 AS/ALE 69 CS 70 R/W / WR 71 DS/RD 72 A7 A6 A5 A4 A3 A2 A1 A0 73 74 75 76 77 78 79 80 WFPS 81 RESET 82 Table 15 - Boundary Scan Register Bits 21 Zarlink Semiconductor Inc. MT90820 Data Sheet Boundary Scan Bit 0 to Bit 117 Device Pin Tristate Control Output Scan Cell Input Scan Cell CLK 83 FE/HCLK 84 F0i 85 STi15 STi14 STi13 STi12 STi11 STi10 STi9 STi8 STi7 STi6 STi5 STi4 STi3 STi2 STi1 STi0 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 STo15 STo14 STo13 STo12 STo11 STo10 STo9 STo8 102 104 106 108 110 112 114 116 103 105 107 109 111 113 115 117 Table 15 - Boundary Scan Register Bits Applications Switch Matrix Architectures The MT90820 is an ideal device for medium to large size switch matrices. Applications where voice and grouped data channels are transported within the same frame, the voice samples have to be time interchanged with a minimum delay while maintaining the integrity of grouped data. To ensure the integrity of grouped data during switching and to provide a minimum delay for voice connections, the MT90820 provides the per-channel selection between variable and constant throughput delay. This can be selected by the V/C bit of the Connection Memory. Figure 5 illustrates how four MT90820 devices can be used to form non-blocking switches up to 4096 channels with data rate of 8.192 Mb/s. 22 Zarlink Semiconductor Inc. MT90820 Data Sheet Serial Input Frame Alignment Evaluation The MT90820 is capable of performing frame alignment evaluation. The frame pulse under evaluation is connected to the FE (frame measurement) pin. An external multiplexer is required to selected one of the frame pulses related to the different input streams. Figure 6 gives an example of performing measurement for 16 frame pulses can be performed. 16 Streams 16 Streams MT90820 #1 IN 16 Streams OUT 16 Streams MT90820 #2 MT90820 #3 Bit Rate (IN/OUT) Size of Switch Matrix MT90820 #4 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s 1,024 - Channel Switch 2,048 - Channel Switch 4,096 - Channel Switch Figure 5 - Switch Matrix with Serial Stream at Various Bit Rates STi0 STi1 STi2 MT90820 Frame Alignment Evaluation circuit STi15 External Mux FE input CLK STo[0:15] FP FP STi0 FP STi1 FP STi2 Central Timing Source FP STi15 Note: 1. Use the external mux to select one of the serial frame pulses. 2. To start a measurement cycle, set the Start Frame Evaluation (SFE) bit in the IMS register low for at least 1 frame. 3. Frame evaluation starts when the SFE bit is changed from low to high. 4. Two frames later, the Complete Frame Evaluation (CFE) bit of the Frame Alignment Register (FAR) changes from low to high to signal the CPU that a valid offset measurement is ready to be read from bit [11:0] of the FAR register. 5. The SFE bit must be set to zero before a new measurement cycle started. Figure 6 - Serial Input Frame Alignment Evaluation for Various Frame Pulses Wide Frame Pulse (WFP) Frame Alignment Mode When the device is the wide frame pulse mode, the device can operate in the HMVIP and MVIP-90 environment if the input data streams are sampled at 3/4 bit time. When input data stream are sampled at half-bit time as specified in the HMVIP and MVIP-90 standard, the device can only operate with data rate of 2 Mb/s. Refer to the ST-BUS output delay parameter, tSOD, as specified in the AC Electrical Characteristic table. 23 Zarlink Semiconductor Inc. MT90820 Data Sheet The MT90820 is designed to accept a common frame pulse F0i, the 4.096 MHz and 16.384 MHz clocks required by the HMVIP standards. To enable the Width Frame Pulse Frame Alignment Mode, the WFPS pin has to be set to HIGH and the DR1and DR0 bits set for 8.192 MB/s data rate operation. Digital Access Cross-Connect System Figure 7 illustrates how the MT90820 can be used to construct, for example, a 256 E1/T1 digital access crossconnect system (DACS). The system consists of 32 trunk cards each having eight E1 or T1 trunk interfaces for a total of 256 trunks. The central switching block is constructed from 16 MT90820 devices. Figure 8 shows how an 8,192 x 8,192 channel switch can be constructed from 4,096 x 4,096 channel switch modules. Figure 5 shows the implementation of the 4,096 x 4,096 channel switch modules from four MT90820 devices. Therefore, 16 MT90820 devices are required to realize an 8,192 x 8,192 non-blocking switch module with 64 input and 64 output streams. Each stream has 128 channels per frame for a data rate of 8.192 Mb/s. Figure 9 shows an eight-stream trunk card block diagram. The MT8986 Multi-rate Digital Switch are used to concentrate the 32-channel 2.048 Mb/s ST-BUS (DSTi and DSTo) streams at each E1/T1 trunk onto four 128channel 8.192 Mb/s streams. It will take 256 MT8986 devices to implement the switching matrix of using 32-channel 2.048 Mb/s ST-BUS streams in a square (16 x 16) configuration. A large saving in component cost and board area can be achieved by using 128-channel 8.192 Mb/s streams. That is, the same capacity can be achieved using 64 MT8986 devices + 16 MT90820 devices for a total of 80 devices. Trunk Card (TC) 0 E10 E17 E18 E115 128 channels at 8.192 Mb/s 8 x E1/T1 Trunk Card 8,192 x 8,192 channel Switch Matrix TC1 8 x E1/T1 Trunk Card TC31 Sixteen MT90820 operate in 8 Mb/s mode 64 input streams x 64 output streams (Figure 9) E1247 E1255 8 x E1/T1 Trunk Card Figure 7 - 256 E1/T1 Digital Access Cross-Connect System (DACS) 24 Zarlink Semiconductor Inc. MT90820 32 Streams 4,096 x 4,096 Switch Matrix (Figure 5) Data Sheet 4,096 x 4,096 Switch Matrix (Figure 5) 32 Streams IN OUT 32 Streams 4,096 x 4,096 Switch Matrix (Figure 5) 4,096 x 4,096 Switch Matrix (Figure 5) 32 Streams Figure 8 - 8,192 x 8,192 Channel Switch Matrix E10 E11 DSTo DSTi E1/T1 Trunk 0 STi0 STi1 DSTo DSTi E1/T1 Trunk 1 STi7 STo0 STo1 E17 DSTo DSTi E1/T1 Trunk 7 STo7 MT8986 2Mb/s to 8Mb/s MT8986 8Mb/s to 2Mb/s STo0 256-channel out STo1 (8.192Mb/s pre channel) STi0 256-channel in STi1 (8.192Mb/s pre channel) Figure 9 - Trunk Card Block Diagram Absolute Maximum Ratings* Parameter Symbol Min. VDD Max. Units 6.0 V VDD +0.3 V 1 Supply Voltage 2 Voltage on any pin I/O (other than supply pins) VI 3 Continuous Current at digital outputs Io 20 mA 4 Package power dissipation (PLCC & PQFP) PD 2 W +125 °C VSS - 0.3 5 Storage temperature TS - 65 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. 25 Zarlink Semiconductor Inc. MT90820 Data Sheet Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 Operating Temperature TOP -40 +85 °C 2 Positive Supply VDD 4.75 5.25 V 3 Input High Voltage VIH 2.4 VDD V 400 mV noise margin 4 Input Low Voltage VIL VSS 0.4 V 400 mV noise margin DC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics Supply Current 3 4 I N P U T S 5 6 7 8 9 Note 1: Min. Typ. @ 2 Mb/s 1 2 Sym. O U T P U T S @ 4 Mb/s IDD @ 8 Mb/s Max. Units 50 mA 90 mA 170 mA 2.0 Test Conditions Output unloaded V Input High Voltage VIH Input Low Voltage VIL 0.8 V Input Leakage (input pins) Input Leakage (bi-directional pins) IIL IBL 15 50 µA µA Input Pin Capacitance CI 10 pF Output High Voltage VOH Output Low Voltage VOL High Impedance Leakage Output Pin Capacitance 2.4 0≤<V≤VDD See Note 1 V IOH = 10mA 0.4 V IOL = 10mA IOZ 5 µA 0 < V < VDD See Note 1 CO 10 pF Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V) AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics Sym. Level Units 1 TTL Threshold VTT 1.5 V 2 TTL Rise/Fall Threshold Voltage High VHM 2.0 V 3 TTL Rise/Fall Threshold Voltage Low VLM 0.8 V 26 Zarlink Semiconductor Inc. Conditions MT90820 Data Sheet AC Electrical Characteristics - Frame Pulse and CLK Characteristic 1 Sym. Min. Typ. Max. Units Notes 295 145 80 ns ns ns WFPS Pin = 0 Frame pulse width (ST-BUS, GCI) Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s tFPW 2 Frame Pulse Setup time before CLK falling (ST-BUS or GCI) tFPS 10 ns WFPS Pin = 0 3 Frame Pulse Hold Time from CLK falling (ST-BUS or GCI) tFPH 16 ns WFPS Pin = 0 4 CLK Period Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s tCP CLK Pulse Width High Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s tCH CLK Pulse Width Low Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s tCL 7 Clock Rise/Fall Time tr, tf 8 Wide frame pulse width Bit rate = 8.192 Mb/s 9 26 26 26 190 110 55 300 150 70 ns ns ns WFPS Pin = 0 85 50 20 150 75 40 ns ns ns WFPS Pin = 0 85 50 20 150 75 40 ns ns ns WFPS Pin = 0 10 ns tHFPW 195 295 ns WFPS Pin = 1 Frame Pulse Setup Time before HCLK falling tHFPS 10 150 ns WFPS Pin = 1 10 Frame Pulse Hold Time from HCLK falling tHFPH 20 150 ns WFPS Pin = 1 11 HCLK (4.096MHz) Period Bit rate = 8.192 Mb/s tHCP 190 300 ns WFPS Pin = 1 12 HCLK (4.096MHz) Pulse Width High Bit rate = 8.192 Mb/s tHCH 85 150 ns WFPS Pin = 1 13 HCLK (4.096MHz) Pulse Width Low Bit rate = 8.192 Mb/s tHCL 85 150 ns WFPS Pin = 1 10 ns 10 ns 5 6 14 HCLK Rise/Fall Time 15 Delay between falling edge of HCLK and falling edge of CLK tHr, tHf tDIF -10 27 Zarlink Semiconductor Inc. WFPS Pin = 0 or 1 MT90820 Data Sheet AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes Characteristic Sym. Min. Typ. Max. Units 1 Sti Set-up Time tSIS 0 ns 2 Sti Hold Time tSIH 20 ns 3 Sto Delay - Active to Active @ 2.048 Mb/s mode @ 4.096 Mb/s mode @ 8.192 Mb/s mode @ 8.192 Mb/s mode tSOD STo delay - Active to High-Z 2.048 Mb/s mode 4.096 Mb/s mode 8.192 Mb/s mode tDZ Sto delay - High-Z to Active 2.048 Mb/s mode 4.096 Mb/s mode 8.192 Mb/s mode tZD Output Driver Enable (ODE) Delay 2.048 Mb/s mode 4.096 Mb/s mode 8.192 Mb/s mode tODE CSTo Output Delay 2.048 Mb/s mode 4.096 Mb/s mode 8.192 Mb/s mode tXCD 4 5 6 7 Note 1: Test Conditions 58 58 58 39 ns ns ns ns CL=200pF CL=200pF CL=200pF CL=30pF 37 37 37 ns ns ns RL=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1 37 37 37 ns ns ns RL=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1 37 37 37 ns ns ns RL=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1 58 58 58 ns ns ns CL=200pF CL=200pF CL=200pF High Impedance is measured by pulling to the appropriate rail with RL , with timing corrected to cancel time taken to discharge CL. 28 Zarlink Semiconductor Inc. MT90820 Data Sheet tFPW F0i VTT tFPS tCP tFPH tCH tCL tr VHM VTT VLM CLK tSOD STo Bit 0, Last Ch (Note1) tf Bit 7, Channel 0 tSIS STi Bit 6, Channel 0 tSIH Bit 7, Channel 0 Bit 0, Last Ch (Note1) VTT Bit 5, Channel 0 Bit 6, Channel 0 VTT Bit 5, Channel 0 Note 1: 2.048 Mb/s mode, last channel = ch 31, 4.196 Mb/s mode, last channel = ch 63, 8.192 Mb/s mode, last channel = ch 127. Figure 10 - ST-BUS Timing for 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0. tFPW F0i VTT tFPS tCP tFPH tCH tCL tr VHM VTT VLM CLK tSOD STo Bit 7, Last Ch (Note1) tf Bit 0, Channel 0 tSIS STi Bit 7, Last Ch (Note1) Bit 1, Channel 0 Bit 2, Channel 0 VTT tSIH Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0 VTT Note 1: 2Mb/s mode, last channel = ch 31, 4Mb/s mode, last channel = ch 63, 8Mb/s mode, last channel = ch 127 Figure 11 - GCI Timing at 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0 29 Zarlink Semiconductor Inc. MT90820 Data Sheet tHFPW tHFPS tHFPH VTT F0i tHCP tHCH tHCL HCLK 4.096MHz tDIF tCP VHM VTT VLM tHf tHr tCH tCL tr CLK 16.384MHz VTT tSOD STo Bit 0, Ch 127 Bit 1, Ch 127 tf Bit 7, Ch 0 tSIS STi Bit 1, Ch 127 Bit 0, Ch 127 Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0 VTT tSIH Bit 7, Ch 0 Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0 VTT Figure 12 - WFP Bus Timing for High Speed Serial Interface (8.192Mb/s), when WFPS pin = 1 Note 1: High Impedance is measured by pulling to the appropriate rail with RL , with timing corrected to cancel time taken to discharge CL. CLK VTT (ST-BUS or) (WFPS mode) CLK (GCI mode) VTT tDZ STo Valid Data HiZ VTT Valid Data VTT tZD STo HiZ tXCD VTT CSTo Figure 13 - Serial Output and External Control 30 Zarlink Semiconductor Inc. MT90820 Data Sheet VTT ODE tODE tODE STo HiZ Valid Data HiZ VTT Figure 14 - Output Driver Enable (ODE) AC Electrical Characteristics - Multiplexed Bus Timing (Mode 1) Characteristics Sym. Min. Typ. Max. Units 1 ALE pulse width tALW 20 ns 2 Address setup from ALE falling tADS 10 ns 3 Address hold from ALE falling tADH 10 ns 4 RD active after ALE falling tALRD 10 ns 5 Data setup from DTA Low on Read tDDR 10 ns 6 CS hold after RD/WR tCSRW 0 ns 7 RD pulse width (fast read) tRW 8 CS setup from RD tCSR 0 9 Data hold after RD tDHR 10 10 WR pulse width (fast write) tWW 11 WR delay after ALE falling tALWR 80 CL=150pF ns ns 75 90 ns CL=150pF, RL=1K, Note 1. ns 10 ns 12 CS setup from WR tCSW 0 ns 13 Data setup from WR (fast write) tDSW 90 ns 14 Valid Data Delay on write (slow write) tSWD 15 Data hold after WR inactive tDHW 16 Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory, @ 2Mb/s @ 4Mb/s @ 8Mb/s tAKD 17 Acknowledgment Hold Time tAKH Note 1: Test Conditions 122 10 ns ns 45 55/60 760/780 400/420 220/240 ns ns ns ns CL=150pF CL=150pF CL=150pF CL=150pF 80 ns CL=150pF, RL=1K, Note 1. High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L. 31 Zarlink Semiconductor Inc. MT90820 Data Sheet tALW VTT ALE tADS AD0-AD7 D8-D15 HiZ tADH HiZ ADDRESS HiZ DATA tALRD VTT tCSRW CS VTT tCSR tRW RD VTT tDHR tWW WR VTT tCSW tSWD tDHW tDSW tALWR tDDR tAKH DTA VTT tAKD Figure 15 - Multiplexed Bus Timing (Mode 1) AC Electrical Characteristics - Multiplexed Bus Timing (Mode 2) Characteristics Sym. Min. Typ. Max. Units 1 AS pulse width tASW 80 ns 2 Address setup from AS falling tADS 10 ns 3 Address hold from AS falling tADH 10 ns 4 Data setup from DTA Low on Read tDDR 10 ns 5 CS hold after DS falling tCSH 0 ns 6 CS setup from DS rising tCSS 0 ns 7 Data hold after write tDHW 10 ns 8 Data setup from DS -Write (fast write) tDWS 25 ns 122 Valid Data Delay on write (slow write) tSWD R/W setup from DS rising tRWS 60 ns 11 R/W hold after DS falling tRWH 10 ns 12 Data hold after read tDHR 10 13 DS delay after AS falling tDSH 10 14 Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory, @ 2Mb/s @ 4Mb/s @ 8Mb/s tAKD Acknowledgment Hold Time tAKH 15 75 CL=150pF ns 9 10 50 Test Conditions ns CL=150pF, RL=1K, Note 1 ns 45 55/60 760/780 400/420 220/240 ns ns ns ns CL=150pF CL=150pF CL=150pF CL=150pF 80 ns CL=150pF, RL=1K, Note 1 Note 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 32 Zarlink Semiconductor Inc. MT90820 Data Sheet DS VTT tRWS tRWH R/W VTT tDSH tASW VTT AS tADS AD0-AD7 D8-D15 WR HiZ tADH VTT DATA HiZ ADDRESS tDHW tDWS tSW tDHR AD0-AD7 D8-D15 RD HiZ VTT DATA HiZ ADDRESS tCSH tCSS VTT CS tAKH tDDR tAKD DTA VTT Figure 16 - Multiplexed Bus Timing (Mode2) AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 CS setup from DS falling tCSS 0 ns 2 R/W setup from DS falling tRWS 10 ns 3 Address setup from DS falling tADS 2 ns 4 CS hold after DS rising tCSH 0 ns 5 R/W hold after DS rising tRWH 5 ns 6 Address hold after DS rising tADH 5 ns 7 Data setup from DTA Low on Read tDDR 0 ns CL=150pF 8 Data hold on read tDHR 10 ns CL=150pF, RL=1K Note 1 9 Data setup on write (fast write) tDSW 20 10 Valid Data Delay on write (slow write) tSWD 11 Data hold on write tDHW 12 Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory, @ 2Mb/s @ 4Mb/s @ 8Mb/s tAKD Acknowledgment Hold Time tAKH 13 Note 1: 50 75 ns 122 8 ns ns 45 55/60 760/780 400/420 220/240 ns ns ns ns CL=150pF CL=150pF CL=150pF CL=150pF 80 ns CL=150pF, RL=1K, Note 1 High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L. 33 Zarlink Semiconductor Inc. MT90820 Data Sheet VTT DS tCSH tCSS VTT CS tRWH tRWS VTT R/W tADS tADH VTT VALID ADDRESS A0-A7 tDHR AD0-AD7 D8-D15 READ VTT VALID READ DATA tDSW tSWD AD0-AD7 D8-D15 WRITE tDHW VTT VALID WRITE DATA tDDR VTT DTA tAKD Figure 17 - Motorola Non-Multiplexed Bus Timing 34 Zarlink Semiconductor Inc. tAKH For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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