LM101AQML www.ti.com SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 LM101AQML Operational Amplifiers Check for Samples: LM101AQML FEATURES 1 • • 2 • Available with Radiation Guarantee Offset Voltage 3 mV Maximum Over Temperature Input Current 100 nA Maximum Over Temperature • • • • Offset Current 20 nA Maximum Over Temperature Ensured Drift Characteristics Offsets Specified Over Entire Common Mode and Supply Voltage Ranges Slew Rate of 10 V/µS as a Summing Amplifier DESCRIPTION The LM101A is a general purpose operational amplifier which features improved performance over industry standards such as the LM709. Advanced processing techniques make possible an order of magnitude reduction in input currents, and a redesign of the biasing circuitry reduces the temperature drift of input current. Improved specifications include: • Offset voltage 3 mV maximum over temperature • Input current 100 nA maximum over temperature • Offset current 20 nA maximum over temperature • Specified drift characteristics • Offsets ensured over entire common mode and supply voltage ranges • Slew rate of 10V/μs as a summing amplifier – This amplifier offers many features which make its application nearly foolproof: overload protection on the input and output, no latch-up when the common mode range is exceeded, and freedom from oscillations and compensation with a single 30 pF capacitor. It has advantages over internally compensated amplifiers in that the frequency compensation can be tailored to the particular application. For example, in low frequency circuits it can be overcompensated for increased stability margin. Or the compensation can be optimized to give more than a factor of ten improvement in high frequency performance for most applications. – In addition, the device provides better accuracy and lower noise in high impedance circuitry. The low input currents also make it particularly well suited for long interval integrators or timers, sample and hold circuits and low frequency waveform generators. Further, replacing circuits where matched transistor pairs buffer the inputs of conventional IC op amps, it can give lower offset voltage and a drift at a lower cost. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LM101AQML SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Schematic Pin connections shown are for 8-pin packages. Connection Diagrams Note: Pin 4 connected to case. Figure 1. TO Package (Top View) See Package Number LMC0008C 2 Figure 2. CDIP Package (Top View) See Package Number NAB0008A Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML LM101AQML www.ti.com SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 Figure 3. CLGA Package (Top View) See Package Number NAD0010A Fast AC/DC Converter Note:Feedforward compensation can be used to make a fast full wave rectifier without a filter. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML 3 LM101AQML SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) Supply Voltage ±22V Differential Input Voltage ±30V Input Voltage (2) ±15V Output Short Circuit Duration Continuous −55°C ≤ TA ≤ +125°C Operating Ambient Temp. Range TJ Max 150°C Power Dissipation at TA = 25°C (3) LMC-Package NAB-Package NAD-Package Thermal Resistance θJA LMC-Package NAB-Package NAD-Package θJC (Typical) (Still Air) 750 mW (500 LF / Min Air Flow) 1200 mW (Still Air) 1000 mW (500 LF / Min Air Flow) 1500 mW (Still Air) 500mW (500 LF / Min Air Flow) 800mW (Still Air) 165°C/W (500 LF / Min Air Flow) 89°C/W (Still Air) 128°C/W (500 LF / Min Air Flow) 75°C/W (Still Air) 233°C/W (500 LF / Min Air Flow) 155°C/W LMC-Package 39°C/W NAB-Package 26°C/W NAD-Package 26°C/W −65°C ≤ TA ≤ +150°C Storage Temperature Range Lead Temperature (Soldering, 10 sec.) 300°C ESD Tolerance (4) 3000V (1) (2) (3) (4) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do no ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax − TA) / θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Human body model, 100 pF discharged through 1.5 kΩ. Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A 4 Subgroup Description Temp (°C) 1 Static tests at 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML LM101AQML www.ti.com SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 LM101A 883 Electrical Characteristics DC Parameters The following conditions apply to all parameters, unless otherwise specified VCC = ±20V, VCM= 0V Symbol Parameter Conditions VIO Input Offset Voltage VCM = -15V, RS = 50Ω Notes VCM = 15V, RS = 50Ω RS = 50Ω VCC = ±5V, RS = 50Ω IIO Input Offset Current VCM = -15V VCM = 15V VCC = ±5V ±IIB Input Bias Current VCM = -15V VCM = 15V VCC = ±5V Subgroups Min Max Units -2.0 2.0 mV 1 -3.0 3.0 mV 2, 3 -2.0 2.0 mV 1 -3.0 3.0 mV 2, 3 -2.0 2.0 mV 1 -3.0 3.0 mV 2, 3 -2.0 2.0 mV 1 -3.0 3.0 mV 2, 3 -10 10 nA 1 -20 20 nA 2, 3 -10 10 nA 1 -20 20 nA 2, 3 -10 10 nA 1 -20 20 nA 2, 3 -10 10 nA 1 -20 20 nA 2, 3 1.0 75 nA 1 1.0 100 nA 2, 3 1.0 75 nA 1 1.0 100 nA 2, 3 1.0 75 nA 1 1.0 100 nA 2, 3 1.0 75 nA 1 1.0 100 nA 2, 3 PSRR+ Power Supply Rejection Ratio +VCC = +20V and +5V, -VCC=-20V, RS=50Ω 80 dB 1, 2, 3 PSRR- Power Supply Rejection Ratio +VCC = +20V, -VCC= -20V and -5V, RS=50Ω 80 dB 1, 2, 3 CMRR Common Mode Rejection Ratio -15V ≤ VCM ≤ 15V, RS = 50Ω 80 ICC Supply Current dB 1, 2, 3 3.0 mA 1 2.5 mA 2 3.5 mA 3 mV 1, 2, 3 -4.0 mV 1, 2, 3 +VIO Adj Input Offset Voltage Adjust −VIO Adj Input Offset Voltage Adjust +IOS Short Circuit Current -45 -7.0 mA 1, 2, 3 -IOS Short Circuit Current 7.0 45 mA 1, 2, 3 VI Input Voltage Range VCC = ±20V -15 15 V 1, 2, 3 +AVS Large Signal Gain VCC = ±15V, RS = 0, RL=2KΩ, VO =10V 50 V/mV 4 25 V/mV 5, 6 VCC = ±15V, RS = 0, RL=2KΩ, VO =-10V 50 V/mV 4 25 V/mV 5, 6 See (2) 1.5 MΩ 4 see (2) 0.5 MΩ 5, 6 -AVS RI (1) (2) Large Signal Gain 4.0 Input Resistance See (1) Parameter specified by the input conditions of several DC parameters Parameter specified by design, not tested. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML 5 LM101AQML SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 www.ti.com LM101A 883 Electrical Characteristics DC Parameters (continued) The following conditions apply to all parameters, unless otherwise specified VCC = ±20V, VCM= 0V Symbol Parameter Conditions +VOP Output Voltage Swing RL = 10KΩ RL = 2KΩ -VOP Output Voltage Swing Units Subgroups 16 V 4, 5, 6 15 V 4, 5, 6 RL = 10KΩ, VCC = ±15V 12 V 4, 5, 6 RL = 2KΩ, VCC = ±15V 10 V 4, 5, 6 Notes Min Max RL = 10KΩ -16 V 4, 5, 6 RL = 2KΩ -15 V 4, 5, 6 RL = 10KΩ, VCC = ±15V -12 V 4, 5, 6 RL = 2KΩ, VCC = ±15V -10 V 4, 5, 6 Max Units Subgroups LM101A 883 Electrical Characteristics AC Parameters The following conditions apply to all parameters, unless otherwise specified VCC = ±20V, RL = 2KΩ, AV = 1 Symbol Parameter Conditions +SR Slew Rate VI = -5V to 5V 0.2 V/µS 7 -SR Slew Rate VI = 5V to -5V 0.2 V/µS 7 GBW Gain Bandwidth VI = 50mVRMS, f = 20KHz 0.25 MHz 7 Min Max Units Subgroups Notes Min LM101A QML and RH Electrical Characteristics (1) DC Parameters The following conditions apply to all parameters, unless otherwise specified VCC = ±20V, VCM = 0V, RS = 50Ω Symbol Parameter Conditions VIO Input Offset Voltage +VCC = 35V, -VCC = -5V, VCM = -15V -2.0 +2.0 mV 1 -3.0 +3.0 mV 2, 3 +VCC = 5V, -VCC = -35V, VCM = +15V -2.0 +2.0 mV 1 -3.0 +3.0 mV 2, 3 VCM = 0V -2.0 +2.0 mV 1 2, 3 IIO Input Offset Current -3.0 +3.0 mV +VCC = 5V, -VCC = -5V, VCM = 0V -2.0 +2.0 mV 1 -3.0 +3.0 mV 2, 3 +VCC = 35V, -VCC = -5V, VCM = -15V, RS = 100KΩ -10 +10 nA 1, 2 -20 +20 nA 3 +VCC = 5V, -VCC = -35V, VCM = +15V, RS = 100KΩ -10 +10 nA 1, 2 -20 +20 nA 3 VCM = 0V, RS = 100KΩ -10 +10 nA 1, 2 -20 +20 nA 3 -10 +10 nA 1, 2 -20 +20 nA 3 +VCC = 5V, -VCC = -5V, VCM = 0V, RS = 100KΩ (1) 6 Notes Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are specified only for the conditions as specified in Mil-Std-883, Method 1019 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML LM101AQML www.ti.com SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 LM101A QML and RH Electrical Characteristics(1) DC Parameters (continued) The following conditions apply to all parameters, unless otherwise specified VCC = ±20V, VCM = 0V, RS = 50Ω Symbol Parameter Conditions ±IIB Input Bias Current +VCC = 35V, -VCC = -5V, VCM = -15V, RS = 100KΩ +PSRR -PSRR Power Supply Rejection Ratio Power Supply Rejection Ratio Max Units Subgroups -0.1 75 nA 1, 2 -0.1 100 nA 3 +VCC = 5V, -VCC = -35V, VCM = +15V, RS = 100KΩ -0.1 75 nA 1, 2 -0.1 100 nA 3 VCM = 0V, RS = 100KΩ -0.1 75 nA 1, 2 -0.1 100 nA 3 +VCC = 5V, -VCC = -5V, VCM = 0V, RS = 100KΩ -0.1 75 nA 1, 2 -0.1 100 nA 3 +VCC = 10V, -VCC = -20V -50 +50 µV/V 1 -100 +100 µV/V 2, 3 -50 +50 µV/V 1 -100 +100 µV/V 2, 3 80 dB 1, 2, 3 4.0 mV 1, 2, 3 mV 1, 2, 3 mA 1, 2, 3 +60 mA 1, 2, 3 +VCC = 20V, -VCC = -10V CMRR Common Mode Rejection Ratio +VIO Adj Adjustment for Input Offset Voltage -VIO Adj Adjustment for Input Offset Voltage +IOS Output Short Circuit Current +VCC = 15V, -VCC = -15V, t ≤ 25mS, VCM = -15V -IOS Output Short Circuit Current +VCC = 15V, -VCC = -15V, t ≤ 25mS, VCM = +15V ICC Power Supply Current +VCC = 15V, -VCC = -15V ΔVIO/ ΔT Δ IIO / ΔT -AVS Notes VCC = ±35V to ±5V, VCM = ±15V -4.0 -60 1 mA 2 3.5 mA 3 See -18 +18 µV/°C 2 +25°C ≤ TA ≤ +125°C See (2) -15 +15 uV/°C 3 Temperature Coefficient of Input Offset Current -55°C ≤ TA ≤ +25°C See (2) -200 +200 pA/°C 2 +25°C ≤ TA ≤ +125°C See (2) -100 +100 pA/°C 3 Large Signal (Open Loop) Voltage RL = 2KΩ, VO = -15V Gain (3) 50 V/mV 4 See (3) 25 V/mV 5, 6 See (3) 50 V/mV 4 (3) 25 V/mV 5, 6 See (3) 50 V/mV 4 See (3) 25 V/mV 5, 6 See (3) 50 V/mV 4 See (3) 25 V/mV 5, 6 See (3) 10 V/mV 4,5, 6 See (3) 10 V/mV 4,5, 6 RL = 10KΩ, VCM = -20V +16 V 4,5, 6 RL = 2KΩ, VCM = -20V +15 Large Signal (Open Loop) Voltage RL = 2KΩ, VO = +15V Gain RL = 10KΩ, VO = +15V Large Signal (Open Loop) Voltage VCC = ±5V,RL = 2KΩ, Gain VO = ±2V VCC = ±5V, RL = 10KΩ, VO = ±2V +VOP Output Voltage Swing -VOP Output Voltage Swing (2) (3) mA -55°C ≤ TA ≤ +25°C See See AVS (2) 3.0 2.32 Temperature Coefficient of Input Offset Voltage RL = 10KΩ, VO = -15V +AVS Min V 4,5, 6 RL = 10KΩ, VCM = 20V -16 V 4,5, 6 RL = 2KΩ, VCM = 20V -15 V 4,5, 6 Calculated parameter Datalog reading of K = V/mV. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML 7 LM101AQML SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 www.ti.com LM101A QM and RH Electrical Characteristics AC Parameters The following conditions apply to all parameters, unless otherwise specified VCC = ±20V, VCM = 0V, RS = 50Ω Symbol Parameter Conditions +SR Slew Rate AV = 1, VI = -5V to +5V -SR Slew Rate Notes AV = 1, VI = +5V to -5V Units Subgroups 0.3 V/µS 7, 8A 0.2 V/µS 8B 0.3 V/µS 7, 8A 0.2 V/µS 8B 7, 8A, 8B Min Max TRTR Rise Time AV = 1, VI = 50mV 800 nS TROS Overshoot AV = 1, VI = 50mV 25 % 7 35 % 8A, 8B NIBB Noise Broadband BW = 10Hz to 5KHz, RS = 0Ω 15 µVRMS 7 NIPC Noise Popcorn BW = 10Hz to 5KHz, RS = 100KΩ 80 µVPK 7 LM101A QM and RH Electrical Characteristics DC Parameters Drift Values The following conditions apply to all parameters, unless otherwise specified VCC = ±20V, VCM = 0V, RS = 50Ω Delta calculations performed on QMLV devices at group B, Subgroup 5 only. Symbol Parameter Conditions VIO Input Offset Voltage ± IIB Input Bias Current 8 Min Max Units Subgroups VCM = 0V -0.5 0.5 mV 1 VCM = 0V, RS = 100KΩ -7.5 7.5 nA 1 Submit Documentation Feedback Notes Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML LM101AQML www.ti.com SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 Typical Performance Characteristics LM101A Input Voltage Range Output Swing Figure 4. Figure 5. Voltage Gain Supply Current Figure 6. Figure 7. Voltage Gain Maximum Power Dissipation Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML 9 LM101AQML SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 10 LM101A (continued) Input Current, LM101A Current Limiting Figure 10. Figure 11. Input Noise Voltage Input Noise Current Figure 12. Figure 13. Common Mode Rejection Power Supply Rejection Figure 14. Figure 15. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML LM101AQML www.ti.com SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 Typical Performance Characteristics LM101A (continued) Closed Loop Output Impedance Figure 16. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML 11 LM101AQML SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics for Various Compensation Circuits Pin connections shown are for 8-pin packages. Single Pole Compensation Two Pole Compensation CS= 30 pF CS= 30 pF C2 = 10 C1 fo= 3 MHz 12 Figure 17. Figure 18. Feedforward Compensation Open Loop Frequency Response Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML LM101AQML www.ti.com SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 Typical Performance Characteristics for Various Compensation Circuits (continued) Pin connections shown are for 8-pin packages. Open Loop Frequency Response Open Loop Frequency Response Figure 21. Figure 22. Large Signal Frequency Response Large Signal Frequency Response Figure 23. Figure 24. Large Signal Frequency Response Voltage Follower Pulse Response Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML 13 LM101AQML SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics for Various Compensation Circuits (continued) Pin connections shown are for 8-pin packages. 14 Voltage Follower Pulse Response Inverter Pulse Response Figure 27. Figure 28. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML LM101AQML www.ti.com SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 TYPICAL APPLICATIONS Pin connections shown are for 8-pin packages. †May be zero or equal to parallel combination of R1 and R2 for minimum offset. Figure 29. Variable Capacitance Multiplier Figure 30. Inverting Amplifier with Balancing Circuit L ≃ R1 R2 C1 RS = R2 RP = R1 fo = 10 kHz Figure 31. Simulated Inductor Figure 32. Sine Wave Oscillator *Adjust for zero integrator drift. Current drift typically 0.1 nA/°C over −55°C to +125°C temperature range. Figure 33. Fast Inverting Amplifier with High Input Impedance Figure 34. Integrator with Bias Current Compensation Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML 15 LM101AQML SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 www.ti.com Application Hints *Protects input †Protects output ‡Protects output—not needed when R4 is used. Figure 35. Protecting Against Gross Fault Conditions Figure 36. Compensating for Stray Input Capacitances or Large Feedback Resistor Figure 37. Isolating Large Capacitive Loads 16 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML LM101AQML www.ti.com SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 Although the LM101A is designed for trouble free operation, experience has indicated that it is wise to observe certain precautions given below to protect the devices from abnormal operating conditions. It might be pointed out that the advice given here is applicable to practically any IC op amp, although the exact reason why may differ with different devices. When driving either input from a low-impedance source, a limiting resistor should be placed in series with the input lead to limit the peak instantaneous output current of the source to something less than 100 mA. This is especially important when the inputs go outside a piece of equipment where they could accidentally be connected to high voltage sources. Large capacitors on the input (greater than 0.1 μF) should be treated as a low source impedance and isolated with a resistor. Low impedance sources do not cause a problem unless their output voltage exceeds the supply voltage. However, the supplies go to zero when they are turned off, so the isolation is usually needed. The output circuitry is protected against damage from shorts to ground. However, when the amplifier output is connected to a test point, it should be isolated by a limiting resistor, as test points frequently get shorted to bad places. Further, when the amplifer drives a load external to the equipment, it is also advisable to use some sort of limiting resistance to preclude mishaps. Precautions should be taken to insure that the power supplies for the integrated circuit never become reversed—even under transient conditions. With reverse voltages greater than 1V, the IC will conduct excessive current, fusing internal aluminum interconnects. If there is a possibility of this happening, clamp diodes with a high peak current rating should be installed on the supply lines. Reversal of the voltage between V+ and V− will always cause a problem, although reversals with respect to ground may also give difficulties in many circuits. The minimum values given for the frequency compensation capacitor are stable only for source resistances less than 10 kΩ, stray capacitances on the summing junction less than 5 pF and capacitive loads smaller than 100 pF. If any of these conditions are not met, it becomes necessary to overcompensate the amplifier with a larger compensation capacitor. Alternately, lead capacitors can be used in the feedback network to negate the effect of stray capacitance and large feedback resistors or an RC network can be added to isolate capacitive loads. Although the LM101A is relatively unaffected by supply bypassing, this cannot be ignored altogether. Generally it is necessary to bypass the supplies to ground at least once on every circuit card, and more bypass points may be required if more than five amplifiers are used. When feed-forward compensation is employed, however, it is advisable to bypass the supply leads of each amplifier with low inductance capacitors because of the higher frequencies involved. Typical Applications Pin connections shown are for 8-pin packages. Figure 38. Standard Compensation and Offset Balancing Circuit Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML 17 LM101AQML SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 www.ti.com Power Bandwidth: 15 kHz Slew Rate: 1V/μs Figure 39. Fast Voltage Follower Power Bandwidth: 250 kHz Small Signal Bandwiidth: 3.5 MHz Slew Rate: 10V/μs Figure 40. Fast Summing Amplifier R3 = R4 + R5 R1 = R2 Figure 41. Bilateral Current Source 18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML LM101AQML www.ti.com SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 Note: Feedforward compensation can be used to make a fast full wave rectifier without a filter. Figure 42. Fast AC/DC Converter R1 = R4; R2 = R3 *,† Matching determines CMRR. Figure 43. Instrumentation Amplifier Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML 19 LM101AQML SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 www.ti.com *Adjust for zero integrator drift. Current drift typically 0.1 nA/°C over 0°C to +70°C temperature range. Figure 44. Integrator with Bias Current Compensation Figure 45. Voltage Comparator for Driving RTL Logic or High Current Driver Figure 46. Low Frequency Square Wave Generator *Polycarbonate-dielectric capacitor Figure 47. Low Drift Sample and Hold 20 Figure 48. Voltage Comparator for Driving DTL or TTL Integrated Circuits Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML LM101AQML www.ti.com SNOSAI0A – JANUARY 2006 – REVISED MARCH 2013 REVISION HISTORY SECTION Date Released Revision Section Originator Changes 01/05/06 A New Release to corporate format L. Lytle 2 MDS datasheets converted into one Corp. datasheet format. MNLM101A-X Rev 0A0 and MRLM101A-X-RH rev 1C2 MDS datasheets will be archived. 03/20/13 A All - Changed layout of National Data Sheet to TI format Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM101AQML 21 PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962L9951501VGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM101AHLQMLV 5962L9951501VGA Q ACO 5962L9951501VGA Q >T 5962L9951501VHA LIFEBUY CFP NAD 10 19 TBD Call TI Call TI -55 to 125 LM101AW LQMLV Q 5962L99515 01VHA ACO 01VHA >T 5962L9951501VPA ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM101AJLQMLV 5962L99515 01VPA Q ACO 01VPA Q >T LM101 MDR ACTIVE DIESALE Y 0 40 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 LM101A MD8 ACTIVE DIESALE Y 0 400 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 LM101AH/883 ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM101AH/883 Q ACO LM101AH/883 Q >T LM101AHLQMLV ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM101AHLQMLV 5962L9951501VGA Q ACO 5962L9951501VGA Q >T LM101AJ/883 ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 (LF412MJ ~ LM101AJ) /883 Q ACO /883 Q >T LM101AJLQMLV ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM101AJLQMLV 5962L99515 01VPA Q ACO 01VPA Q >T LM101AWLQMLV LIFEBUY CFP NAD 10 19 TBD Call TI Call TI -55 to 125 LM101AW LQMLV Q 5962L99515 01VHA ACO Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 28-Jul-2016 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 01VHA >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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OTHER QUALIFIED VERSIONS OF LM101AQML, LM101AQML-SP : Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2016 • Military: LM101AQML • Space: LM101AQML-SP NOTE: Qualified Version Definitions: • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3 MECHANICAL DATA NAB0008A J08A (Rev M) www.ti.com MECHANICAL DATA NAD0010A W10A (Rev H) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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