REJ09B0329-0200
The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and
additions. Details should always be checked by referring to the
relevant text.
16
H8S/2199R Group,
H8S/2199R F-ZTAT™
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2100 Series
H8S/2199R
H8S/2198R
H8S/2197R
H8S/2197S
H8S/2196R
H8S/2196S
Rev.2.00
Revision Date: Jan. 15, 2007
HD6432199R
HD64F2199R
HD6432198R
HD6432197R
HD6432197S
HD6432196R
HD6432196S
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev.2.00 Jan. 15, 2007 page ii of xliv
REJ09B0329-0200
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed
usage notes on the products covered by this manual, refer to the relevant sections of the manual. If
the descriptions under General Precautions in the Handling of MPU/MCU Products and in the
body of the manual differ from each other, the description in the body of the manual takes
precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may
occur due to the false recognition of the pin state as an input signal. Unused pins should
be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm
that the change will not lead to problems.
⎯ The characteristics of MPU/MCU in the same group but having different type numbers
may differ because of the differences in internal memory capacity and layout pattern.
When changing to products of different type numbers, implement a system-evaluation test
for each of the products.
Rev.2.00 Jan. 15, 2007 page iii of xliv
REJ09B0329-0200
Rev.2.00 Jan. 15, 2007 page iv of xliv
REJ09B0329-0200
Preface
This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit
architecture as its core, and the peripheral functions required to configure a system.
This LSI is equipped with ROM, RAM, digital servo circuits, a sync separator, an OSD, a data
slicer, seven types of timers, three types of PWMs, two types of serial communication interfaces
2
(SCIs), an I C bus interface (IIC), a D/A converter, an A/D converter, and I/O ports as on-chip
supporting modules. This LSI is suitable for use as an embedded processor for high-level control
TM
systems. Its on-chip ROM is flash memory (F-ZTAT *) that provides flexibility as it can be
reprogrammed in no time to cope with all situations from the early stages of mass production to
full-scale mass production. This is particularly applicable to application devices with
specifications that will most probably change.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who will be using the H8S/2199R Group and
TM
H8S/2199R F-ZTAT in the design of application systems. Members of this
audience are expected to understand the fundamentals of electrical circuits, logical
circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
TM
characteristics of the H8S/2199R Group and H8S/2199R F-ZTAT to the above
audience. Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for
a detailed description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU’s functions
Read the H8S/2600 Series, H8S/2000 Series Software Manual.
• In order to understand the details of a register when its name is known
The addresses, bits, and initial values of the registers are summarized in appendix B, Internal
I/O Registers.
Rev.2.00 Jan. 15, 2007 page v of xliv
REJ09B0329-0200
Examples:
Related Manuals:
Register name:
The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Number notation:
Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx
Signal notation:
An overbar is added to a low-active signal: xxxx
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev.2.00 Jan. 15, 2007 page vi of xliv
REJ09B0329-0200
H8S/2199R Gruop and H8S/2199R F-ZTAT
TM
manuals:
Document Title
H8S/2199R Gruop, H8S/2199R F-ZTAT
Document No.
TM
Hardware Manual
H8S/2600 Series, H8S/2000 Series Software Manual
This manual
REJ09B0139
User’s manuals for development tools:
Document Title
Document No.
H8S, H8S/300 Series C/C++ Compiler, Assembler, Optimizing Linkage
Editor User’s Manual
REJ10B0058
H8S, H8S/300 Series Simulator/Debugger User’s Manual
ADE-702-037
High-performance Embedded Workshop User’s Manual
ADE-702-201
Application Notes:
Document Title
Document No.
H8S Series Technical Q&A Application Note
REJ05B0397
Rev.2.00 Jan. 15, 2007 page vii of xliv
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Rev.2.00 Jan. 15, 2007 page viii of xliv
REJ09B0329-0200
Main Revisions in This Edition
Item
Page
Revision (See Manual for Details)
All
⎯
• Notification of change in company name amended
(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.
• Product naming convention amended
(Before) H8S/2199R Series → (After) H8S/2199R Group
⎯
Package code amended
(Before) FP-112 → (After) PRQP0112JA-A
2.1.3 Difference from
H8S/300 CPU
21
Expanded address space
Note * added
Normal mode* supports the same 64-kbytee address space ...
Note: * Normal mode is not available in this LSI.
2.2 CPU Operating
Modes
22
Note * added
H8S/2000 CPU has two operating modes: Normal* and
advanced. Normal mode* supports a maximum 64-Mbyte
address space.
Note: * Normal mode is not available in this LSI.
2.3 Address Space
27
Note * added
... 64-kbyte address space in normal mode*, and maximum ...
Note: * Normal mode is not available in this LSI.
2.6.1 Overview
36
Bit manipulation (Before) RSET → (After) BSET
Table 2.1 Instruction
Classification
2.6.3 Table of
Instructions Classified
by Function
Table 2.4 Arithmetic
Instruction
Table 2.1 amended
41
Size description amended
ADDS, SUBS (Before) B → (After) L
DAA, DAS (Before) B/W → (After) B
Rev.2.00 Jan. 15, 2007 page ix of xliv
REJ09B0329-0200
Item
Page
Revision (See Manual for Details)
2.6.3 Table of
Instructions Classified
by Function
48
Table 2.10 amended
Instruction
Size*
Function
EEPMOV.B
—
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L −1 → R4L
Until R4L = 0
else next;
EEPMOV.W
—
if R4 ≠ 0 then
Repeat @ER5+ → ER6+
R4 −1 → R4
Until R4 = 0
else next;
Table 2.10 Block Data
Transfer Instructions
Transfers a data block according to parameters set in general
registers R4L or R4, ER5, and ER6
R4L or R4: size of block (bytes)
2.7.1 Addressing Mode 51
Table 2.11 amended
Table 2.11
Modes
Symbol of Absolute address amended
Addressing
(Before) @aa:8/#@aa:16/@aa:24//@aa:32 → (After)
@aa:8/@aa:16/@aa:24//@aa:32
Table 2.12 Absolute
53
Address Access Ranges
Table 2.12 amended
Absolute Address
Data address
2.8.1 Overview
59
Advanced Mode
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits
(@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF, H'FF8000 to
H'FFFFFF
Figure 2.16 amended
RES = High
Figure 2.16 State
Transitions
7.3.3 Erase Block
Register 1 (EBR1)
Normal Mode
8 bits
(@aa:8)
SLEEP instruction with LSON = 0, SSBY = 1, TMA3 = 0
141
Bit figure amended
Bit :
7
EB7
Initial value
R/W :
7.3.4 Erase Block
Register 2 (EBR2)
142
0
R/W
Bit figure amended
Bit :
7
EB15
Initial value :
R/W :
10.3.2 Register
Configuration
193
0
R/W
Port Mode Register 1 (PMR1)
Description amended
When the pin functions of P16/IC and P15/IRQ5 to P10/IRQ0
are switched by PMR1, ...
10.4.3 Pin Functions
200
P27/SYSCI bit table amended
(Before) PCR → (After) PCR27
Rev.2.00 Jan. 15, 2007 page x of xliv
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Item
Page
Revision (See Manual for Details)
10.5.3 Pin Functions
209
Description amended
P34/PWM2: P34/PWM2 is switched as shown below ...
10.6.1 Overview
211
Description amended
... It is switched by port mode register 4 (PMR4), timer output ...
10.8 Overview
226
Description amended
Port 7 consists of pins that are used both as standard I/O ports
(P77 to P70), HSW timing generation circuit ... outputs (PPG7
to PPG0), and realtime output port (RPB to RP8). ...
10.8.3 Pin Functions
231
Description amended
P73/PPG3 to P70/PPG0: P73/PPG3 to P70/PPG0 are switched
as shown below ...
10.9.2 Register
Configuration
235
10.9.3 Pin Functions
241
Description amended
... When reset, PMR8 is initialized to H'00. ...
Description amended
P84/H.Amp SW/G: ... according to the PMR84 bit in PMR8,
PMRC4 bit in PMRC, and PCR84 bit in PCR8.
13.2.5 Timer Counter K 267
(TCK)
15.2.1 Timer R Mode
Register 1 (TMRM1)
294
16.6 Exemplary Uses
of Timer X1
338
Description amended
... The inputting clock can be selected by the EXN and PS22
bits of the TMJ, and the PS21 and PS20 bits of the TMJ. ...
Description amended
Bit 0⎯Capture Signals of the TMRU-1 (CPS): In combination
with the LAT bit (Bit 7) of the TMRM2, this bit works ...
Description amended
2. Each time a comparing match occurs, the OLVLA bit and the
OLVLB bit are reserved by use of the software.
17.2.1 Watchdog Timer 347
Counter (WTCNT)
18.2.2 8-bit PWM
Control Register
(PW8CR)
360
18.2.3 Port Mode
Register 3 (PMR3)
361
20.2.2 PWM Data
Registers U and L
(PWDRU, PWDRL)
376
Description amended
WTCNT is an 8-bit readable/writable* up-counter. ...
Description amended
... PW8CR is initialized to H'F0 by a reset.
Description amended
Bits 5 to 2⎯P35/PWM3 to P32/PWM0 Pin Switching (PMR35
to PMR32): These bits set whether the P3n/PWMm pin is used
as I/O pin or it is used as 8-bit PWM output PWMm pin.
Description amended
PWM data registers U and L ...in one PWM waveform cycle. ...
Rev.2.00 Jan. 15, 2007 page xi of xliv
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Item
Page
Revision (See Manual for Details)
22.2.4 Transmit Data
Register 1 (TDR1)
394
Description amended
22.2.7 Serial Status
Register 1 (SSR1)
402
... When the SCI detects that TSR1 is empty, ...
Bit 7 description amended
[Setting condition] 1. When the TE bit in SCR1 is 0
403
Bit 6 description amended
[Setting condition] When serial reception ... is transferred from
RSR1 to RDR1
405
Bit 1 description amended
Bit 1
MPB
Description
0
[Clearing condition]
(Initial value)
When data with a 0 multiprocessor bit is received*
22.2.8 Bit Rate
Register 1 (BRR1)
406
Description amended
BRR1 is an 8-bit register ... by bits CKS1 and CKS0 in SMR1.
...
Rev.2.00 Jan. 15, 2007 page xii of xliv
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Item
Page
Revision (See Manual for Details)
22.2.8 Bit Rate
Register 1 (BRR1)
407, 408 Table 22.3 amended
Operating Frequecy φ (MHz)
Table 22.3 BRR1
Settings for Various Bit
Rates (Asynchronous
Mode)
2.097152
2
2.4576
3
Bit Rate
(bits/s)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%) n
N
1200
0
51
0.16
0
54
−0.71
0
63
0.00
0
77
0.16
2400
0
25
0.16
0
26
1.12
0
31
0.00
0
38
0.16
4800
0
12
0.16
0
13
−2.54
0
15
0.00
0
19
−2.40
9600
—
—
—
0
6
−2.54
0
7
0.00
0
9
−2.40
19200
—
—
—
—
—
—
0
3
0.00
0
4
−2.40
N
Error (%)
Error (%)
Operating Frequecy φ (MHz)
4
3.6864
4.9152
5
Bit Rate
(bits/s)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%) n
110
2
64
0.69
2
70
0.03
2
86
0.31
2
88
0.25
4800
0
23
0.00
0
25
0.16
0
31
0.00
0
32
−1.38
1.70
9600
0
11
0.00
0
12
0.16
0
15
0.00
0
15
19200
0
5
0.00
—
—
—
0
7
0.00
0
7
1.70
31250
—
—
—
0
3
0.00
0
4
−1.73
0
4
0.00
38400
0
2
0.00
—
—
—
0
3
0.00
0
3
1.70
Operating Frequecy φ (MHz)
9600
6.144
6
Bit Rate
(bits/s)
n
0
8
7.3728
N
Error (%)
n
N
Error (%)
n
N
Error (%) n
N
Error (%)
19
−2.40
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
−2.40
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.34
—
—
—
0
7
0.00
38400
0
4
−2.40
0
4
0.00
0
5
0.00
—
—
—
Operating Frequecy φ (MHz)
22.2.9 Serial Interface 413
Mode Register 1
(SCMR1)
22.3.2 Operation in
Asynchronous Mode
Figure 22.7 Sample
Serial Reception Data
Flowchart (1)
424
10
9.8304
Bit Rate
(bits/s)
n
N
Error (%)
n
N
9600
0
31
0.00
0
32
−1.38
19200
0
15
0.00
0
15
1.70
31250
0
9
−1.73
0
9
0.00
38400
0
7
0.00
0
7
1.70
Error (%)
Bit 3 description amended
TDR1 contents are transmitted ...
Figure 22.7 amended
[2] [3] Receive error handling and break detection: ... and FER
flags in SSR1 to identify the error. After performing the
appropriate error handling, ensure that the ORER, PER, and
FER flags are all cleared to 0. ...
[4] SCI status check and receive data read: Read SSR1 and
check that RDRF = 1, then ...
Rev.2.00 Jan. 15, 2007 page xiii of xliv
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Item
Page
22.3.3 Multiprocessor 429
Communication
Function
Revision (See Manual for Details)
Figure 22.11 amended
[2] SCI status check and transmit data write: Read SSR1 and
check that the TDRE flag is set to 1, then ...
Figure 22.11 Sample
Multiprocessor Serial
Transmission Flowchart
Figure 22.13 Sample 432
Multiprocessor Serial
Reception Flowchart (1)
Figure 22.13 amended
22.3.4 Operation in
Synchronous Mode
Figure 22.17 amended
437
[3] SCI status check, ID reception and comparison: Read
SSR1 and check that the RDRF flag is set to 1, then ...
Set data transfer format in SMR1 and SCMR1
Figure 22.17 Sample
SCI Initialization
Flowchart
Figure 22.22 Sample
Flowchart of
Simultaneous Serial
Transmit and Receive
Operations
443
Figure 22.22 amended
RDRF = 1
2
23.2.5 I C Bus Control 464
Register (ICCR)
23.3.2 Master Transmit 482
Operation
23.3.4 Slave Receive
Operation
485
23.4 Usage Note
499
Bit 7 description amended
Bit 7
ICE
Description
1
I 2C bus interface module enabled for transfer operations (pins SCL and SDA are
driving the bus)
ICMR and ICDR can be accessed
Description amended
[11] ... When there is data to be transmitted, go to the step [9]
to continue next transmission. ...
Description amended
5. ... At this time, RDRF flag is cleared to 0.
Description amended
2
6. ... The I C bus interface SCL and SDA output timing is
prescribed by tcyc, as shown in table 23.5. ...
Rev.2.00 Jan. 15, 2007 page xiv of xliv
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Item
Page
Revision (See Manual for Details)
23.4 Usage Note
504 to
511
10. Notes on WAIT Function
11. Notes on ICDR Reads and ICCR Access in Slave Transmit
Mode
12. Notes on TRS Bit Setting in Slave Mode
13. Notes on Arbitration Lost in Master Mode
14. Notes on Interrupt Occurrence after ACKB Reception
15. Notes on TRS Bit Setting and ICDR Register Access
Description added
26.2.1 Overview
556
Description amended
This LSI is equipped with ... and twenty-nine pins multiplexed
with general-purpose ports. ...
26.4.5 Register
Description
601
FIFO Output Pattern Register 2 (FPDRB)
Description amended
Bit 13⎯S-TRIGB Bit (STRIGB): ... When the STRIGB is
selected by the ISEL, ...
26.4.6 Operation
608
26.7.4 Register
Description
Figure 26.23 amended
Example of setting: DFCRA = H'02, DFCRB = H'08, ...
Figure 26.23 Example
of Timing Waveform of
HSW (for 12 DFG
Pulses)
632
Drum Pulse Preset Data Registers (DPPR1, DPPR2)
Description amended
... The preset data can be calculated from the following
equation by using H'8000 as the reference value.
26.13.5 Register
Description
698
26.13.6 Operation
701
Figure 26.50 Example
of CTLM Switchover
Timing (When phase
Control Is Performed by
REF30P and DVCFG2
in REC Mode)
Bit 0 description amended
•
ASM Mark Direct Mode: ... The duty I/O flag is 1 when the
duty cycle of the PB-CTL signal is below 65% (when an
ASM mark is not detected).
Note 1 amended
Note: 1. Ta is the interval calculated from RCDR3.
Rev.2.00 Jan. 15, 2007 page xv of xliv
REJ09B0329-0200
Item
Page
Revision (See Manual for Details)
26.13.6 Operation
702
Note 1 amended
Figure 26.51 Example
of CTLM Switchover
Timing (When phase
Control Is Performed by
CREF and DVCFG2 in
REC Mode)
26.15.5 Register
Description
Note: 1. Ta is the interval calculated from RCDR3.
736
Horizontal Sync Signal Threshold Register (HTR)
Description amended
... Thus, if φs = 5 MHz, NTSC system is used, ...
(HVTH - 2) × 0.4 μs ≤ 2.35 μs < (HVTH - 1) × 0.4 μs
∴HVTH ≥ H'7
26.15.6 Noise
Detection
741
Description amended
Example of Setting: ... Accordingly, ...
(Value of HPWR3 - 0) + 1) × 0.4 (μs) = 4.7 (μs)
∴HPWR3 - 0 = H'B ...
27.1.2 Block Diagram 753
Figure 27.1 amended
27.2.1 Sync Separation 755
Input Mode Register
(SEPIMR)
27.2.2 Sync Separation 762
Control Register
(SEPCR)
AFCpc
AFCLPF
AFCosc
AFC oscillator
Figure 27.1 Sync
Separator Block
Diagram
Description amended
Bits order than bit 5 CCMPSL are cleared to 0 ...
Bit 2 description amended
... Forcibly operates the half Hsync killer (HHK)* function when
...
Note * added
Note: * HHK: Half Hsync Killer
Rev.2.00 Jan. 15, 2007 page xvi of xliv
REJ09B0329-0200
Item
Page
27.2.4 Horizontal Sync 765
Signal Threshold
Register (HVTHR)
Revision (See Manual for Details)
Figure 27.3 title amended
Figure 27.3 HVTH
Value and SEPH
Generation Timing when
Equalization Pulses Are
Detected
766
Description amended
In general, ... , set the HVTH value so that 2.35-μs equalizing
pulses can be detected.
Figure 27.8 Timing of 768
Hsync-Vsync PhaseDifference Error Due to
Noise Occurrence after
Equalizing Pulse Is Lost
at Hsync Pulse Position
"HC" deleted from figure 27.8
Figure 27.9 Timing of 769
Forcible HHK Operation
in V Blanking Period
when Equalizating Pulse
Is Not Detected
"HC" deleted from figure 27.9
770
Figure 27.10 title amended
Figure 27.11 VVTH
771
Value and SEPV
Generation Timing when
Digital LPF Is Enabled
Figure 27.11 title amended
27.2.6 Field Detection 772
Window Register
(FWIDR)
(1) Bit 0 of SEPCR Register
27.3.5 Noise Detection 789
Description amended
27.2.5 Vertical Sync
Signal Threshold
Register (VVTHR)
Figure 27.10 VVTH
Value and SEPV
Generation Timing
Bit 0 table amended
(Before) LD → (After) FLD
... The noise detection window signal is se to 1 ... at the HHK
clearing timing specified by bits HM6 to HM0 of the HCMMR. ...
Rev.2.00 Jan. 15, 2007 page xvii of xliv
REJ09B0329-0200
Item
Page
Revision (See Manual for Details)
28.2.1 Slice Even(Odd-) Fields Mode
Register (SEVFD,
SODFD)
1004
Bits 4 to 0 notes amended
28.2.5 Module Stop
Control Register
(MSTPCR)
811
Notes: 1. 576 when bit 0 (FRQSEL) of SEPIMR in the sync
separator is 0, and 448 when FRQSEL is 1.
2. fh: Horizontal sync signal frequency
Bit figure amended
MSTPCRH
Bit:
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
Initial value:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
28.4 32-Bit Slice
Operation
819
Note: * 576 when ... is set to 0. 448 when bit FRQSEL (bit 0) in
SEPIMR (synchronization separator) is set to 1.
Figure 28.13 Sampling
Clock when Bit DSL32B
Is 1
29.2.3 On-Screen
Display Configuration
Note * amended
829
Figure 29.4
Correspondence
between Display Data
RAM and On-Screen
Display
Note amended
Note: D800 to DAFE indicate the lower 16 bits of addresses in
the on-screen display RAM.
29.3.6 Character Data 834
ROM (OSDROM)
Figure 29.7 amended
Figure 29.7 OSD ROM
Map
045FFF*
1
Bit data for character code H'000 (blank character display)*
2
Notes: 1. Character code H'000 is reserved for blank character
display and ...
040000 :H'F0 040001 :H'00 040002 :H'F0 040003 :H'00 ...
040022 :H'F0 040023 :H'00 040024 :H'FF
04003F :H'FF
2. These addresses represent the H8S/2199R Group
addresses.
Rev.2.00 Jan. 15, 2007 page xviii of xliv
REJ09B0329-0200
Item
Page
Revision (See Manual for Details)
29.3.7 Display Data
RAM (OSDRAM)
839
Bits 11 to 9 bit table amended
OSDRAM
Character Color
Bit 11
Bit 10
Bit 9
C.Video Output
CR
CG
CB
NTSC
PAL
0
0
0
Black
Black
Black
1
π
±π
Blue
0
7π/4
±7π/4
Green
1
3π/2
±3π/2
Cyan
1
29.4.5 Row Registers 842
(CLINEn, N = rows 1 to
12)
846
R,G,B Outputs
Bit figure amended
Bit 4 (Before) CLUn2 → (After) CLUn0
Bit 0⎯Cursor Brightness/Halftone Levels Specification Bit
(KLUn, n = 1 to 12)
•
Cursor Brightness in Text Display Mode
•
Halftone Levels in Superimposed Mode
Bit table amended
(Before) KLU → (After) KLUn
29.6.5 OSDV Interrupt 858
Bit figure amended
R/W description in bit 10 (Before) R/W → (After) ⎯
31.4.8 Flash Memory
Characteristics
950
Table 31.32 Flash
Memory Characteristics
Table 31.32 amended
Item
Symbol
Min Typ
Programming time*1*2*4
tP
—
Erase time*1*3*5
tE
Reprogramming count
NWEC
tDRP
10
Data retention time*
951
10
Max
Unit
10
200
ms/128
bytes
—
100
1200 ms/block
100
*8
10000 —
*9
Times
—
Years
—
Notes
Notes 6 to 8 added
Notes: 6. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
7. Reference value for 25C° (as a guide line, rewriting should
normally function up to this value).
8. Data retention characteristics when rewriting is performed
within the specification range, including the minimum value.
B.2 Function List
1022
H'D029: CFIC: Digital Filter
Figure amended
Capstan phase system Z-1 initialization bit
0
1
Phase system Z-1 does not reflect CZp value. (Initial value)
Phase system Z-1 reflects CZp value.
Rev.2.00 Jan. 15, 2007 page xix of xliv
REJ09B0329-0200
Item
Page
Revision (See Manual for Details)
B.2 Function List
1071
H'D106: TCRX: Timer X1
Figure amended
Buffer enable B
1103
0
ICRD is not used as buffer register for ICRB
(Initial value)
1
ICRD is used as buffer register for ICRB
H'D200 to H'D20B: CLINE1 to CLINE12: OSD
Figure amended
Bit 4 (Before) CLUn2 → (After) CLUn0
Cursor color specification bits
(Cursor Colors in Text Display Mode)
Bit 3
Bit 2
Bit 1
Character Brightness Level
Cursor Color (C.Video Output) Cursor Color (R, G, B Output)
KRn
KGn
KBn
NTSC
PAL
0
0
0
Black
Black
Black
(Initial value)
π
±π
Blue
1
±7π/4
1
0
7π/4
Green
±3π/2
1
3π/2
Cyan
π/2
±π/2
1
0
0
Red
±3π/4
1
3π/4
Magenta
1
0
Same phase
±0
Yellow
1
White
White
White
1112
H'D222: SODFD: Data Slicer
Figure amended
Bit
:
7
SLVLO2
6
SLVLO1
5
SLVLO0
4
DLYO4
3
DLYO3
2
DLYO2
1
DLYO1
0
DLYO0
Bit 4 (Before) DLYO3 → (After) DLYO4
1115
H'D240: SEPIMR: Sync Separator
Figure amended
Bit 5 (Before) CCMPSL → (After) CCMPSL*
1128
H'FFCD: PMR0: I/O Port
Figure amended
(Before) P07/AN7 to P00/IRQ0 rin function select bits→ (After)
P07/AN7 to P00/AN0 pin switching
1137
H'FFE3: PUR3: I/O Port
Figure amended
Bit
:
Initial value :
R/W
:
7
PUR37
6
PUR36
5
PUR35
4
PUR34
3
PUR33
2
PUR32
1
PUR31
0
PUR30
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Note:
Rev.2.00 Jan. 15, 2007 page xx of xliv
REJ09B0329-0200
0
P3n pin has no pull-up MOS transistor
1
P3n pin has pull-up MOS transistor
n = 7 to 0
(Initial value)
Item
Page
Revision (See Manual for Details)
B.2 Function List
1138
H'FFE5: Real Time Output Trigger Select Register 1 RTPSR1:
I/O Port
Figure amended
:
Bit
7
6
5
4
3
2
1
0
RTPSR17 RTPSR16 RTPSR15 RTPSR14 RTPSR13 RTPSR12 RTPSR11 RTPSR10
Subheading amended
H'FFE6: Real Time Output Trigger Select Register 2 RTPSR2:
I/O Port
1141
H'FFEB: LPWRCR: System Control
Note * deleted from DTON description
(Before) • ... to subactive mode*, or transition is made directly
to sleep mode or standby mode → (After) • ... to subactive
mode, or transition is made directly to sleep mode or standby
mode
1142
H'FFEE: STCR: System Control
2
Note * added to I C control description
Used combined with CKS2 to CKS0 in ICMR0*
E.1 Power Supply Rise 1163
and Fall Order
Figure E.1 Power
Supply Rise and Fall
Order
Appendix G Package
Dimensions
Figure E.1 amended
VCC, AVCC
Vin
1173
SVCC, OVCC
Figure G.1 replaced
Figure G.1 Package
Dimensions
(PRQP0112JA-A)
Rev.2.00 Jan. 15, 2007 page xxi of xliv
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All trademarks and registered trademarks are the property of their respective owners.
Rev.2.00 Jan. 15, 2007 page xxii of xliv
REJ09B0329-0200
Contents
Section 1 Overview .............................................................................................................
1.1
1.2
1.3
1
Overview........................................................................................................................... 1
Internal Block Diagram..................................................................................................... 7
Pin Arrangement and Functions........................................................................................ 9
1.3.1 Pin Arrangement .................................................................................................. 9
1.3.2 Pin Functions ....................................................................................................... 11
Section 2 CPU ...................................................................................................................... 19
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Overview...........................................................................................................................
2.1.1 Features................................................................................................................
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................
2.1.3 Differences from H8/300 CPU.............................................................................
2.1.4 Differences from H8/300H CPU..........................................................................
CPU Operating Modes ......................................................................................................
2.2.1 Normal Mode (Not available for this LSI)...........................................................
2.2.2 Advanced Mode ...................................................................................................
Address Space ...................................................................................................................
Register Configuration ......................................................................................................
2.4.1 Overview..............................................................................................................
2.4.2 General Registers .................................................................................................
2.4.3 Control Registers .................................................................................................
2.4.4 Initial Register Values..........................................................................................
Data Formats .....................................................................................................................
2.5.1 General Register Data Formats ............................................................................
2.5.2 Memory Data Formats .........................................................................................
Instruction Set ...................................................................................................................
2.6.1 Overview..............................................................................................................
2.6.2 Instructions and Addressing Modes .....................................................................
2.6.3 Table of Instructions Classified by Function .......................................................
2.6.4 Basic Instruction Formats ....................................................................................
2.6.5 Notes on Use of Bit-Manipulation Instructions ...................................................
Addressing Modes and Effective Address Calculation .....................................................
2.7.1 Addressing Mode .................................................................................................
2.7.2 Effective Address Calculation..............................................................................
Processing States...............................................................................................................
2.8.1 Overview..............................................................................................................
2.8.2 Reset State............................................................................................................
19
19
20
21
21
22
22
24
27
28
28
29
30
32
33
33
35
36
36
38
39
49
50
51
51
54
58
58
59
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REJ09B0329-0200
2.8.3 Exception-Handling State ....................................................................................
2.8.4 Program Execution State......................................................................................
2.8.5 Power-Down State ...............................................................................................
2.9 Basic Timing.....................................................................................................................
2.9.1 Overview..............................................................................................................
2.9.2 On-Chip Memory (ROM, RAM) .........................................................................
2.9.3 On-Chip Supporting Module Access Timing ......................................................
2.10 Usage Note........................................................................................................................
2.10.1 TAS Instruction....................................................................................................
2.10.2 STM/LDM Instruction .........................................................................................
60
61
62
63
63
63
63
64
64
64
Section 3 MCU Operating Modes .................................................................................. 65
3.1
3.2
3.3
3.4
Overview...........................................................................................................................
3.1.1 Operating Mode Selection ...................................................................................
3.1.2 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
3.2.1 Mode Control Register (MDCR) .........................................................................
3.2.2 System Control Register (SYSCR) ......................................................................
Operating Mode (Mode 1) ................................................................................................
Address Map in Each Operating Mode.............................................................................
65
65
65
66
66
66
67
68
Section 4 Power-Down State............................................................................................ 71
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Overview...........................................................................................................................
4.1.1 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
4.2.1 Standby Control Register (SBYCR) ....................................................................
4.2.2 Low-Power Control Register (LPWRCR) ...........................................................
4.2.3 Timer Register A (TMA) .....................................................................................
4.2.4 Module Stop Control Register (MSTPCR) ..........................................................
Medium-Speed Mode........................................................................................................
Sleep Mode .......................................................................................................................
4.4.1 Sleep Mode ..........................................................................................................
4.4.2 Clearing Sleep Mode............................................................................................
Module Stop Mode ...........................................................................................................
4.5.1 Module Stop Mode ..............................................................................................
Standby Mode ...................................................................................................................
4.6.1 Standby Mode ......................................................................................................
4.6.2 Clearing Standby Mode .......................................................................................
4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode..........................
Watch Mode......................................................................................................................
Rev.2.00 Jan. 15, 2007 page xxiv of xliv
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71
76
76
76
78
80
81
82
83
83
83
84
84
85
85
85
85
87
4.7.1 Watch Mode.........................................................................................................
4.7.2 Clearing Watch Mode ..........................................................................................
4.8 Subsleep Mode..................................................................................................................
4.8.1 Subsleep Mode.....................................................................................................
4.8.2 Clearing Subsleep Mode ......................................................................................
4.9 Subactive Mode.................................................................................................................
4.9.1 Subactive Mode ...................................................................................................
4.9.2 Clearing Subactive Mode.....................................................................................
4.10 Direct Transition ...............................................................................................................
4.10.1 Overview of Direct Transition .............................................................................
87
87
88
88
88
89
89
89
90
90
Section 5 Exception Handling ......................................................................................... 91
5.1
5.2
5.3
5.4
5.5
5.6
Overview...........................................................................................................................
5.1.1 Exception Handling Types and Priority ...............................................................
5.1.2 Exception Handling Operation.............................................................................
5.1.3 Exception Sources and Vector Table ...................................................................
Reset..................................................................................................................................
5.2.1 Overview..............................................................................................................
5.2.2 Reset Sequence ....................................................................................................
5.2.3 Interrupts after Reset............................................................................................
Interrupts ...........................................................................................................................
Trap Instruction.................................................................................................................
Stack Status after Exception Handling..............................................................................
Notes on Use of the Stack .................................................................................................
91
91
92
92
94
94
94
95
96
97
98
99
Section 6 Interrupt Controller .......................................................................................... 101
6.1
6.2
6.3
Overview...........................................................................................................................
6.1.1 Features................................................................................................................
6.1.2 Block Diagram .....................................................................................................
6.1.3 Pin Configuration.................................................................................................
6.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
6.2.1 System Control Register (SYSCR) ......................................................................
6.2.2 Interrupt Control Registers A to D (ICRA to ICRD) ...........................................
6.2.3 IRQ Enable Register (IENR) ...............................................................................
6.2.4 IRQ Edge Select Registers (IEGR) ......................................................................
6.2.5 IRQ Status Register (IRQR) ................................................................................
6.2.6 Port Mode Register 1 (PMR1) .............................................................................
Interrupt Sources ...............................................................................................................
6.3.1 External Interrupts ...............................................................................................
101
101
102
103
103
104
104
105
106
107
108
109
110
110
Rev.2.00 Jan. 15, 2007 page xxv of xliv
REJ09B0329-0200
6.4
6.5
6.3.2 Internal Interrupts ................................................................................................
6.3.3 Interrupt Exception Vector Table ........................................................................
Interrupt Operation............................................................................................................
6.4.1 Interrupt Control Modes and Interrupt Operation ................................................
6.4.2 Interrupt Control Mode 0 .....................................................................................
6.4.3 Interrupt Control Mode 1 .....................................................................................
6.4.4 Interrupt Exception Handling Sequence ..............................................................
6.4.5 Interrupt Response Times ....................................................................................
Usage Notes ......................................................................................................................
6.5.1 Contention between Interrupt Generation and Disabling.....................................
6.5.2 Instructions That Disable Interrupts.....................................................................
6.5.3 Interrupts during Execution of EEPMOV Instruction..........................................
112
113
116
116
118
120
123
124
125
125
126
126
Section 7 ROM ..................................................................................................................... 127
7.1
7.2
7.3
7.4
7.5
Overview...........................................................................................................................
7.1.1 Block Diagram.....................................................................................................
Overview of Flash Memory ..............................................................................................
7.2.1 Features................................................................................................................
7.2.2 Block Diagram.....................................................................................................
7.2.3 Flash Memory Operating Modes .........................................................................
7.2.4 Pin Configuration.................................................................................................
7.2.5 Register Configuration.........................................................................................
Flash Memory Register Descriptions................................................................................
7.3.1 Flash Memory Control Register 1 (FLMCR1).....................................................
7.3.2 Flash Memory Control Register 2 (FLMCR2).....................................................
7.3.3 Erase Block Register 1 (EBR1) ...........................................................................
7.3.4 Erase Block Register 2 (EBR2) ...........................................................................
7.3.5 Serial/Timer Control Register (STCR) ................................................................
On-Board Programming Modes........................................................................................
7.4.1 Boot Mode ...........................................................................................................
7.4.2 User Program Mode.............................................................................................
Programming/Erasing Flash Memory ...............................................................................
7.5.1 Program Mode (n = 1 when the Target Address Range Is H'00000 to H'3FFFF
and n = 2 when the Target Address Range Is H'40000 to H'47FFF)...................
7.5.2 Program-Verify Mode (n = 1 when the Target Address Range Is H'00000 to
H'3FFFF and n = 2 when the Target Address Range Is H'40000 to H'47FFF) ....
7.5.3 Erase Mode (n = 1 when the Target Address Range Is H'00000 to H'3FFFF
and n = 2 when the Target Address Range Is H'40000 to H'47FFF)....................
7.5.4 Erase-Verify Mode (n = 1 when the Target Address Range Is H'00000 to
H'3FFFF and n = 2 when the Target Address Range Is H'40000 to H'47FFF) ....
Rev.2.00 Jan. 15, 2007 page xxvi of xliv
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127
128
128
129
130
134
134
135
135
138
141
142
143
144
145
150
151
151
152
154
156
7.6
7.7
7.8
7.9
Flash Memory Protection..................................................................................................
7.6.1 Hardware Protection ............................................................................................
7.6.2 Software Protection..............................................................................................
7.6.3 Error Protection....................................................................................................
Interrupt Handling when Programming/Erasing Flash Memory.......................................
Flash Memory Programmer Mode ....................................................................................
7.8.1 Programmer Mode Setting ...................................................................................
7.8.2 Socket Adapters and Memory Map......................................................................
7.8.3 Programmer Mode Operation ..............................................................................
7.8.4 Memory Read Mode ............................................................................................
7.8.5 Auto-Program Mode ............................................................................................
7.8.6 Auto-Erase Mode .................................................................................................
7.8.7 Status Read Mode ................................................................................................
7.8.8 Status Polling .......................................................................................................
7.8.9 Programmer Mode Transition Time.....................................................................
7.8.10 Notes on Memory Programming..........................................................................
Note on Switching from F–ZTAT Version to Mask-ROM Version .................................
157
157
158
158
159
160
160
160
161
162
165
167
168
170
170
171
172
Section 8 RAM ..................................................................................................................... 173
8.1
Overview........................................................................................................................... 173
8.1.1 Block Diagram ..................................................................................................... 173
Section 9 Clock Pulse Generator..................................................................................... 175
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
Overview...........................................................................................................................
9.1.1 Block Diagram .....................................................................................................
9.1.2 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
9.2.1 Standby Control Register (SBYCR) ....................................................................
9.2.2 Low-Power Control Register (LPWRCR) ...........................................................
Oscillator...........................................................................................................................
9.3.1 Connecting a Crystal Resonator...........................................................................
9.3.2 External Clock Input ............................................................................................
Duty Adjustment Circuit ...................................................................................................
Medium-Speed Clock Divider ..........................................................................................
Bus Master Clock Selection Circuit ..................................................................................
Subclock Oscillator Circuit ...............................................................................................
9.7.1 Connecting 32.768 kHz Crystal Resonator ..........................................................
9.7.2 When Subclock Is Not Needed ............................................................................
Subclock Waveform Shaping Circuit................................................................................
Notes on the Resonator .....................................................................................................
175
175
175
176
176
176
177
177
179
182
182
182
182
182
183
183
184
Rev.2.00 Jan. 15, 2007 page xxvii of xliv
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Section 10 I/O Port .............................................................................................................. 185
10.1 Overview...........................................................................................................................
10.1.1 Port Functions ......................................................................................................
10.1.2 Port Input .............................................................................................................
10.1.3 MOS Pull-Up Transistors ....................................................................................
10.2 Port 0.................................................................................................................................
10.2.1 Overview..............................................................................................................
10.2.2 Register Configuration.........................................................................................
10.2.3 Pin Functions .......................................................................................................
10.2.4 Pin States .............................................................................................................
10.3 Port 1.................................................................................................................................
10.3.1 Overview..............................................................................................................
10.3.2 Register Configuration.........................................................................................
10.3.3 Pin Functions .......................................................................................................
10.3.4 Pin States .............................................................................................................
10.4 Port 2.................................................................................................................................
10.4.1 Overview..............................................................................................................
10.4.2 Register Configuration.........................................................................................
10.4.3 Pin Functions .......................................................................................................
10.4.4 Pin States .............................................................................................................
10.5 Port 3.................................................................................................................................
10.5.1 Overview..............................................................................................................
10.5.2 Register Configuration.........................................................................................
10.5.3 Pin Functions .......................................................................................................
10.5.4 Pin States .............................................................................................................
10.6 Port 4.................................................................................................................................
10.6.1 Overview..............................................................................................................
10.6.2 Register Configuration.........................................................................................
10.6.3 Pin Functions .......................................................................................................
10.6.4 Pin States .............................................................................................................
10.7 Port 6.................................................................................................................................
10.7.1 Overview..............................................................................................................
10.7.2 Register Configuration.........................................................................................
10.7.3 Pin Functions .......................................................................................................
10.7.4 Operation .............................................................................................................
10.7.5 Pin States .............................................................................................................
10.8 Port 7.................................................................................................................................
10.8.1 Overview..............................................................................................................
10.8.2 Register Configuration.........................................................................................
10.8.3 Pin Functions .......................................................................................................
Rev.2.00 Jan. 15, 2007 page xxviii of xliv
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185
185
185
188
189
189
189
191
191
192
192
192
196
197
198
198
198
200
203
204
204
204
208
210
211
211
211
214
216
217
217
218
222
224
225
226
226
227
231
10.8.4 Operation .............................................................................................................
10.8.5 Pin States..............................................................................................................
10.9 Port 8.................................................................................................................................
10.9.1 Overview..............................................................................................................
10.9.2 Register Configuration.........................................................................................
10.9.3 Pin Functions .......................................................................................................
10.9.4 Pin States..............................................................................................................
232
233
234
234
235
240
242
Section 11 Timer A ............................................................................................................. 243
11.1 Overview...........................................................................................................................
11.1.1 Features................................................................................................................
11.1.2 Block Diagram .....................................................................................................
11.1.3 Register Configuration.........................................................................................
11.2 Register Descriptions ........................................................................................................
11.2.1 Timer Mode Register A (TMA)...........................................................................
11.2.2 Timer Counter A (TCA) ......................................................................................
11.2.3 Module Stop Control Register (MSTPCR) ..........................................................
11.3 Operation...........................................................................................................................
11.3.1 Operation as the Interval Timer ...........................................................................
11.3.2 Operation as Clock Timer ....................................................................................
11.3.3 Initializing the Counts..........................................................................................
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245
247
247
248
248
248
248
Section 12 Timer B ............................................................................................................. 249
12.1 Overview...........................................................................................................................
12.1.1 Features................................................................................................................
12.1.2 Block Diagram .....................................................................................................
12.1.3 Pin Configuration.................................................................................................
12.1.4 Register Configuration.........................................................................................
12.2 Register Descriptions ........................................................................................................
12.2.1 Timer Mode Register B (TMB) ...........................................................................
12.2.2 Timer Counter B (TCB).......................................................................................
12.2.3 Timer Load Register B (TLB) .............................................................................
12.2.4 Port Mode Register A (PMRA) ...........................................................................
12.2.5 Module Stop Control Register (MSTPCR) ..........................................................
12.3 Operation...........................................................................................................................
12.3.1 Operation as the Interval Timer ...........................................................................
12.3.2 Operation as the Auto Reload Timer ...................................................................
12.3.3 Event Counter ......................................................................................................
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250
250
251
251
253
253
254
255
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256
256
256
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Section 13 Timer J............................................................................................................... 257
13.1 Overview...........................................................................................................................
13.1.1 Features................................................................................................................
13.1.2 Block Diagram.....................................................................................................
13.1.3 Pin Configuration.................................................................................................
13.1.4 Register Configuration.........................................................................................
13.2 Register Descriptions ........................................................................................................
13.2.1 Timer Mode Register J (TMJ) .............................................................................
13.2.2 Timer J Control Register (TMJC) ........................................................................
13.2.3 Timer J Status Register (TMJS)...........................................................................
13.2.4 Timer Counter J (TCJ) .........................................................................................
13.2.5 Timer Counter K (TCK) ......................................................................................
13.2.6 Timer Load Register J (TLJ)................................................................................
13.2.7 Timer Load Register K (TLK) .............................................................................
13.2.8 Module Stop Control Register (MSTPCR) ..........................................................
13.3 Operation ..........................................................................................................................
13.3.1 8-bit Reload Timer (TMJ-1) ................................................................................
13.3.2 8-bit Reload Timer (TMJ-2) ................................................................................
13.3.3 Remote Controlled Data Transmission ................................................................
13.3.4 TMJ-2 Expansion Function..................................................................................
257
257
257
259
259
260
260
263
266
267
267
268
268
269
270
270
270
271
275
Section 14 Timer L ............................................................................................................. 277
14.1 Overview...........................................................................................................................
14.1.1 Features................................................................................................................
14.1.2 Block Diagram.....................................................................................................
14.1.3 Register Configuration.........................................................................................
14.2 Register Descriptions ........................................................................................................
14.2.1 Timer L Mode Register (LMR) ...........................................................................
14.2.2 Linear Time Counter (LTC).................................................................................
14.2.3 Reload/Compare Match Register (RCR) .............................................................
14.2.4 Module Stop Control Register (MSTPCR) ..........................................................
14.3 Operation ..........................................................................................................................
14.3.1 Compare Match Clear Operation .........................................................................
14.3.2 Auto-Reload Operation........................................................................................
14.3.3 Interval Timer Operation .....................................................................................
14.3.4 Interrupt Request..................................................................................................
14.4 Typical Usage ...................................................................................................................
14.5 Reload Timer Interrupt Request Signal.............................................................................
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287
Section 15 Timer R ............................................................................................................. 289
15.1 Overview...........................................................................................................................
15.1.1 Features................................................................................................................
15.1.2 Block Diagram .....................................................................................................
15.1.3 Pin Configuration.................................................................................................
15.1.4 Register Configuration.........................................................................................
15.2 Register Descriptions ........................................................................................................
15.2.1 Timer R Mode Register 1 (TMRM1)...................................................................
15.2.2 Timer R Mode Register 2 (TMRM2)...................................................................
15.2.3 Timer R Control/Status Register (TMRCS).........................................................
15.2.4 Timer R Capture Register 1 (TMRCP1) ..............................................................
15.2.5 Timer R Capture Register 2 (TMRCP2) ..............................................................
15.2.6 Timer R Load Register 1 (TMRL1) .....................................................................
15.2.7 Timer R Load Register 2 (TMRL2) .....................................................................
15.2.8 Timer R Load Register 3 (TMRL3) .....................................................................
15.2.9 Module Stop Control Register (MSTPCR) ..........................................................
15.3 Operation...........................................................................................................................
15.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1..................
15.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2..................
15.3.3 Reload Counter Timer TMRU-3..........................................................................
15.3.4 Mode Identification..............................................................................................
15.3.5 Reeling Controls ..................................................................................................
15.3.6 Acceleration and Braking Processes of the Capstan Motor .................................
15.3.7 Slow Tracking Mono-Multi Function ..................................................................
15.4 Interrupt Cause..................................................................................................................
15.5 Settings for Respective Functions .....................................................................................
15.5.1 Mode Identification..............................................................................................
15.5.2 Reeling Controls ..................................................................................................
15.5.3 Slow Tracking Mono-Multi Function ..................................................................
15.5.4 Acceleration and Braking Processes of the Capstan Motor .................................
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289
291
291
292
292
294
297
299
299
300
300
301
301
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302
302
303
304
304
304
305
307
308
308
309
310
311
Section 16 Timer X1 ........................................................................................................... 313
16.1 Overview...........................................................................................................................
16.1.1 Features................................................................................................................
16.1.2 Block Diagram .....................................................................................................
16.1.3 Pin Configuration.................................................................................................
16.1.4 Register Configuration.........................................................................................
16.2 Register Descriptions ........................................................................................................
16.2.1 Free Running Counter (FRC)...............................................................................
16.2.2 Output Comparing Registers A and B (OCRA and OCRB) ................................
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317
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16.3
16.4
16.5
16.6
16.7
16.2.3 Input Capture Registers A through D (ICRA through ICRD)..............................
16.2.4 Timer Interrupt Enabling Register (TIER)...........................................................
16.2.5 Timer Control/Status Register X (TCSRX) .........................................................
16.2.6 Timer Control Register X (TCRX) ......................................................................
16.2.7 Timer Output Comparing Control Register (TOCR) ...........................................
16.2.8 Module Stop Control Register (MSTPCR) ..........................................................
Operation ..........................................................................................................................
16.3.1 Operation of Timer X1.........................................................................................
16.3.2 Counting Timing of the FRC ...............................................................................
16.3.3 Output Comparing Signal Outputting Timing .....................................................
16.3.4 FRC Clearing Timing ..........................................................................................
16.3.5 Input Capture Signal Inputting Timing ................................................................
16.3.6 Input Capture Flag (ICFA through ICFD) Setting Up Timing ............................
16.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing ........................
16.3.8 Overflow Flag (CVF) Setting Up Timing............................................................
Operation Mode of Timer X1 ...........................................................................................
Interrupt Causes ................................................................................................................
Exemplary Uses of Timer X1 ...........................................................................................
Precautions when Using Timer X1 ...................................................................................
16.7.1 Competition between Writing and Clearing with the FRC ..................................
16.7.2 Competition between Writing and Counting Up with the FRC ...........................
16.7.3 Competition between Writing and Comparing Match with the OCR ..................
16.7.4 Changing Over the Internal Clocks and Counter Operations...............................
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331
331
332
333
333
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336
336
337
337
338
339
339
340
341
342
Section 17 Watchdog Timer (WDT).............................................................................. 345
17.1 Overview...........................................................................................................................
17.1.1 Features................................................................................................................
17.1.2 Block Diagram.....................................................................................................
17.1.3 Register Configuration.........................................................................................
17.2 Register Descriptions ........................................................................................................
17.2.1 Watchdog Timer Counter (WTCNT)...................................................................
17.2.2 Watchdog Timer Control/Status Register (WTCSR)...........................................
17.2.3 System Control Register (SYSCR) ......................................................................
17.2.4 Notes on Register Access.....................................................................................
17.3 Operation ..........................................................................................................................
17.3.1 Watchdog Timer Operation .................................................................................
17.3.2 Interval Timer Operation .....................................................................................
17.3.3 Timing of Setting of Overflow Flag (OVF) .........................................................
17.4 Interrupts...........................................................................................................................
17.5 Usage Notes ......................................................................................................................
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354
355
17.5.1 Contention between Watchdog Timer Counter (WTCNT) Write and Increment 355
17.5.2 Changing Value of CKS2 to CKS0...................................................................... 355
17.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 356
Section 18 8-Bit PWM ....................................................................................................... 357
18.1 Overview...........................................................................................................................
18.1.1 Features................................................................................................................
18.1.2 Block Diagram .....................................................................................................
18.1.3 Pin Configuration.................................................................................................
18.1.4 Register Configuration.........................................................................................
18.2 Register Descriptions ........................................................................................................
18.2.1 8-bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3)...........
18.2.2 8-bit PWM Control Register (PW8CR) ...............................................................
18.2.3 Port Mode Register 3 (PMR3) .............................................................................
18.2.4 Module Stop Control Register (MSTPCR) ..........................................................
18.3 8-Bit PWM Operation .......................................................................................................
357
357
357
358
358
359
359
360
360
361
362
Section 19 12-Bit PWM..................................................................................................... 363
19.1 Overview...........................................................................................................................
19.1.1 Features................................................................................................................
19.1.2 Block Diagram .....................................................................................................
19.1.3 Pin Configuration.................................................................................................
19.1.4 Register Configuration.........................................................................................
19.2 Register Descriptions ........................................................................................................
19.2.1 12-Bit PWM Control Registers (CPWCR, DPWCR) ..........................................
19.2.2 12-Bit PWM Data Registers (DPWDR, CPWDR) ..............................................
19.2.3 Module Stop Control Register (MSTPCR) ..........................................................
19.3 Operation...........................................................................................................................
19.3.1 Output Waveform ................................................................................................
363
363
364
365
365
366
366
368
369
370
370
Section 20 14-Bit PWM..................................................................................................... 373
20.1 Overview...........................................................................................................................
20.1.1 Features................................................................................................................
20.1.2 Block Diagram .....................................................................................................
20.1.3 Pin Configuration.................................................................................................
20.1.4 Register Configuration.........................................................................................
20.2 Register Descriptions ........................................................................................................
20.2.1 PWM Control Register (PWCR)..........................................................................
20.2.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................
20.2.3 Module Stop Control Register (MSTPCR) ..........................................................
373
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374
374
375
375
375
376
377
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20.3 14-Bit PWM Operation..................................................................................................... 378
Section 21 Prescalar Unit .................................................................................................. 379
21.1 Overview...........................................................................................................................
21.1.1 Features................................................................................................................
21.1.2 Block Diagram.....................................................................................................
21.1.3 Pin Configuration.................................................................................................
21.1.4 Register Configuration.........................................................................................
21.2 Registers............................................................................................................................
21.2.1 Input Capture Register 1 (ICR1)..........................................................................
21.2.2 Prescalar Unit Control/Status Register (PCSR) ...................................................
21.2.3 Port Mode Register 1 (PMR1) .............................................................................
21.3 Noise Cancel Circuit .........................................................................................................
21.4 Operation ..........................................................................................................................
21.4.1 Prescalar S (PSS) .................................................................................................
21.4.2 Prescalar W (PSW) ..............................................................................................
21.4.3 Stable Oscillation Wait Time Count ....................................................................
21.4.4 8-bit PWM ...........................................................................................................
21.4.5 8-bit Input Capture Using IC Pin .........................................................................
21.4.6 Frequency Division Clock Output .......................................................................
379
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381
381
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382
382
384
385
385
385
386
386
387
387
387
Section 22 Serial Communication Interface 1 (SCI1) .............................................. 389
22.1 Overview...........................................................................................................................
22.1.1 Features................................................................................................................
22.1.2 Block Diagram.....................................................................................................
22.1.3 Pin Configuration.................................................................................................
22.1.4 Register Configuration.........................................................................................
22.2 Register Descriptions ........................................................................................................
22.2.1 Receive Shift Register 1 (RSR1) .........................................................................
22.2.2 Receive Data Register 1 (RDR1) .........................................................................
22.2.3 Transmit Shift Register 1 (TSR1) ........................................................................
22.2.4 Transmit Data Register 1 (TDR1)........................................................................
22.2.5 Serial Mode Register 1 (SMR1)...........................................................................
22.2.6 Serial Control Register 1 (SCR1).........................................................................
22.2.7 Serial Status Register 1 (SSR1) ...........................................................................
22.2.8 Bit Rate Register 1 (BRR1) .................................................................................
22.2.9 Serial Interface Mode Register 1 (SCMR1).........................................................
22.2.10 Module Stop Control Register (MSTPCR) ..........................................................
22.3 Operation ..........................................................................................................................
22.3.1 Overview..............................................................................................................
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389
391
392
392
393
393
393
394
394
395
398
402
406
413
414
415
415
22.3.2 Operation in Asynchronous Mode .......................................................................
22.3.3 Multiprocessor Communication Function............................................................
22.3.4 Operation in Synchronous Mode .........................................................................
22.4 SCI Interrupts....................................................................................................................
22.5 Usage Notes ......................................................................................................................
417
427
435
444
445
Section 23 I2C Bus Interface (IIC) ................................................................................. 451
23.1 Overview...........................................................................................................................
23.1.1 Features................................................................................................................
23.1.2 Block Diagram .....................................................................................................
23.1.3 Pin Configuration.................................................................................................
23.1.4 Register Configuration.........................................................................................
23.2 Register Descriptions ........................................................................................................
2
23.2.1 I C Bus Data Register (ICDR) .............................................................................
23.2.2 Slave Address Register (SAR) .............................................................................
23.2.3 Second Slave Address Register (SARX) .............................................................
2
23.2.4 I C Bus Mode Register (ICMR) ...........................................................................
2
23.2.5 I C Bus Control Register (ICCR) .........................................................................
2
23.2.6 I C Bus Status Register (ICSR)............................................................................
23.2.7 Serial/Timer Control Register (STCR) ................................................................
23.2.8 DDC Switch Register (DDCSWR) ......................................................................
23.2.9 Module Stop Control Register (MSTPCR) ..........................................................
23.3 Operation...........................................................................................................................
2
23.3.1 I C Bus Data Format ............................................................................................
23.3.2 Master Transmit Operation ..................................................................................
23.3.3 Master Receive Operation....................................................................................
23.3.4 Slave Receive Operation......................................................................................
23.3.5 Slave Transmit Operation ....................................................................................
23.3.6 IRIC Setting Timing and SCL Control ................................................................
2
23.3.7 Automatic Switching from Formatless Transfer to I C Bus Format Transfer......
23.3.8 Noise Canceler .....................................................................................................
23.3.9 Sample Flowcharts...............................................................................................
23.3.10 Initializing Internal Status....................................................................................
23.4 Usage Notes ......................................................................................................................
451
451
452
453
454
455
455
457
459
460
464
471
475
476
478
479
479
481
483
485
488
489
491
492
492
496
498
Section 24 A/D Converter ................................................................................................. 513
24.1 Overview...........................................................................................................................
24.1.1 Features................................................................................................................
24.1.2 Block Diagram .....................................................................................................
24.1.3 Pin Configuration.................................................................................................
513
513
514
515
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24.1.4 Register Configuration.........................................................................................
24.2 Register Descriptions ........................................................................................................
24.2.1 Software-Triggered A/D Result Register (ADR).................................................
24.2.2 Hardware-Triggered A/D Result Register (AHR) ...............................................
24.2.3 A/D Control Register (ADCR) ............................................................................
24.2.4 A/D Control/Status Register (ADCSR) ...............................................................
24.2.5 Trigger Select Register (ADTSR)........................................................................
24.2.6 Port Mode Register 0 (PMR0) .............................................................................
24.2.7 Module Stop Control Register (MSTPCR) ..........................................................
24.3 Interface to Bus Master .....................................................................................................
24.4 Operation ..........................................................................................................................
24.4.1 Software-Triggered A/D Conversion...................................................................
24.4.2 Hardware- or External-Triggered A/D Conversion .............................................
24.5 Interrupt Sources...............................................................................................................
516
517
517
517
518
521
524
524
525
526
527
527
528
529
Section 25 Address Trap Controller (ATC) ................................................................. 531
25.1 Overview...........................................................................................................................
25.1.1 Features................................................................................................................
25.1.2 Block Diagram.....................................................................................................
25.1.3 Register Configuration.........................................................................................
25.2 Register Descriptions ........................................................................................................
25.2.1 Address Trap Control Register (ATCR) ..............................................................
25.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0) ...................................................
25.3 Precautions in Usage.........................................................................................................
25.3.1 Basic Operations ..................................................................................................
25.3.2 Enabling...............................................................................................................
25.3.3 Bcc Instruction.....................................................................................................
25.3.4 BSR Instruction....................................................................................................
25.3.5 JSR Instruction.....................................................................................................
25.3.6 JMP Instruction....................................................................................................
25.3.7 RTS Instruction....................................................................................................
25.3.8 SLEEP Instruction ...............................................................................................
25.3.9 Competing Interrupt.............................................................................................
531
531
531
532
532
532
533
534
534
536
536
540
541
543
544
545
549
Section 26 Servo Circuits .................................................................................................. 553
26.1 Overview...........................................................................................................................
26.1.1 Functions..............................................................................................................
26.1.2 Block Diagram.....................................................................................................
26.2 Servo Port .........................................................................................................................
26.2.1 Overview..............................................................................................................
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553
554
556
556
26.3
26.4
26.5
26.6
26.7
26.8
26.2.2 Block Diagram .....................................................................................................
26.2.3 Pin Configuration.................................................................................................
26.2.4 Register Configuration.........................................................................................
26.2.5 Register Description.............................................................................................
26.2.6 DFG/DPG Input Signals ......................................................................................
Reference Signal Generators.............................................................................................
26.3.1 Overview..............................................................................................................
26.3.2 Block Diagram .....................................................................................................
26.3.3 Register Configuration.........................................................................................
26.3.4 Register Description.............................................................................................
26.3.5 Operation .............................................................................................................
HSW (Head-switch) Timing Generator ............................................................................
26.4.1 Overview..............................................................................................................
26.4.2 Block Diagram .....................................................................................................
26.4.3 HSW Timing Generator Configuration................................................................
26.4.4 Register Configuration.........................................................................................
26.4.5 Register Description.............................................................................................
26.4.6 Operation .............................................................................................................
26.4.7 Interrupts..............................................................................................................
26.4.8 Cautions ...............................................................................................................
High-Speed Switching Circuit for Four-Head Special Playback ......................................
26.5.1 Overview..............................................................................................................
26.5.2 Block Diagram .....................................................................................................
26.5.3 Pin Configuration.................................................................................................
26.5.4 Register Description.............................................................................................
Drum Speed Error Detector ..............................................................................................
26.6.1 Overview..............................................................................................................
26.6.2 Block Diagram .....................................................................................................
26.6.3 Register Configuration.........................................................................................
26.6.4 Register Description.............................................................................................
26.6.5 Operation .............................................................................................................
26.6.6 fH Correction in Trick Play Mode.........................................................................
Drum Phase Error Detector...............................................................................................
26.7.1 Overview..............................................................................................................
26.7.2 Block Diagram .....................................................................................................
26.7.3 Register Configuration.........................................................................................
26.7.4 Register Description.............................................................................................
26.7.5 Operation .............................................................................................................
26.7.6 Phase Comparison................................................................................................
Capstan Speed Error Detector ...........................................................................................
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560
564
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565
565
567
568
573
588
588
588
590
591
591
606
612
613
614
614
615
615
616
618
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618
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621
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628
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629
630
631
632
635
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26.9
26.10
26.11
26.12
26.13
26.8.1 Overview..............................................................................................................
26.8.2 Block Diagram.....................................................................................................
26.8.3 Register Configuration.........................................................................................
26.8.4 Register Description.............................................................................................
26.8.5 Operation .............................................................................................................
Capstan Phase Error Detector ...........................................................................................
26.9.1 Overview..............................................................................................................
26.9.2 Block Diagram.....................................................................................................
26.9.3 Register Configuration.........................................................................................
26.9.4 Register Description.............................................................................................
26.9.5 Operation .............................................................................................................
X-Value and Tracking Adjustment Circuit .......................................................................
26.10.1 Overview..............................................................................................................
26.10.2 Block Diagram.....................................................................................................
26.10.3 Register Description.............................................................................................
Digital Filters ....................................................................................................................
26.11.1 Overview..............................................................................................................
26.11.2 Block Diagram.....................................................................................................
26.11.3 Arithmetic Buffer.................................................................................................
26.11.4 Register Configuration.........................................................................................
26.11.5 Register Description.............................................................................................
26.11.6 Filter Characteristics ............................................................................................
26.11.7 Operations in Case of Transient Response...........................................................
-1
26.11.8 Initialization of Z ................................................................................................
Additional V Signal Generator .........................................................................................
26.12.1 Overview..............................................................................................................
26.12.2 Pin Configuration.................................................................................................
26.12.3 Register Configuration.........................................................................................
26.12.4 Register Description.............................................................................................
26.12.5 Additional V Pulse Signal....................................................................................
CTL Circuit.......................................................................................................................
26.13.1 Overview..............................................................................................................
26.13.2 Block Diagram.....................................................................................................
26.13.3 Pin Configuration.................................................................................................
26.13.4 Register Configuration.........................................................................................
26.13.5 Register Description.............................................................................................
26.13.6 Operation .............................................................................................................
26.13.7 CTL Input Section ...............................................................................................
26.13.8 Duty Discriminator ..............................................................................................
26.13.9 CTL Output Section.............................................................................................
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639
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647
647
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649
650
653
655
655
655
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660
661
663
664
665
673
675
675
677
677
678
678
678
680
683
683
684
685
685
686
700
703
706
712
26.13.10 Trapezoid Waveform Circuit..............................................................................
26.13.11 Note on CTL Interrupt........................................................................................
26.14 Frequency Dividers ...........................................................................................................
26.14.1 Overview ............................................................................................................
26.14.2 CTL Frequency Divider .....................................................................................
26.14.3 CFG Frequency Divider .....................................................................................
26.14.4 DFG Noise Removal Circuit ..............................................................................
26.15 Sync Signal Detector.........................................................................................................
26.15.1 Overview ............................................................................................................
26.15.2 Block Diagram ...................................................................................................
26.15.3 Pin Configuration ...............................................................................................
26.15.4 Register Configuration .......................................................................................
26.15.5 Register Description ...........................................................................................
26.15.6 Noise Detection ..................................................................................................
26.15.7 Activation of the Sync Signal Detector ..............................................................
26.16 Servo Interrupt ..................................................................................................................
26.16.1 Overview ............................................................................................................
26.16.2 Register Configuration .......................................................................................
26.16.3 Register Description ...........................................................................................
715
716
716
716
716
721
730
732
732
733
734
734
734
741
744
744
744
744
745
Section 27 Sync Separator for OSD and Data Slicer ................................................ 751
27.1 Overview...........................................................................................................................
27.1.1 Features ..............................................................................................................
27.1.2 Block Diagram ...................................................................................................
27.1.3 Pin Configuration ...............................................................................................
27.1.4 Register Configuration .......................................................................................
27.2 Register Description..........................................................................................................
27.2.1 Sync Separation Input Mode Register (SEPIMR) ..............................................
27.2.2 Sync Separation Control Register (SEPCR).......................................................
27.2.3 Sync Separation AFC Control Register (SEPACR) ...........................................
27.2.4 Horizontal Sync Signal Threshold Register (HVTHR) ......................................
27.2.5 Vertical Sync Signal Threshold Register (VVTHR) ..........................................
27.2.6 Field Detection Window Register (FWIDR) ......................................................
27.2.7 H Complement and Mask Timing Register (HCMMR) .....................................
27.2.8 Noise Detection Counter (NDETC) ...................................................................
27.2.9 Noise Detection Level Register (NDETR) .........................................................
27.2.10 Data Slicer Detection Window Register (DDETWR) ........................................
27.2.11 Internal Sync Frequency Register (INFRQR) ....................................................
27.3 Operation...........................................................................................................................
27.3.1 Selecting Source Signals for Sync Separation....................................................
751
752
752
754
754
755
755
760
763
765
769
772
774
776
777
778
780
781
781
Rev.2.00 Jan. 15, 2007 page xxxix of xliv
REJ09B0329-0200
27.3.2
27.3.3
27.3.4
27.3.5
27.3.6
27.3.7
Vsync Separation .................................................................................................
Hsync Separation .................................................................................................
Field Detection.....................................................................................................
Noise Detection....................................................................................................
Automatic Frequency Controller (AFC) ..............................................................
Module Stop Control Register (MSTPCR) ..........................................................
787
788
789
789
790
795
Section 28 Data Slicer ........................................................................................................ 797
28.1 Overview...........................................................................................................................
28.1.1 Features................................................................................................................
28.1.2 Block Diagram.....................................................................................................
28.1.3 Pin Configuration.................................................................................................
28.1.4 Register Configuration.........................................................................................
28.1.5 Data Slicer Use Conditions ..................................................................................
28.2 Register Description..........................................................................................................
28.2.1 Slice Even- (Odd-) Field Mode Register (SEVFD, SODFD) ..............................
28.2.2 Slice Line Setting Registers 1 to 4 (SLINE1 to SLINE4)....................................
28.2.3 Slice Detection Registers 1 to 4 (SDTCT1 to SDTCT4) .....................................
28.2.4 Slice Data Registers 1 to 4 (SDATA1 to SDATA4) ............................................
28.2.5 Module Stop Control Register (MSTPCR) ..........................................................
28.2.6 Monitor Output Setting Register (DOUT) ...........................................................
28.3 Operation ..........................................................................................................................
28.3.1 Slice Line Specification .......................................................................................
28.3.2 Slice Sequence .....................................................................................................
28.4 32-Bit Slice Operation ......................................................................................................
797
797
798
799
800
800
801
801
805
807
810
811
812
813
813
816
817
Section 29 On-Screen Display (OSD) ........................................................................... 821
29.1 Overview...........................................................................................................................
29.1.1 Features................................................................................................................
29.1.2 Block Diagram.....................................................................................................
29.1.3 Pin Configuration.................................................................................................
29.1.4 Register Configuration.........................................................................................
29.1.5 TV Formats and Display Modes ..........................................................................
29.2 Description of Display Functions......................................................................................
29.2.1 Superimposed Mode and Text Display Mode......................................................
29.2.2 Character Configuration.......................................................................................
29.2.3 On-Screen Display Configuration........................................................................
29.3 Settings in Character Units ...............................................................................................
29.3.1 Character Configuration.......................................................................................
29.3.2 Character Colors ..................................................................................................
Rev.2.00 Jan. 15, 2007 page xl of xliv
REJ09B0329-0200
821
821
823
824
825
826
826
826
827
828
829
829
829
29.4
29.5
29.6
29.7
29.8
29.9
29.3.3 Halftones/Cursors ................................................................................................
29.3.4 Blinking ...............................................................................................................
29.3.5 Button Display .....................................................................................................
29.3.6 Character Data ROM (OSDROM).......................................................................
29.3.7 Display Data RAM (OSDRAM)..........................................................................
Settings in Row Units .......................................................................................................
29.4.1 Button Patterns.....................................................................................................
29.4.2 Display Enlargement............................................................................................
29.4.3 Character Brightness ............................................................................................
29.4.4 Cursor Color, Brightness, Halftone Levels ..........................................................
29.4.5 Row Registers (CLINEn, n = rows 1 to 12).........................................................
Settings in Screen Units ....................................................................................................
29.5.1 Display Positions .................................................................................................
29.5.2 Turning the OSD Display On and Off .................................................................
29.5.3 Display Method....................................................................................................
29.5.4 Blinking Period ....................................................................................................
29.5.5 Borders.................................................................................................................
29.5.6 Background Color and Brightness .......................................................................
29.5.7 Character, Cursor, and Background Chroma Saturation ......................................
29.5.8 Display Position Registers (HPOS and VPOS)....................................................
29.5.9 Screen Control Register (DCNTL) ......................................................................
Other Settings....................................................................................................................
29.6.1 TV Format............................................................................................................
29.6.2 Display Data RAM Control .................................................................................
29.6.3 Timing of OSD Display Updates Using Register Rewriting................................
29.6.4 4fsc/2fsc ...............................................................................................................
29.6.5 OSDV Interrupts ..................................................................................................
29.6.6 OSD Format Register (DFORM) .........................................................................
Digital Output ...................................................................................................................
29.7.1 R, G, and B Outputs.............................................................................................
29.7.2 YCO and YBO Outputs .......................................................................................
29.7.3 Digital Output Specification Register (DOUT) ...................................................
29.7.4 Module Stop Control Register (MTSTPCR)........................................................
Notes on OSD Font Creation ............................................................................................
29.8.1 Note 1 on Font Creation (Font Width) .................................................................
29.8.2 Note 2 on Font Creation (Borders).......................................................................
29.8.3 Note 3 on Font Creation (Blinking) .....................................................................
29.8.4 Note 4 on Font Creation (Buttons).......................................................................
OSD Oscillator, AFC, and Dot Clock ...............................................................................
29.9.1 Sync Signals.........................................................................................................
830
831
832
833
835
840
840
840
840
840
842
847
847
848
848
848
849
849
849
850
851
857
857
857
857
858
858
858
862
862
865
866
868
870
870
870
872
873
874
874
Rev.2.00 Jan. 15, 2007 page xli of xliv
REJ09B0329-0200
29.9.2 AFC Circuit..........................................................................................................
29.9.3 Dot Clock.............................................................................................................
29.9.4 4/2fsc....................................................................................................................
29.10 OSD Operation in CPU Operation Modes ........................................................................
29.11 Character Data ROM (OSDROM) Access by CPU..........................................................
29.11.1 Serial Timer Control Register (STCR) ................................................................
874
874
875
877
878
878
Section 30 Power Supply Circuit .................................................................................... 879
30.1 Overview........................................................................................................................... 879
30.2 Power Supply Connection (Internal Power Supply Step-Down Circuit On-Chip) ........... 879
Section 31 Electrical Characteristics ............................................................................. 881
31.1 Absolute Maximum Ratings .............................................................................................
31.2 Electrical Characteristics of HD6432199R, HD6432198R, HD6432197R, and
HD6432196R ....................................................................................................................
31.2.1 DC Characteristics of HD6432199R, HD6432198R, HD6432197R, and
HD6432196R .......................................................................................................
31.2.2 Allowable Output Currents of HD6432199R, HD6432198R, HD6432197R,
and HD6432196R ................................................................................................
31.2.3 AC Characteristics of HD6432199R, HD6432198R, HD6432197R, and
HD6432196R .......................................................................................................
31.2.4 Serial Interface Timing of HD6432199R, HD6432198R, HD6432197R, and
HD6432196R .......................................................................................................
31.2.5 A/D Converter Characteristics of HD6432199R, HD6432198R, HD6432197R,
and HD6432196R ................................................................................................
31.2.6 Servo Section Electrical Characteristics of HD6432199R, HD6432198R,
HD6432197R, and HD6432196R ........................................................................
31.2.7 OSD Electrical Characteristics of HD6432199R, HD6432198R, HD6432197R,
and HD6432196R ................................................................................................
31.3 Electrical Characteristics of HD6432197S and HD6432196S..........................................
31.3.1 DC Characteristics of HD6432197S and HD6432196S ⎯ Preliminary ⎯.........
31.3.2 Allowable Output Currents of HD6432197S and HD6432196S .........................
31.3.3 AC Characteristics of HD6432197S and HD6432196S.......................................
31.3.4 Serial Interface Timing of HD6432197S and HD6432196S................................
31.3.5 A/D Converter Characteristics of HD6432197S and HD6432196S ....................
31.3.6 Servo Section Electrical Characteristics of HD6432197S and HD6432196S......
31.3.7 OSD Electrical Characteristics of HD6432197S and HD6432196S....................
31.4 Electrical Characteristics of HD64F2199R.......................................................................
31.4.1 DC Characteristics of HD64F2199R ...................................................................
31.4.2 Allowable Output Currents of HD64F2199R ......................................................
Rev.2.00 Jan. 15, 2007 page xlii of xliv
REJ09B0329-0200
881
882
882
889
890
893
897
898
901
905
905
911
912
915
919
920
923
927
927
934
31.4.3
31.4.4
31.4.5
31.4.6
31.4.7
31.4.8
AC Characteristics of HD64F2199R ...................................................................
Serial Interface Timing of HD64F2199R.............................................................
A/D Converter Characteristics of HD64F2199R .................................................
Servo Section Electrical Characteristics of HD64F2199R...................................
OSD Electrical Characteristics of HD64F2199R.................................................
Flash Memory Characteristics .............................................................................
935
938
942
943
946
950
Appendix A Instruction Set .............................................................................................. 953
A.1
A.2
A.3
A.4
A.5
A.6
Instructions........................................................................................................................ 953
Instruction Codes .............................................................................................................. 964
Operation Code Map......................................................................................................... 974
Number of Execution States.............................................................................................. 978
Bus Status during Instruction Execution ........................................................................... 988
Change of Condition Codes ............................................................................................ 1002
Appendix B Internal I/O Registers ............................................................................... 1007
B.1
B.2
Addresses ........................................................................................................................ 1007
Function List ................................................................................................................... 1017
Appendix C Pin Circuit Diagrams ................................................................................ 1148
C.1
Pin Circuit Diagrams....................................................................................................... 1148
Appendix D Port States in Each Processing State.................................................... 1162
D.1
Pin Circuit Diagrams....................................................................................................... 1162
Appendix E Usage Notes................................................................................................. 1163
E.1
E.2
E.3
Power Supply Rise and Fall Order.................................................................................. 1163
Sample External Circuits................................................................................................. 1166
Handling of Pins When OSD Is Not Used ...................................................................... 1171
Appendix F Product Lineup ........................................................................................... 1172
Appendix G Package Dimensions ................................................................................ 1173
Rev.2.00 Jan. 15, 2007 page xliii of xliv
REJ09B0329-0200
Rev.2.00 Jan. 15, 2007 page xliv of xliv
REJ09B0329-0200
Section 1 Overview
Section 1 Overview
1.1
Overview
The H8S/2199R Group comprises microcomputers (MCUs) built around the H8S/2000 CPU,
adopting Renesas Technology proprietary architecture, and equipped with on-chip supporting
modules.
The H8S/2000 has an internal 32-bit architecture, is provided with sixteen 16-bit general registers
and a concise, optimized instruction set designed for high-speed operation, and can address a 16Mbyte linear address space.
The H8S/2199R Group is equipped with a digital servo circuit, sync separator, OSD, data slicer,
ROM, RAM, seven types of timers, three types of PWM, two types of serial communication
2
interface, an I C bus interface, A/D converter, and I/O port as on-chip supporting modules.
The on-chip ROM is either flash memory (F-ZTAT™*) or mask ROM, with a capacity of 256,
128, 112, 96, or 80 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte
and word data to be accessed in one state. Instruction fetching has been speeded up, and
processing speed increased.
Using the H8S/2199R Group can implement a system suitable for VTR control. This manual
describes the H8S/2199R Group hardware. For details on instructions, see the H8S/2600 and
H8S/2000 Series Software Manual.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Rev.2.00 Jan. 15, 2007 page 1 of 1174
REJ09B0329-0200
Section 1 Overview
Table 1.1
Features of the H8S/2199R Group
Item
Specifications
CPU
•
General-register architecture
⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
•
High-speed operation suitable for real-time control
⎯ Maximum operating frequency: 10 MHz/4 V to 5.5 V
⎯ High-speed arithmetic operations
8/16/32-bit register-register add/subtract: 100 ns (10-MHz operation)
16 × 16-bit register-register multiply: 2000 ns (10-MHz operation)
32 ÷ 16-bit register-register divide: 2000 ns (10-MHz operation)
•
Instruction set suitable for high-speed operation
⎯ Sixty-five basic instructions
⎯ 8/16/32-bit transfer/arithmetic and logic instructions
⎯ Unsigned/signed multiply and divide instructions
⎯ Powerful bit-manipulation instructions
•
CPU operating modes
⎯ Advanced mode: 16-Mbyte address space
Timer
•
Seven types of timer are incorporated
⎯ Timer A
•
8-bit interval timer
•
Clock source can be selected among 8 types of internal clock of
which frequencies are divided from the system clock (φ) and
subclock (φSUB)
•
Functions as clock time base by subclock input
⎯ Timer B
•
Functions as 8-bit interval timer or reload timer
•
Clock source can be selected among 7 types of internal clock or
external event input
⎯ Timer J
•
Functions as two 8-bit down counters or one 16-bit down counter
(reload timer/event counter timer/timer output, etc., 5 types of
operation modes)
•
Remote controlled transmit function
•
Take up/Supply Reel Pulse Frequency division
Rev.2.00 Jan. 15, 2007 page 2 of 1174
REJ09B0329-0200
Section 1 Overview
Item
Specifications
⎯ Timer L
Timer
•
8-bit up/down counter
•
Clock source can be selected among 2 types of internal clock, CFG
frequency division signal, and PB and REC-CTL (control pulse)
•
Compare-match clearing function/auto reload function
⎯ Timer R
•
Three reload timers
•
Mode discrimination
•
Reel control
•
Capstan motor acceleration/deceleration detection function
•
Slow tracking mono-multi
⎯ Timer X1 (except for the H8S/2197S and H8S/2196S)
•
16-bit free-running counter
•
Clock source can be selected among 3 types of internal clock and
DVCFG
•
Two output compare outputs
•
Four input capture inputs
⎯ Watchdog timer
•
Functions as watchdog timer or 8-bit interval timer
•
Generates reset signal or NMI at overflow
⎯ Divides system clock frequency and generates frequency division clock
for supporting module functions
Prescaler unit
⎯ Divides subclock frequency and generates input clock for Timer A
(clock time base)
⎯ Generates 8-bit PWM frequency and duty period
⎯ 8-bit input capture at external signal edge
⎯ Frequency division clock output enabled
PWM
•
Three types of PWM are incorporated
⎯ 14-bit PWM: Pulse resolution type × 1 channel (except for the
H8S/2197S and H8S/2196S)
⎯ 8-bit PWM: Duty control type × 4 channels (H8S/2197S and
H8S/2196S : 2 channel)
⎯ 12-bit PWM: Pulse pitch control type × 2 channels
Rev.2.00 Jan. 15, 2007 page 3 of 1174
REJ09B0329-0200
Section 1 Overview
Item
Specifications
⎯ Asynchronous mode or synchronous mode selectable
Serial
communication
interface (SCI)
⎯ Desired bit rate selectable with built-in baud rate generator
⎯ Multiprocessor communication function
⎯ Conforms to Phillips I C bus interface standard
2
2
I C bus interface
(2 channels)
(H8S/2197S and
H8S/2196S :
1 channel)
⎯ Start and stop conditions generated automatically
⎯ Selection of acknowledge output levels when receiving, and automatic
loading of acknowledge bit when transmitting
⎯ Selection of acknowledgement mode or serial mode (without
acknowledge bit)
⎯ Resolution: 10 bits
A/D converter
⎯ Input: 12 channels
⎯ High-speed conversion: 13.4 μs minimum conversion time (10-MHz
operation)
⎯ Sample-and-hold function
⎯ A/D conversion can be activated by software or external trigger
Address trap
controller
⎯ Interrupt occurs when the preset address is found during bus cycle
I/O port
⎯ 56 input/output pins
⎯ To-be-trapped addresses can be individually set at three different
locations
⎯ 8 input-only pins
⎯ Can be switched for each supporting module
Servo circuit
•
Digital servo circuits on-chip
⎯ Input and output circuits
⎯ Error detection circuit
⎯ Phase and gain compensation
Sync signal
(servo)
•
On-chip sync signal detection circuit
⎯ Can separately detect horizontal and vertical sync signals
⎯ Noise detection function
Sync separator for •
OSD and data
slicer
Sync separator including AFC
⎯ Horizontal and vertical sync signals separated from the composite
video signal
⎯ Noise detection
⎯ Selection of sync separation methods
Rev.2.00 Jan. 15, 2007 page 4 of 1174
REJ09B0329-0200
Section 1 Overview
Item
OSD (On Screen
Display)
Specifications
⎯ Screen of 32 characters × 12 lines
⎯ 384 types of characters (H8S/2199R F-ZTAT: 512 types of characters
H8S/2197S and H8S/2196S: 256 types of characters)
⎯ Character configuration: 12 dots × 18 lines
⎯ Character colors:
Eight hues
⎯ Background colors: Eight hues
⎯ Cursor colors:
Eight hues
⎯ Halftone display
⎯ Button display
Data slicer
⎯ Slice lines: Four lines (H8S/2197S and H8S/2196S: two lines)
⎯ Slice levels: Seven levels
⎯ Sampling clock generated by AFC
⎯ Slice interrupt
⎯ Error detection
Memory
⎯ Flash memory or mask ROM (Refer to the product line-up)
⎯ High-speed static RAM
Power-down state
Product Name
ROM
RAM
H8S/2199R
128 k (256 k*) bytes
4 k (8 k*) bytes
H8S/2198R
112 k bytes
4 k bytes
H8S/2197R
96 k bytes
4 k bytes
H8S/2196R
80 k bytes
H8S/2197S
96 k bytes
H8S/2196S
80 k bytes
3 k bytes
⎯ Medium-speed mode
⎯ Sleep mode
⎯ Module stop mode
⎯ Standby mode
⎯ Subclock operation
Subactive mode, watch mode, subsleep mode
Interrupt controller
⎯ Six external interrupt pins (IRQ5 to IRQ0)
⎯ 44 internal interrupt sources (H8S/2197S and H8S/2196S : 35 internal
interrupt sources)
⎯ Three priority levels settable
Rev.2.00 Jan. 15, 2007 page 5 of 1174
REJ09B0329-0200
Section 1 Overview
Item
Specifications
Clock pulse
generator
•
Two types of clock pulse generator on-chip
⎯ System clock pulse generator: 8 to 10 MHz
⎯ Subclock pulse generator: 32.768 kHz
Packages
⎯ 112-pin plastic QFP (PRQP0112JA-A)
Product lineup
Part No.
Group
Mask ROM
Versions
H8S/2199R HD6432199R
F-ZTAT
Versions
ROM/RAM
(bytes)
Packages
HD64F2199R 128 k/4 k
(256 k*/
8 k*)
PRQP0112JA-A
HD6432198R
⎯
112 k/4 k
PRQP0112JA-A
HD6432197R
⎯
96 k/4 k
PRQP0112JA-A
HD6432196R
⎯
80 k/4 k
PRQP0112JA-A
HD6432197S
⎯
96 k/3 k
PRQP0112JA-A
HD6432196S
⎯
80 k/3 k
PRQP0112JA-A
Note: * F-ZTAT version
Rev.2.00 Jan. 15, 2007 page 6 of 1174
REJ09B0329-0200
Section 1 Overview
1.2
Internal Block Diagram
Port 3
Port 4
Port 6
Port 7
External address bus
External data bus
VCC
VSS
VCL
VSS
VSS
VCC
MD0
RES
X1
X2
OSC1
OSC2
External data bus
Subclock pulse
generator
Subclock pulse
pulse generator
External address bus
P77/PPG7/RPB
P76/PPG6/RPA
P75/PPG5/RP9
P74/PPG4/RP8
P73/PPG3
P72/PPG2
P71/PPG1
P70/PPG0
Bus
controller
Port 1
RAM
Interrupt
controller
Address trap
controller
14-bit PWM
12-bit PWM
8-bit PWM
Prescaler unit
Watchdog
timer
Timer A
Timer L
Timer B
SCI1
I2C bus
interface
Timer J
Timer R
A/D converter
Timer X1
Servo circuit
Data slicer
Port 8
AFC
4fscin/2fscin
4fscout/2fscout
AFC pc
AFC osc
AFC LPF
VLPF/Vsync
Sync
separation
Csync/Hsync
OSD
(Analog input/output)
OVCC
OVSS
DPG
DFG
CFG
DRMPWM
CAPPWM
CTL(+)
CTL(–)
CTLBias
CTLAmp(o)
CTLSMT(i)
AUDIO FF
VIDEO FF
Vpulse
CTL FB
CTL REF
Servo pins (CTL input/output
amplifier, three-level output, etc.)
Sub-carrier
oscillator
Sync signal
detection
SVCC
SVSS
OSD
Hsync(Csync)
AVCC
AVSS
P87/DPG
P86/EXTTRG
P85/COMP/B
P84/H.Amp SW/G
P83/C.Rotary/R
P82/EXCTL
P81/EXCAP/YBO
P80/YCO
P67/RP7/TMBI
P66/RP6/ADTRG
P65/RP5
P64/RP4
P63/RP3
P62/RP2
P61/RP1
P60/RP0
Internal address bus
CVin2
AN8
AN9
ANA
ANB
P47/RPTRG
P46/FTOB
P45/FTOA
P44/FTID
P43/FTIC
P42/FTIB
P41/FTIA
P40/PWM14
Internal data bus
CVin1
CVout
P07/AN7
P06/AN6
P05/AN5
P04/AN4
P03/AN3
P02/AN2
P01/AN1
P00/AN0
P37/TMO
P36/BUZZ
P35/PWM3
P34/PWM2
P33/PWM1
P32/PWM0
P31/SV2
P30/SV1
ROM
Port 0
P17/TMOW
P16/IC
P15/IRQ5
P14/IRQ4
P13/IRQ3
P12/IRQ2
P11/IRQ1
P10/IRQ0
H8S/2000 CPU
Analog
port
P27/SYNCI
P26/SCL0
P25/SDA0
P24/SCL1
P23/SDA1
P22/SCK1
P21/SO1
P20/SI1
Port 2
Figure 1.1 shows an internal block diagram of the H8S/2199R Group.
Figure 1.1 Internal Block Diagram of H8S/2199R Group (except for the H8S/2197S and
H8S/2196S)
Rev.2.00 Jan. 15, 2007 page 7 of 1174
REJ09B0329-0200
Section 1 Overview
Port 3
Port 4
Port 6
Port 7
External address bus
External data bus
VCC
VSS
VCL
VSS
VSS
VCC
MD0
RES
X1
X2
OSC1
OSC2
External data bus
Subclock pulse
generator
Subclock pulse
pulse generator
External address bus
P77/PPG7/RPB
P76/PPG6/RPA
P75/PPG5/RP9
P74/PPG4/RP8
P73/PPG3
P72/PPG2
P71/PPG1
P70/PPG0
Bus
controller
Port 1
RAM
Interrupt
controller
Address trap
controller
12-bit PWM
8-bit PWM
Prescaler unit
Watchdog
timer
Timer A
Timer L
Timer B
SCI1
I2C bus
interface
Timer J
Timer R
A/D converter
Data slicer
Servo circuit
OSD
Port 8
4fscin/2fscin
4fscout/2fscout
AFC pc
AFC osc
AFC LPF
VLPF/Vsync
Sync
separation
CVin2
OSD
(Analog input/output)
Csync/Hsync
DPG
DFG
CFG
DRMPWM
CAPPWM
CTL(+)
CTL(–)
CTLBias
CTLAmp(o)
CTLSMT(i)
AUDIO FF
VIDEO FF
Vpulse
CTL FB
CTL REF
Servo pins (CTL input/output
amplifier, three-level output, etc.)
AFC
Sync signal
detection
SVCC
SVSS
Sub-carrier
oscillator
Hsync(Csync)
AVCC
AVSS
P87/DPG
P86/EXTTRG
P85/COMP/B
P84/H.Amp SW/G
P83/C.Rotary/R
P82/EXCTL
P81/EXCAP/YBO
P80/YCO
P67/RP7/TMBI
P66/RP6/ADTRG
P65/RP5
P64/RP4
P63/RP3
P62/RP2
P61/RP1
P60/RP0
Internal address bus
CVin1
CVout
AN8
AN9
ANA
ANB
P47/RPTRG
P46
P45
P44
P43
P42
P41
P40
Internal data bus
OVCC
OVSS
P07/AN7
P06/AN6
P05/AN5
P04/AN4
P03/AN3
P02/AN2
P01/AN1
P00/AN0
P37/TMO
P36/BUZZ
P35
P34
P33/PWM1
P32/PWM0
P31/SV2
P30/SV1
ROM
Port 0
P17/TMOW
P16/IC
P15/IRQ5
P14/IRQ4
P13/IRQ3
P12/IRQ2
P11/IRQ1
P10/IRQ0
H8S/2000 CPU
Analog
port
P27
P26
P25
P24/SCL1
P23/SDA1
P22/SCK1
P21/SO1
P20/SI1
Port 2
Figure 1.2 shows an internal block diagram of the H8S/2197S and H8S/2196S.
Figure 1.2 Internal Block Diagram of the H8S/2197S and H8S/2196S
Rev.2.00 Jan. 15, 2007 page 8 of 1174
REJ09B0329-0200
Section 1 Overview
1.3
Pin Arrangement and Functions
1.3.1
Pin Arrangement
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
P33/PWM1
P34/PWM2
MD0
VCL
OSC2
VSS
OSC1
RES
X1
X2
FWE
P40/PWM14
P41/FTIA
P42/FTIB
P43/FTIC
P44/FTID
P45/FTOA
P46/FTOB
P47/RPTRG
P20/SI1
P21/SO1
P22/SCK1
P23/SDA1
P24/SCL1
P25/SDA0
P26/SCL0
P27/SYNCI
VSS
Figure 1.3 shows the pin arrangement of the H8S/2199R Group.
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PRQP0112JA-A
(Top view)
VCC
P35/PWM3
P36/BUZZ
P37/TMO
P60/RP0
P61/RP1
P62/RP2
P63/RP3
P64/RP4
P65/RP5
P66/RP6/ADTRG
P67/RP7/TMBI
P17/TMOW
P16/IC
P15/IRQ5
P14/IRQ4
P13/IRQ3
P12/IRQ2
P11/IRQ1
P10/IRQ0
AVCC
P00/AN0
P01/AN1
P02/AN2
P03/AN3
P04/AN4
P05/AN5
P06/AN6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
SVSS
CTLREF
CTL(+)
CTL(–)
CTLBias
CTLFB
CTLAmp(o)
CTLSMT(i)
CFG
SVCC
AFCpc
AFCosc
AFCLPF
Csync/Hsync
VLPF/Vsync
CVin2
CVin1
OVCC
CVout
OVSS
4fscout/2fscout
4fscin/2fscin
AVSS
ANB
ANA
AN9
AN8
P07/AN7
P32/PWM0
P31/SV2
P30/SV1
P70/PPG0
P71/PPG1
P72/PPG2
P73/PPG3
P74/PPG4/RP8
P75/PPG5/RP9
P76/PPG6/RPA
P77/PPG7/RPB
P80/YCO
P81/EXCAP/YBO
P82/EXCTL
P83/C.Rotary/R
P84/H.Amp SW/G
P85/COMP/B
P86/EXTTRG
P87/DPG
DFG
VIDEO FF
AUDIO FF
DRM PWM
CAP PWM
Vpulse
VSS
Csync
VCC
Figure 1.3 Pin Arrangement of H8S/2199R Group (except for the H8S/2197S and
H8S/2196S)
Rev.2.00 Jan. 15, 2007 page 9 of 1174
REJ09B0329-0200
Section 1 Overview
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
P33/PWM1
P34
MD0
VCL
OSC2
VSS
OSC1
RES
X1
X2
NC
P40
P41
P42
P43
P44
P45
P46
P47/RPTRG
P20/SI1
P21/SO1
P22/SCK1
P23/SDA1
P24/SCL1
P25
P26
P27
VSS
Figure 1.4 shows the pin arrangement of the H8S/2197S and H8S/2196S.
PRQP0112JA-A
(Top view)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
SVSS
CTLREF
CTL(+)
CTL(–)
CTLBias
CTLFB
CTLAmp(o)
CTLSMT(i)
CFG
SVCC
AFCpc
AFCosc
AFCLPF
Csync/Hsync
VLPF/Vsync
CVin2
CVin1
OVCC
CVout
OVSS
4fscout/2fscout
4fscin/2fscin
AVSS
ANB
ANA
AN9
AN8
P07/AN7
P32/PWM0
P31/SV2
P30/SV1
P70/PPG0
P71/PPG1
P72/PPG2
P73/PPG3
P74/PPG4/RP8
P75/PPG5/RP9
P76/PPG6/RPA
P77/PPG7/RPB
P80/YCO
P81/EXCAP/YBO
P82/EXCTL
P83/C.Rotary/R
P84/H.Amp SW/G
P85/COMP/B
P86/EXTTRG
P87/DPG
DFG
VIDEO FF
AUDIO FF
DRM PWM
CAP PWM
Vpulse
VSS
Csync
VCC
Figure 1.4 Pin Arrangement of H8S/2197S and H8S/2196S
Rev.2.00 Jan. 15, 2007 page 10 of 1174
REJ09B0329-0200
VCC
P35
P36/BUZZ
P37/TMO
P60/RP0
P61/RP1
P62/RP2
P63/RP3
P64/RP4
P65/RP5
P66/RP6/ADTRG
P67/RP7/TMBI
P17/TMOW
P16/IC
P15/IRQ5
P14/IRQ4
P13/IRQ3
P12/IRQ2
P11/IRQ1
P10/IRQ0
AVCC
P00/AN0
P01/AN1
P02/AN2
P03/AN3
P04/AN4
P05/AN5
P06/AN6
Section 1 Overview
1.3.2
Pin Functions
Table 1.2 summarizes the functions of the H8S/2199R Group pins.
Table 1.2
Pin Functions
Type
Symbol
Pin No.
I/O
Name and Function
Power
supply
VCC
56, 112
Input
Power supply:
All Vcc pins should be connected to the system
power supply (+5 V)
VSS
57, 79,
110
Input
Ground:
All Vss pins should be connected to the system
power supply (0 V)
SVCC
10
Input
Servo power supply:
SVcc pin should be connected to the servo
analog power supply (+5 V)
SVSS
1
Input
Servo ground:
SVss pin should be connected to the servo
analog power supply (0 V)
AVCC
36
Input
Analog power supply:
Power supply pin for A/D converter. It should be
connected to the system power supply (+5 V)
when the A/D converter is not used
AVSS
23
Input
Analog ground:
Ground pin for A/D converter. It should be
connected to the system power supply (0 V)
OVCC
18
Input
OSD power supply:
OVCC should be connected to the OSD analog
power supply (+5 V)
OVSS
20
Input
OSD ground:
OVSS should be connected to the OSD analog
power supply (0 V)
VCL
81
Input
Smoothing capacitor connection:
Connect 0.1-µF power-smoothing capacitance
between VCL and VSS
OSC1
78
Input
OSC2
80
Output
Connected to a crystal oscillator. It can also input
an external clock. See section 9, Clock Pulse
Generator, for typical connection diagrams for a
crystal oscillator and external clock input
X1
76
Input
X2
75
Output
Clock
Connected to a 32.768 kHz crystal oscillator. See
section 9, Clock Pulse Generator, for typical
connection diagrams
Rev.2.00 Jan. 15, 2007 page 11 of 1174
REJ09B0329-0200
Section 1 Overview
Type
Symbol
Pin No.
I/O
Name and Function
Operating
mode
control
MD0
82
Input
Mode pin:
This pin sets the operating mode. This pin
should not be changed while the MCU is in
operation
System
control
RES
77
Input
Reset input:
When this pin is driven low, the chip is reset
FWE
74
Input
Flash memory enable:
Enables/disables flash memory programming.
This pin is available only with MCU with flash
memory on-chip.
IRQ0
37
Input
External interrupt request 0:
External interrupt input pin for which rising edge
sense, falling edge sense or both edges sense
are selectable
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
38
39
40
41
42
Input
External interrupt requests 1 to 5:
External interrupt input pins for which rising or
falling edge sense are selectable
IC
43
Input
Input capture input:
Input capture input pin for prescaler unit
TMOW
44
Output
Frequency division clock output:
Output pin for clock of which frequency is
divided by prescaler
TMBI
45
Input
Timer B event input:
Input pin for events to be input to Timer B
counter
IRQ1
IRQ2
38
39
Input
Timer J event input:
Input pin for events to be input to Timer J RDT1or RDT-2 counter
TMO
53
Output
Timer J timer output:
Output pin for toggle at underflow of RDT-1 of
Timer J, or remote controlled transmit data
BUZZ
54
Output
Timer J buzzer output:
Output pin for toggle which is selectable among
fixed frequency, 1 Hz frequency divided from
subclock (32 kHz), and frequency division CTL
signal
Interrupts
Prescaler
unit
Timers
Rev.2.00 Jan. 15, 2007 page 12 of 1174
REJ09B0329-0200
Section 1 Overview
Type
Symbol
Pin No.
I/O
Name and Function
Timers
IRQ3
40
Input
Timer R input capture:
Input pin for input capture of Timer R TMRU-1 or
TMRU-2
FTOA*
FTOB*
68
67
Output
Timer X1 output compare A and B output:
Output pin for output compare A and B of Timer
X1
FTIA*
FTIB*
FTIC*
FTID*
72
71
70
69
Input
Timer X1 input capture A, B, C and D input:
Input pin for input capture A, B, C and D of
Timer X1
PWM0
PWM1
PWM2*
PWM3*
85
84
83
55
Output
8-bit PWM square waveform output:
Output pin for waveform generated by 8-bit
PWM 0, 1, 2 and 3
PWM14*
73
Output
14-bit PWM square waveform output:
Output pin for waveform generated by 14-bit
PWM
SCK1
63
Input
/output
SCI clock input/output:
Clock input pins for SCI 1
SI1
65
Input
SCI receive data input:
Receive data input pins for SCI 1
SO1
64
Output
SCI transmit data output:
Transmit data output pins for SCI 1
SCL0*
SCL1
59
61
Input
/output
I C bus interface clock input/output:
2
Clock input/output pin for I C bus interface
SDA0*
SDA1
60
62
Input
/output
I C bus interface data input/output:
2
Data input/output pin for I C bus interface
SYNCI*
58
Input
I C bus interface clock input:
2
I C formatless serial clock input
PWM
Serial
communication
interface
(SCI)
2
I C bus
interface
2
2
2
Rev.2.00 Jan. 15, 2007 page 13 of 1174
REJ09B0329-0200
Section 1 Overview
Type
Symbol
A/D
converter
Servo
circuits
Pin No.
I/O
Name and Function
AN7 to AN0 28 to 35
Input
Analog input channels 7 to 0:
Analog data input pins. A/D conversion is started
by a software triggering
AN8
AN9
ANA
ANB
27
26
25
24
Input
Analog input channels 8, 9, A and B:
Analog data input pins. A/D conversion is started
by an external trigger, a hardware trigger, or
software
ADTRG
46
Input
A/D conversion external trigger input:
A/D conversion for analog data input pins 8, 9,
A, and B is started by an external trigger
AUDIO FF
106
Output
Audio FF:
Output pin for audio head switching signal
VIDEO FF
105
Output
Video FF:
Output pin for video head switching signal
CAPPWM
108
Output
Capstan mix:
12-bit PWM output pin giving result of capstan
speed error and phase error after filtering
DRMPWM
107
Output
Drum mix:
12-bit PWM output pin giving result of drum
speed error and phase error after filtering
Vpulse
109
Output
Additional V pulse:
Three-level output pin for additional V signal
synchronized to the VIDEO FF signal
C.Rotary
99
Output
Color rotary signal:
Output pin for color signal processing control
signal in four-head special-effects playback
H.AmpSW
100
Output
Head-amp switch:
Output pin for preamplifier output select signal in
four-head special-effects playback.
COMP
101
Input
Compare input:
Input pin for signal giving the result of
preamplifier output comparison in four-head
special-effects playback.
CTL (+)
CTL (-)
3
4
Input
/output
CTL head (+) and (-) pins:
I/O pins for CTL signals
CTL Bias
5
Input
CTL primary amp bias supply:
Bias supply pin for CTL primary amp
Rev.2.00 Jan. 15, 2007 page 14 of 1174
REJ09B0329-0200
Section 1 Overview
Type
Symbol
Pin No.
I/O
Name and Function
Servo
circuits
CTL Amp
(o)
7
Output
CTL amp output:
Output pin for CTL amp
CTL SMT (i) 8
Input
CTL Schmitt amp input:
Input pin for CTL Schmitt amp
CTLFB
6
Input
CLT feedback input:
Input pin for CTL amp high-range characteristics
control
CTLREF
2
Output
CTL amp reference voltage output:
Output pin for 1/2 Vcc (SV)
CFG
9
Input
Capstan FG input:
Schmitt comparator input pin for CFG signal
DFG
104
Input
Drum FG input:
Schmitt input pin for DFG signal
DPG
103
Input
Drum PG input:
Schmitt input pin for DPG signal
EXCTL
98
Input
External CTL input:
Input pin for external CTL signal
Csync
111
Input
Mixed sync signal input:
Input pin for mixed sync signal
EXCAP
97
Input
Capstan external sync signal input:
Signal input pin for external synchronization of
capstan phase control
EXTTRG
102
Input
External trigger signal input:
Signal input pin for synchronization with
reference signal generator
SV1
87
Output
Servo monitor output pin 1:
Output pin for servo module internal signal
SV2
86
Output
Servo monitor output pin 2:
Output pin for servo module internal signal
PPG7 to
PPG0
95 to 88
Output
PPG:
Output pin for HSW timing generator. To be
used when head switching is required as well as
AUDIO FF and VIDEO FF
Rev.2.00 Jan. 15, 2007 page 15 of 1174
REJ09B0329-0200
Section 1 Overview
Type
Symbol
Pin No.
I/O
Name and Function
Sync
separator
Csync/
Hsync
14
Input/
output
Sync signal input/output:
Composite sync signal input/output or horizontal
sync signal input
VLPF/
Vsync
15
Input
Sync signal input:
Pin for connecting external LPF for vertical sync
signal or input pin for vertical sync signal
AFC pc
11
Input/
output
AFC oscillation:
Pin for connecting external circuit for AFC
oscillation
AFC osc
12
Input/
output
AFC oscillation:
Pin for connecting external circuit for AFC
oscillation
AFC LPF
13
Input/
output
Pin for connecting external LPF for AFC
4 fsc in/
2 fsc in
22
Input
fsc oscillation:
Input pin for subcarrier oscillator. 4fsc or 2fsc can
be selected
fsc: Subcarrier frequency
4 fsc out/
2 fsc out
21
Output
fsc oscillation:
Output pin for subcarrier oscillator. 4fsc or 2fsc
can be selected
fsc: Subcarrier frequency
CVin2
16
Input
Composite video input:
Composite video signal input. Input 2-Vp-p
composite video signal, and the sync tip of the
signal is clamped to about 2.0 V
CVin1
17
Input
Composite video input:
Composite video signal input for OSD. Input 2Vp-p composite video signal, and the sync tip of
the signal is clamped to about 1.4 V
CVout
19
Output
Composite video output:
Composite video signal output for OSD. 2-Vp-p
composite video signal is output
R
99
Output
OSD digital output:
Color signal R output
G
100
Output
OSD digital output:
Color signal G output
B
101
Output
OSD digital output:
Color signal B output
OSD
Rev.2.00 Jan. 15, 2007 page 16 of 1174
REJ09B0329-0200
Section 1 Overview
Type
Symbol
Pin No.
I/O
Name and Function
OSD
YCO
96
Output
OSD digital output:
Character data output
YBO
97
Output
OSD digital output:
Character display position output
Data slicer CVin2
16
Input
Composite video input:
Composite video signal input. Input 2-Vp-p
composite video signal, and the sync tip of the
signal is clamped to about 2.0 V.
I/O port
P07 to P00
28 to 35
Input
Port 0:
8-bit input pins
P17 to P10
44 to 37
Input
/output
Port 1:
8-bit I/O pins
P27 to P20
58 to 65
Input
/output
Port 2:
8-bit I/O pins
P37 to P30
53 to 55
83 to 87
Input
/output
Port 3:
8-bit I/O pins
P47 to P40
66 to 73
Input
/output
Port 4:
8-bit I/O pins
P67 to P60
45 to 52
Input
/output
Port 6:
8-bit I/O pins
P77 to P70
95 to 88
Input
/output
Port 7:
8-bit I/O pins
P87 to P80
103 to 96 Input
/output
Port 8:
8-bit I/O pins
RP7 to RP0
45 to 52
Output
Realtime output port:
8-bit realtime output pins
RPB to RP8
95 to 92
Output
Realtime output port:
4-bit realtime output pins
RPTRG
66
Input
Realtime output port trigger input:
Input pin for realtime output port trigger
Note:
*
Not available in the H8S/2197S or H8S/2196S.
Rev.2.00 Jan. 15, 2007 page 17 of 1174
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Section 1 Overview
Rev.2.00 Jan. 15, 2007 page 18 of 1174
REJ09B0329-0200
Section 2 CPU
Section 2 CPU
2.1
Overview
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is
ideal for realtime control.
2.1.1
Features
The H8S/2000 CPU has the following features.
• Upward-compatible with H8/300 and H8/300H CPUs
Can execute H8/300 and H8/300H object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• Sixty-five basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 16-Mbyte address space
Program: 16 Mbytes
Data:
16 Mbytes (4 Gbytes architecturally)
Rev.2.00 Jan. 15, 2007 page 19 of 1174
REJ09B0329-0200
Section 2 CPU
• High-speed operation
All frequently-used instructions execute in one or two states
Maximum clock rate:
10 MHz
8/16/32-bit register-register add/subtract: 100 ns
8 × 8-bit register-register multiply:
1200 ns
16 ÷ 8-bit register-register divide:
1200 ns
16 × 16-bit register-register multiply:
2000 ns
32 ÷ 16-bit register-register divide:
2000 ns
• Two CPU operating modes
Normal mode*/Advanced mode
Note: * Normal mode is not available for this LSI.
• Power-down state
Transition to power-down state by SLEEP instruction
CPU clock speed selection
2.1.2
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions differ as follows.
Number of Execution States
Instruction
Mnemonic
H8S/2600
H8S/2000
MULXU
MULXU.B Rs, Rd
3
12
MULXU.W Rs, Erd
4
20
MULXS.B Rs, Rd
4
13
MULXS.W Rs, Erd
5
21
MULXS
There are also differences in the address space, EXR register functions, power-down state, etc.,
depending on the product.
Rev.2.00 Jan. 15, 2007 page 20 of 1174
REJ09B0329-0200
Section 2 CPU
2.1.3
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
Eight 16-bit extended registers, and one 8-bit control register, have been added.
• Expanded address space
Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing mode
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
Two-bit shift instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
Note: * Normal mode is not available for this LSI.
2.1.4
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional control register
One 8-bit control register has been added.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Two-bit shift instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
Rev.2.00 Jan. 15, 2007 page 21 of 1174
REJ09B0329-0200
Section 2 CPU
2.2
CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal* and advanced. Normal mode* supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16
Mbytes for the program area and a maximum of 4 Gbytes for the data area).
The mode is selected by the mode pins of the microcontroller.
Note: * Normal mode is not available for this LSI.
Normal mode*
Maximum 64 kbytes for program
and data areas combined
Advanced mode
Maximum 16 Mbytes for program
and data areas combined
CPU operating mode
Note: * Normal mode is not available for this LSI.
Figure 2.1 CPU Operating Modes
2.2.1
Normal Mode (Not available for this LSI)
The exception vector table and stack have the same structure as in the H8/300 CPU.
(1) Address Space
A maximum address space of 64 kbytes can be accessed.
(2) Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments
of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the
corresponding general register (Rn) is used as an address register. If the general register is
referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment
(@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register
(En) will be affected.
Rev.2.00 Jan. 15, 2007 page 22 of 1174
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Section 2 CPU
(3) Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses
(EA) are valid.
(4) Exception Vector Table and Memory Indirect Branch Addresses
In normal mode the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The configuration of the exception vector table in normal
mode is shown in figure 2.2. For details of the exception vector table, see section 5, Exception
Handling.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
(Reserved for system use)
Exception vector table
Exception vector 1
Exception vector 2
Figure 2.2 Exception Vector Table (Normal Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note
that this area is also used for the exception vector table.
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Section 2 CPU
(5) Stack Structure
When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and
condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as
shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack. For details,
see section 5, Exception Handling.
SP
PC
(16 bits)
SP
CCR
CCR*
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Note: * Ignored when returning.
Figure 2.3 Stack Structure in Normal Mode
2.2.2
Advanced Mode
(1) Address Space
Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program
and data areas combined).
(2) Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments
of 32-bit registers or address registers.
(3) Instruction Set
All instructions and addressing modes can be used.
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Section 2 CPU
(4) Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in
units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the
lower 24 bits (figure 2.4). For details of the exception vector table, see section 5, Exception
Handling.
H'00000000
Reserved
Reset exception vector
H'00000003
Reserved
H'00000004
H'00000007
H'00000008
Exception vector table
H'0000000B
(Reserved for system use)
H'0000000C
H'00000010
Reserved
Exception vector 1
Figure 2.4 Exception Vector Table (Advanced Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing
a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as
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Section 2 CPU
H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the
first part of this range is also the exception vector table.
(5) Stack Structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call,
and the PC and condition-code register (CCR) are pushed onto the stack in exception handling,
they are stored as shown in figure 2.5. The extended control register (EXR) is not pushed onto the
stack. For details, see section 5, Exception Handling.
SP
Reserved
CCR
SP
PC
(24 bits)
PC
(24 bits)
(a) Subroutine Branch
(b) Exception Handling
Figure 2.5 Stack Structure in Advanced Mode
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Section 2 CPU
2.3
Address Space
Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-kbyte address space in normal mode*, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode.
Note: * Normal mode is not available for this LSI.
H'0000
H'00000000
H'FFFF
Program area
H'00FFFFFF
Data area
Cannot be used
with this LSI
H'FFFFFFFF
(a) Normal mode*
(b) Advanced mode
Note: * Normal mode is not available for this LSI.
Figure 2.6 Memory Map
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Section 2 CPU
2.4
Register Configuration
2.4.1
Overview
The CPU has the internal registers shown in figure 2.7. There are two types of registers: general
registers and control registers.
General Registers (Rn) and Extended Registers (En)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
EXR* T – – – – I2 I1 I0
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
Legend:
:
SP
:
PC
EXR :
:
T
I2 to I0 :
CCR :
:
I
:
UI
Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit
H
U
N
Z
V
C
:
:
:
:
:
:
Note: * Does not affect operation in this LSI.
Figure 2.7 CPU Registers
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Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Section 2 CPU
2.4.2
General Registers
The CPU has eight 32-bit general registers. These general registers are all functionally alike and
can be used as both address registers and data registers. When a general register is used as a data
register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used
as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER
registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to
R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers.
The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These
registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. Figure 2.8
illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
RH registers
(R0H to R7H)
ER registers
(ER0 to ER7)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.8 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the
stack.
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Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.9 Stack
2.4.3
Control Registers
The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),
and 8-bit condition-code register (CCR).
(1) Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0.)
(2) Extended Control Register (EXR)
An 8-bit register. In this LSI, this register does not affect operation.
Bit 7: Trace Bit (T): This bit is reserved. In this LSI, this bit does not affect operation.
Bits 6 to 3: Reserved: These bits are reserved. They are always read as 1.
Bits 2 to 0: Interrupt Mask Bits (I2 to I0): These bits are reserved. In this LSI, these bits do not
affect operation.
(3) Condition: Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
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Section 2 CPU
Bit 7: Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted
regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, see section 6, Interrupt Controller.
Bit 6: User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For
details, see section 6, Interrupt Controller.
Bit 5: Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4: User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
Bit 3: Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.
Bit 2: Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1: Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0
otherwise.
Bit 0: Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
a. Add instructions, to indicate a carry
b. Subtract instructions, to indicate a borrow
c. Shift and rotate instructions, to store the carry
The carry flag is also used as a bit accumulator by bit-manipulation instructions.
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction
on the flag bits, see appendix A.1, Instructions.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
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Section 2 CPU
2.4.4
Initial Register Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.
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Section 2 CPU
2.5
Data Formats
The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.
Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte
operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit
BCD data.
2.5.1
General Register Data Formats
Figure 2.10 shows the data formats in general registers.
Data type
General Register
Data Format
1-bit data
RnH
7 6 5 4 3 2 1 0
1-bit data
RnL
Don't care
4-bit BCD data
RnH
Upper digit Lower digit
7
0
Don't care
7
7
4 3
0
Don't care
7
4-bit BCD data
7
Byte data
Don't care
RnH
LSB
7
RnL
0
0
MSB
Byte data
4 3
Upper digit Lower digit
Don't care
RnL
0
7 6 5 4 3 2 1 0
0
Don't care
MSB
LSB
Figure 2.10 General Register Data Formats (1)
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Section 2 CPU
Data Type
General Register
Word data
Rn
Data format
15
0
MSB
Word data
En
15
0
MSB
Longword data
LSB
LSB
ERn
31
16 15
MSB
En
0
Rn
Legend:
ERn : General register ER
En
: General register E
Rn
: General register R
RnH : General register RH
RnL : General register RL
MSB : Most significant bit
LSB : Least significant bit
Figure 2.11 General Register Data Formats (2)
Rev.2.00 Jan. 15, 2007 page 34 of 1174
REJ09B0329-0200
LSB
Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.12 shows the data formats in memory.
The CPU can access word data and longword data in memory, but word or longword data must
begin at an even address. If an attempt is made to access word or longword data at an odd address,
no address error occurs but the least significant bit of the address is regarded as 0, so the access
starts at the preceding address. This also applies to instruction fetches.
Data Type
Data Format
Address
7
1-bit data
Address L
Byte data
Address L MSB
Word data
Address 2M MSB
7
0
6
5
4
3
1
0
LSB
LSB
Address 2M +1
Longword data
2
Address 2N MSB
Address 2N +1
Address 2N +2
LSB
Address 2N +3
Figure 2.12 Memory Data Formats
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
Rev.2.00 Jan. 15, 2007 page 35 of 1174
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Section 2 CPU
2.6
Instruction Set
2.6.1
Overview
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in
table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Size
Types
Data transfer
MOV
BWL
5
1
1
POP* , PUSH*
5
5
LDM* , STM*
WL
MOVFPE* , MOVTPE*
3
Arithmetic
L
3
B
ADD, SUB, CMP, NEG
BWL
ADDX, SUBX, DAA, DAS
B
INC, DEC
BWL
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
BW
EXTU, EXTS
4
TAS*
WL
B
Logic operations
AND, OR, XOR, NOT
BWL
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, BWL
ROTXR
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BLD, BILD, BST,
BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR
14
Branch
Bcc* , JMP, BSR, JSR, RTS
⎯
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC,
XORC, NOP
⎯
9
Block data transfer
EEPMOV
⎯
1
2
B
19
Total: 65 types
Legend:
B:
Byte
W:
Word
L:
Longword
Rev.2.00 Jan. 15, 2007 page 36 of 1174
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Section 2 CPU
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP.
POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in the H8S/2199 Group.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
5. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
Rev.2.00 Jan. 15, 2007 page 37 of 1174
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Section 2 CPU
2.6.2
Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU
can use.
Table 2.2
Combinations of Instructions and Addressing Modes
Logic
operation
Arithmetic operations
@(d:8, PC)
@(d:16, PC)
@@aa:8
—
@-ERn/@ERn+
BWL
—
—
@aa:32
@(d:32, ERn)
BWL
—
—
@aa:24
@(d:16, ERn)
BWL
—
—
@aa:16
@ERn
BWL
—
—
@aa:8
Rn
Data transfer
MOV
BWL
—
POP, PUSH
—
LDM*3, STM*3
MOVFPE,
—
1
MOVTPE*
ADD, CMP
BWL
SUB
WL
ADDX, SUBX
B
ADDS, SUBS
—
INC, DEC
—
DAA, DAS
—
MULXU,
—
DIVXU
MULXS,
—
DIVXS
NEG
—
EXTU, EXTS
—
2
TAS*
—
AND, OR,
BWL
XOR
NOT
—
Shift
—
Bit manipulation
—
Bcc, BSR
—
Branch JMP, JSR
—
RTS
—
TRAPA
—
RTE
—
SLEEP
—
LDC
B
STC
—
ANDC,
B
ORC, XORC
NOP
—
—
Block data transfer
System control
BWL
—
—
Instruction
#xx
Function
Addressing Modes
B
—
—
BWL
—
—
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
WL
L
—
—
—
—
—
—
B
—
—
—
—
—
—
BWL
BWL
B
L
BWL
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
—
—
—
—
—
—
—
—
—
—
BWL
WL
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
BWL
BWL
B
—
—
—
—
—
—
B
B
—
—
B
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
W
W
—
—
B
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
Legend:
B:
Byte
W:
Word
L:
Longword
Notes: 1. Cannot be used in this LSI.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
Rev.2.00 Jan. 15, 2007 page 38 of 1174
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Section 2 CPU
2.6.3
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the functions of the instructions. The notation used in table 2.3 is
defined below.
Operation Notation
Rs
General register (destination)*
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
Disp
Displacement
+
Addition
−
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Move
∼
NOT (logical complement)
Rd
:8/:16/:24/:32
Note:
*
8-, 16-, 24-, or 32-bit length
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
1
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general
register
MOVFPE
B
Cannot be used in this LSI
MOVTPE
B
Cannot be used in this LSI
POP
W/L
@SP+ → Rn
Pops a general register from the stack
POP.W Rn is identical to MOV.W @SP+, Rn
POP.L ERn is identical to MOV.L @SP+, ERn
PUSH
W/L
Rn → @-SP
Pushes a general register onto the stack
PUSH.W Rn is identical to MOV.W Rn, @-SP
PUSH.L ERn is identical to MOV.L ERn, @-SP
2
LDM*
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack
STM*
2
L
Rn (register list) → @-SP
Pushes two or more general registers onto the stack
Notes: 1. Size refers to the operand size.
B:
Byte
W:
Word
L:
Longword
2. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
Rev.2.00 Jan. 15, 2007 page 40 of 1174
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Section 2 CPU
Table 2.4
Arithmetic Instructions
Instruction
Size*
Function
ADD
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
ADDX
SUBX
B
INC
DEC
B/W/L
ADDS
SUBS
L
DAA
DAS
B
MULXU
B/W
1
Performs addition or subtraction on data in two general registers,
or on immediate data and data in a general register. (Immediate
byte data cannot be subtracted from byte data in a general
register. Use the SUBX or ADD instruction)
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two
general registers, or on immediate data and data in a general
register
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte
operands can be incremented or decremented by 1 only)
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit
register
Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general
register by referring to the CCR to produce 4-bit BCD data
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers:
either 16 bits ÷ 8 bits × 8-bit quotient and 8-bit remainder or 32
bits ÷ 16 bits × 16-bit quotient and 16-bit remainder
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Section 2 CPU
Instruction
Size*
Function
DIVXS
B/W
Rd ÷ Rs → Rd
1
Performs signed division on data in two general registers: either
16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷
16 bits → 16-bit quotient and 16-bit remainder
CMP
B/W/L
Rd - Rs, Rd - #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to
the result
NEG
B/W/L
0 - Rd → Rd
Takes the two's complement (arithmetic complement) of data in
a general register
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the
lower 16 bits of a 32-bit register to longword size, by extending
the sign bit
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the
lower 16 bits of a 32-bit register to longword size, by padding
with zeros on the left
TAS
B
@ERd - 0, 1 → (<bit 7> of @ERd)*
2
Tests memory contents, and sets the most significant bit (bit 7)
to 1
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev.2.00 Jan. 15, 2007 page 42 of 1174
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Section 2 CPU
Table 2.5
Logic Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and
another general register or immediate data
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and
another general register or immediate data
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register
and another general register or immediate data
NOT
B/W/L
~ Rd → Rd
Takes the one's complement (logical complement) of general
register contents
Note:
*
B:
W:
L:
Size refers to the operand size.
Byte
Word
Longword
Table 2.6
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B/W/L
Rd (shift) → Rd
SHLL
SHLR
B/W/L
ROTL
ROTR
B/W/L
ROTXL
ROTXR
B/W/L
Note:
Performs an arithmetic shift on general register contents
A 1-bit or 2-bit shift is possible
Rd (shift) → Rd
Performs a logical shift on general register contents
A 1-bit or 2-bit shift is possible
Rd (rotate) → Rd
Rotates general register contents
1-bit or 2-bit rotation is possible
Rd (rotate) → Rd
Rotates general register contents through the carry flag
1-bit or 2-bit rotation is possible
*
B:
W:
L:
Size refers to the operand size.
Byte
Word
Longword
Rev.2.00 Jan. 15, 2007 page 43 of 1174
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Section 2 CPU
Table 2.7
Bit Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to
1. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to
0. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register
BNOT
B
~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand.
The bit number is specified by 3-bit immediate data or the lower
three bits of a general register
BTST
B
~ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand
and sets or clears the Z flag accordingly. The bit number is
specified by 3-bit immediate data or the lower three bits of a
general register
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag
BIAND
B
C ∧ [~(<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the
carry flag
The bit number is specified by 3-bit immediate data
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag
BIOR
B
C∨ [~(<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry
flag
The bit number is specified by 3-bit immediate data
Rev.2.00 Jan. 15, 2007 page 44 of 1174
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Section 2 CPU
Instruction
Size*
Function
BOXR
B
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the carry
flag
BIXOR
B
C ⊕ [~ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in
a general register or memory operand and stores the result in
the carry flag
The bit number is specified by 3-bit immediate data
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory
operand to the carry flag
BILD
B
~ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or
memory operand to the carry flag
The bit number is specified by 3-bit immediate data
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general
register or memory operand
BIST
B
~ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand
The bit number is specified by 3-bit immediate data
Note:
* Size refers to the operand size.
B: Byte
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Section 2 CPU
Table 2.8
Branch Instructions
Instruction
Size*
Function
Bcc
⎯
Branches to a specified address if a specified condition is true
The branching conditions are listed below
Mnemonic
Description
Condition
BRA (BT)
Always (True)
Always
BRN (BF)
Never (False)
Never
BHI
HIgh
CVZ = 0
BLS
Low of Same
CVZ = 1
BCC (BHS)
Carry Clear
(High or Same)
C=0
BCS (BLO)
Carry Set (LOw)
C=1
BNE
Not Equal
Z=0
BEQ
EQual
Z=1
BVC
oVerflow Clear
V=0
BVS
oVerflow Set
V=1
BPL
PLus
N=0
BMI
MInus
N=1
BGE
Greater or Equal
NV = 0
BLT
Less Than
N⊕V=1
BGT
Greater Than
Z∨ (N ⊕ V) = 0
BLE
Less or Equal
Z∨ (N ⊕ V) = 1
JMP
⎯
Branches unconditionally to a specified address
BSR
⎯
Branches to a subroutine at a specified address
JSR
⎯
Branches to a subroutine at a specified address
RTS
⎯
Returns from a subroutine
Rev.2.00 Jan. 15, 2007 page 46 of 1174
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Section 2 CPU
Table 2.9
System Control Instructions
Instruction
Size*
Function
TRAPA
⎯
Starts trap-instruction exception handling
RTE
⎯
Returns from an exception-handling routine
SLEEP
⎯
Causes a transition to a power-down state
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves contents of a general register or memory or immediate
data to CCR or EXR. Although CCR and EXR are 8-bit registers,
word-size transfers are performed between them and memory.
The upper 8 bits are valid
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or
memory. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper
8 bits are valid
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data
ORC
B
CCR∨ #IMM → CCR, EXR∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with
immediate data
NOP
⎯
PC + 2 → PC
Only increments the program counter
Note:
* Size refers to the operand size.
B: Byte
W: Word
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Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction
Size*
Function
EEPMOV.B
⎯
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L −1 → R4L
Until R4L = 0
else next;
EEPMOV.W
⎯
if R4 ≠ 0 then
Repeat @ER5+ → ER6+
R4 −1 → R4
Until R4 = 0
else next;
Transfers a data block according to parameters set in general
registers R4L or R4, ER5, and ER6
R4L or R4: size of block (bytes)
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Section 2 CPU
2.6.4
Basic Instruction Formats
The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (op field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Figure 2.13 shows examples of instruction formats.
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B@(d:16, Rn), Rm, etc.
EA (disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16, etc.
Figure 2.13 Instruction Formats (Examples)
(1) Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried out
on the operand. The operation field always includes the first four bits of the instruction. Some
instructions have two operation fields.
(2) Register Field
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4
bits. Some instructions have two register fields. Some have no register field.
(3) Effective Address Extension
Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
Rev.2.00 Jan. 15, 2007 page 49 of 1174
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Section 2 CPU
(4) Condition Field
Specifies the branching condition of Bcc instructions.
2.6.5
Notes on Use of Bit-Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit
manipulation, then write back the byte of data. Caution is therefore required when using these
instructions on a register containing write-only bits, or a port.
The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant
flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling
routine, etc.
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Section 2 CPU
2.7
Addressing Modes and Effective Address Calculation
2.7.1
Addressing Mode
The CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset
of these addressing modes. Arithmetic and logic instructions can use the register direct and
immediate modes. Data transfer instructions can use all addressing modes except program-counter
relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@-ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
(1) Register Direct–Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing
the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to
E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as
32-bit registers.
(2) Register Indirect–@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand in memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
Rev.2.00 Jan. 15, 2007 page 51 of 1174
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Section 2 CPU
(3) Register Indirect with Displacement–@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
(4) Register Indirect with Post-Increment or Pre-Decrement–@ERn+ or @-ERn
a. Register indirect with post-increment–@ERn+
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address
register contents and the sum is stored in the address register. The value added is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the register
value should be even.
b. Register indirect with pre-decrement–@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the result becomes the address of a memory operand. The result is
also stored in the address register. The value subtracted is 1 for byte access, 2 for word access,
or 4 for longword access. For word or longword access, the register value should be even.
(5) Absolute Address–@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32).
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.12 indicates the accessible absolute address ranges.
Rev.2.00 Jan. 15, 2007 page 52 of 1174
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Section 2 CPU
Table 2.12 Absolute Address Access Ranges
Absolute Address
Data address
Normal Mode
Advanced Mode
8 bits
(@aa:8)
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits
(@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF, H'FF8000 to
H'FFFFFF
32 bits
(@aa:32)
Program instruction
address
H'000000 to H'FFFFFF
24 bits
(@aa:24)
(6) Immediate–#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
(7) Program-Counter Relative–@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.
Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0
(H'00). The PC value to which the displacement is added is the address of the first byte of the next
instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to
+32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should
be an even number.
(8) Memory Indirect–@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode
the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00).
Rev.2.00 Jan. 15, 2007 page 53 of 1174
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Section 2 CPU
Note that the first part of the address range is also the exception vector area. For further details,
see section 5, Exception Handling.
Specified by
@aa:8
Branch address
Specified by
@aa:8
Reserved
Branch address
(a) Normal Mode*
(b) Advanced Mode
Note: * Not available for this LSI
Figure 2.14 Branch Address Specification in Memory Indirect Mode
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or an instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)
2.7.2
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode.
In normal mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit
address.
Note: * Not available for this LSI.
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Section 2 CPU
Table 2.13 Effective Address Calculation
No.
Addressing Mode and
Instruction Format
1
Register direct (Rn)
op
2
Effective Address
Calculation
Effective Address (EA)
Operand is general register
contents
rm rn
Register indirect (@ERn)
31
0
3
24 23
0
Don’t
care
General register contents
op
31
r
Register indirect with displacement
@(d:16, ERn) or @(d:32, ERn)
31
0
General register contents
31
op
r
disp
31
0
0
Sign extension
4
24 23
Don’t
care
disp
Register indirect with post-increment or pre-decrement
•
Register indirect with post-increment @ERn+
31
0
24 23
0
Don’t
care
General register contents
op
31
r
1, 2, or
4
•
Register indirect with pre-decrement @–ERn
31
0
General register contents
31
op
24 23
0
Don’t
care
r
Operand
Size
Byte
Word
Longword
Value
Added
1
2
4
1, 2, or
4
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Section 2 CPU
No.
Addressing Mode and
Instruction Format
5
Absolute address
Effective Address
Calculation
Effective Address (EA)
@aa:8
31
op
24 23
Don’t
care
abs
@aa:16
31
op
0
H'FFFF
24 23 16 15
Sign
extension
0
24 23
0
Don’t
care
abs
@aa:24
31
op
87
Don’t
care
abs
@aa:32
op
31
abs
6
Immediate #xx:8/#xx:16/#xx:32
op
7
24 23
0
Don’t
care
Operand is immediate data
IMM
Program-counter relative
@(d:8, PC)/@(d:16, PC)
0
23
PC contents
op
disp
Rev.2.00 Jan. 15, 2007 page 56 of 1174
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23
Sign
extension
0
disp
31
24 23
Don’t
care
0
Section 2 CPU
No.
Addressing Mode and
Instruction Format
8
Memory indirect @@aa:8
•
Effective Address
Calculation
Effective Address (EA)
Normal mode*
op
abs
31
87
0
abs
H'000000
31
24 23
Don’t
care
16 15
0
H'00
0
15
Memory
contents
•
Advanced mode
op
abs
31
87
abs
H'000000
31
0
Memory contents
Note:
*
0
31
24 23
0
Don’t
care
Not available for this LSI.
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Section 2 CPU
2.8
Processing States
2.8.1
Overview
The CPU has four main processing states: the reset state, exception-handling state, program
execution state, and power-down state. Figure 2.15 shows a diagram of the processing states.
Figure 2.16 indicates the state transitions.
Reset state
The CPU and all on-chip supporting modules have been initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal processing flow in response
to a reset, interrupt or trap instruction.
Processing
states
Program execution
state
The CPU executes program instructions in sequence.
Sleep mode
Power-down state
CPU operation is stopped
to conserve power.*
Standby mode
Note: * The power-down state also includes a medium-speed mode, modue stop mode, sub-active mode,
sub-sleep mode and watch mode.
Figure 2.15 Processing States
Rev.2.00 Jan. 15, 2007 page 58 of 1174
REJ09B0329-0200
Section 2 CPU
est
equ
tr
rup
qu
r
Inte
Exception-handling state
S
w LE
SS ith EP
BY LS in
=0 ON stru
=0 ct
, ion
Sleep mode
Re
En
d
of
ex
ce
es
pt
tf
io
or
n
ha
ex
ce
nd
pt
ion ling
ha
nd
lin
g
Program execution state
S
w LE
SS ith EP
TM B LS in
A3 Y=1 ON stru
=0 , =0 ct
, ion
External interrupt request
Standby mode
Power-down state*2
RES = High
Reset state *1
Notes:
1. From any state, a transition to the reset state occurs whenever RES goes low. A transition can
also be made to the reset state when the watchdog timer overflows.
2. The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For
details, see section 4, Power-Down State.
Figure 2.16 State Transitions
2.8.2
Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. All
interrupts are disabled in the reset state. Reset exception handling starts when the RES signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, see section 17,
Watchdog Timer (WDT).
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Section 2 CPU
2.8.3
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
(1) Types of Exception Handling and Their Priority
Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14 indicates
the types of exception handling and their priority. Trap instruction exception handling is always
accepted in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Table 2.14 Exception Handling Types and Priority
Priority
Type of Exception Detection Timing
Start of Exception Handling
High
Reset
Synchronized with clock
Exception handling starts immediately
after a low-to-high transition at the
RES pin, or when the watchdog timer
overflows
Interrupt
End of instruction
execution or end of
exception-handling
1
sequence*
When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence
Trap instruction
When TRAPA instruction Exception handling starts when a trap
2
is executed
(TRAPA) instruction is executed*
Low
Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.
2. Trap instruction exception handling is always accepted in the program execution state.
(2) Reset Exception Handling
After the RES pin has gone low and the reset state has been entered, when RES goes high again,
reset exception handling starts. When reset exception handling starts the CPU fetches a start
address (vector) from the exception vector table and starts program execution from that address.
All interrupts, including NMI, are disabled during reset exception handling and after it ends.
Rev.2.00 Jan. 15, 2007 page 60 of 1174
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Section 2 CPU
(3) Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer
(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU
alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start
address (vector) from the exception vector table and program execution starts from that start
address.
Figure 2.17 shows the stack after exception handling ends.
Normal Mode*2
SP
Advanced Mode
CCR
CCR*1
SP
CCR
PC
(24 bits)
PC
(16 bits)
Notes:
1. Ignored when returning.
2. Normal mode is not available for this LSI.
Figure 2.17 Stack Structure after Exception Handling (Examples)
2.8.4
Program Execution State
In this state the CPU executes program instructions in sequence.
Rev.2.00 Jan. 15, 2007 page 61 of 1174
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Section 2 CPU
2.8.5
Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,
standby mode, subsleep mode, and watch mode. There are also three other power-down modes:
medium-speed mode, module stop mode, and subactive mode. In medium-speed mode, the CPU
operates on a medium-speed clock. Module stop mode permits halting of the operation of
individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode are
power-down modes that use subclock input. For details, see section 4, Power-Down State.
(1) Sleep Mode
A transition to sleep mode is made if the SLEEP instruction is executed while the software
standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the low-power
control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations stop
immediately after execution of the SLEEP instruction. The contents of CPU registers are retained.
(2) Standby Mode
A transition to standby mode is made if the SLEEP instruction is executed while the SSBY bit in
SBYCR is set to 1 and the LSON bit in LPWRCR and the TMA3 bit in the TMA (timer A) are
both cleared to 0. In standby mode, the CPU and clock halt and all MCU operations stop. As long
as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained.
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Section 2 CPU
2.9
Basic Timing
2.9.1
Overview
The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge
of φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one or two
states. Different methods are used to access on-chip memory and on-chip supporting modules.
2.9.2
On-Chip Memory (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2.18 shows the on-chip memory access cycle.
Bus cycle
T1
φ
Internal address bus
Address
Internal read signal
Read access
Internal data bus
Read data
Internal write signal
Write access
Internal data bus
Write data
Figure 2.18 On-Chip Memory Access Cycle
2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the
access timing for the on-chip supporting modules.
Rev.2.00 Jan. 15, 2007 page 63 of 1174
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Section 2 CPU
Bus cycle
T2
T1
φ
Internal address bus
Address
Internal read signal
Read access
Internal data bus
Read data
Internal write signal
Write access
Internal data bus
Write data
Figure 2.19 On-Chip Supporting Module Access Cycle
2.10
Usage Note
2.10.1
TAS Instruction
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers.
If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0,
ER1, ER4, or ER5 is used.
2.10.2
STM/LDM Instruction
ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM
instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored by
one STM/LDM instruction. The following ranges can be specified in the register list.
Two registers : ER0⎯ER1, ER2⎯ER3, or ER4⎯ER5
Three registers : ER0⎯ER2 or ER4⎯ER6
Four registers : ER0⎯ER3
The STM/LDM instruction including ER7 is not generated by the Renesas Technology H8S and
H8/300 series C/C++ compilers.
Rev.2.00 Jan. 15, 2007 page 64 of 1174
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Overview
3.1.1
Operating Mode Selection
This LSI has one operating mode (mode 1). This mode is selected depending on settings of the
mode pin (MD0). Table 3.1 lists the MCU operating modes.
Table 3.1
MCU Operating Mode Selection
MCU Operating Mode
MD0
CPU Operating Mode
Description
0
0
⎯
⎯
1
1
Advanced
Single-chip mode
The CPU's architecture allows for 4 Gbytes of address space, but this LSI actually accesses a
maximum of 16 Mbytes. Mode 1 operation starts in single-chip mode after reset release. This LSI
can only be used in mode 1. This means that the mode pins must be set at mode 1. Do not changes
the inputs at the mode pins during operation.
3.1.2
Register Configuration
This LSI has a mode control register (MDCR) that indicates the inputs at the mode pin (MD0) and
a system control register (SYSCR) and that controls the operation of this LSI. Table 3.2
summarizes these registers.
Table 3.2
MCU Registers
Name
Abbreviation
R/W
Initial Value
Address*
Mode control register
MDCR
R
Undetermined
H'FFE9
System control register
SYSCR
R/W
H'09
H'FFE8
Note:
*
Lower 16 bits of the address.
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Section 3 MCU Operating Modes
3.2
Register Descriptions
3.2.1
Mode Control Register (MDCR)
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
MDS0
Initial value :
0
0
0
0
0
0
0
—*
R/W :
—
—
—
—
—
—
—
R
Bit :
Note: * Determined by MD0 pin
MDCR is an 8-bit read-only register monitors the current operating mode of this LSI.
Bits 7 to 1⎯Reserved: These bits cannot be modified and are always read as 0.
Bit 0⎯Mode Select 0 (MDS0): This bit indicates the value which reflects the input levels at
mode pin (MD0) (the current operating mode). Bit MDS0 corresponds to MD0 pin. They are readonly bits-they cannot be written to. The mode pin (MD0) input levels are latched into these bits
when MDCR is read.
3.2.2
System Control Register (SYSCR)
7
6
5
4
3
2
1
0
—
—
INTM1
INTM0
XRST
—
—
—
Initial value :
0
0
0
0
1
0
0
1
R/W :
—
—
R
R/W
R
—
—
—
Bit :
Bits 7 and 6⎯Reserved: These bits cannot be modified and are always read as 0.
Rev.2.00 Jan. 15, 2007 page 66 of 1174
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Section 3 MCU Operating Modes
Bits 5 and 4⎯Interrupt control modes 1 and 0 (INTM1, INTM0)
These bits are for selecting the interrupt control mode of the interrupt controller. For details of the
interrupt control modes, see section 6.4.1, Interrupt Control Modes and Interrupt Operation.
Bit 5
Bit 4
INTM1
INTM0
Interrupt Control
Mode
Description
0
0
0
Interrupt is controlled by bit I
1
1
Interrupt is controlled by bits I and UI, and ICR
0
⎯
Cannot be used in this LSI
1
⎯
Cannot be used in this LSI
1
(Initial value)
Bit 3⎯External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a
read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow.
Bit 3
XRST
Description
0
A reset is generated by watchdog timer overflow
1
A reset is generated by an external reset
(Initial value)
Bits 2 and 1⎯Reserved: These bits cannot be modified and are always read as 0.
Bit 0⎯Reserved: This bit is always read as 1.
3.3
Operating Mode (Mode 1)
The CPU can access a 16 Mbyte address space in advanced mode.
Rev.2.00 Jan. 15, 2007 page 67 of 1174
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Section 3 MCU Operating Modes
3.4
Address Map in Each Operating Mode
Vector area
H'0000FF
On-chip ROM
(80 kbytes)
Absolute address, 16 bits
H'000000
H8S/2197R
Memory indirect
branch address
H8S/2196R
H'000000
Vector area
On-chip ROM
(96 kbytes)
H'007FFF
H'013FFF
H'017FFF
H'040000
H'045FFF
H'040000
OSD ROM
(24 kbytes)
H'045FFF
OSD ROM
(24 kbytes)
H'FFD000
Internal I/O register
H'FFD2FF
H'FFFF00
H'FFFFAF
H'FFFFB0
Internal I/O register
4 kbytes
On-chip RAM
Absolute address,
8 bits
H'FFD800
OSD RAM (768 bytes)
H'FFDAFF
H'FFEFB0
Absolute address, 16 bits
H'FF8000
H'FFD000
Internal I/O register
H'FFD2FF
H'FFD800
OSD RAM (768 bytes)
H'FFDAFF
H'FFEFB0
On-chip RAM
(4 kbytes)
H'FFFFAF
H'FFFFB0
Internal I/O register
H'FFFFFF
H'FFFFFF
Figure 3.1 Address Map (1)
Rev.2.00 Jan. 15, 2007 page 68 of 1174
REJ09B0329-0200
Section 3 MCU Operating Modes
H8S/2198R
H'000000
H8S/2199R
H8S/2199R (F-ZTAT version)
H'000000
H'000000
Vector area
Vector area
Vector area
On-chip ROM
(112 kbytes)
On-chip ROM
(128 kbytes)
Flash memory
(256 kbytes)
H'01BFFF
H'040000
H'045FFF
OSD ROM
(24 kbytes)
H'01FFFF
H'040000
H'045FFF
H'03FFFF
OSD ROM
(24 kbytes)
H'047FFF
Flash memory (OSD)
(32 kbytes)
H'FFD000
Internal I/O register
H'FFD2FF
H'FFD000
Internal I/O register
H'FFD2FF
H'FFD000
Internal I/O register
H'FFD2FF
H'FFD800
OSD RAM (768 bytes)
H'FFDAFF
H'FFEFB0
H'FFD800
OSD RAM (768 bytes)
H'FFDAFF
H'FFEFB0
H'FFD800
OSD RAM (768 bytes)
H'FFDAFF
H'FFDFB0
On-chip RAM
(4 kbytes)
H'FFFFAF
H'FFFFB0
On-chip RAM
(4 kbytes)
H'FFFFAF
H'FFFFB0
Internal I/O register
H'FFFFFF
On-chip RAM
(8 kbytes)
H'FFFFAF
H'FFFFB0
Internal I/O register
Internal I/O register
H'FFFFFF
H'FFFFFF
Figure 3.2 Address Map (2)
Rev.2.00 Jan. 15, 2007 page 69 of 1174
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Section 3 MCU Operating Modes
H8S/2196S
H'000000
H'000000
Vector area
Vector area
On-chip ROM
(80 kbytes)
On-chip ROM
(96 kbytes)
H'013FFF
H'040000
H'043FFF
H8S/2197S
H'017FFF
OSD ROM
(16 kbytes)
H'FFD000
H'040000
OSD ROM
(16 kbytes)
H'043FFF
H'FFD000
Internal I/O register
Internal I/O register
H'FFD2FF
H'FFD2FF
H'FFD800
H'FFD800
OSD RAM
(768 bytes)
OSD RAM
(768 bytes)
H'FFDAFF
H'FFDAFF
H'FFF3B0
H'FFF3B0
On-chip RAM
(3 kbytes)
H'FFFFAF
H'FFFFB0
Internal I/O register
On-chip RAM
(3 kbytes)
H'FFFFAF
H'FFFFB0
Internal I/O register
H'FFFFFF
H'FFFFFF
Figure 3.3 Address Map (3)
Rev.2.00 Jan. 15, 2007 page 70 of 1174
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Section 4 Power-Down State
Section 4 Power-Down State
4.1
Overview
In addition to the normal program execution state, this LSI has a power-down state in which
operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip supporting modules, and
so on. This LSI operating modes are as follows:
1. High-speed mode
2. Medium-speed mode
3. Sub-active mode
4. Sleep mode
5. Sub-sleep mode
6. Watch mode
7. Module stop mode
8. Standby mode
Of these, 2 to 8 are power-down modes. Certain combinations of these modes can be set. After a
reset, the MCU is in high-speed mode.
Table 4.1 shows the internal chip states in each mode, and table 4.2 shows the conditions for
transition to the various modes. Figure 4.1 shows a mode transition diagram.
Rev.2.00 Jan. 15, 2007 page 71 of 1174
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Section 4 Power-Down State
Table 4.1
H8S/2199R Group Internal States in Each Mode
Function
MediumHigh-Speed Speed
System clock
Functioning Functioning Functioning Functioning Halted
Subclock pulse
generator
Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning
CPU
operation
External
interrupts
Sleep
Instruction Functioning Mediums
speed
Halted
Registers
Retained
Module
Stop
Watch
Functioning Halted
Sub-active Sub-sleep
Standby
Halted
Halted
Subclock
operation
Retained
Halted
Halted
Halted
Retained
Retained
Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning
IRQ0
IRQ1
IRQ2
Halted
Halted
Functioning Halted
IRQ3
IRQ4
IRQ5
On-chip
I/O
supporting
Timer A
module
operation
Functioning Functioning Retained
Functioning Retained
Halted
Functioning Functioning Functioning Functioning Subclock
/halted
operation
(retained)
Subclock
operation
Subclock
operation
Halted
(retained)
Functioning Functioning Functioning Functioning Halted
/halted
(retained)
(retained)
Halted
(retained)
Halted
(retained)
Halted
(retained)
Halted
(reset)
Halted
(reset)
Halted
(reset)
Watchdog Functioning Functioning Functioning Functioning Halted
timer
(retained)
Halted
(retained)
Halted
(retained)
Halted
(retained)
8-bit PWM Functioning Functioning Functioning Functioning Halted
/halted
(retained)
(retained)
Halted
(retained)
Halted
(retained)
Halted
(retained)
12-bit
PWM
Functioning Functioning Halted
(reset)
Halted
(reset)
Halted
(reset)
Halted
(reset)
14-bit
2
PWM*
Functioning Functioning Functioning Functioning Halted
/halted
(retained)
(retained)
Halted
(retained)
Halted
(retained)
Halted
(retained)
PSU
Functioning Functioning Functioning Functioning/ Subclock
halted
operation
Functioning Functioning Functioning Functioning/ Halted*1
1
halted*
Subclock
operation
Halted*1
Subclock
operation
Halted*1
Halted
IIC
Functioning/ Halted
halted
(retained)
(retained)
Halted
(retained)
Halted
(retained)
Halted
(retained)
A/D
Functioning Halted
/halted
(reset)
(reset)
Halted
(reset)
Halted
(reset)
Halted
(reset)
Functioning Halted
/halted
(reset)
(reset)
Halted
(reset)
Halted
(reset)
Halted
(reset)
Functioning Halted
/halted
(retained)
(retained)
Halted
(retained)
Halted
(retained)
Halted
(retained)
Timer B
Timer J
Functioning Halted
Timer L
Functioning Halted
(reset)
/halted
(reset)
Timer R
Timer X1*
2
SCI1
Servo
circuit
Functioning Functioning Halted
(reset)
Sync
Functioning Functioning Halted
separator
(retained)
Rev.2.00 Jan. 15, 2007 page 72 of 1174
REJ09B0329-0200
Functioning Halted
/halted
(reset)
(reset)
Halted*1
Section 4 Power-Down State
Function
MediumHigh-Speed Speed
Sleep
Data slicer Functioning Functioning Halted
On-chip
supporting
(reset)
module
OSD
operation
Module
Stop
Watch
Functioning Halted
/halted
(reset)
(reset)
Sub-active Sub-sleep
Standby
Halted
(reset)
Halted
(reset)
Halted
(reset)
Notes: "Halted (retained)" means that internal register values are retained. The internal state is
"operation suspended."
"Halted (reset)" means that internal register values and internal states are initialized.
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
In the power-down mode, the analog section of the servo circuits are not turned off,
therefore Vcc (Servo) current does not go low. When power-down is needed, externally
shut down the analog system power.
1. The SCI1 status differs from the internal register. For details, refer to section 22, Serial
Communication Interface 1 (SCII).
2. Not available in the H8S/2197S or H8S/2196S.
Rev.2.00 Jan. 15, 2007 page 73 of 1174
REJ09B0329-0200
Section 4 Power-Down State
Reset state
Program-halted state
Program execution state
SLEEP
instruction a
Standby
mode
Interrupt 1
SLEEP
instruction
a
Interrupt
1
SLEEP
instruction
b
Interrupt 2
SLEEP
instruction b
SLEEP
instruction b
Interrupt 2
SLEEP
instruction e
Active
(high-speed)
mode
g
Interrupt 3
h
SLEEP
instruction
c
Sleep
(high-speed)
mode
SLEEP
instruction
d
SLEEP
instruction e
Active
(medium-speed)
mode
SLEEP
Interrupt 2 instruction
c
Watch
mode
Program-halted state
Sleep
(medium-speed)
mode
Interrupt 3
SLEEP
instruction
d
SLEEP
instruction 1
Subactive
mode
Interrupt 4
Subsleep
mode
Power-down mode
Conditions for mode transition (1)
Conditions for mode transition (2)
Interruption factor
Flag LSON SSBY TMA3 DTON
IRQ0 to 1
a
0
1
0
*
1
b
*
1
1
0
2
IRQ0 to 1, Timer A interruption
1
3
All interruption (excluding servo system)
1
1
4
IRQ0 to 5, Timer A interruption
c
0
1
1
1
1
e
0
0
*
*
f
1
0
1
*
d
g
SCK1 to 0 = 0
h
SCK1 to 0 ≠ 0 (either 1 bit = 0)
Legend: * Don't care
Note: When a transition is made between
modes by means of an interrupt,
transition cannot be made on interrupt
source generation alone. Ensure that
interrupt handling is performed after
accepting the interrupt request
Figure 4.1 Mode Transitions
Rev.2.00 Jan. 15, 2007 page 74 of 1174
REJ09B0329-0200
Section 4 Power-Down State
Table 4.2
State before
Transition
Power-Down Mode Transition Conditions
Control Bit States at Time of
Transition
TMA3
LSON
DTON
State after Transition
by SLEEP Instruction
State after Return
by Interrupt
High-speed/
0
medium-speed
*
0
*
Sleep
High-speed/
1
medium-speed*
0
*
1
*
⎯
⎯
1
0
0
*
Standby
High-speed/
1
medium-speed*
1
0
1
*
⎯
⎯
1
1
0
0
Watch
High-speed/
1
medium-speed*
1
1
1
0
Watch
Subactive
Subactive
SSBY
1
1
0
1
⎯
⎯
1
1
1
1
Subactive
⎯
0
0
*
*
⎯
⎯
0
1
0
*
⎯
⎯
0
1
1
*
Subsleep
Subactive
1
0
*
*
⎯
⎯
1
1
0
0
Watch
High-speed/
2
medium-speed*
1
1
1
0
Watch
Subactive
1
1
0
1
High-speed/
2
medium-speed*
⎯
1
1
1
1
⎯
⎯
Legend: * Don't care
Notes: ⎯: Do not set.
1. Returns to the state before transition.
2. Mode varies depending on the state of SCK1 to SCK0.
Rev.2.00 Jan. 15, 2007 page 75 of 1174
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Section 4 Power-Down State
4.1.1
Register Configuration
The power-down state is controlled by the SBYCR, LPWRCR, TMA (Timer A), and MSTPCR
registers. Table 4.3 summarizes these registers.
Table 4.3
Power-Down State Registers
Name
Abbreviation
R/W
Initial Value
Address*
Standby control register
SBYCR
R/W
H'00
H'FFEA
Low-power control register
LPWRCR
R/W
H'00
H'FFEB
Module stop control register
MSTPCRH
R/W
H'FF
H'FFEC
MSTPCRL
R/W
H'FF
H'FFED
TMA
R/W
H'30
H'FFBA
Timer mode register A
Note:
Lower 16 bits of the address.
*
4.2
Register Descriptions
4.2.1
Standby Control Register (SBYCR)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
—
—
SCK1
SCK0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
—
—
R/W
R/W
SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is
initialized to H'00 by a reset.
Rev.2.00 Jan. 15, 2007 page 76 of 1174
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Section 4 Power-Down State
Bit 7⎯Software Standby (SSBY): Determines the operating mode, in combination with other
control bits, when a power-down mode transition is made by executing a SLEEP instruction. The
SSBY setting is not changed by a mode transition due to an interrupt, etc.
Bit 7
SSBY
Description
0
Transition to sleep mode after execution of SLEEP instruction in high-speed mode
or medium-speed mode
Transition to subsleep mode after execution of SLEEP instruction in subactive
mode
(Initial value)
1
Transition to standby mode, subactive mode, or watch mode after execution of
SLEEP instruction in high-speed mode or medium-speed mode
Transition to watch mode or high-speed mode after execution of SLEEP instruction
in subactive mode
Bits 6 to 4⎯Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU
waits for the clock to stabilize when standby mode, watch mode, or subactive mode is cleared and
a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or
instruction. With crystal oscillation, see table 4.5 and make a selection according to the operating
frequency so that the standby time is at least 10 ms (the oscillation settling time).
Bit 6
Bit 5
Bit 4
STS2
STS1
STS0
Description
0
0
0
Standby time = 8192 states
0
0
1
Standby time = 16384 states
0
1
0
Standby time = 32768 states
0
1
1
Standby time = 65536 states
1
0
0
Standby time = 131072 states
1
0
1
Standby time = 262144 states
1
1
*
Reserved
Legend: * Don't care
Bits 3 and 2⎯Reserved: These bits cannot be modified and are always read as 0.
Rev.2.00 Jan. 15, 2007 page 77 of 1174
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Section 4 Power-Down State
Bits 1 and 0⎯System Clock Select 1 and 0 (SCK1, SCK0): These bits select the CPU clock for
the bus master in high-speed mode and medium-speed mode.
Bit 1
Bit 0
SCK1
SCK0
Description
0
0
Bus master is in high-speed mode (Initial value)
0
1
Medium-speed clock is φ/16
1
0
Medium-speed clock is φ/32
1
1
Medium-speed clock is φ/64
4.2.2
Low-Power Control Register (LPWRCR)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
DTON
LSON
NESEL
—
—
—
SA1
SA0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
—
—
—
R/W
R/W
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
LPWRCR is initialized to H'00 by a reset.
Bit 7⎯Direct-Transfer on Flag (DTON): Specifies whether a direct transition is made between
high-speed mode, medium-speed mode, and subactive mode when making a power-down
transition by executing a SLEEP instruction. The operating mode to which the transition is made
after SLEEP instruction execution is determined by a combination of other control bits.
Bit 7
DTON
Description
0
•
When a SLEEP instruction is executed in high-speed mode or medium-speed
mode, a transition is made to sleep mode, standby mode, or watch mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made
to subsleep mode or watch mode
(Initial value)
•
When a SLEEP instruction is executed in high-speed mode or medium-speed
mode, transition is made directly to subactive mode, or a transition is made to
sleep mode or standby mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made
directly to high-speed mode, or a transition is made to subsleep mode
1
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Section 4 Power-Down State
Bit 6⎯Low-Speed on Flag (LSON): Determines the operating mode in combination with other
control bits when making a power-down transition by executing a SLEEP instruction. Also
controls whether a transition is made to high-speed mode or to subactive mode when watch mode
is cleared.
Bit 6
LSON
Description
0
•
When a SLEEP instruction is executed in high-speed mode or medium-speed
mode, transition is made to sleep mode, standby mode, or watch mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made
to watch mode, or directly to high-speed mode
•
After watch mode is cleared, a transition is made to high-speed mode
(Initial value)
•
When a SLEEP instruction is executed in high-speed mode a transition is made
to watch mode, subactive mode, sleep mode or standby mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made
to subsleep mode or watch mode
•
After watch mode is cleared, a transition is made to subactive mode
1
Bit 5⎯Noise Elimination Sampling Frequency Select (NESEL): Selects the frequency at which
the subclock (φw) generated by the subclock pulse generator is sampled with the clock (φ)
generated by the system clock oscillator. When φ = 5 MHz or higher, clear this bit to 0.
Bit 5
NESEL
Description
0
Sampling at φ divided by 16
1
Sampling at φ divided by 4
Bits 4 to 2⎯Reserved: These bits cannot be modified and are always read as 0.
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Section 4 Power-Down State
Bits 1 and 0⎯Subactive Mode Clock Select 1 and 0 (SA1, SA0): These bits select the CPU
operating clock in the subactive mode. These bits cannot be modified in the subactive mode.
Bit 1
Bit 0
SA1
SA0
Description
0
0
Operating clock of CPU is φw/8
0
1
Operating clock of CPU is φw/4
1
*
Operating clock of CPU is φw/2
(Initial value)
Legend: * Don’t care
4.2.3
Timer Register A (TMA)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
TMAOV
TMAIE
—
—
TMA3
TMA2
TMA1
TMA0
0
0
1
1
0
0
0
0
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Only 0 can be written, to clear the flag.
The timer register A (TMA) controls timer A interrupts and selects input clock.
Only bit 3 is explained here. For details of other bits, see section 11.2.1, Timer Mode Register A
(TMA). TMA is a readable/writable register which is initialized to H'30 by a reset.
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Section 4 Power-Down State
Bit 3⎯Clock Source, Prescaler Select (TMA3): Selects timer A clock source between PSS and
PSW. It also controls transition operation to the power-down mode. The operation mode to which
the MCU is transited after SLEEP instruction execution is determined by the combination with
other control bits.
For details, see the description of clock select 2 to 0 in section 11.2.1, Timer Mode Register A
(TMA).
Bit 3
TMA3
Description
0
•
Timer A counts φ-based prescaler (PSS) divided clock pulses
•
When a SLEEP instruction is executed in high-speed mode or medium-speed
mode, a transition is made to sleep mode or software standby mode
(Initial value)
•
Timer A counts φw-based prescaler (PSW) divided clock pulses
•
When a SLEEP instruction is executed in high-speed mode or medium-speed
mode, a transition is made to sleep mode, watch mode, or subactive mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made
to subsleep mode, watch mode, or high-speed mode
1
4.2.4
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control.
MSTPCR is initialized to H'FFFF by a reset.
MSTPCRH and MSTPCRL Bits 7 to 0⎯Module Stop (MSTP 15 to MSTP 0): These bits
specify module stop mode. See table 4.4 for the method of selecting on-chip supporting modules.
MSTPCRH, MSTPCRL
Bits 7 to 0
MSTP 15 to MSTP 0
Description
0
Module stop mode is cleared
1
Module stop mode is set
(Initial value)
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Section 4 Power-Down State
4.3
Medium-Speed Mode
When the SCK1 and SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode
changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU
operates on the operating clock (φ16, φ32 or φ64) specified by the SCK1 and SCK0 bits. The onchip supporting modules other than the CPU always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/16 is selected as the operating clock, on-chip
memory is accessed in 16 states, and internal I/O registers in 32 states.
Medium-speed mode is cleared by clearing the both bits SCK1 and SCK0 to 0. A transition is
made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR
are cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt,
medium-speed mode is restored.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, and the LSON bit in
LPWRCR and the TMA3 bit in TMA (Timer A) are both cleared to 0, a transition is made to
software standby mode. When standby mode is cleared by an external interrupt, medium-speed
mode is restored.
When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is
cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.
Figure 4.2 shows the timing for transition to and clearance of medium-speed mode.
Medium-speed mode
Internal φ,
supporting module clock
CPU clock
Internal address bus
SBYCR
SBYCR
Internal write signal
Figure 4.2 Medium-Speed Mode Transition and Clearance Timing
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Section 4 Power-Down State
4.4
Sleep Mode
4.4.1
Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR
are both cleared to 0, the CPU will enter sleep mode. In sleep mode, CPU operation stops but the
contents of the CPU's internal registers are retained. Other supporting modules (excluding some
functions) do not stop.
4.4.2
Clearing Sleep Mode
Sleep mode is cleared by any interrupt, or with the RES pin.
Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared and
interrupt exception handling is started. Sleep mode will not be cleared if interrupts are disabled, or
if interrupts other than NMI have been masked by the CPU.
Clearing with the RES Pin: When the RES pin is driven low, the reset state is entered. When the
RES pin is driven high after the prescribed reset input period, the CPU begins reset exception
handling.
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Section 4 Power-Down State
4.5
Module Stop Mode
4.5.1
Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules. When the corresponding
MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a
transition is made to module stop mode. The CPU continues operating independently.
Table 4.4 shows MSTP bits and the on-chip supporting modules.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating again at the end of the bus cycle. In module stop mode, the internal states of
modules excluding some modules are retained.
After reset release, all modules are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
Table 4.4
MSTP Bits and Corresponding On-Chip Supporting Modules
Register
Bit
Module
MSTPCRH
MSTP15
Timer A
MSTP14
Timer B
MSTPCRL
Note:
*
MSTP13
Timer J
MSTP12
Timer L
MSTP11
Timer R
MSTP10
Timer X1*
MSTP9
Sync separator
MSTP8
Serial communication interface 1 (SCI1)
MSTP7
2
I C bus interface (IIC0)*
MSTP6
MSTP5
I C bus interface (IIC1)
14-bit PWM*
MSTP4
8-bit PWM
MSTP3
Data slicer
MSTP2
A/D converter
MSTP1
Servo circuit, 12-bit PWM
MSTP0
OSD
2
This bit has no function in the H8S/2197S or H8S/2196S.
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Section 4 Power-Down State
4.6
Standby Mode
4.6.1
Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in
LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is cleared to 0, standby mode will
be entered. In this mode, the CPU, on-chip supporting modules, and oscillator (except for
subclock oscillator) all stop. However, the contents of the CPU's internal registers and data in the
on-chip RAM, as well as on-chip peripheral circuits (with some exceptions), are maintained in the
current state. (Timer X1 and SCI1 are partially reset.) The I/O port, at this time, is caused to the
high impedance state.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
4.6.2
Clearing Standby Mode
Standby mode is cleared by an external interrupt (pin IRQ0 to IRQ1), or by means of the RES pin.
Clearing with an Interrupt: When an IRQ0 to IRQ1 interrupt request signal is input, clock
oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable
clocks are supplied to the entire chip, standby mode is cleared, and interrupt exception handling is
started.
Standby mode cannot be cleared with an IRQ0 to IRQ1 interrupt if the corresponding enable bit
has been cleared to 0 or has been masked by the CPU.
Clearing with the RES Pin: When the RES pin is driven low, clock oscillation is started. At the
same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin
must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins
reset exception handling.
4.6.3
Setting Oscillation Settling Time after Clearing Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 10 ms (the
oscillation settling time).
Table 4.5 shows the standby times for different operating frequencies and settings of bits STS2 to
STS0.
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Section 4 Power-Down State
Table 4.5
Oscillation Settling Time Settings
STS2
STS1
STS0
Standby Time
10 MHz
8 MHz
Unit
0
0
0
8192 states
0.8
1.0
ms
1
16384 states
1.6
2.0
0
32768 states
3.3
4.1
1
65536 states
6.6
8.2
0
131072 states
1
13.1*
1
16.4*
1
262144 states
26.2
32.8
*
Reserved
⎯
⎯
1
1
0
1
Legend: * Don't care
Note: 1. Recommended time setting
Using an External Clock: Any value can be set.
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Section 4 Power-Down State
4.7
Watch Mode
4.7.1
Watch Mode
If a SLEEP instruction is executed in high-speed mode, medium-speed mode or subactive mode
when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3
bit in TMA (Timer A) is set to 1, the CPU will make a transition to watch mode.
In this mode, the CPU and all on-chip supporting modules except timer A stop. As long as the
prescribed voltage is supplied, the contents of CPU registers, some on-chip supporting module
registers, and on-chip RAM, are retained, and I/O ports are placed in the high-impedance state.
4.7.2
Clearing Watch Mode
Watch mode is cleared by an interrupt (Timer A interrupt, or pin IRQ0 to IRQ1), or by means of
the RES pin.
Clearing with an Interrupt: When an interrupt request signal is input, watch mode is cleared and
a transition is made to high-speed mode or medium-speed mode if the LSON bit in LPWRCR is
cleared to 0, or to subactive mode if the LSON bit is set to 1. When making a transition to
medium-speed mode, after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable
clocks are supplied to the entire chip, and interrupt exception handling is started.
Watch mode cannot be cleared with an IRQ0 to IRQ1 interrupt if the corresponding enable bit has
been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant
interrupt has been disabled by the interrupt enable register or masked by the CPU.
See section 4.6.3, Setting Oscillation Settling Time after Clearing Standby Mode, for the
oscillation settling time setting when making a transition from watch mode to high-speed mode or
medium-speed mode.
Clearing with the RES Pin: See Clearing with the RES Pin in section 4.6.2, Clearing Standby
Mode.
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Section 4 Power-Down State
4.8
Subsleep Mode
4.8.1
Subsleep Mode
If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0,
the LSON bit in LPWRCR is set to 1, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU
will make a transition to subsleep mode.
In this mode, the CPU and all on-chip supporting modules other than Timer A stop. As long as the
prescribed voltage is supplied, the contents of CPU registers, some on-chip supporting module
registers, and on-chip RAM, are retained, and I/O ports are placed in the high-impedance state.
4.8.2
Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (Timer A interrupt, or pin IRQ0 to IRQ5), or by means of
the RES pin.
Clearing with an Interrupt: When an interrupt request signal is input, subsleep mode is cleared
and interrupt exception handling is started. Subsleep mode cannot be cleared with an IRQ0 to
IRQ5 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting
module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable
register or masked by the CPU.
Clearing with the RES Pin: See (2) Clearing with the RES Pin in section 4.6.2, Clearing Standby
Mode.
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Section 4 Power-Down State
4.9
Subactive Mode
4.9.1
Subactive Mode
If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON
bit in LPWRCR, and the TMA3 bit in TMA (timer A) are all set to 1, the CPU will make a
transition to subactive mode. When an interrupt is generated in watch mode, if the LSON bit in
LPWRCR is set to 1, a transition is made to subactive mode. When an interrupt is generated in
subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU performs
sequential program execution at low speed on the subclock. In this mode, all on-chip supporting
modules other than timer A stop.
4.9.2
Clearing Subactive Mode
Subsleep mode is cleared by a SLEEP instruction, or by means of the RES pin.
Clearing with a SLEEP Instruction: When a SLEEP instruction is executed while the SSBY bit
in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (timer
A) is set to 1, subactive mode is cleared and a transition is made to watch mode. When a SLEEP
instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit in LPWRCR is
set to 1, and the TMA3 bit in TMA (timer A) is set to 1, a transition is made to subsleep mode.
When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit is
set to 1 and the LSON bit is cleared to 0 in LPWRCR, and the TMA3 bit in TMA (timer A) is set
to 1, a transition is made directly to high-speed or medium-speed mode.
For details of direct transition, see section 4.10, Direct Transition.
Clearing with the RES Pin: See Clearing with the RES Pin in section 4.6.2, Clearing Standby
Mode.
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Section 4 Power-Down State
4.10
Direct Transition
4.10.1
Overview of Direct Transition
There are three operating modes in which the CPU executes programs: high-speed mode, mediumspeed mode, and subactive mode. A transition between high-speed mode and subactive mode
without halting the program* is called a direct transition. A direct transition can be carried out by
setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction. After the transition,
direct transition interrupt exception handling is started.
Direct Transition from High-Speed Mode to Subactive Mode: If a SLEEP instruction is
executed in high-speed mode while the SSBY bit in SBYCR, the LSON bit and DTON bit in
LPWRCR, and the TMA3 bit in TMA (Timer A) are all set to 1, a transition is made to subactive
mode.
Direct Transition from Subactive Mode to High-Speed Mode/Medium-Speed Mode: If a
SLEEP instruction is executed in subactive mode while the SSBY bit in SBYCR is set to 1, the
LSON bit is cleared to 0 and the DTON bit is set to 1 in LPWRCR, and the TMA3 bit in TMA
(timer A) is set to 1, after the elapse of the time set in bits STS2 to STS0 in SBYCR, a transition is
made to directly to high-speed mode or medium-speed mode.
Note: * At the time of transition from subactive mode to high- or medium-speed mode, an
oscillation stabilization wait time is generated.
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Section 5 Exception Handling
Section 5 Exception Handling
5.1
Overview
5.1.1
Exception Handling Types and Priority
As table 5.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 5.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR.
Table 5.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES pin, or
when the watchdog timer overflows
Low
1
Trace*
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1
Interrupt
Starts when execution of the current instruction or exception
2
handling ends, if an interrupt request has been issued*
Direct transition
Started by a direct transition resulting from execution of a SLEEP
instruction
Trap instruction
3
(TRAPA)*
Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. (They cannot be used in
this LSI.) Trace exception handling is not executed after execution of an RTE
instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in the program
execution state.
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Section 5 Exception Handling
5.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:
1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack.
2. The interrupt mask bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
5.1.3
Exception Sources and Vector Table
The exception sources are classified as shown in figure 5.1. Different vector addresses are
assigned to different exception sources.
Table 5.2 lists the exception sources and their vector addresses.
• Reset
• Trace (cannot be used in this LSI)
External interrupts … NMI*, IRQ5 to IRQ0
Exception sources
• Interrupts
Internal interrupts … Interrupt sources in on-chip supporting modules
• Direct transition
• Trap instruction
Note: * In this LSI, the watchdog timer generates NMIs.
Figure 5.1 Exception Sources
Rev.2.00 Jan. 15, 2007 page 92 of 1174
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Section 5 Exception Handling
Table 5.2
Exception Vector Table
Exception Source
Vector Number
Vector Address*
Reset
0
H'0000 to H'0003
Reserved for system use
1
H'0004 to H'0007
2
H'0008 to H'000B
3
H'000C to H'000F
4
H'0010 to H'0013
Direct transition
NMI*
External interrupt
2
Trap instruction (4 sources)
Reserved for system use
Address trap
5
H'0014 to H'0017
6
H'0018 to H001B
7
H'001C to H'001F
8
H'0020 to H'0023
9
H'0024 to H'0027
10
H'0028 to H'002B
11
H'002C to H'002F
12
H'0030 to H'0033
13
H'0034 to H'0037
14
H'0038 to H'003B
15
H'003C to H'003F
#0
16
H'0040 to H'0043
#1
17
H'0044 to H'0047
#2
18
H'0048 to H'004B
19
H'004C to H'004F
Internal interrupt (IC)
Internal interrupt (HSW1)
20
H'0050 to H'0053
External interrupt
IRQ0
21
H'0054 to H'0057
IRQ1
22
H'0058 to H'005B
IRQ2
23
H'005C to H'005F
IRQ3
24
H'0060 to H'0063
IRQ4
25
H'0064 to H'0067
IRQ5
26
H'0068 to H'006B
Internal interrupt*
27
|
31
H'006C to H'006F
|
H'007C to H'007F
Reserved
32
|
33
H'0080 to H'0083
|
H'0084 to H'0087
34
|
67
H'0088 to H'008B
|
H'010C to H'010F
2
Internal interrupt*
3
1
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Section 5 Exception Handling
Notes: 1. Lower 16 bits of the address.
2. In this LSI, the watch dog timer generates NMIs.
3. For details on internal interrupt vectors, see section 6.3.3, Interrupt Exception Vector
Table.
5.2
Reset
5.2.1
Overview
A reset has the highest exception priority. When the RES pin goes low, all processing halts and the
LSI enters the reset state. A reset initializes the internal state of the CPU and the registers of onchip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset
exception handling begins when the RES pin changes from low to high.
The LSIs can also be reset by overflow of the watchdog timer. For details, see section 17,
Watchdog Timer (WDT).
5.2.2
Reset Sequence
The LSI enters the reset state when the RES pin goes low. To ensure that the chip is reset, hold the
RES pin low during the oscillation stabilizing time of the clock oscillator when powering on. To
reset the chip during operation, hold the RES pin low for at least 20 states. For pin states in a reset,
see appendix D, Port States in the Different Processing States.
When the RES pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
2. The reset exception vector address is read and transferred to the PC, and program execution
starts from the address indicated by the PC.
Figure 5.2 shows examples of the reset sequence.
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Section 5 Exception Handling
Vector
fetch
Internal
Fetch of first program
processing instruction
φ
RES
Internal address bus
(1)
(3)
Internal read signal
Internal write signal
High level
Internal data bus
(1)
(2)
(3)
(4)
(2)
(4)
: Reset exception vector address ((1) = H'0000 or H'000000)
: Start address (contents of reset exception vector address)
: Start address ((3) = (2))
: First program instruction
Figure 5.2 Reset Sequence (Mode 1)
5.2.3
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx:32, SP).
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Section 5 Exception Handling
5.3
Interrupts
Interrupt exception handling can be requested by six external sources (IRQ5 to IRQ0) and internal
sources in the on-chip supporting modules. Figure 5.3 shows the interrupt sources and the number
of interrupts of each type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
prescaler unit (PSU), Timers A, B, J, L, R and X1 (TMR), serial communication interface (SCI),
2
A/D converter (ADC), I C bus interface (IIC), servo circuits, sync detection, data slicer, OSD,
address trap, etc. Each interrupt source has a separate vector address. NMI is the highest-priority
interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two
interrupt control modes and can assign interrupts other than NMI to either three priority/mask
levels to enable multiplexed interrupt control. For details on interrupts, see section 6, Interrupt
Controller.
NMI*1 (1)
External
interrupts
IRQ5 to IRQ0 (6)
WDT*2 (1)
Interrupts
PSU (1)
TMR (15)*3
SCI (4)
Internal
interrupts
ADC (1)
IIC (3)*4
Servo circuits (9)
Synchronized detection (1)
Address trap (3)
Notes: Numbers in parentheses are the numbers of interrupt sources.
1. In this LSI, the watchdog timer generates NMIs.
2. When the watchdog timer is used as an interval timer, it generates an interrupt
request at each counter overflow.
3. The number of interrupt sources is eight in the H8S/2197S or H8S/2196S.
4. The number of interrupt sources is one in the H8S/2197S or H8S/2196S.
Figure 5.3 Interrupt Sources and Number of Interrupts
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Section 5 Exception Handling
5.4
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 5.3 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 5.3
Status of CCR and EXR after Trap Instruction Exception Handling
EXR*
CCR
Interrupt Control
Mode
I
UI
I2 to I0
T
0
1
⎯
⎯
⎯
1
1
1
⎯
⎯
Legend:
1:
Set to 1
0:
Cleared to 0
⎯:
Retains value prior to execution.
*:
Does not affect operation in this LSI.
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Section 5 Exception Handling
5.5
Stack Status after Exception Handling
Figures 5.4 and 5.5 show the stack after completion of trap instruction exception handling and
interrupt exception handling.
SP→
CCR
CCR*
PC
(16 bits)
Interrupt control modes 0 and 1
Note: * Ignored on return.
Figure 5.4 Stack Status after Exception Handling (Normal Mode)*
Note: * Normal mode is not available for this LSI.
SP→
CCR
PC
(24 bits)
Interrupt control modes 0 and 1
Figure 5.5 Stack Status after Exception Handling (Advanced Mode)
Rev.2.00 Jan. 15, 2007 page 98 of 1174
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Section 5 Exception Handling
5.6
Notes on Use of the Stack
When accessing word data or longword data, this chip assumes that the lowest address bit is 0.
The stack should always be accessed by word transfer instruction or longword transfer instruction,
and the value of the stack pointer (SP: ER7) should always be kept even.
Use the following instructions to save registers:
PUSH.W
Rn (or MOV.W Rn, @-SP)
PUSH.L
ERn (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.WRn (or MOV.W @SP+, Rn)
POP.LERn (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 5.6 shows an example of what
happens when the SP value is odd.
CCR
SP
R1L
H'FFFEFA
H'FFFEFB
SP
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFF
SP
TRAPA instruction executed
SP set to H'FFFEFF
Legend: CCR
PC
R1L
SP
MOV.B R1L, @-ER7
Data saved above SP
Contents of CCR lost
: Condition-code register
: Program counter
: General register R1L
: Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, is advanced mode.
Figure 5.6 Operation when SP Value Is Odd
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Section 5 Exception Handling
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REJ09B0329-0200
Section 6 Interrupt Controller
Section 6 Interrupt Controller
6.1
Overview
6.1.1
Features
This LSI controls interrupts by means of an interrupt controller. The interrupt controller has the
following features:
• Two Interrupt Control Modes
⎯ Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits
in the system control register (SYSCR).
• Priorities Settable with ICR
⎯ An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority
levels can be set for each module for all interrupts except NMI.
• Independent Vector Addresses
⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Six External Interrupt Pins
⎯ NMI is the highest-priority interrupt, and is accepted at all times.
⎯ Falling edge, rising edge, or both edge detection can be selected for interrupt IRQ0.
⎯ Falling edge or rising edge can be individually selected for interrupts IRQ5 to IRQ1.
Note: * In this LSI, the watch dog timer generates NMIs.
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Section 6 Interrupt Controller
6.1.2
Block Diagram
Figure 6.1 shows a block diagram of the interrupt controller.
INTM1, INTM0
SYSCR
Interrupt
request
Vector
number
IRQ input
IRQ input
unit IRQR
IEGR
IENR
Priority
determination
I, UI
CCR
Internal
interrupt
requests
CPU
ICR
Interrupt controller
Legend:
IEGR
: IRQ edge select register
IENR
: IRQ enable register
IRQR
: IRQ status register
ICR
: Interrupt control register
SYSCR : System control register
Figure 6.1 Block Diagram of Interrupt Controller
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Section 6 Interrupt Controller
6.1.3
Pin Configuration
Table 6.1 summarizes the pins of the interrupt controller.
Table 6.1
Interrupt Controller Pins
Name
Symbol
I/O
Function
External interrupt
request 0
IRQ0
Input
Maskable external interrupts; rising, falling, or both
edges can be selected
External interrupt
requests 1 to 5
IRQ1 to
IRQ5
Input
Maskable external interrupts: rising, or falling edges
can be selected
6.1.4
Register Configuration
Table 6.2 summarizes the registers of the interrupt controller.
Table 6.2
Interrupt Controller Registers
R/W
Initial Value
1
Address*
Name
Abbreviation
System control register
SYSCR
R/W
H'00
H'FFE8
IRQ edge select register
IEGR
R/W
H'00
H'FFF0
IRQ enable register
IENR
R/W
H'00
H'FFF1
IRQ status register
IRQR
R/ (W)*
H'00
H'FFF2
Interrupt control register A
ICRA
R/W
H'00
H'FFF3
Interrupt control register B
ICRB
R/W
H'00
H'FFF4
Interrupt control register C
ICRC
R/W
H'00
H'FFF5
Interrupt control register D
ICRD
R/W
H'00
H'FFF6
Port mode register 1
PMR1
R/W
H'00
H'FFCE
2
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
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Section 6 Interrupt Controller
6.2
Register Descriptions
6.2.1
System Control Register (SYSCR)
Bit :
7
—
6
—
5
INTM1
4
INTM0
3
XRST
2
—
1
—
0
—
Initial value :
0
—
0
—
0
R
0
R/W
1
R
0
—
0
—
0
—
R/W :
SYSCR is an 8-bit readable register that selects the interrupt control mode. Only bits 5, 4, 2 and 1
are described here; for details on the other bits, see section 3.2.2, System Control Register
(SYSCR). SYSCR is initialized to H'08 by a reset.
Bits 5 and 4⎯Interrupt Control Mode (INTM1, INTM0): These bits select one of two
interrupt control modes for the interrupt controller. The INTM1 bit must not be set to 1.
Bit 5
Bit 4
INTM1
INTM0
Interrupt Control
Mode
Description
0
0
0
Interrupts are controlled by I bit (Initial value)
1
1
Interrupts are controlled by I and UI bits and ICR
0
⎯
Cannot be used in this LSI
1
⎯
Cannot be used in this LSI
1
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Section 6 Interrupt Controller
6.2.2
Interrupt Control Registers A to D (ICRA to ICRD)
Bit :
7
ICR7
6
ICR6
5
ICR5
4
ICR4
3
ICR3
2
ICR2
1
ICR1
0
ICR0
Initial value :
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W :
The ICR registers are four 8-bit readable/writable registers that set the interrupt control level for
interrupts other than NMI.
The correspondence between ICR settings and interrupt sources is shown in table 6.3.
The ICR registers are initialized to H'00 by a reset.
Bits 7 to 0⎯Interrupt Control Level (ICR7 to ICR0): Set the control level for the
corresponding interrupt source.
Bit n
ICRn
Description
0
Corresponding interrupt source is control level 0 (non-priority)
1
Corresponding interrupt source is control level 1 (priority)
Note:
n = 7 to 0
Table 6.3
ICRA
ICRB
ICRC
ICRD
Note:
(Initial value)
*
Correspondence between Interrupt Sources and ICR Settings
ICRA7
ICRA6
ICRA5
ICRA4
ICRA3
ICRA2
ICRA1
ICRA0
Reserved
Input
capture
HSW1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
Sync
separator,
OSD
ICRB7
ICRB6
ICRB5
ICRB4
ICRB3
ICRB2
ICRB1
ICRB0
Data slicer Sync
separator
Servo
(drum,
capstan
latch)
Timer A
Timer B
Timer J
Timer R
Timer L
ICRC7
ICRC5
ICRC4
ICRC3
ICRC2
ICRC1
ICRC0
A/D
ICRD0
ICRC6
Timer X1*
Synchronized
detection
Watchdog
timer
Servo
IIC1
SCI1
(UART)
IIC0*
ICRD7
ICRD6
ICRD5
ICRD4
ICRD3
ICRD2
ICRD1
HSW2
Reserved
Reserved
Reserved
Reserved
Reserved Reserved Reserved
This bit has no function in the H8S/2197S or H8S/2196S.
Rev.2.00 Jan. 15, 2007 page 105 of 1174
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Section 6 Interrupt Controller
6.2.3
IRQ Enable Register (IENR)
Bit :
7
—
6
—
5
IRQ5E
4
IRQ4E
3
IRQ3E
2
IRQ2E
1
IRQ1E
0
IRQ0E
Initial value :
0
—
0
—
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W :
IENR is an 8-bit readable/writable register that controls enabling and disabling of interrupt
requests IRQ5 to IRQ0.
IENR is initialized to H'00 by a reset.
Bits 7 and 6⎯Reserved: These bits are always read as 0. Do not write 1 to them.
Bits 5 to 0⎯IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits select whether IRQ5 to
IRQ0 are enabled or disabled.
Bit n
IRQnE
Description
0
IRQn interrupt disabled
1
IRQn interrupt enabled
Note:
n = 5 to 0
Rev.2.00 Jan. 15, 2007 page 106 of 1174
REJ09B0329-0200
(Initial value)
Section 6 Interrupt Controller
6.2.4
IRQ Edge Select Registers (IEGR)
2
1
0
7
6
5
4
3
—
IRQ5EG
IRQ4EG
IRQ3EG
IRQ2EG
Initial value :
0
0
0
0
0
0
0
0
R/W :
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit :
IRQ1EG IRQ0EG1 IRQ0EG0
IEGR is an 8-bit readable/writable register that selects detected edge of the input at pins IRQ5 to
IRQ0. IEGR register is initialized to H'00 by a reset.
Bit 7⎯Reserved: This bit is always read as 0. Do not write 1 to it.
Bits 6 to 2⎯IRQ5 to IRQ1 Pins Detected Edge Select (IRQ5EG to IRQ1EG): These bits select
detected edge for interrupts IRQ5 to IRQ1.
Bits 6 to 2
IRQnEG
Description
0
Interrupt request generated at falling edge of IRQn pin input
Interrupt request generated at rising edge of IRQn pin input
1
Note:
(Initial value)
n = 5 to 1
Bits 1 and 0⎯IRQ0 Pin Detected Edge Select (IRQ0EG1, IRQ0EG0): These bits select
detected edge for interrupt IRQ0.
Bit 1
Bit 0
IRQ0EG1
IRQ0EG0
Description
0
0
Interrupt request generated at falling edge of IRQ0 pin input
(Initial value)
0
1
Interrupt request generated at rising edge of IRQ0 pin input
1
*
Interrupt request generated at both falling and rising edges of IRQ0 pin
input
Legend: * Don't care
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Section 6 Interrupt Controller
6.2.5
IRQ Status Register (IRQR)
Bit :
7
—
6
—
5
IRQ5F
4
IRQ4F
3
IRQ3F
2
IRQ2F
1
IRQ1F
0
IRQ0F
Initial value :
0
—
0
—
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
R/W :
Note: * Only 0 can be written, to clear the flag.
IRQR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt
requests.
IRQR is initialized to H'00 by a reset.
Bits 7 and 6⎯Reserved: These bits are always read as 0. Do not write 1 to them.
Bits 5 to 0⎯IRQ5 to IRQ0 Flags: These bits indicate the status of IRQ5 to IRQ0 interrupt
requests.
Bit n
IRQnF
Description
0
[Clearing conditions]
(Initial value)
(1) Cleared by reading IRQnF set to 1, then writing 0 in IRQnF
(2) When IRQn interrupt exception handling is executed
1
[Setting conditions]
(1) When a falling edge occurs in IRQn input while falling edge detection is set
(IRQnEG = 0)
(2) When a rising edge occurs in IRQn input while rising edge detection is set
(IRQnEG = 0)
(3) When a falling or rising edge occurs in IRQ0 input while both-edge detection is
set (IRQ0EG1 = 1)
Note:
n = 5 to 0
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Section 6 Interrupt Controller
6.2.6
Port Mode Register 1 (PMR1)
Bit :
Initial value :
R/W :
7
PMR17
6
PMR16
5
PMR15
4
PMR14
3
PMR13
2
PMR12
1
PMR11
0
PMR10
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port Mode Register 1 (PMR1) controls pin function switching-over of port 1. Switching is
specified for each bit.
PMR1 is an 8-bit readable/writable register and is initialized to H'00 by a reset.
Only bits 5 to 0 are explained here. For details, see section 10.3.2, Register Configuration.
Bits 5 to 0⎯P15/IRQ5 to P10/IRQ0 pin switching (PMR15 to PMR10): These bits are for
setting the P1n/IRQn pin as the input pin for P1n or as the IRQn pin for external interrupt request
input.
Bit n
PMR1n
Description
0
P1n/IRQn pin functions as the P1n input/output pin
1
P1n/IRQn pin functions as the IRQn input/output pin
Note:
(Initial value)
n = 5 to 0
Notes on switching the pin function by PMR1 are as follows:
• When the port is set as the IC input pin or IRQ5 to IRQ0 input pin, the pin level must be high
or low regardless of active mode or power-down mode. Do not set the pin level at medium.
• Switching the pin function of P16/IC or P15/IRQ5 to P10/IRQ0 may be mistakenly identified
as edge detection and detection signal may be generated. To prevent this, operate as follows:
⎯ Set the interrupt enable/disable flag to disable before switching the pin function.
⎯ Clear the applicable interrupt request flag to 0 after switching the pin function and
executing another instruction.
Rev.2.00 Jan. 15, 2007 page 109 of 1174
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Section 6 Interrupt Controller
Program example
:
MOV.B R0L,@IENR ⋅⋅⋅⋅⋅⋅ Interrupt disabled
MOV.B R1L,@PMR1 ⋅⋅⋅⋅⋅⋅ Pin function change
NOP
⋅⋅⋅⋅⋅⋅ Optional instruction
BCLR m @IRQR
⋅⋅⋅⋅⋅⋅ Applicable interrupt clear
MOV.B R1L,@IENR ⋅⋅⋅⋅⋅⋅ Interrupt enabled
:
6.3
Interrupt Sources
Interrupt sources comprise external interrupts (IRQ5 to IRQ0) and internal interrupts.
6.3.1
External Interrupts
There are six external interrupt sources; IRQ5 to IRQ0. Of these, IRQ1 to IRQ0 can be used to
restore this chip from standby mode.
• IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins
IRQ5 to IRQ0. Interrupts IRQ5 to IRQ0 have the following features:
(a) Using IEGR, it is possible to select whether an interrupt is requested by a falling edge,
rising edge, or both edges, at pin IRQ0.
(b) Using IEGR, it is possible to select whether an interrupt is requested by a falling edge or
rising edge at pins IRQ5 to IRQ1.
(c) Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IENR.
(d) The interrupt control level can be set with ICR.
(e) The status of interrupt requests IRQ5 to IRQ0 is indicated in IRQR. IRQR flags can be
cleared to 0 by software.
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Section 6 Interrupt Controller
Figure 6.2 shows a block diagram of interrupts IRQ5 to IRQ0.
IRQnE
IRQnEG
IRQnF
Edge detection
circuit
IRQn input
S
Q
IRQn interrupt
request
R
Note: n = 5 to 0
Clear signal
Figure 6.2 Block Diagram of Interrupts IRQ5 to IRQ0
Figure 6.3 shows the timing of IRQnF setting.
Internal φ
IRQn
input pin
IRQnF
Figure 6.3 Timing of IRQnF Setting
The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 26.
Upon detection of IRQ5 to IRQ0 interrupts, the applicable pin is set in the port register 1 (PMR1)
as IRQn pin.
Rev.2.00 Jan. 15, 2007 page 111 of 1174
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Section 6 Interrupt Controller
6.3.2
Internal Interrupts
There are 38 sources for internal interrupts from on-chip supporting modules.
• For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If any one of these is set to
1, an interrupt request is issued to the interrupt controller.
• The interrupt control level can be set by means of ICR.
• The NMI is the highest priority interrupt and is always accepted regardless of the control mode
and CPU interrupt mask bit. In this LSI, NMIs are used as interrupts generated by the
watchdog timer.
Rev.2.00 Jan. 15, 2007 page 112 of 1174
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Section 6 Interrupt Controller
6.3.3
Interrupt Exception Vector Table
Table 6.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.
Priorities among modules can be set by means of ICR. The situation when two or more modules
are set to the same priority, and priorities within a module, are fixed as shown in table 6.4.
Table 6.4
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Priority Interrupt Source
Origin of
Interrupt Source
Vector
No.
Vector Address
ICR
High
Reset
External pin
0
H'0000 to H'0003
⎯
Reserved
⎯
1
H'0004 to H'0007
⎯
⎯
2
H'0008 to H'000B
⎯
⎯
3
H'000C to H'000F
⎯
⎯
4
H'0010 to H'0013
⎯
⎯
5
H'0014 to H'0017
⎯
Direct transition
Instruction
6
H'0018 to H'001B
⎯
NMI
Watchdog timer
7
H'001C to H'001F
⎯
Instruction
8
H'0020 to H'0023
⎯
TRAPA#1
9
H'0024 to H'0027
⎯
TRAPA#2
10
H'0028 to H'002B
⎯
TRAPA#3
11
H'002C to H'002F
⎯
12
H'0030 to H'0033
⎯
13
H'0034 to H'0037
14
H'0038 to H'003B
15
H'003C to H'003F
Trap instruction
Reserved
TRAPA#0
⎯
Remarks
Low
Rev.2.00 Jan. 15, 2007 page 113 of 1174
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Section 6 Interrupt Controller
Priority Interrupt Source
High
Address trap
#0
Origin of
Interrupt Source
Vector
No.
Vector Address
ICR
ATC
16
H'0040 to H'0043
⎯
17
H'0044 to H'0047
#1
18
H'0048 to H'004B
IC
#2
PSU
19
H'004C to H'004F
ICRA6
HSW1
Servo circuit
20
H'0050 to H'0053
ICRA5
IRQ0
External pin
21
H'0054 to H'0057
ICRA4
IRQ1
22
H'0058 to H'005B
ICRA3
IRQ2
23
H'005C to H'005F
ICRA2
IRQ3
24
H'0060 to H'0063
IRQ4
25
H'0064 to H'0067
IRQ5
26
H'0068 to H'006B
External V interrupt
Sync separator
27
H'006C to H'006F
OSD V interrupt
OSD
28
H'0070 to H'0073
Data slicer odd field interrupt
Data slicer
29
H'0074 to H'0077
30
H'0078 to H'007B
Data slicer even field interrupt
ICRA0
ICRB7
Noise interrupt
Sync separator
31
H'007C to H'007F
ICRB6
Reserved
⎯
32
H'0080 to H'0083
⎯
33
H'0084 to H'0087
34
H'0088 to H'008B
35
H'008C to H'008F
Drum latch 1 (speed)
Servo circuit
Capstan latch 1 (speed)
ICRB5
TMAI
Timer A
36
H'0090 to H'0093
ICRB4
TMBI
Timer B
37
H'0094 to H'0097
ICRB3
TMJ1I
Timer J
38
H'0098 to H'009B
ICRB2
39
H'009C to H'009F
40
H'00A0 to H'00A3
41
H'00A4 to H'00A7
TMJ2I
TMR1I
Timer R
TMR2I
TMR3I
Low
ICRA1
TMLI
Timer L
Rev.2.00 Jan. 15, 2007 page 114 of 1174
REJ09B0329-0200
ICRB1
42
H'00A8 to H'00AB
43
H'00AC to H'00AF ICRB0
Remarks
Section 6 Interrupt Controller
Priority Interrupt Source
High
ICXA*
Vector Address
ICR
Timer X1*
ICRC7
44
H'00B0 to H'00B3
45
H'00B4 to H'00B7
ICXC*
46
H'00B8 to H'00BB
ICXD*
47
H'00BC to H'00BF
OCX1*
48
H'00C0 to H'00C3
OCX2*
49
H'00C4 to H'00C7
OVFX*
50
H'00C8 to H'00CB
51
H'00CC to H'00CF ICRC6
Sync signal
detection
Reserved
⎯
52
H'00D0 to H'00D3
8-bit interval timer
Watchdog timer
53
H'00D4 to H'00D7 ICRC5
CTL
Servo circuit
54
H'00D8 to H'00DB ICRC4
Drum latch 2 (speed)
55
H'00DC to H'00DF
Capstan latch 2 (speed)
56
H'00E0 to H'00E3
Drum latch 3 (phase)
57
H'00E4 to H'00D7
Capstan latch 3 (phase)
58
H'00E8 to H'00EB
IIC1
59
H'00EC to H'00EF ICRC3
SCI1
(UART)
60
H'00F0 to H'00F3
61
H'00F4 to H'00F7
TXI
62
H'00F8 to H'00FB
TEI
63
H'00FC to H'00FF
64
H'0100 to H'0103
65
H'0104 to H'0107
IIC1
SCI1
ERI
RXI
Note:
Vector
No.
ICXB*
VD interrupts
Low
Origin of
Interrupt Source
ICRC2
IIC0*
DDCSW*
IIC0*
A/D conversion end
A/D
66
H'0108 to H'010B
ICRC0
HSW2
Servo circuit
67
H'010C to H'010F
ICRD7
*
Remarks
ICRC1
Not available in the H8S/2197S or H8S/2196S.
Rev.2.00 Jan. 15, 2007 page 115 of 1174
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Section 6 Interrupt Controller
6.4
Interrupt Operation
6.4.1
Interrupt Control Modes and Interrupt Operation
Interrupt operations in this LSI differ depending on the interrupt control mode.
The NMI interrupt* and address trap interrupts are accepted at all times except in the reset state. In
the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for
each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request.
Interrupt sources in which the enable bits are set to 1 are controlled by the interrupt controller.
Table 6.5 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated
by the I and UI bits in the CPU’s CCR.
Note: * In this LSI, the NMI interrupt is generated by the watchdog timer.
Table 6.5
Interrupt Control Modes
Interrupt
Control
Mode
SYSCR
INTM1
0
0
1
INTM0
Priority
Setting
Register
Interrupt
Mask Bits
0
ICR
I
Interrupt mask control is
performed by the I bit
Priority can be set with ICR
1
ICR
I, UI
3-level interrupt mask control is
performed by the I and UI bits
Priority can be set with ICR
Rev.2.00 Jan. 15, 2007 page 116 of 1174
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Description
Section 6 Interrupt Controller
Figure 6.4 shows a block diagram of the priority decision circuit.
ICR
I
UI
Interrupt acceptance
control and 3-level
mask control
Interrupt source
Default priority
determination
Vector number
Interrupt control modes 0 and 1
Figure 6.4 Block Diagram of Interrupt Priority Determination Operation
• Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1,
interrupt acceptance control and 3-level mask control is performed by means of the I and UI
bits in CCR, and ICR (control level). Table 6.6 shows the interrupts selected in each interrupt
control mode.
Table 6.6
Interrupts Selected in Each Interrupt Control Mode
Interrupt Mask Bit
Interrupt Control
Mode
I
UI
Selected Interrupts
0
0
*
1
*
All interrupts (control level 1 has priority)
1
NMI* and address trap interrupts
0
*
1
0
All interrupts (control level 1 has priority)
1
NMI* , address trap and control level 1 interrupts
1
NMI* and address trap interrupts
1
1
Legend: * Don't care
Note: 1. In this LSI, the NMI interrupt is generated by the watchdog timer.
• Default Priority Determination: If the same value is set for ICR, acceptance of multiple
interrupts is enabled, and so only the interrupt source with the highest priority according to the
preset default priorities is selected and has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 6.7 shows operations and control signal functions in each interrupt control mode.
Rev.2.00 Jan. 15, 2007 page 117 of 1174
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Section 6 Interrupt Controller
Table 6.7
Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt Acceptance Control,
3-Level Control
Setting
Interrupt
Control Mode INTM1
INTM0
0
0
1
1
0
I
UI
ICR
Default Priority
Determination
{
IM
⎯
PR
{
{
IM
IM
PR
{
Legend:
{:
Interrupt operation control performed
IM:
Used as interrupt mask bit
PR:
Sets priority
⎯:
Not used
6.4.2
Interrupt Control Mode 0
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by
the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and
disabled when set to 1. Control level 1 interrupt sources have higher priority.
Figure 6.5 shows a flowchart of the interrupt acceptance operation in this case.
• If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
• When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
according to the control level set in ICR, has priority for selection, and other interrupt requests
are held pending. If a number of interrupt requests with the same control level setting are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 6.4 is selected.
• The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I
1
bit is set to 1, only an NMI* or an address trap interrupt is accepted, and other interrupt
requests are held pending.
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
• The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
• Next, the I bit in CCR is set to 1. This disables all interrupts except NMI* and address trap.
• A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Rev.2.00 Jan. 15, 2007 page 118 of 1174
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Section 6 Interrupt Controller
Note: * In this LSI, the NMI interrupt is generated by the watchdog timer.
Program execution state
No
Interrupt
generated?
Yes
Yes
NMI
No
Yes
Address trap
interrupt?
No
Control level 1
interrupt?
No
Hold pending
Yes
IC
No
No
IC
Yes
Yes
No
HSW1
HSW1
Yes
No
Yes
HSW2
HSW2
Yes
Yes
No
I=0
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 6.5 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Control Mode 0
Rev.2.00 Jan. 15, 2007 page 119 of 1174
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Section 6 Interrupt Controller
6.4.3
Interrupt Control Mode 1
Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts
by means of the I and UI bits in the CPU’s CCR and ICR.
• Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when
set to 1.
• Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and
disabled when both the I bit and the UI bit are set to 1.
For example, if the interrupt enable bit for an interrupt request is set to 1, and H'04, H'00, H'00 and
H'00 are set in ICRA, ICRB, ICRC and ICRD respectively, (i.e. IRQ2 interrupt is set to control
level 1 and other interrupts to control level 0), the situation is as follows:
• When I = 0, all interrupts are enabled
(Priority order: NMI > IRQ2 > IC > HSW1 > ...)
• When I = 1 and UI = 0, only NMI, address trap and IRQ2 interrupts are enabled
• When I = 1 and UI = 1, only NMI and address trap interrupts are enabled
Figure 6.6 shows the state transitions in these cases.
I←0
Only NMI, address trap and
IRQ2 interrupts enabled
All interrupts enabled
I ← 1, UI ← 0
I←0
Exception handling
execution or
I ← 1, UI ← 1
UI ← 0
Exception handling
execution or UI ← 1
Only NMI and address trap
interrupts enabled
Figure 6.6 Example of State Transitions in Interrupt Control Mode 1
Figure 6.7 shows an operation flowchart of interrupt reception.
Rev.2.00 Jan. 15, 2007 page 120 of 1174
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Section 6 Interrupt Controller
(1) If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
(2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
according to the control level set in ICR, has priority for selection, and other interrupt requests
are held pending. If a number of interrupt requests with the same control level setting are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 6.4 is selected.
(3) The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect.
An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If
the I bit is set to 1, only NMI* and address trap interrupts are accepted, and other interrupt
requests are held pending.
An interrupt request set to interrupt control level 1 has priority over an interrupt request set to
interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1 and
the UI bit is cleared to 0.
When both the I bit and the UI bit are set to 1, only NMI* and address trap interrupts are
accepted, and other interrupt requests are held pending.
(4) When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
(5) The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
(6) Next, the I and UI bits in CCR are set to 1. This masks all interrupts except NMI* and address
trap.
(7) A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Note: * In this LSI, the NMI interrupt is generated by the watchdog timer.
Rev.2.00 Jan. 15, 2007 page 121 of 1174
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Section 6 Interrupt Controller
Program execution state
No
Interrupt
generated?
Yes
Yes
NMI
No
Yes
Address trap
interrupt?
No
No
Control level 1
interrupt?
Hold pending
Yes
IC
No
No
IC
Yes
Yes
No
HSW1
HSW1
Yes
Yes
HSW2
HSW2
Yes
I=0
No
Yes
No
I=0
Yes Yes
UI = 0
No
No
Yes
Save PC and CCR
I ← 1, UI ← 1
Read vector address
Branch to interrupt handling routine
Figure 6.7 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Control Mode 1
Rev.2.00 Jan. 15, 2007 page 122 of 1174
REJ09B0329-0200
Instruction code (Not executed.)
Instruction prefetch address (Not executed.)
SP-2
SP-4
(2)(4)
(3)
(5)
(7)
(4)
(3)
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the
return address.)
(2)
(1)
(1)
Internal
data bus
Internal
write signal
Internal read
signal
Internal
address bus
Interrupt
request signal
φ
Instruction
prefetch
Internal
operation
Interrupt
acceptance
(6)
(5)
(8)
(7)
(6)(8)
(9)(11)
(10)(12)
(13)
(14)
Stack
(12)
(11)
Internal
operation
(14)
(13)
Interrupt handling routine
instruction prefetch
First instruction of interrupt handling routine
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
(10)
(9)
Vector fetch
6.4.4
Interrupt level
determination
Wait for end of
instruction
Section 6 Interrupt Controller
Interrupt Exception Handling Sequence
Figure 6.8 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control 0 is set in advanced mode, and the program area and stack area are in onchip memory.
Figure 6.8 Interrupt Exception Handling
Rev.2.00 Jan. 15, 2007 page 123 of 1174
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Section 6 Interrupt Controller
6.4.5
Interrupt Response Times
Table 6.8 shows interrupt response times-the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The symbols used in table
6.8 are explained in table 6.9.
Table 6.8
Interrupt Response Times
No.
Number of States
Advanced Mode
1
Interrupt priority determination*
2
Number of wait states until executing instruction ends*
3
PC, CCR stack save
2 ⋅ Sk
4
Vector fetch
2 ⋅ SI
5
3
Instruction fetch*
2 ⋅ SI
6
4
Internal processing*
2
1
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
Table 6.9
3
2
1 to 19 + 2⋅SI
12 to 32
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instruction.
Prefetch after interrupt acceptance and interrupt handling routine prefetch.
Internal processing after interrupt acceptance and internal processing after vector fetch.
Number of States in Interrupt Handling Routine Execution
Object of Access
Symbol
Internal Memory
Instruction fetch SI
1
Stack operation SK
1
Rev.2.00 Jan. 15, 2007 page 124 of 1174
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Section 6 Interrupt Controller
6.5
Usage Notes
6.5.1
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 6.9 shows an example in which the OCIAE bit in timer X1 TIER is cleared to 0.
TIER write cycle
by CPU
OCIA interrupt
exception handling
φ
Internal
address bus
TIER address
Internal
write signal
OCIAE
OCFA
OCIA
interrupt signal
Figure 6.9 Contention between Interrupt Generation and Disabling
Rev.2.00 Jan. 15, 2007 page 125 of 1174
REJ09B0329-0200
Section 6 Interrupt Controller
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
6.5.2
Instructions That Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
6.5.3
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1: EEPMOV.W
MOV.W
R4,R4
BNE
L1
Rev.2.00 Jan. 15, 2007 page 126 of 1174
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Section 7 ROM
Section 7 ROM
7.1
Overview
The H8S/2199R has 128 kbytes or 256 kbytes of on-chip ROM (flash memory or mask ROM), the
H8S/2198R has 112 kbytes, the H8S/2197R and H8S/2197S have 96 kbytes, and the H8S/2196R
and H8S/2196S have 80 kbytes*. The ROM is connected to the CPU by a 16-bit data bus. The
CPU accesses both byte and word data in one state, enabling faster instruction fetches and higher
processing speed.
The flash memory versions of the H8S/2199R can be erased and programmed on-board as well as
with a general-purpose PROM programmer.
Note: * For details on product line-up, refer to section 1, Overview.
7.1.1
Block Diagram
Figure 7.1 shows a block diagram of the ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000001
H'000002
H'000003
H'01FFFE
H'01FFFF
Figure 7.1 ROM Block Diagram (H8S/2199R)
Rev.2.00 Jan. 15, 2007 page 127 of 1174
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Section 7 ROM
7.2
Overview of Flash Memory
7.2.1
Features
The features of the flash memory are summarized below.
• Four flash memory operating modes
⎯ Program mode
⎯ Erase mode
⎯ Program-verify mode
⎯ Erase-verify mode
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in
single-block units). When erasing all blocks, the individual blocks must be erased sequentially.
Block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks. (In
OSD ROM, block erasing can be performed on 1-kbyte, 2-kbyte, and 28-kbyte blocks).
• Programming/erase times
The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming,
equivalent to 78 μs (typ.) per byte, and the erase time is 100 ms (typ.) per block.
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
⎯ Boot mode
⎯ User program mode
• Automatic bit rate adjustment
If data transfer on boot mode, automatic adjustment is possible at host transfer bit rates and
LSI's bit rates.
• Protect modes
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase/verify operations.
• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
Rev.2.00 Jan. 15, 2007 page 128 of 1174
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Section 7 ROM
7.2.2
Block Diagram
Figure 7.2 shows a block diagram of the flash memory.
Internal address bus
Internal data bus (16 bits)
STCR
Module bus
FLMCR1
FLMCR2
Bus interface/controller
Operating
mode
FWE pin
Mode pin
EBR1
EBR2
Flash memory
(OSD ROM)
(32 kbytes)
Flash memory
(256 kbytes)
Legend:
: Serial/timer control register
STCR
FLMCR1 : Flash memory control register 1
FLMCR2 : Flash memory control register 2
: Erase block register 1
EBR1
: Erase block register 2
EBR2
Figure 7.2 Block Diagram of Flash Memory (H8S/2199R Only)
Rev.2.00 Jan. 15, 2007 page 129 of 1174
REJ09B0329-0200
Section 7 ROM
7.2.3
Flash Memory Operating Modes
Mode Transitions
When each mode pin and the FWE pin are set in the reset state and a reset-start is executed, the
MCU enters one of the operating modes shown in figure 7.3. In user mode, flash memory can be
read but not programmed or erased.
Flash memory can be programmed and erased in boot mode, user program mode, and programmer
mode.
Reset state
RES = 0
0
On-board program mode
=
Boot mode
RES = 0
14
User
program
mode
FWE = 1, MD0 = 0,
P12 = P13 = P14 = 1
S
=
0
=0
,P
FWE = 0
or
SWE = 0
=0
1
0, =
= 13
D0 P
M 12 =
P
RES
User mode
FWE = 1
SWE = 1
WE
1, F
RE
=
MD1
Programmer
mode
Note: Only make a transition between user mode
and user program mode when the CPU is not
accessing the flash memory.
Figure 7.3 Flash Memory Mode Transitions
Rev.2.00 Jan. 15, 2007 page 130 of 1174
REJ09B0329-0200
Section 7 ROM
On-Board Programming Modes
• Boot mode
2. Writing control program transfer
1. Initial state
The flash memory is in the erased state when the
device is shipped. The description here applies to
the case where the old program version or data is
being rewritten. The user should prepare the
programming control program and new application
program beforehand in the host.
When boot mode is entered, the boot program in
this LSI chip (originally incorporated in the chip) is
started, and SCI communication check is carried
out, and the boot program required for flash memory
erasing is automatically transferred to the RAM boot
program area.
<Host>
<Host>
Programming control
program
Programming control
program
New application
program
New application
program
<This LSI>
<This LSI>
SCI
Boot program
<Flash memory>
<RAM>
SCI
Boot program
<Flash memory>
<RAM>
Boot program area
Application
program
(old version)
Application
program
(old version)
3. Flash memory initialization
4. Writing new application program
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
<Host>
The programming control program transferred from
the host to RAM by SCI communication is executed,
and the new application program in the host is
written into the flash memory.
<Host>
Programming control
program
New application
program
<This LSI>
<This LSI>
SCI
Boot program
<Flash memory>
<Flash memory>
<RAM>
<RAM>
Programming control
program
Boot program area
Flash memory erase
SCI
Boot program
New application
program
Program execution state
Figure 7.4 Boot Mode
Rev.2.00 Jan. 15, 2007 page 131 of 1174
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Section 7 ROM
• User program mode
1. Initial state
2. Programming/erase control program transfer
(1) The FWE assessment program that confirms that
the FWE pin has been driven high, and (2) the
program that will transfer the programming/erase
control program from the flash memory to on-chip RAM
should be written into the flash memory by the user
beforehand. (3) The programming/erase control
program should be prepared in the host or in the flash
memory.
When the FWE pin is driven high, user software
confirms this fact, executes the transfer program in the
flash memory, and transfers the programming/erase
control program to RAM.
<Host>
<Host>
Programming/erase control program
New application
program
New application
program
<This LSI>
<This LSI>
SCI
Boot program
<Flash memory>
<RAM>
<Flash memory>
FWE assessment program
Transfer program
SCI
Boot program
<RAM>
FWE assessment program
Transfer program
Programming/erase
control program
Application
program
(old version)
Application
program
(old version)
3. Flash memory initialization
4. Writing new application program
The programming/erase control program in RAM is
executed, and the flash memory is initialized (to H'FF).
Erasing can be performed in block units, but not in byte
units.
Next, the new application program in the host is written
into the erased flash memory blocks. Do not write to
unerased blocks.
<Host>
<Host>
New application
program
<This LSI>
<This LSI>
SCI
Boot program
<Flash memory>
<RAM>
FWE assessment program
Transfer program
SCI
Boot program
<Flash memory>
<RAM>
FWE assessment program
Transfer program
Programming/erase control program
Programming/erase control program
New application
program
Flash memory erase
Program execution state
Figure 7.5 User Program Mode (Example)
Rev.2.00 Jan. 15, 2007 page 132 of 1174
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Section 7 ROM
Differences between Boot Mode and User Program Mode
Boot Mode
User Program Mode
Entire memory erase
Yes
Yes
Block erase
No
Yes
Programming control program*
Program/program-verify
Erase/erase-verify
Program/program-verify
Note:
*
To be provided by the user, in accordance with the recommended algorithm.
Block Configuration
The main ROM area is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte
blocks. The OSD ROM area is divided into two 1-kbyte blocks, one 2-kbyte block, and one 28kbyte block.
Address H'00000
Address H'40000
1 kbyte
4 kbytes × 8
1 kbyte
32 kbytes
32 kbytes
256 kbytes
2 kbytes
64 kbytes
28 kbytes
64 kbytes
Address H'47FFF
OSD ROM area
64 kbytes
Address H'3FFFF
Main ROM area
Figure 7.6 Flash Memory Block Configuration
Rev.2.00 Jan. 15, 2007 page 133 of 1174
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Section 7 ROM
7.2.4
Pin Configuration
The flash memory is controlled by means of the pins shown in table 7.1.
Table 7.1
Flash Memory Pins
Pin Name
Abbreviation
I/O
Function
Reset
RES
Input
Reset
Flash write enable
FWE
Input
Flash program/erase protection by hardware
Mode 0
MD0
Input
Sets this LSI operating mode
Port 12
P12
Input
Sets this LSI operating mode when MD0 = 0
Port 13
P13
Input
Sets this LSI operating mode when MD0 = 0
Port 14
P14
Input
Sets this LSI operating mode when MD0 = 0
Transmit data
SO1
Output
Serial transmit data output
Receive data
SI1
Input
Serial receive data input
7.2.5
Register Configuration
Table 7.2 shows the registers used to control the flash memory when enabled. In order for these
registers to be accessed, the FLSHE bit must be set to 1 in STCR.
Table 7.2
Flash Memory Registers
Initial Value
Address*
R/W*
2
R/W*
2
H'00*
4
H'00*
H'FFF8
5
R/W*
2
H'00*
4
H'FFFA
5
R/W*
2
H'00*
4
H'FFFB
Register Name
Abbreviation
R/W
Flash memory control register 1
Flash memory control register 2
FLMCR1*
5
FLMCR2*
Erase block register 1
EBR1*
Erase block register 2
EBR2*
Serial/timer control register
STCR
5
Notes: 1.
2.
3.
4.
R/W
3
H'00
1
H'FFF9
H'FFEE
Lower 16 bits of the address.
When the FWE bit in FLMCR1 is not set at 1, writes are disabled.
When a high level is input to the FWE pin, the initial value is H'80.
When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
FLMCR1 is not set, these registers are initialized to H'00.
5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid
for these registers, the access requiring 2 states.
Rev.2.00 Jan. 15, 2007 page 134 of 1174
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Section 7 ROM
7.3
Flash Memory Register Descriptions
7.3.1
Flash Memory Control Register 1 (FLMCR1)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
FWE
SWE1
ESU1
PSU1
EV1
PV1
E1
P1
—*
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Determined by the state of the FWE pin.
FLMCR1 is an 8-bit register used for flash memory operating mode control. With addresses
H'00000 to H'3FFFF, program-verify mode or erase-verify mode is entered by setting SWE to 1
when FWE = 1, then setting the PV1 bit and EV1 bit. Program mode is entered by setting SWE1
when FWE = 1, then setting the SWE1 bit and PSU1, and finally setting the P1 bit. With addresses
H'00000 to H'3FFFF, erase mode is entered by setting SWE1 when FWE = 1, then setting the
ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a reset, in standby mode or
watch mode, when a low level is input to the FWE pin, and when a high level is input to the FWE
pin while the SWE1 bit in FLMCR1 is not set to 1. Its initial value is H'80 when a high level is
input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled,
a read will return H'00, and writes are invalid. Writes to the SWE1 bit in FLMCR1 are enabled
only when FWE = 1; writes to the ESU1, PSU1, EV1 and PV1 bits only when FWE = 1 and
SWE1 = 1; writes to the E1 bit only when FWE = 1, SWE1 = 1, and ESU1 = 1; and writes to the
P1 bit only when FWE = 1, SWE1 = 1, and PSU1 = 1.
Bit 7⎯Flash Write Enable (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7
FWE
Description
0
When a low level is input to the FWE pin (hardware-protected state)
1
When a high level is input to the FWE pin
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Section 7 ROM
Bit 6⎯Software Write Enable (SWE): Enables or disables flash memory programming. SWE
should be set before setting bits 5 to 0, bits 7 to 0 in EBR1, and bits 3 to 0 in EBR2.
Bit 6
SWE1
Description
0
Writes are disabled
1
Writes are enabled
(Initial value)
[Setting condition]
Setting is available when FWE = 1 is selected
Bit 5⎯Erase Set-Up 1 (ESU1): Prepares for erase mode. ESU1 should be set to 1 before setting
the E1 bit in FLMCR1 to 1. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same
time.
Bit 5
ESU1
Description
0
Erase set-up cleared
1
Transition to erase set-up mode
(Initial value)
[Setting condition]
Setting is available when FWE = 1 and SWE1 = 1 are selected
Bit 4⎯Program Set-Up 1 (PSU1): Prepares for program mode. PSU1 should be set to 1 before
setting the P1 bit in FLMCR1 to 1. Do not set the SWE1, ESU1, EV1, PV1, E1 or P1 bit at the
same time.
Bit 4
PSU1
Description
0
Program set-up cleared
1
Transition to program set-up mode
[Setting condition]
Setting is available when FWE = 1 and SWE1 = 1 are selected
Rev.2.00 Jan. 15, 2007 page 136 of 1174
REJ09B0329-0200
(Initial value)
Section 7 ROM
Bit 3⎯Erase-Verify (EV1): Selects erase-verify mode transition or clearing. Do not set the
SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time.
Bit 3
EV1
Description
0
Erase-verify mode cleared
1
Transition to erase-verify mode
(Initial value)
[Setting condition]
Setting is available when FWE = 1 and SWE1 = 1 are selected
Bit 2⎯Program-Verify (PV1): Selects program-verify mode transition or clearing. Do not set the
SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time.
Bit 2
PV1
Description
0
Program-verify mode cleared
1
Transition to program-verify mode
(Initial value)
[Setting condition]
Setting is available when FWE = 1 and SWE1 = 1 are selected
Bit 1⎯Erase (E1): Selects erase mode transition or clearing. Do not set the SWE1, ESU1, PSU1,
EV1, PV1, or P1 bit at the same time.
Bit 1
E1
Description
0
Erase mode cleared
1
Transition to erase mode
(Initial value)
[Setting condition]
Setting is available when FWE = 1, SWE1 = 1, and ESU1 = 1 are selected
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Section 7 ROM
Bit 0⎯Program (P1): Selects program mode transition or clearing (target address range :
H'00000 to H'3FFFF). Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time.
Bit 0
P1
Description
0
Program mode cleared
1
Transition to program mode
(Initial value)
[Setting condition]
Setting is available when FWE = 1, SWE1 = 1, and PSU1 = 1 are selected
7.3.2
Flash Memory Control Register 2 (FLMCR2)
Bit :
7
6
5
4
3
2
1
0
FLER
SWE2
ESU2
PSU2
EV2
PV2
E2
P2
Initial value :
0
0
0
0
0
0
0
0
R/W :
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FLMCR2 is an 8-bit register used for flash memory operating control mode.
With addresses H'40000 to H'47FFF, program-verify mode and erase-verify mode is entered by
setting SWE2 when FWE (FLMCR1) = 1, then setting the EV2 bit and the PV2 bit. Program mode
is entered by setting SWE2 when FWE (FLMCR1) = 1, then setting the SWE2 bit and PSU2 bit,
and finally setting the P2 bit.
With addresses H'40000 to H'47FFF, erase mode is entered by setting SWE2 when FWE
(FLMCR1) = 1, then setting the ESU2 bit , and finally setting the E2 bit. FLMCR2 is initialized to
H'00 by a reset, in standby mode or watch mode, when a low level is input to the FWE pin, and
when a high level is input to the FWE pin while the SWE2 bit in FLMCR2 is set to 1. FLER can
be initialized only by a reset.
Writes to the SWE2 bit in the FLMCR2 are enabled only when FWE (FLMCR1) = 1; writes to the
ESU2, PSV2, EV2, and PV2 bits only when FWE (FLMCR1) = 1 and SWE2 = 1; writes to the E2
bit only when FWE (FLMCR1) = 1, SW2 = 1, and ESU2 = 1; writes to the P2 bit only when FWE
(FLMCR1) = 1, SWE2 = 1, and PSU2 = 1.
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Section 7 ROM
Bit 7⎯Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state.
Bit 7
FLER
Description
0
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset
1
(Initial value)
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 7.6.3, Error Protection
Bit 6⎯Software Write Enable 2 (SWE2): Enables or disables flash memory programming
(target address range: H'40000 to H'47FFF). SW2 should be set when setting bits 5 to 0 and bits 7
to 4 in EBR2.
Bit 6
SWE2
Description
0
Writes are disabled
1
Writes are enabled
(Initial value)
[Setting condition]
Setting is available when FWE = 1 is selected
Bit 5⎯Erase Set-up 2 (ESU2): Prepares for erase mode. (Target address range: H'40000 to
H'47FFF). Do not set the PSU2, EV2, PV2, W2, P2 bits at the same time.
Bit 5
ESU2
Description
0
Erase set-up cleared
1
Transition to erase set-up mode
(Initial value)
[Setting condition]
Setting is enabled when FWE = 1 and SWE2 = 1 are selected
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Section 7 ROM
Bit 4⎯Program Set-up 2 (PSU2): Prepares for program mode (Target address rang: H'40000 to
H'47FFF). Do not set the ESU2, EV2, PV2, E2, P2 bits at the same time.
Bit 4
PSU2
Description
0
Program set-up cleared
1
Transition to program set-up mode
(Initial value)
[Setting condition]
Setting is enabled when FWE = 1 and SWE2 = 1 are selected
Bit 3⎯Erase-Verify 2 (EV2): Selects erase-verify mode transition or clearing (target address
range : H'40000 to H'47FFF). Do not set the ESU2, PSU2, PV2, E2, P2 bits at the same time.
Bit 3
EV2
Description
0
Erase-verify mode cleared
1
Transition to erase-verify mode
(Initial value)
[Setting condition]
Setting is available when FWE = 1 and SWE2 = 1 are selected
Bit 2⎯Program-Verify 2 (PV2): Selects program-verify mode transition or clearing (target
address range: H'40000 to H'47FFF). Do not set the ESU2, PSU2, EV2, E2, and P2 bits at the
same time.
Bit 2
PV2
Description
0
Program-verify mode cleared
1
Transition to program-verify mode
[Setting condition]
Setting is available when FWE = 1 and SWE2 = 1 are selected
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Section 7 ROM
Bit 1⎯Erase 2 (E2): Selects erase mode transition or clearing (target address range: H'40000 to
H'47FFF, do not set the ESU2, PSU2, EV2, PV2, and P2 bits at the same time.
Bit 1
E2
Description
0
Erase mode cleared
1
Transition to erase mode
[Setting condition]
Setting is available when FWE = 1, SWE2 = 1, and ESU2 = 1 are selected
Bit 0⎯Program 2 (P2): Selects program mode transition or clearing (target address range:
H'40000 to H'47FFF). Do not set the ESU2, PSU2, EV2, PV2, and E2 bits at the same time.
Bit 0
P2
Description
0
Program mode cleared
1
Transition to program mode
[Setting condition]
Setting is available when FWE = 1, SWE2 = 1, and PSU2 = 1 are selected
7.3.3
Erase Block Register 1 (EBR1)
Bit :
Initial value
R/W :
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR1 is an 8-bit register that specify the flash memory erase area block by block.
EBR1 is initialized to H'00 by a reset, in standby mode or watch mode, when a low level is input
to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is
not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are
erase-protected. Set only one bit in EBR1 and EBR2. More than one bit cannot be set. If set, all
bits are cleared to 0.
Table 7.3 shows the flash memory block configuration.
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Section 7 ROM
7.3.4
Erase Block Register 2 (EBR2)
Bit :
7
6
5
4
3
2
1
0
EB15
EB14
EB13
EB12
EB11
EB10
EB9
EB8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value :
R/W :
EBR2 is an 8-bit register that specify the flash memory erase area block by block; EBR2 is
initialized to H'00 by a reset, in standby mode or watch mode, and when a low level is input to the
FWE pin. Bits 3 to 0 are initialized to 0 when a high level is input to the FWE pin and the SWE1
in FLMCR1 is not set. Bits7 to 4 are initialized to 0 when the SWE2 in FLMCR2 is not set. When
a bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected.
Set only one bit in EBR1 and EBR2. More than one bit cannot be set. If set, all bits are cleared to
0.
The flash memory block configuration is shown in table 7.3.
Table 7.3
Flash Memory Erase Blocks
Block (Size)
Address
EB0 (4 kbytes)
H'000000 to H'000FFF
EB1 (4 kbytes)
H'001000 to H'001FFF
EB2 (4 kbytes)
H'002000 to H'002FFF
EB3 (4 kbytes)
H'003000 to H'003FFF
EB4 (4 kbytes)
H'004000 to H'004FFF
EB5 (4 kbytes)
H'005000 to H'005FFF
EB6 (4 kbytes)
H'006000 to H'006FFF
EB7 (4 kbytes)
H'007000 to H'007FFF
EB8 (32 kbytes)
H'008000 to H'00FFFF
EB9 (64 kbytes)
H'010000 to H'01FFFF
EB10 (64 kbytes)
H'020000 to H'02FFFF
EB11 (64 kbytes)
H'030000 to H'03FFFF
EB12 (1 kbyte)
H'040000 to H'0403FF
EB13 (1 kbyte)
H'040400 to H'0407FF
EB14 (2 kbytes)
H'040800 to H'040FFF
EB15 (28 kbytes)
H'041000 to H'047FFF
Rev.2.00 Jan. 15, 2007 page 142 of 1174
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Section 7 ROM
7.3.5
Serial/Timer Control Register (STCR)
Bit
:
Initial value
:
R/W
:
7
6
5
4
—
IICX1
IICX0
—
0
0
0
0
0
0
—
R/W
R/W
—
R/W
R/W
3
2
FLSHE OSROME
1
0
—
—
0
0
—
—
2
STCR is an 8-bit read/write register that controls the I C bus interface operating mode, on-chip
flash memory (in F-ZTAT versions), and OSD ROM. For details on IIC bus interface, refer to
2
section 23, I C Bus Interface (IIC). If a module controlled by STCR is not used, do not write 1 to
the corresponding bit. STCR is initialized to H'00 by a reset.
2
2
Bits 6 and 5⎯I C Control (IICX1, IICX0): These bits control the operation of the I C bus
2
interface. For details, see section 23, I C Bus Interface (IIC).
Bit 3⎯Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables
read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash
memory control registers are deselected. In this case, the flash memory control register contents
are retained.
Bit 3
FLSHE
Description
0
Flash memory control registers deselected
1
Flash memory control registers selected
(Initial value)
Bit 2⎯OSD ROM Enable (OSROME): Controls the OSD character data ROM (OSDROM)
access. When this bit is set to 1, the OSDROM can be accessed by the CPU, and when this bit is
cleared to 0, the OSDROM cannot be accessed by the CPU but accessed by the OSD module.
Before writing to or erasing the OSDROM in the F-ZTAT version, be sure to set this bit to 1.
Note: During OSD display, the OSDROM cannot be accessed by the CPU. Before accessing the
OSDROM by the CPU, be sure to clear the OSDON bit in the screen control register to 0
then set the OSROME bit to 1. If the OSROME bit is set to 1 during OSD display, the
character data ROM cannot be accessed correctly by CPU.
Bit 2
OSROME
Description
0
OSD ROM is accessed by the OSD
1
OSD ROM is accessed by the CPU
(Initial value)
Rev.2.00 Jan. 15, 2007 page 143 of 1174
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Section 7 ROM
Bits 7, 4, 1 and 0⎯Reserved: Always read as 0. Do not write 1 to these bits.
7.4
On-Board Programming Modes
When pins are set to on-board programming mode, program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
7.4. For a diagram of the transitions to the various flash memory modes, see figure 7.3.
Table 7.4
Setting On-Board Programming Modes
Mode
Pin
Mode Name
FWE
Boot mode
1
User program mode
1*
1
MD0
P12
P13
P14
0
1*
1*
1*
1
⎯
2
⎯
2
2
⎯
Notes: 1. In user program mode, the FWE pin should not be constantly set to 1. Set FWE to 1 to
make a transition to user program mode before performing a program/erase/verify
operation.
2. Can be used as I/O ports after boot mode is initiated.
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Section 7 ROM
7.4.1
Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
When a reset-start is executed after the LSI’s pins have been set to boot mode, the boot program
built into the LSI is started and the programming control program prepared in the host is serially
transmitted to the LSI via the SCI. In the LSI, the programming control program received via the
SCI is written into the programming control program area in on-chip RAM. After the transfer is
completed, control branches to the start address of the programming control program area and the
programming control program execution state is entered (flash memory programming is
performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
Figure 7.7 shows the system configuration in boot mode. Figure 7.8 shows the boot program mode
execution procedure.
This LSI
Flash memory
Host
Write data reception
Verify data
transmission
SI1
SCI1
On-chip RAM
SO1
Figure 7.7 System Configuration in Boot Mode
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Section 7 ROM
Start
Set pins to boot mode
and execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
The LSI measures low period
of H'00 data transmitted by host
The LSI calculates bit rate and
sets value in bit rate register
After bit rate adjustment, the LSI
transmits one H'00 data byte to
host to indicate end of adjustment
Host confirms normal reception
of bit rate adjustment end
indication (H'00), and transmits
one H'55 data byte
After receiving H'55,
LSI transmits one H'AA
data byte to host
Host transmits number
of programming control program
bytes (N), upper byte followed
by lower byte
The LSI transmits received
number of bytes to host as verify
data (echo-back)
n=1
Host transmits programming control
program sequentially in byte units
The LSI transmits received
programming control program to
host as verify data (echo-back)
n+1→n
Transfer received programming
control program to on-chip RAM
No
n = N?
Yes
End of transmission
Check flash memory data, and
if data has already been written,
erase all blocks
After confirming that all flash
memory data has been erased,
The LSI transmits one H'AA
data byte to host
Execute programming control
program transferred to on-chip RAM
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
Figure 7.8 Boot Mode Execution Procedure
Rev.2.00 Jan. 15, 2007 page 146 of 1174
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Section 7 ROM
Automatic SCI Bit Rate Adjustment
Start
bit
D0
D1
D2
D3
D4
D5
D6
Low period (9 bits) measured (H'00 data)
D7
Stop
bit
High period
(1 or more bits)
Figure 7.9 Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the LSI measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host's transmission bit rate and the LSI system clock frequency, there will be a
discrepancy between the bit rates of the host and the LSI. To ensure correct SCI operation, the
host's transfer bit rate should be set to (4800, 9600, 19200) bps.
Table 7.5 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the LSI’s bit rate is possible. The boot program should be executed within this
system clock range.
Table 7.5
System Clock Frequencies for which Automatic Adjustment of This LSI Bit
Rate Is Possible
Host Bit Rate (bps)
System Clock Frequency
4800
8 MHz to 10 MHz
9600
8 MHz to 10 MHz
19200
8 MHz to 10 MHz
Rev.2.00 Jan. 15, 2007 page 147 of 1174
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Section 7 ROM
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2048-byte area from
H'FFDFB0 to H'FFE7AF is reserved for use by the boot program, as shown in figure 7.10. The
area to which the programming control program is transferred is H'FFE7B0 to H'FFFFAF (6144
bytes). The boot program area can be used when the programming control program transferred
into RAM enters the execution state. A stack area should be set up as required.
H'FFDFB0
Boot program
area*
(2048 bytes)
H'FFE7AF
Programming
control program
area
(6144 bytes)
H'FFFFAF
Note: * The boot program area cannot be used until a transition is made to the execution
state for the programming control program transferred to RAM. Note that the boot
program reamins stored in this area after a branch is made to the programming
control program.
Figure 7.10 RAM Areas in Boot Mode
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Section 7 ROM
Notes on Use of Boot Mode:
1. When the LSI comes out of reset in boot mode, it measures the low period of the input at the
SCI's SI1 pin. The reset should end with SI1 pin high. After the reset ends, it takes about 100
states for the LSI to get ready to measure the low period of the SI1 pin input.
2. In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The SI1 and SO1 pins should be pulled up on the board.
5. Before branching to the programming control program (H'FFE7B0 in RAM area), the LSI
terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE
and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data
output pin, SO1, goes to the high-level output state (P21PCR = 1, P21PDR = 1).
The contents of the CPU's internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control program.
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area
must be specified for use by the programming control program.
The initial values of other on-chip registers are not changed.
6. Boot mode can be entered by making the pin settings shown in table 7.4 and executing a resetstart.
When the LSI detects the boot mode setting at reset release*, it retains that state internally.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
the FWE pin and mode pins, and executing reset release*. Boot mode can also be cleared by a
WDT overflow reset.
If the mode pin input levels are changed in boot mode, the boot mode state will be maintained
in the microcomputer, and boot mode continued, unless a reset occurs. However, the FWE pin
must not be driven low while the boot program is running or flash memory is being
programmed or erased.
Note: * Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4
states) with respect to the reset release timing.
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Section 7 ROM
7.4.2
User Program Mode
When set to user program mode, the LSI can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing on-board means of FWE control and supply of
programming data, and storing a program/erase control program in part of the program area as
necessary.
In this mode, the LSI starts up in mode 1 and applies a high level to the FWE pin. The flash
memory itself cannot be read while the SWE1 bit is set to 1 to perform programming or erasing,
so the control program that performs programming and erasing should be run in on-chip RAM or
external memory.
Figure 7.11 shows the procedure for executing the program/erase control program when
transferred to on-chip RAM.
Write the FWE assessment program and
transfer program (and the program/erase
control program if necessary) beforehand
MD0 = 1
Reset start
Transfer program/erase
control program to RAM
Branch to program/erase control
program in RAM area
FWE = high
Execute program/erase control
program (flash memory rewriting)
Clear FWE
Branch to flash memory
application program
Note:
Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only
when the flash memory is programmed or erased. Also, while a high level is applied to the
FWE pin, the watchdog timer should be activated to prevent overprogramming or
overerasing due to program runaway, etc.
Figure 7.11 User Program Mode Execution Procedure
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Section 7 ROM
7.5
Programming/Erasing Flash Memory
In the on-board programming modes, flash memory programming and erasing is performed by
software, using the CPU. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. With addresses H'00000 to H'3FFFF,
transitions to these modes can be made by setting the PSU1, ESU1, P1, E1, PV1 and EV1 bits in
FLMCR1. With addresses H'40000 to H'47FFF, transitions to these modes can be made by setting
the PSU2, ESU2, P2, E2, PV2, and EV2 bits in the FLMCR2.
The flash memory cannot be read while being programmed or erased. Therefore, the program that
controls flash memory programming/erasing (the programming control program) should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE1, ESU1, PSU1, EV1, PV1,
E1, and P1 bits in FLMCR1, and the SWE2, ESU2, PSU2, EV2, PV2, E2, and P2 in
FLMCR2, is executed by a program in flash memory.
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
3. Perform programming in the erased state. Do not perform additional programming on
previously programmed addresses.
4. Do not write to addresses H'00000 to H'3FFFF and H'40000 to H'47FFF at the same
time. Otherwise operation cannot be guaranteed.
5. Do not operate the OSD when writing or erasing addresses H'40000 to H'47FFF. Do
not set the OSROME in STCR to 1 before manipulating the flash control register.
7.5.1
Program Mode (n = 1 when the Target Address Range Is H'00000 to H'3FFFF and
n = 2 when the Target Address Range Is H'40000 to H'47FFF)
Follow the procedure shown in the program/program-verify flowchart in figure 7.12 to write data
or programs to flash memory. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a
time.
Following the elapse of 1.0 μs or more after the SWEn bit is set to 1 in flash memory control
register n (FLMCRn), 128-byte program data is stored in the program data area and reprogram
data area, and the 128-byte data in the reprogram data area written consecutively to the write
addresses. The lower 8 bits of the start address written to must be H'00, or H'80. One hundred and
twenty-eight consecutive byte data transfers are performed. The program address and program
data are latched in the flash memory. A 128-byte data transfer must be performed even if writing
fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Rev.2.00 Jan. 15, 2007 page 151 of 1174
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Section 7 ROM
Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup)
is carried out by setting the PSUn bit in FLMCRn, and after the elapse of 50 μs or more, the
operating mode is switched to program mode by setting the Pn bit in FLMCRn. The time during
which the Pn bit is set is the flash memory programming time. Make a program setting for one
programming operation using the table in the programming flowchart.
7.5.2
Program-Verify Mode (n = 1 when the Target Address Range Is H'00000 to
H'3FFFF and n = 2 when the Target Address Range Is H'40000 to H'47FFF)
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the Pn bit in
FLMCRn is cleared, then the PSUn bit is cleared at least 5 μs later). The watchdog timer is cleared
after the elapse of 5 μs or more, and the operating mode is switched to program-verify mode by
setting the PVn bit in FLMCRn. Before reading in program-verify mode, a dummy write of H'FF
data should be made to the addresses to be read. The dummy write should be executed after the
elapse of 4 μs or more. When the flash memory is read in this state (verify data is read in 16-bit
units), the data at the latched address is read. Wait at least 2 μs after the dummy write before
performing this read operation. Next, the originally written data is compared with the verify data,
and reprogram data is computed (see figure 7.12) and transferred to the reprogram data area. After
128 bytes of data have been verified, exit program-verify mode, wait for at least 2 μs, then clear
the SWEn bit in FLMCRn. If reprogramming is necessary, set program mode again, and repeat the
program/program-verify sequence as before. However, ensure that the program/program-verify
sequence is not repeated more than 1,000 times on the same bits.
Rev.2.00 Jan. 15, 2007 page 152 of 1174
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Section 7 ROM
Start of programming
Start
Set SWE1 (2) bit in FLMCR(2)
tsswe: Wait 1 µs
Write pulse application subroutine
Store 128-byte program data in program
data area and reprogram data area
Programming pulse apply subroutine
*4
Enable WDT
n=1
Set PSU1 (2) bit in FLMCR1 (2)
m=0
tspsu: Wait 50 µs
Write 128-byte program data in RAM reprogram
data area consecutevely to flash memory
Set P1 (2) bit in FLMCR1 (2)
tsp10 or tsp30 or tsp200:
Wait 10 µs or 30 µs or 200 µs
Call subroutine
Programming pulse 30 µs or 200 µs
*5
*1
Refer to note *6
for the pulse width
Set PV1(2) bit in FLMCR1(2)
Clear P1(2) bit in FLMCR1 (2)
tspv: Wait 4 µs
tcp: Wait 5 µs
H'FF dummy write to verify address
Clear PSU1(2) bit in FLMCR1 (2)
Increment address
tcpsu: Wait 5 µs
tspvr: Wait 2 µs
Disable WDT
n ←n + 1
*2
Read verify data
End of subroutine
Note: 6. Programming pulse width
Program data = verify data?
Number of times
of programming
Programming
time (z) µs
1
2
3
4
5
6
7
8
9
10
11
12
13
30
30
30
30
30
30
200
200
200
200
200
200
200
998
999
1000
200
200
200
NG
m=1
OK
NG
6 ≥ n?
OK
Calculate additional program data
Transfer additional program data to additional program data area *4
Calculate reprogram data
*3
Transfer reprogram data to reprogram data area
*4
NG
Complete 128-byte
data verification?
OK
Clear PV1(2) bit in FLMCR1(2)
tcpv: Wait 2 µs
The programming pulse must be 10 µs in
additional programming
NG
6≥n?
OK
RAM
Write 128-byte program data in RAM additional
data area consecutively to flash memory
Program data storage are
(128 bytes)
*1
Call subroutine
Write pulse additional program pulse 10 µs
Reprogram data storage
area (128 bytes)
m = 0?
NG
n ≥ 1000?
OK
Clear SWE1(2) bit in FLMCR1(2)
Additional program data
storage area (128 bytes)
NG
OK
Clear SWE1 (2) bit in FLMCR1(2)
tcswe: Wait 100 µs
tcwe: Wait 100 µs
End of programming
Programming Failure
Perform programming after erasing data. Do not perform additional programming to addresses that have already been written to.
Notes: 1. Data transfer is performed by byte transfer. The lower eight bits of the start address must be H'00 or H'80. A 128-byte data transfer must be performed even if writing
fewer than 128 bytes: in this case, H'FF must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even in case of the bit which is already-programmed in the 128-byte programming loop, perform additional programming if the bit fails at the next verify.
4. An area for storing program data (128 bytes), reprogram data (128 bytes), and additional program (128bytes) must be provided in RAM. The contents of the reprogram
and additional program areas are rewritten as programming processes.
5. A 30 µs or 200 µs programming pulse must be applied.
For details on programming pulse, refer to Note 6.
To perform additional data programming, apply a programming pulse of 10 µs. Reprogram data X' is the reprogram data after program pulse is applied.
Reprogram Data Calculation Table
Source Data (D) Verify data (V) Reprogram data (X)
0
1
0
0
0
1
1
1
0
1
1
1
Comments
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Additiona l program data calculation table
Reprogram data (X') Verify data (V) Additional program data (Y)
Comments
0
0
0
Additional programming performed
1
0
1
Additional programming not performed
1
1
0
1
1
1
Additional programming not performed
Figure 7.12 Program/Program-Verify Flowchart
Rev.2.00 Jan. 15, 2007 page 153 of 1174
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Section 7 ROM
7.5.3
Erase Mode (n = 1 when the Target Address Range Is H'00000 to H'3FFFF and n =
2 when the Target Address Range Is H'40000 to H'47FFF)
Flash memory erasing should be performed block by block following the procedure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 7.13.
To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in
erase block register 1 or 2 (EBR1 or EBR2) at least 1 μs after setting the SWEn bit to 1 in flash
memory control register n (FLMCRn). Next, the watchdog timer is set to prevent overerasing in
the event of program runaway, etc.
Set more than 19.8 ms as the WDT overflow period. After this, preparation for erase mode (erase
setup) is carried out by setting the ESUn bit in FLMCRn, and after a elapse of 100 μs or more, the
operating mode is switched to erase mode by setting the En bit in FLMCRn. The time during
which the En bit is set is the flash memory erase time. Ensure that erase time does not exceed 10
ms.
Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased
to 0) is not necessary before starting the erase procedure.
Rev.2.00 Jan. 15, 2007 page 154 of 1174
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Section 7 ROM
START
*1
Set SWE1 (2) bit in FLMCR1 (2)
tsswe: Wait 1 µs
n=1
Set EBR1 (2)
*3
Enable WDT
Set ESU1 (2) bit in FLMCR1 (2)
tsesu: Wait 100 µs
Set E1 (2) bit in FLMCR1 (2)
tse: Wait 10 ms
Clear E1 (2) bit in FLMCR1 (2)
tce: Wait 10 µs
Clear ESU1 (2) bit in FLMCR1 (2)
tcesu: Wait 10 µs
Disable WDT
Set EV1 (2) bit in FLMCR1 (2)
tsev: Wait 20 µs
n←n+1
Set block start address to
verify address
H'FF dummy write to verify address
tsevr: Wait 2 µs
Read verify data
Increment
address
Verify data = all 1?
*2
NO
YES
NO
Last address
of block?
YES
Clear EV1 (2) bit in FLMCR1 (2)
Clear EV1 (2) bit in FLMCR1 (2)
tcev: Wait 4 µs
tcev: Wait 4 µs
NO
*4
*5
End of erasing of
all erase blocks?
YES
Notes: 1.
2.
3.
4.
5.
n ≥ (N)?
NO
YES
Clear SWE1 (2) bit in FLMCR1 (2)
Clear SWE1 (2) bit in FLMCR1 (2)
tcswe: Wait 100 µs
tcswe: Wait 100 µs
End of erasing
Erase failure
Preprogramming (setting erase block data to all 0) is not necessary.
Verify data is read in 16-bit (word) units.
Set only one bit in EBR. More than two bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
For the value of N, see table 31.32, Flash Memory Characteristics.
Figure 7.13 Erase/Erase-Verify Flowchart
Rev.2.00 Jan. 15, 2007 page 155 of 1174
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Section 7 ROM
7.5.4
Erase-Verify Mode (n = 1 when the Target Address Range Is H'00000 to H'3FFFF
and n = 2 when the Target Address Range Is H'40000 to H'47FFF)
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the En bit in FLMCRn is cleared, then the
ESUn bit is cleared at least 10 μs later), the watchdog timer is cleared after the elapse of 10 μs or
more, and the operating mode is switched to erase-verify mode by setting the EVn bit in
FLMCRn. Before reading in erase-verify mode, a dummy write of H'FF data should be made to
the addresses to be read. The dummy write should be executed after the elapse of 6.0 μs or more.
When the flash memory is read in this state (verify data is read in 16-bit units), the data at the
latched address is read. Wait at least 2 μs after the dummy write before performing this read
operation. If the read data has been erased (all 1), a dummy write is performed to the next address,
and erase-verify is performed. If the read data has not been erased, set erase mode again, and
repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/eraseverify sequence is not repeated more than 100 times. When verification is completed, exit eraseverify mode, and wait for at least 4 μs. If erasure has been completed on all the erase blocks, clear
the SWEn bit in FLMCRn. If there are any unerased blocks, make a 1 bit setting for the flash
memory area to be erased, and repeat the erase/erase-verify sequence in the same way.
Rev.2.00 Jan. 15, 2007 page 156 of 1174
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Section 7 ROM
7.6
Flash Memory Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
7.6.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1
and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 7.6.)
In error protected state, the FLMCR1, FLMCR2, EBR1, and EBR2 settings are maintained.
Table 7.6
Hardware Protection
Functions
Item
Description
Program
Erase
FWE pin
protection
•
When a low level is input to the FWE pin, FLMCR1, Yes
FLMCR2 (excluding the FLER bit), EBR1, and EBR2
are initialized, and the program/erase-protected state
is entered
Yes
Reset/standby
protection
•
In a reset (including a WDT overflow reset) and in
standby mode or watch mode, FLMCR1, FLMCR2,
EBR1, and EBR2 are initialized, and the
program/erase-protected state is entered
Yes
Yes
•
In a reset via the RES pin, the reset state is not
entered unless the RES pin is held low until
oscillation stabilizes after powering on. In the case of
a reset during operation, hold the RES pin low for
the RES pulse width specified in the AC
characteristics
Rev.2.00 Jan. 15, 2007 page 157 of 1174
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Section 7 ROM
7.6.2
Software Protection
Software protection can be implemented by setting the SWE1 bit in FLMCR1 and SWE2 bit in
FLMCR2 and erase block registers 1 and 2 (EBR1, EBR2). When software protection is in effect,
setting the P1 or E1 bit in flash memory control register 1 (FLMCR1) or P2 or E2 bit in flash
memory control register 2 (FLMCR2) does not cause a transition to program mode or erase mode.
(See table 7.7.)
Table 7.7
Software Protection
Functions
Item
Description
Program
Erase
SWE bit
protection
•
Clearing the SWE bit to 0 in FLMCR1 sets the
program/erase-protected state for all blocks
(Execute in on-chip RAM or external memory)
Yes
Yes
Block
specification
protection
•
Erase protection can be set for individual blocks by
settings in erase block registers 1 and 2 (EBR1,
EBR2)
⎯
Yes
•
Setting EBR1 and EBR2 to H'00 places all blocks in
the erase-protected state
7.6.3
Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing. If the MCU
malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and
the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are
retained, but program mode or erase mode is aborted at the point at which the error occurred.
Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV1,
PV2, EV1 and EV2 bit setting is enabled, and a transition can be made to verify mode. FLER bit
setting conditions are as follows:
• When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (including standby) is executed during programming/erasing
Rev.2.00 Jan. 15, 2007 page 158 of 1174
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Section 7 ROM
Error protection is released only by a reset and in hardware standby mode.
Figure 7.14 shows the flash memory state transition diagram.
Program mode
Erase mode
Reset
(hardware protection)
RES = 0
RD VF PR ER FLER = 0
Error occurrence
E
(S rror
lee oc
p i cur
ns re
tru nc
cti e
on
)
Error protection mode
RD VF PR ER FLER = 1
RD VF PR ER FLER = 0
S
RE
=0
Power-down mode
Power-down mode release
Error protection
mode (power-down mode)
RD VF PR ER FLER = 1
FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2
initialization state
Legend:
RD: Memory read possible
VF : Verify-read possible
PR : Programming possible
ER : Erasing possible
RES = 0
FLMCR1, FLMCR2,
EBR1, EBR2 initialization
state
RD: Memory read impossible
VF : Verify-read impossible
PR : Programming impossible
ER : Erasing impossible
Figure 7.14 Flash Memory State Transitions
7.7
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts are disabled when flash memory is being programmed or erased (when the P1 or E1
bit is set in FLMCR1, or the P2 or E2 bit is set in FLMR2), and while the boot program is
1
executing in boot mode* , to give priority to the program or erase operation. There are three
reasons for this:
• Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
• In the interrupt exception handling sequence during programming or erasing, the vector would
2
not be read correctly* , possibly resulting in MCU runaway.
• If interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
Rev.2.00 Jan. 15, 2007 page 159 of 1174
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Section 7 ROM
For these reasons, in on-board programming mode alone there are conditions for disabling
interrupt, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All requests must therefore be disabled inside and
outside the MCU during FWE application. Interrupt is also disabled in the error-protection state
while the P1 or E1 bit remains set in FLMCR1, or the P2 or E2 bit remains set in FLMCR2.
Notes: 1. Interrupt requests must be disabled inside and outside the MCU until data write by the
write control program is complete.
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased (while the P or E bit is
set in FLMCR1 or FLMCR2), correct read data will not be obtained (undetermined
values will be returned).
• If the interrupt entry in the interrupt vector table has not been programmed yet,
interrupt exception handling will not be executed correctly.
7.8
Flash Memory Programmer Mode
7.8.1
Programmer Mode Setting
Programs and data can be written and erased in programmer mode as well as in the on-board
programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported with these device types. In auto-program mode,
auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode,
detailed internal signals are output after execution of an auto-program or auto-erase operation.
7.8.2
Socket Adapters and Memory Map
In programmer mode, a socket adapter is mounted on the PROM programmer. The socket adapter
product codes are listed in table 7.8.
Figure 7.15 shows the memory map in programmer mode.
Table 7.8
Socket Adapter Product Codes
Part No.
Package
Socket Adapter Product Code
HD64F2199R
112-pin QFP
ME2199ESHF1H
(Minato Electronics)
Rev.2.00 Jan. 15, 2007 page 160 of 1174
REJ09B0329-0200
Section 7 ROM
H8S/2199R
MCU mode
H'000000
Programmer mode
H'00000
On-chip ROM area
H'047FFF
H'47FFF
Figure 7.15 Memory Map in Programmer Mode
7.8.3
Programmer Mode Operation
Table 7.9 shows how the different operating modes are set when using programmer mode, and
table 7.10 lists the commands used in programmer mode. Details of each mode are given below.
• Memory Read Mode: Memory read mode supports byte reads.
• Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time.
Status polling is used to confirm the end of auto-programming.
• Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory.
Status polling is used to confirm the end of auto-erasing.
• Status Read Mode: Status polling is used for auto-programming and auto-erasing, and normal
termination can be confirmed by reading the IO6 signal. In status read mode, error information
is output if an error occurs.
Table 7.9
Settings for Each Operating Mode in Programmer Mode
Pin Names
Mode
CE
FWE
OE
WE
IO0 to IO7
A0 to A18
Read
H or L
L
L
H
Data output
Ain
Output disable
H or L
L
H
H
Hi-Z
X
Command write
1
Chip disable*
H or L*
L
H
L
Data input
Ain*
H
X
X
Hi-Z
X
H or L
3
2
Notes: 1. Chip disable is not a standby state; internally, it is an operation state.
2. Ain indicates that there is also address input in auto-program mode.
3. For command writes when making a transition to auto-program or auto-erase mode,
input a high level to the FWE pin.
Rev.2.00 Jan. 15, 2007 page 161 of 1174
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Section 7 ROM
Table 7.10 Programmer Mode Commands
Command Name
1st Cycle
Number of
Cycles
Mode
Address
2nd Cycle
Data
Mode
Address
Data
Memory read mode
1+n
write
X
H'00
read
RA
Dout
Auto-program mode
129
write
X
H'40
write
WA
Din
Auto-erase mode
2
write
X
H'20
write
X
H'20
Status read mode
2
write
X
H'71
write
X
H'71
Notes: 1. In auto-program mode. 129 cycles are required for command writing by a simultaneous
128-byte write.
2. In memory read mode, the number of cycles depends on the number of address write
cycles (n).
7.8.4
Memory Read Mode
• After the end of an auto-program, auto-erase, or status read operation, the command wait state
is entered. To read memory contents, a transition must be made to memory read mode by
means of a command write before the read is executed.
• Command writes can be performed in memory read mode, just as in the command wait state.
• Once memory read mode has been entered, consecutive reads can be performed.
• After power-on, memory read mode is entered.
− Preliminary −
Table 7.11 AC Characteristics in Memory Read Mode (1)
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Command write cycle
tnxtc
20
⎯
μs
CE hold time
tceh
0
⎯
ns
CE setup time
tces
0
⎯
ns
Data hold time
tdh
50
⎯
ns
Data setup time
tds
50
⎯
ns
Write pulse width
twep
70
⎯
ns
WE rise time
tr
⎯
30
ns
WE fall time
tf
⎯
30
ns
Rev.2.00 Jan. 15, 2007 page 162 of 1174
REJ09B0329-0200
Section 7 ROM
Memory read mode
Command write
A18 to A0
ADDRESS STABLE
CE
OE
WE
twep
tceh
tnxtc
tces
tf
tr
IO7 to IO0
DATA
H'00
tdh
tds
Note: Data is latched on the rising edge of WE.
Figure 7.16 Memory Read Mode Timing Waveforms after Command Write
Table 7.12 AC Characteristics when Entering Another Mode from Memory Read Mode
− Preliminary −
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Command write cycle
tnxtc
20
⎯
μs
CE hold time
tceh
0
⎯
ns
CE setup time
tces
0
⎯
ns
Data hold time
tdh
50
⎯
ns
Data setup time
tds
50
⎯
ns
Write pulse width
twep
70
⎯
ns
WE rise time
tr
⎯
30
ns
WE fall time
tf
⎯
30
ns
Rev.2.00 Jan. 15, 2007 page 163 of 1174
REJ09B0329-0200
Section 7 ROM
Other mode command write
A18 to A0
ADDRESS STABLE
CE
twep
tceh
tnxtc
OE
tces
WE
tf
DATA
IO7 to IO0
tr
H'XX
tdh
tds
Note: Do not enable WE and OE at the same time.
Figure 7.17 Timing Waveforms when Entering Another Mode from Memory Read Mode
− Preliminary −
Table 7.13 AC Characteristics in Memory Read Mode (2)
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Access time
tacc
⎯
20
μs
CE output delay time
tce
⎯
150
ns
OE output delay time
toe
⎯
150
ns
Output disable delay time
tdf
⎯
100
ns
Data output hold time
toh
5
⎯
ns
A18 to A0
ADDRESS STABLE
ADDRESS STABLE
CE
VIL
OE
tacc
VIL
VIH
WE
tacc
toh
DATA
IO7 to IO0
toh
DATA
Figure 7.18 Timing Waveforms for CE/OE Enable State Read
Rev.2.00 Jan. 15, 2007 page 164 of 1174
REJ09B0329-0200
Section 7 ROM
A18 to A0
ADDRESS STABLE
ADDRESS STABLE
tacc
CE
tce
tce
OE
toe
toe
VIH
WE
tdf
tdf
tacc
IO7 to IO0
DATA
DATA
toh
toh
Figure 7.19 Timing Waveforms for CE/OE Clocked Read
7.8.5
Auto-Program Mode
AC Characteristics
− Preliminary −
Table 7.14 AC Characteristics in Auto-Program
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Command write cycle
tnxtc
20
⎯
μs
CE hold time
tceh
0
⎯
ns
CE setup time
tces
0
⎯
ns
Data hold time
tdh
50
⎯
ns
Data setup time
tds
50
⎯
ns
Write pulse width
twep
70
⎯
ns
Status polling start time
twsts
1
⎯
ms
Status polling access time
tspa
⎯
150
ns
Address setup time
tas
0
⎯
ns
Address hold time
tah
60
⎯
ns
Memory write time
twrite
1
3000
ms
WE rise time
tr
⎯
30
ns
WE fall time
tf
⎯
30
ns
Write setup time
tpns
100
⎯
ns
Write end setup time
tpnh
100
⎯
ns
Rev.2.00 Jan. 15, 2007 page 165 of 1174
REJ09B0329-0200
Section 7 ROM
FWE
tpns
tpnh
A18 to A0
ADDRESS STABLE
CE
tceh
tas
tah
tnxtc
OE
WE
IO7
tnxtc
twep
Data transfer
1 byte to 128 bytes
tces
tf
twsts
tspa
twrite(1 to 3,000 ms)
Programming operation
end identification signal
tr
tds
tdh
Programming normal end
identification signal
IO6
Programming wait
IO5 to IO0
H'40
DATA
DATA
H'00
Figure 7.20 Auto-Program Mode Timing Waveforms
Notes on Use of Auto-Program Mode
• In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers.
• A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this
case, H'FF data must be written to the extra addresses.
• The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective
address is input, processing will switch to a memory write operation but a write error will be
flagged.
• Memory address transfer is performed in the second cycle (figure 7.20). Do not perform
transfer after the second cycle.
• Do not perform a command write during a programming operation.
• Perform one auto-programming operation for a 128-byte block for each address.
Characteristics are not guaranteed for two or more programming operations.
• Confirm normal end of auto-programming by checking IO6. Alternatively, status read mode
can also be used for this purpose (IO7 status polling uses the auto-program operation end
identification pin).
• The status polling IO6 and IO7 pin information is retained until the next command write. Until
the next command write is performed, reading is possible by enabling CE and OE.
Rev.2.00 Jan. 15, 2007 page 166 of 1174
REJ09B0329-0200
Section 7 ROM
7.8.6
Auto-Erase Mode
AC Characteristics
− Preliminary −
Table 7.15 AC Characteristics in Auto-Erase Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Command write cycle
tnxtc
20
⎯
μs
CE hold time
tceh
0
⎯
ns
CE setup time
tces
0
⎯
ns
Data hold time
tdh
50
⎯
ns
Data setup time
tds
50
⎯
ns
Write pulse width
twep
70
⎯
ns
Status polling start time
tests
1
⎯
ms
Status polling access time
tspa
⎯
150
ns
Memory erase time
terase
100
40000
ms
WE rise time
tr
⎯
30
ns
WE fall time
tf
⎯
30
ns
Erase setup time
tens
100
⎯
ns
Erase end setup time
tenh
100
⎯
ns
FWE
tens
tenh
A18 to A0
CE
tces
tceh
tspa
OE
WE
tests
tnxtc
twep
tf
tr
IO7
tdh
Erase normal end
identification signal
IO6
IO5 to IO0
tnxtc
terase (100 to 40000ms)
Erase end
identification signal
tds
CLin
DLin
H'20
H'20
H'00
Figure 7.21 Auto-Erase Mode Timing Waveforms
Rev.2.00 Jan. 15, 2007 page 167 of 1174
REJ09B0329-0200
Section 7 ROM
Notes on Use of Erase-Program Mode
• Auto-erase mode supports only entire memory erasing.
• Do not perform a command write during auto-erasing.
• Confirm normal end of auto-erasing by checking IO6. Alternatively, status read mode can also
be used for this purpose (IO7 status polling uses the auto-erase operation end identification
pin).
• The status polling IO6 and IO7 pin information is retained until the next command write. Until
the next command write is performed, reading is possible by enabling CE and OE.
7.8.7
Status Read Mode
Status read mode is used to identify what type of abnormal end has occurred. Use this mode when
an abnormal end occurs in auto-program mode or auto-erase mode.
The return code is retained until a command write for other than status read mode is performed.
− Preliminary −
Table 7.16 AC Characteristics in Status Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Command write cycle
tnxtc
20
⎯
μs
CE hold time
tceh
0
⎯
ns
CE setup time
tces
0
⎯
ns
Data hold time
tdh
50
⎯
ns
Data setup time
tds
50
⎯
ns
Write pulse width
twep
70
⎯
ns
OE output delay time
toe
⎯
150
ns
Disable delay time
tdf
⎯
100
ns
CE output delay time
tce
⎯
150
ns
WE rise time
tr
⎯
30
ns
WE fall time
tf
⎯
30
ns
Rev.2.00 Jan. 15, 2007 page 168 of 1174
REJ09B0329-0200
Section 7 ROM
A18 to A0
CE
tnxtc
tce
OE
tnxtc
twep
WE
tces
tceh
tf
tds
IO7 to IO0
tr
tnxtc
twep
tces
tf
tdf
toe
tceh
tr
tds
tdh
tdh
H'71
H'71
DATA
Note: IO2 and IO3 are undefined.
Figure 7.22 Status Read Mode Timing Waveforms
Table 7.17 Status Read Mode Return Commands
Pin Name
IO7
IO6
Attribute
Normal end Command
identification error
Initial value 0
0
Indications Normal
end: 0
Command
error: 1
Abnormal
end: 1
IO5
IO4
IO3 IO2 IO1
IO0
Programming Erase error
error
⎯
⎯
Programming Effective
or erase count address error
exceeded
0
0
0
0
0
⎯
Count
exceeded: 1
Effective
address
error: 1
0
Programming Erase error: 1 ⎯
error: 1
Otherwise: 0
Otherwise: 0 Otherwise: 0
Otherwise: 0
Otherwise: 0
Note: IO2 and IO3 are undefined.
Rev.2.00 Jan. 15, 2007 page 169 of 1174
REJ09B0329-0200
Section 7 ROM
7.8.8
Status Polling
The IO7 status polling flag indicates the operating status in auto-program or auto-erase mode.
The IO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase
mode.
Table 7.18 Status Polling Output Truth Table
Pin Names
Internal Operation
in Progress
Abnormal End
⎯
Normal End
IO7
0
1
0
1
IO6
0
0
1
1
IO0 to IO5
0
0
0
0
7.8.9
Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 7.19 Command Wait State Transition Time Specifications
Item
Symbol
Min
Max
Unit
Standby release
(oscillation stabilization time)
tosc1
10
⎯
ms
Programmer mode setup time
tbmv
10
⎯
ms
VCC hold time
tdwn
0
⎯
ms
VCC
RES
tosc1
tbmv
tdwn
Memory read
mode
Command wait
state
Auto-program mode
Auto-erase mode
Command
Don't care
wait state
Normal/abnormal
end identification
FWE
Don't care
Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low.
Figure 7.23 Oscillation Stabilization Time,
Boot Program Transfer Time, and Power Supply Fall Sequence
Rev.2.00 Jan. 15, 2007 page 170 of 1174
REJ09B0329-0200
Section 7 ROM
7.8.10
Notes on Memory Programming
• When programming addresses which have previously been programmed, carry out autoerasing before auto-programming.
• When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas.
For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level.
2. Auto-programming should be performed once only on the same address block.
Rev.2.00 Jan. 15, 2007 page 171 of 1174
REJ09B0329-0200
Section 7 ROM
7.9
Note on Switching from F–ZTAT Version to Mask-ROM Version
The mask ROM version does not have the internal registers for flash memory control that are
provided in the F-ZTAT version. Table 7.20 lists the registers that are present in the F-ZTAT
version but not in the mask ROM version. If a register listed in table 7.20 is read in the mask
ROM version, an undefined value will be returned. Therefore, if application software developed
on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure
that the registers in table 7.20 have no effect.
Table 7.20 Registers Present in F-ZTAT Version but Absent in Mask ROM Version
Register
Abbreviation
Address
Flash memory control register 1
FLMCR1
H'FFF8
Flash memory control register 2
FLMCR2
H'FFF9
Erase block register 1
EBR1
H'FFFA
Erase block register 2
EBR2
H'FFFB
Rev.2.00 Jan. 15, 2007 page 172 of 1174
REJ09B0329-0200
Section 8 RAM
Section 8 RAM
8.1
Overview
The H8S/2199R, H8S/2198R, H8S/2197R, and H8S/2196R have 4 kbytes, H8S/2197S, and
H8S/2196S have 3 kbytes, and H8S/2199R F-ZTAT version has 8 kbytes of on-chip high-speed
static RAM. The on-chip RAM is connected to the CPU by a 16-bit data bus, enabling both byte
data and word data to be accessed in one state. This makes it possible to perform fast word data
transfer.
8.1.1
Block Diagram
Figure 8.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFEFB0
H'FFEFB1
H'FFEFB2
H'FFEFB3
H'FFEFB4
H'FFEFB5
H'FFFFAE
H'FFFFAF
Figure 8.1 Block Diagram of RAM (H8S/2199R)
Rev.2.00 Jan. 15, 2007 page 173 of 1174
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Section 8 RAM
Rev.2.00 Jan. 15, 2007 page 174 of 1174
REJ09B0329-0200
Section 9 Clock Pulse Generator
Section 9 Clock Pulse Generator
9.1
Overview
This LSI has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus
master clock, and internal clocks.
The clock pulse generator consists of a system clock oscillator, a duty adjustment circuit, clock
selection circuit, medium-speed clock divider, subclock oscillator, and subclock division circuit.
9.1.1
Block Diagram
Figure 9.1 shows a block diagram of the clock pulse generator.
Duty
adjustment
circuit
System
clock
oscillator
OSC1
OSC2
φ/16, φ/32, φ/64
φw/2, φw/4, φw/8
φ or φ SUB
Bus master clock
To CPU
Mediumspeed clock
divider
Clock
selection
circuit
φ SUB
X1
Subclock
division
circuit
Subclock
oscillator
X2
Internal clock
To supporting modules
Timer A
count clock
φSUB (φw/2, φw/4, φw/8)
Figure 9.1 Block Diagram of Clock Pulse Generator
9.1.2
Register Configuration
The clock pulse generator is controlled by SBYCR and LPWRCR. Table 9.1 shows the register
configuration.
Table 9.1
CPG Registers
Name
Abbreviation
R/W
Initial Value
Address*
Standby control register
SBYCR
R/W
H'00
H'FFEA
Low-power control register
LPWRCR
R/W
H'00
H'FFEB
Note:
*
Lower 16 bits of the address.
Rev.2.00 Jan. 15, 2007 page 175 of 1174
REJ09B0329-0200
Section 9 Clock Pulse Generator
9.2
Register Descriptions
9.2.1
Standby Control Register (SBYCR)
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
—
—
SCK1
SCK0
Bit :
Initial value :
R/W :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
—
—
R/W
R/W
SBYCR is an 8-bit readable/writable register that performs power-down mode control. Only bits 0
and 1 are described here. For a description of the other bits, see section 4.2.1, Standby Control
Register (SBYCR). SBYCR is initialized to H'00 by a reset.
Bits 1 and 0⎯System Clock Select 1 and 0 (SCK1, SCK0): These bits select the bus master
clock for high-speed mode and medium-speed mode.
Bit 1
Bit 0
SCK1
SCK0
Description
0
0
Bus master is in high-speed mode
1
Medium-speed clock is φ/16
0
Medium-speed clock is φ/32
1
Medium-speed clock is φ/64
1
9.2.2
(Initial value)
Low-Power Control Register (LPWRCR)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
DTON
LSON
NESEL
—
—
—
SA1
SA0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
—
—
—
R/W
R/W
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
Only bit 1 and 0 is described here. For a description of the other bits, see section 4.2.2, LowPower Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset.
Rev.2.00 Jan. 15, 2007 page 176 of 1174
REJ09B0329-0200
Section 9 Clock Pulse Generator
Bits 1 and 0⎯Subactive Mode Clock Select (SA1, SA0): Select CPU clock for subactive mode.
In subactive mode, writes are disabled.
Bit 1
Bit 0
SA1
SA0
Description
0
0
CPU operating clock is φw/8
1
CPU operating clock is φw/4
*
CPU operating clock is φw/2
1
(Initial value)
Legend: * Don't care
9.3
Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
9.3.1
Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure
9.2. An AT-cut parallel-resonance crystal should be used.
CL1
OSC1
CL1 = CL2 = 10 to 22pF
OSC2
CL2
Figure 9.2 Connection of Crystal Resonator (Example)
Crystal Resonator: Figure 9.3 shows the equivalent circuit of the crystal resonator. Use a crystal
resonator that has the characteristics shown in table 9.2 and the same frequency as the system
clock (φ).
CL
L
Rs
OSC2
OSC1
C0
AT-cut parallel-resonance type
Figure 9.3 Crystal Resonator Equivalent Circuit
Rev.2.00 Jan. 15, 2007 page 177 of 1174
REJ09B0329-0200
Section 9 Clock Pulse Generator
Table 9.2
Crystal Resonator Parameters
Frequency (MHz)
8
10
RSmax (Ω)
80
60
COmax (pF)
7
7
Note on Board Design: When a crystal resonator is connected, the following points should be
noted.
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 9.4.
When designing the board, place the crystal resonator and its load capacitors as close as possible
to the OSC1 and OSC2 pins.
Avoid
Signal A Signal B
CL2
This LSI
OSC1
OSC2
CL1
Figure 9.4 Example of Incorrect Board Design
Rev.2.00 Jan. 15, 2007 page 178 of 1174
REJ09B0329-0200
Section 9 Clock Pulse Generator
9.3.2
External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure
9.5. If the OSC2 pin is left open, make sure that stray capacitance is no more than 10 pF.
In example (b), make sure that the external clock is held high in standby mode, subactive mode,
subsleep mode, and watch mode.
OSC1
OSC2
External clock input
Open
(a) OSC2 pin left open
OSC1
External clock input
OSC2
(b) Inverted-phase clock input at OSC2 pin
Figure 9.5 External Clock Input (Examples)
Rev.2.00 Jan. 15, 2007 page 179 of 1174
REJ09B0329-0200
Section 9 Clock Pulse Generator
External Clock: The external clock signal should have the same frequency as the system clock
(φ).
Table 9.3 and figure 9.6 show the input conditions for the external clock.
Table 9.3
External Clock Input Conditions
VCC = 4.0 to 5.5 V
Item
Symbol
Min
Max
Unit
Test Conditions
External clock input low
pulse width
tEXL
40
⎯
ns
Figure 9.6
External clock input high
pulse width
tEXH
40
⎯
ns
External clock rise time
tEXr
⎯
10
ns
External clock fall time
tEXf
⎯
10
ns
tEXH
tEXL
OSC1
tEXr
tEXf
Figure 9.6 External Clock Input Timing
Table 9.4 shows the external clock output settling delay time, and figure 9.7 shows the external
clock output settling delay timing. The oscillator and duty adjustment circuit have a function for
adjusting the waveform of the external clock input at the OSC1 pin. When the prescribed clock
signal is input at the OSC1 pin, internal clock signal output is fixed after the elapse of the external
clock output settling delay time (tDEXT). As the clock signal output is not fixed during the tDEXT
period, the reset signal should be driven low to maintain the reset state.
Rev.2.00 Jan. 15, 2007 page 180 of 1174
REJ09B0329-0200
Section 9 Clock Pulse Generator
Table 9.4
External Clock Output Settling Delay Time
Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V
Item
External clock output settling
delay time
Note:
Min
Max
Unit
Notes
*
500
⎯
μs
Figure 9.7
tDEXT
tDEXT includes 20 tCYC of RES pulse width (tRESW).
*
VCC
Symbol
4.0 V
OSC1
φ
(Internal)
RES
tDEXT*
Note: * tDEXT includes 20 tcyc of RES pulse width (tRESW).
Figure 9.7 External Clock Output Settling Delay Timing
Rev.2.00 Jan. 15, 2007 page 181 of 1174
REJ09B0329-0200
Section 9 Clock Pulse Generator
9.4
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
9.5
Medium-Speed Clock Divider
The medium-speed divider divides the system clock to generate φ/16, φ/32, and φ/64 clocks.
9.6
Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/16, φ/32 or φ/64) to be supplied to the bus master (CPU), according to the settings of bits
SCK2 to SCK0 in SBYCR.
9.7
Subclock Oscillator Circuit
9.7.1
Connecting 32.768 kHz Crystal Resonator
When using a subclock, connect a 32.768 kHz crystal resonator to X1 and X2 pins as shown in
figure 9.8.
For precautions on connecting, see Note on Board Design, in section 9.3.1 Connecting a Crystal
Resonator.
C1
X1
X2
C2
C1 = C2 = 15 pF (Typ)
Figure 9.8 Connecting a 32.768 kHz Crystal Resonator (Example)
Rev.2.00 Jan. 15, 2007 page 182 of 1174
REJ09B0329-0200
Section 9 Clock Pulse Generator
Figure 9.9 shows a crystal resonator equivalent circuit.
CS
Ls
Rs
X1
X2
C0
C0 = 1.5 pF (Typ)
RS = 14 kΩ (Typ)
fW = 32.768 kHz
Type: MX38T (Nihon Denpa Kogyo Co., Ltd.)
Note: Values shown are the reference values.
Figure 9.9 32.768 kHz Crystal Resonator Equivalent Circuit
9.7.2
When Subclock Is Not Needed
Connect X1 pin to VCL, and X2 pin should remain open as shown in figure 9.10.
VCL
X1
Open
X2
Figure 9.10 Terminal When Subclock Is Not Needed
9.8
Subclock Waveform Shaping Circuit
To eliminate noise in the subclock input from the X1 pin, this circuit samples the clock using a
clock obtained by dividing the φ clock. The sampling frequency is set with the NESEL bit in
LPWRCR. For details, see section 4.2.2, Low-Power Control Register (LPWRCR). The clock is
not sampled in subactive mode, subsleep mode, or watch mode.
Rev.2.00 Jan. 15, 2007 page 183 of 1174
REJ09B0329-0200
Section 9 Clock Pulse Generator
9.9
Notes on the Resonator
Resonator characteristics are closely related to the user board design. Perform appropriate
assessment of resonator connection, mask version and F-ZTAT, by referring to the connection
example given in this section. The resonator circuit rate differs depending on the free capacity of
the resonator and the execution circuit, so consult with the resonator manufacturer before
determination. Make sure the voltage applied to the resonator pin does not exceed the maximum
rated voltage.
Rev.2.00 Jan. 15, 2007 page 184 of 1174
REJ09B0329-0200
Section 10 I/O Port
Section 10 I/O Port
10.1
Overview
10.1.1
Port Functions
This LSI has seven 8-bit I/O ports (including one CMOS high-current port), and one 8-bit input
port. Table 10.1 shows the functions of each port. Each I/O part a port control register (PCR) that
controls an input and output and a port data register (PDR) for storing output data. The input and
output can be controlled in a unit of bit. The pin whose peripheral function is used both as an
alternative function can set the pin function in a unit of bit by a port mode register (PMR).
10.1.2
Port Input
• Reading a Port
⎯ When a general port of PCR = 0 (input) is read, the pin level is read.
⎯ When a general port of PCR = 1 (output) is read, the value of the corresponding PDR bit is
read.
⎯ When the pins (excluding AN7 to AN0 and RPB7 to RP0 pins) set to the peripheral
function are read, the results are as given in items (1) and (2) according to the PCR value.
• Processing Input Pins
The general input port or general I/O port is gated by read signals. Unused pins can be left
open if they are not read. However, if an open pin is read, a feedthrough current may apply
during the read period according to an intermediate level. The read period is about one-state.
Relevant ports: P0, P1, P2, P3, P4, P5, P6, P7, and P8
When an alternative pin is set to an alternative function other than the general I/O, always set
the pin level to a high or low level. If the pin is left open, a feedthrough current applies
according to an intermediate level, which adversely affects reliability, causes malfunctions,
and in the worst case may damage the pin.
Because the PMR is not initialized in low power consumption mode, pay attention to the pin
input level after the mode has been shifted to the low power consumption mode.
Relevant pins: IC, IRQ0 to IRQ5, SCK1, SI1, SDA1, SCL1, SDA0*, SCL0*, SYNCI*,
FTIA*, FTIB*, FTIC*, FTID*, RPTRG, TMBI, ADTRG, EXCTL, COMP, DPG, EXCAP,
and EXTTRG
Note: * Not available in the H8S/2197S or H8S/2196S.
Rev.2.00 Jan. 15, 2007 page 185 of 1174
REJ09B0329-0200
Section 10 I/O Port
Table 10.1 Port Functions
Port
Description
Pins
Alternative Functions
Function
Switching
Register
Port 0
P07 to P00 inputonly ports
P07/AN7 to
P00/AN0
Analog data input channels 7 to 0
PMR0
Port 1
P17 to P10 I/O ports P17/TMOW
(Built-in MOS pullup transistors)
P16/IC
Prescalar unit frequency division
clock output
PMR1
P15/IRQ5 to
P10/IRQ0
Port 2
Port 3
P27 to P20 I/O ports P27/SYNCI
(Built-in MOS pullP26/SCL0
up transistors)
P25/SDA0
Prescalar unit input capture input
External interrupt request input
Formatless serial clock input*
2
I C bus interface clock I/O*
I C bus interface data I/O*
2
2
P24/SCL1
I C bus interface clock I/O
P23/SDA1
I C bus interface data I/O
P22/SCK1
SCI1 clock I/O
P21/SO1
SCI1 transmit data output
P20/SI1
SCI1 receive data input
P37 to P30 I/O ports P37/TMO
(Built-in MOS pullP36/BUZZ
up transistors)
P35/PWM3
P34/PWM2
P33/PWM1
P32/PWM0
P31/SV2
STCR
ICCR
2
Timer J timer output
SMR
SCR
PMR3
Timer J buzzer output
8-bit PWM3 output*
8-bit PWM2 output*
8-bit PWM1 output
8-bit PWM0 output
Servo monitor output
P30/SV1
Port 4
P47 to P40 I/O ports P47/RPTRG
Realtime output port trigger input
PMR4
Timer X output compare B output*
Timer X output compare A output*
TOCR
⎯
P43/FTIC
Timer X input capture D input*
Timer X input capture C input*
P42/FTIB
Timer X input capture B input*
P41/FTIA
Timer X input capture A input*
14-bit PWM output*
P46/FTOB
P45/FTOA
P44/FTID
P40/PWM14
Rev.2.00 Jan. 15, 2007 page 186 of 1174
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PMR4
Section 10 I/O Port
Port
Description
Port 6
P63 to P60 I/O ports P67/RP7/
TMBI
Port 7
Pins
Realtime output port
PMR6
Timer B event output
PMRA
P66/RP6/
ADTRG
Realtime output port
P65/RP5 to
P60/RP0
Realtime output port
P77 to P70 I/O ports P77/PPG7/
RPB to P74/
PPG4/RP8
P73/PPG3 to
P70/PPG0
Port 8
Alternative Functions
Function
Switching
Register
P87 to P80 I/O ports P87/DPG
A/D conversion start external trigger
input
PPG output
PMR7
Realtime output port
PMRB
PPG output
DPG signal input
PMR8
P86/EXTTRG
External trigger signal input
PMRC
P85/COMP/B
Pre-amplifier output result signal
input
Color signal output (B)
P84/H.Amp
SW/G
Pre-amplifier output select signal
input
Color signal output (G)
P83/C.Rotary/R Control signal output for processing
color signals
Color signal output (R)
P82/EXCTL
External CTL signal input
P81/EXCAP/
YBO
External capstan signal input
P80/YCO
OSD character data output
OSD character position output
Notes: This LSI does not have port 5.
* These alternative functions are not available in the H8S/2197S or H8S/2196S.
Rev.2.00 Jan. 15, 2007 page 187 of 1174
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Section 10 I/O Port
10.1.3
MOS Pull-Up Transistors
The MOS pull-up transistors in ports 1 to 3 can be switched on or off by the MOS pull-up select
registers 1 to 3 (PUR1 to PUR3) in units of bits. Settings in PUR1 to PUR3 are valid when the pin
function is set to an input by PCR1 to PCR3. If the pin function is set to an output, the MOS pullup transistor is turned off. Figure 10.1 shows the circuit configuration of a pin with a MOS pull-up
transistor.
STBY
PUR
VCC
VCC
PCR
PDR
VSS
Input data
Legend:
STBY
PUR
PCR
PDR
: Low power consumption mode signal
(The pull-up MOS transistor is turned off by the STBY signal in low power
consumption mode except for sleep mode)
: MOS pull-up select register
: Port control register
: Port data register
Figure 10.1 Circuit Configuration of Pin with MOS Pull-Up Transistor
Rev.2.00 Jan. 15, 2007 page 188 of 1174
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Section 10 I/O Port
10.2
Port 0
10.2.1
Overview
Port 0 is an 8-bit input-only port. Table 10.2 shows the port 0 configuration.
Port 0 consists of pins that are used both as standard input ports (P07 to P00) and analog input
channels (AN7 to AN0). It is switched by port mode register 0 (PMR0).
Table 10.2 Port 0 Configuration
Port
Function
Alternative Function
Port 0
P07 (standard input port)
AN7 (analog input channel)
P06 (standard input port)
AN6 (analog input channel)
P05 (standard input port)
AN5 (analog input channel)
P04 (standard input port)
AN4 (analog input channel)
P03 (standard input port)
AN3 (analog input channel)
P02 (standard input port)
AN2 (analog input channel)
P01 (standard input port)
AN1 (analog input channel)
P00 (standard input port)
AN0 (analog input channel)
10.2.2
Register Configuration
Table 10.3 shows the port 0 register configuration.
Table 10.3 Port 0 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Port mode register 0
PMR0
R/W
Byte
H'00
H'FFCD
Port data register 0
PDR0
R
Byte
⎯
H'FFC0
Note:
*
Lower 16 bits of the address.
Rev.2.00 Jan. 15, 2007 page 189 of 1174
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Section 10 I/O Port
Port Mode Register 0 (PMR0)
Bit :
Initial value :
R/W :
7
PMR07
6
PMR06
5
PMR05
4
PMR04
3
PMR03
2
PMR02
1
PMR01
0
PMR00
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port mode register 0 (PMR0) controls switching of each pin function of port 0. The switching is
specified in a unit of bit.
PMR0 is an 8-bit read/write enable register. When reset, PMR0 is initialized to H'00.
Bits 7 to 0⎯P07/AN7 to P00/AN0 Pin Switching (PMR07 to PMR00): PMR07 to PMR00 set
whether the P0n/ANn pin is used as a P0n input pin or an ANn pin for the analog input channel of
an A/D converter.
Bit n
PMR0n
Description
0
The P0n/ANn pin functions as a P0n input pin
1
The P0n/ANn pin functions as an ANn input pin
Note:
(Initial value)
n = 7 to 0
Port Data Register 0 (PDR0)
Bit :
Initial value :
R/W :
7
PDR07
6
PDR06
5
PDR05
4
PDR04
3
PDR03
2
PDR02
1
PDR01
0
PDR00
—
R
—
R
—
R
—
R
—
R
—
R
—
R
—
R
Port data register 0 (PDR0) reads the port states. When the corresponding bit of PMR0 is 0
(general input port), the pin state is read if PDR0 is read. When the corresponding bit of PMR0 is
1 (analog input channel), 1 is read if PDR0 is read.
PDR0 is an 8-bit read-only register. When PDR0 is reset, its values become undefined.
Rev.2.00 Jan. 15, 2007 page 190 of 1174
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Section 10 I/O Port
10.2.3
Pin Functions
This section describes the pin functions of port 0 and their selection methods.
P07/AN7 to P00/AN0: P07/AN7 to P00/AN0 are switched according to the PMR0n bit of PMR0
as shown below.
PMR0n
Pin Function
0
P0n input pin
1
ANn input pin
Note:
10.2.4
n = 7 to 0
Pin States
Table 10.4 shows the pin 0 states in each operation mode.
Table 10.4 Port 0 Pin States
Pins
Reset
Active
Sleep
Standby
Watch
Subactive
Subsleep
P07/AN7 to
P00/AN0
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
Rev.2.00 Jan. 15, 2007 page 191 of 1174
REJ09B0329-0200
Section 10 I/O Port
10.3
Port 1
10.3.1
Overview
Port 1 is an 8-bit I/O port. Table 10.5 shows the port 1 configuration.
Port 1 consists of pins that are used both as standard I/O ports (P17 to P10) and frequency division
clock output (TMOW), input capture input (IC), or external interrupt request inputs (IRQ5 to
IRQ0). It is switched by port mode register 1 (PMR1) and port control register 1 (PCR1).
Port 1 can select the functions of MOS pull-up transistors.
Table 10.5 Port 1 Configuration
Port
Function
Port 1
10.3.2
Alternative Function
P17 (standard I/O port)
TMOW (frequency division clock output)
P16 (standard I/O port)
IC (input capture input)
P15 (standard I/O port)
IRQ5 (external interrupt request input)
P14 (standard I/O port)
IRQ4 (external interrupt request input)
P13 (standard I/O port)
IRQ3 (external interrupt request input)
P12 (standard I/O port)
IRQ2 (external interrupt request input)
P11 (standard I/O port)
IRQ1 (external interrupt request input)
P10 (standard I/O port)
IRQ0 (external interrupt request input)
Register Configuration
Table 10.6 shows the port 1 register configuration.
Table 10.6 Port 1 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Port mode register 1
PMR1
R/W
Byte
H'00
H'FFCE
Port control register 1
PCR1
W
Byte
H'00
H'FFD1
Port data register 1
PDR1
R/W
Byte
H'00
H'FFC1
MOS pull-up select register PUR1
1
R/W
Byte
H'00
H'FFE1
Note:
*
Lower 16 bits of the address.
Rev.2.00 Jan. 15, 2007 page 192 of 1174
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Section 10 I/O Port
Port Mode Register 1 (PMR1)
Bit :
Initial value :
R/W :
7
PMR17
6
PMR16
5
PMR15
4
PMR14
3
PMR13
2
PMR12
1
PMR11
0
PMR10
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is
specified in a unit of bit.
PMR1 is an 8-bit read/write enable register. When reset, PMR1 is initialized to H'00.
Note the following items when the pin functions are switched by PMR1.
• If port 1 is set to an IC input pin and IRQ5 to IRQ0 by PMR1, the pin level needs be set to the
high or low level regardless of the active mode and low power consumption mode. The pin
level must not be set to an intermediate level.
• When the pin functions of P16/IC and P15/IRQ5 to P10/IRQ0 are switched by PMR1, they are
incorrectly recognized as edge detection according to the state of a pin signal and a detection
signal may be generated. To prevent this, perform the operation in the following procedure.
⎯ Before switching the pin functions, inhibit an interrupt enable flag from being interrupted.
⎯ After having switched the pin functions, clear the relevant interrupt request flag to 0 by a
single instruction.
Program Example:
:
MOV.B R0L,@IENR ⋅⋅⋅⋅⋅⋅ Interrupt disabled
MOV.B R1L,@PMR1 ⋅⋅⋅⋅⋅⋅ Pin function change
NOP
⋅⋅⋅⋅⋅⋅ Optional instruction
BCLR m @IRQR
⋅⋅⋅⋅⋅⋅ Applicable interrupt clear
MOV.B R1L,@IENR ⋅⋅⋅⋅⋅⋅ Interrupt enabled
:
Bit 7⎯P17/TMOW Pin Switching (PMR17): PMR17 sets whether the P17/TMOW pin is used
as a P17 I/O pin or a TMOW pin for the frequency division clock output.
Bit 7
PMR17
Description
0
The P17/TMOW pin functions as a P17 I/O pin
1
The P17/TMOW pin functions as a TMOW output pin
(Initial value)
Rev.2.00 Jan. 15, 2007 page 193 of 1174
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Section 10 I/O Port
Bit 6⎯P16/IC Pin Switching (PMR16): PMR16 sets whether the P16/IC pin as a P16 I/O pin or
an IC pin for the input capture input of the prescalar unit. The IC pin has a built-in noise cancel
circuit. See section 21, Prescalar Unit.
Bit 6
PMR16
Description
0
The P16/IC pin functions as a P16 I/O pin
1
The P16/IC pin functions as an IC input pin
(Initial value)
Bits 5 to 0⎯P15/IRQ5 to P10/IRQ0 Pin Switching (PMR15 to PMR10): PMR15 to PMR10 set
whether the P1n/IRQn pin is used as a P1n I/O pin or an IRQn pin for the external interrupt
request input.
Bit n
PMR1n
Description
0
The P1n/IRQn pin functions as a P1n I/O pin
1
The P1n/IRQn pin functions as an IRQn input pin
Note:
(Initial value)
n = 5 to 0
Port Control Register 1 (PCR1)
Bit :
Initial value :
R/W :
7
PCR17
6
PCR16
5
PCR15
4
PCR14
3
PCR13
2
PCR12
1
PCR11
0
PCR10
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Port control register 1 (PCR1) controls the I/Os of pins P17 to P10 of port 1 in a unit of bit.
When PCR1 is set to 1, the corresponding P17 to P10 pins become output pins, and when it is set
to 0, they become input pins. When the relevant pin is set to a general I/O by PMR1, settings of
PCR1 and PDR1 become valid.
PCR1 is an 8-bit write-only register. When PCR1 is read, 1 is read. When reset, PCR1 is
initialized to H'00.
Rev.2.00 Jan. 15, 2007 page 194 of 1174
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Section 10 I/O Port
Bits 7 to 0⎯P17 to P10 Pin Switching (PCR17 toPCR10)
Bit n
PCR1n
Description
0
The P1n pin functions as an input pin
1
Note:
(Initial value)
The P1n pin functions as an output pin
n = 7 to 0
Port Data Register 1 (PDR1)
Bit :
Initial value :
R/W :
7
PDR17
6
PDR16
5
PDR15
4
PDR14
3
PDR13
2
PDR12
1
PDR11
0
PDR10
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port data register 1 (PDR1) stores the data for the pins P17 to P10 of port 1. When PCR1 is 1
(output), the PDR1 values are directly read if port 1 is read. Accordingly, the pin states are not
affected. When PCR1 is 0 (input), the pin states are read if port 1 is read.
PDR1 is an 8-bit read/ write enable register. When reset, PDR1 is initialized to H'00.
MOS Pull-Up Select Register 1 (PUR1)
Bit :
Initial value :
R/W :
7
PUR17
6
PUR16
5
PUR15
4
PUR14
3
PUR13
2
PUR12
1
PUR11
0
PUR10
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
MOS pull-up selector register 1 (PUR1) controls the on and off of the MOS pull-up transistor of
port 1. Only the pin whose corresponding bit of PCR1 was set to 0 (input) becomes valid. When
the corresponding bit of PCR1 is set to 1 (output), the corresponding bit of PUR1 becomes invalid
and the MOS pull-up transistor is turned off.
PUR1 is an 8-bit read/ write enable register. When reset, PUR1 is initialized to H'00.
Bits 7 to 0⎯P17 to P10 MOS Pull-Up Control (PCR17 to PCR10)
Bit n
PUR1n
Description
0
The P1n pin has no MOS pull-up transistor
1
The P1n pin has a MOS pull-up pin
Note:
(Initial value)
n = 7 to 0
Rev.2.00 Jan. 15, 2007 page 195 of 1174
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Section 10 I/O Port
10.3.3
Pin Functions
This section describes the port 1 pin functions and their selection methods.
P17/TMOW: P17/TMOW is switched as shown below according to the PMR17 bit in PMR1 and
the PCR17 bit in PCR1.
PMR17
PCR17
Pin Function
0
0
P17 input pin
1
P17 output pin
*
TMOW output pin
1
Legend: * Don’t care
P16/IC: P16/IC is switched as shown below according to the PMR16 bit in PMR1, the NC on/off
bit in prescalar unit control/status register (PCSR), and the PCR16 bit in PCR1.
PMR16
PCR16
NC on/off
Pin Function
0
0
*
P16 input pin
1
1
*
P16 output pin
0
1
IC input pin
Noise cancel invalid
Noise cancel valid
Legend: * Don’t care
P15/IRQ5 to P10/IRQ0: P15/IRQ15 to P10/IRQ0 are switched as shown below according to the
PMR1n bit in PMR1 and the PCR1n bit in PCR1.
PMR1n
PCR1n
Pin Function
0
0
P1n input pin
1
P1n output pin
*
IRQn input pin
1
Legend: * Don’t care.
Notes: 1. n = 5 to 0
2. The IRQ5 to IRQ0 input pins can select the leading or falling edge as an edge sense
(the IRQ0 pin can select both edges). See section 6.2.4, IRQ Edge Select Register
(IEGR).
3. IRQ1 or IRQ2 can be used as a timer J event input and IRQ3 can be used as a timer R
input capture input. For details, see section 13, Timer J or section 15, Timer R.
Rev.2.00 Jan. 15, 2007 page 196 of 1174
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Section 10 I/O Port
10.3.4
Pin States
Table 10.7 shows the port 1 pin states in each operation mode.
Table 10.7 Port 1 Pin States
Pins
Reset
P17/TMOW Highimpedance
P16/IC
P15/IRQ5 to
P10/IRQ0
Active
Sleep
Standby
Watch
Subactive
Subsleep
Operation
Holding
Highimpedance
Highimpedance
Operation
Holding
Note: If the IC input pin and IRQ5 to IRQ0 input pins are set, the pin level need be set to the high
or low level regardless of the active mode and low power consumption mode. Note that the
pin level must not reach an intermediate level.
Rev.2.00 Jan. 15, 2007 page 197 of 1174
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Section 10 I/O Port
10.4
Port 2
10.4.1
Overview
Port 2 is an 8-bit I/O port. Table 10.8 shows the port 2 configuration.
Port 2 consists of pins that are used both as standard I/O ports (P27 to P20) and SCI clock I/O
2
(SCK1), receive data input (SI1), send data output (SO1), I C bus interface clock I/O (SCL0,
SCL1), or data I/O (SDA0, SDA1). It is switched by serial mode register (SMR), serial control
register (SCR), and port control register 2 (PCR2).
Port 2 can select the MOS pull-up function.
Table 10.8 Port 2 Configuration
Port
Function
Alternative Function
Port 2
P27 (standard I/O port)
SYNCI (Formatless serial clock input)
P26 (standard I/O port)
SCL0 (I C bus interface clock I/O)
P25 (standard I/O port)
SDA0 (I C bus interface data I/O)
P24 (standard I/O port)
SCL1 (I C bus interface clock I/O)
P23 (standard I/O port)
SDA1 (I C bus interface data I/O)
P22 (standard I/O port)
SCK1 (SCI1 clock I/O)
P21 (standard I/O port)
SO1 (SCI1 transmit data output)
P20 (standard I/O port)
SI1 (SCI1 receive data input)
2
2
2
2
Note: The H8S/2197S and H8S/2196S do not have SYNCI, SCL0, and SDA0 pin functions.
10.4.2
Register Configuration
Table 10.9 shows the port 2 register configuration.
Table 10.9 Port 2 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Port control register 2
PCR2
W
Byte
H'00
H'FFD2
Port data register 2
PDR2
R/W
Byte
H'00
H'FFC2
MOS pull-up select
register 2
PUR2
R/W
Byte
H'00
H'FFE2
Note:
*
Lower 16 bits of the address.
Rev.2.00 Jan. 15, 2007 page 198 of 1174
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Section 10 I/O Port
Port Control Register 2 (PCR2)
Bit :
Initial value :
R/W :
7
PCR27
6
PCR26
5
PCR25
4
PCR24
3
PCR23
2
PCR22
1
PCR21
0
PCR20
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Port control register 2 (PCR2) controls the I/Os of pins P27 to P20 of port 2 in a unit of bit.
When PCR2 is set to 1, the corresponding P27 to P20 pins become output pins, and when it is set
to 0, they become input pins. When the relevant pin is set to a general I/O, settings of PCR2 and
PDR2 are valid.
PCR2 is an 8-bit write-only register. When PCR2 is read, 1 is read. When reset, PCR2 is
initialized to H'00.
Bits 7 to 0⎯P27 to P20 Pin Switching (PCR27 to PCR20)
Bit n
PCR2n
Description
0
The P2n pin functions as an input pin
1
The P2n pin functions as an output pin
Note:
(Initial value)
n = 7 to 0
Port Data Register 2 (PDR2)
Bit :
Initial value :
R/W :
7
PDR27
6
PDR26
5
PDR25
4
PDR24
3
PDR23
2
PDR22
1
PDR21
0
PDR20
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port data register 2 (PDR2) stores the data for the pins P27 to P20 of port 2. When PCR2 is 1
(output), the PDR2 values are directly read if port 2 is read. Accordingly, the pin states are not
affected. When PCR2 is 0 (input), the pin states are read if port 2 is read.
PDR2 is an 8-bit read/write enable register. When reset, PDR2 is initialized to H'00.
Rev.2.00 Jan. 15, 2007 page 199 of 1174
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Section 10 I/O Port
MOS Pull-Up Select Register 2 (PUR2)
Bit :
Initial value :
R/W :
7
PUR27
6
PUR26
5
PUR25
4
PUR24
3
PUR23
2
PUR22
1
PUR21
0
PUR20
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
MOS pull-up selector register 2 (PUR2) controls the ON and OFF of the MOS pull-up transistor
of port 2. Only the pin whose corresponding bit of PCR2 was set to 0 (input) becomes valid. If the
corresponding bit of PCR2 is set to 1 (output), the corresponding bit of PUR2 becomes invalid and
the MOS pull-up transistor is turned off.
PUR2 is an 8-bit read/write enable register. When reset, PUR2 is initialized to H'00.
Bits 7 to 0⎯P27 to P20 Pull-Up MOS Control (PUR27 to PUR20)
Bit n
PUR2n
Description
0
The P2n pin has no MOS pull-up transistor
1
The P2n pin has a MOS pull-up transistor
Note:
10.4.3
(Initial value)
n = 7 to 0
Pin Functions
This section describes the port 2 pin functions and their selection methods.
P27/SYNCI: P27/SYNCI is switched as shown below according to the PCR27 bit in PCR2.
PCR27
Pin Function
0
P27 input pin
1
P27 output pin
Notes: Because the SYNCI always functions, the alternative pin need always be set to the high or
low level regardless of active mode or low power consumption mode.
The H8S/2197S and H8S/2196S do not have SYNCI pin function.
Rev.2.00 Jan. 15, 2007 page 200 of 1174
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Section 10 I/O Port
P26/SCL0: P26/SCL0 is switched as shown below according to the PCR26 bit in PCR2 and the
2
ICE bit in the I C Bus control register 0 (ICCR0).
ICE
PCR26
Pin Function
0
0
P26 input pin
1
P26 output pin
*
SCL0 I/O pin
1
Legend: * Don’t care
Notes:
The H8S/2197S and H8S/2196S do not have SCL0 pin function.
P25/SDA0: P25/SDA0 is switched as shown below according to the PCR25 bit in PCR2 and the
2
ICE bit in the I C Bus control register 0 (ICCR0).
ICE
PCR25
Pin Function
0
0
P25 input pin
1
P25 output pin
*
SDA0 I/O pin
1
Legend: * Don’t care
Notes:
The H8S/2197S and H8S/2196S do not have SDA0 pin function.
P24/SCL1: P24/SCL1 is switched as shown below according to the PCR24 bit in PCR2 and the
2
ICE bit in the I C Bus control register 1 (ICCR1).
ICE
PCR24
Pin Function
0
0
P24 input pin
1
P24 output pin
*
SCL1 I/O pin
1
Legend: * Don’t care
P23/SDA1: P23/SDA1 is switched as shown below according to the PCR23 bit in PCR2 and the
2
ICE bit in the I C Bus control register 1 (ICCR1).
ICE
PCR23
Pin Function
0
0
P23 input pin
1
P23 output pin
*
SDA1 I/O pin
1
Legend: * Don’t care
Rev.2.00 Jan. 15, 2007 page 201 of 1174
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Section 10 I/O Port
P22/SCK1: P22/SCK1 is switched as shown below according to the PCR22 bit in PCR2, the C/A
bit in SMR, and the CKE1 and CKE0 bits in SCR.
CKE1
C/A
CKE0
PCR22
Pin Function
0
0
0
0
P22 input pin
1
P22 output pin
*
SCK1 output pin
1
1
1
*
SCK1 input pin
*
Legend: * Don’t care
P21/SO1: P21/SO1 is switched as shown below according to the PCR21 bit in PCR2 and the TE
bit in SCR.
TE
PCR21
Pin Function
0
0
P21 input pin
1
P21 output pin
*
SO1 output pin
1
Legend: * Don’t care
P20/SI1: P20/SI1 is switched as shown below according to the PCR20 bit in PCR2 and the RE bit
in SCR.
RE
PCR20
Pin Function
0
0
P20 input pin
1
P20 output pin
*
SI1 input pin
1
Legend: * Don’t care
Rev.2.00 Jan. 15, 2007 page 202 of 1174
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Section 10 I/O Port
10.4.4
Pin States
Table 10.10 shows the port 2 pin states in each operation mode.
Table 10.10 Port 2 Pin States
Pins
Reset
Active
Sleep
Standby
Watch
Subactive
Subsleep
P27/SYNCI
P26/SCL0
P25/SDA0
P24/SCL1
P23/SDA1
P22/SCK1
P21/SO1
P20/SI1
Highimpedance
Operation
Holding
Highimpedance
Highimpedance
Operation
Holding
Note: Because the SYNCI, SCL0, SDA0, SCL1, and SDA1 always function, the alternative pin
need always be set to the high or low level regardless of active mode or low power
consumption mode.
If the SCK1, and SI1 input pins are set, the pin level needs be set to the high or low level
regardless of the active mode and low power consumption mode. Note that the pin level
must not reach an intermediate level.
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Section 10 I/O Port
10.5
Port 3
10.5.1
Overview
Port 3 is an 8-bit I/O port. Table 10.11 shows the port 3 configuration.
Port 3 consists of pins that are used both as standard I/O ports (P37 to P30) and timer J timer
output (TMO), buzzer output (BUZZ), 8-bit PWM outputs (PWM3 to PWM0), SCI2 strobe output
(STRB), or chip select input (CS). It is switched by port mode register 3 (PMR3) and port control
register 3 (PCR3).
Port 3 can select the MOS pull-up function.
Table 10.11 Port 3 Configuration
Port
Function
Alternative Function
Port 3
P37 (standard I/O port)
TMO (timer J timer output)
P36 (standard I/O port)
BUZZ (timer J buzzer output)
P35 (standard I/O port)
PWM3 (8-bit PWM output)
P34 (standard I/O port)
PWM2 (8-bit PWM output)
P33 (standard I/O port)
PWM1 (8-bit PWM output)
P32 (standard I/O port)
PWM0 (8-bit PWM output)
P31 (standard I/O port)
SV2 (servo monitor output)
P30 (standard I/O port)
SV1 (servo monitor output)
Note: The H8S/2197S and H8S/2196S do not have PWM3 and PWM2 pin functions.
10.5.2
Register Configuration
Table 10.12 shows the port 3 register configuration.
Table 10.12 Port 3 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Port mode register 3
PMR3
R/W
Byte
H'00
H'FFD0
Port control register 3
PCR3
W
Byte
H'00
H'FFD3
Port data register 3
PDR3
R/W
Byte
H'00
H'FFC3
MOS pull-up select
register 3
PUR3
R/W
Byte
H'00
H'FFE3
Note:
*
Lower 16 bits of the address.
Rev.2.00 Jan. 15, 2007 page 204 of 1174
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Section 10 I/O Port
Port Mode Register 3 (PMR3)
Bit :
Initial value :
R/W :
7
PMR37
6
PMR36
5
PMR35
4
PMR34
3
PMR33
2
PMR32
1
PMR31
0
PMR30
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port mode register 3 (PMR3) controls switching of each pin function of port 3. The switching is
specified in a unit of bit.
PMR3 is an 8-bit read/write enable register. When reset, PMR3 is initialized to H'00.
Bit 7⎯P37/TMO Pin Switching (PMR37): PMR37 sets whether the P37/TMO pin is used as a
P37 I/O pin or a TMO pin for the timer J output timer.
Bit 7
PMR37
Description
0
The P37/TMO pin functions as a P37 I/O pin
1
The P37/TMO pin functions as a TMO output pin
(Initial value)
Notes: If the TMO pin is used for remote control sending, a careless timer output pulse may be
output when the remote control mode is set after the output has been switched to the TMO
output. Perform the switching and setting in the following order.
1. Set the remote control mode.
2. Set the TMJ-1 and 2 counter data of the timer J.
3. Switch the P37/TMO pin to the TMO output pin.
4. Set the ST bit to 1.
Bit 6⎯P36/BUZZ Pin Switching (PMR36): PMR36 sets whether the P36/BUZZ pin as a P36
I/O pin or an BUZZ pin for the timer J buzzer output. For the selection of the BUZZ output, see
13.2.2, Timer J Control Register (TMJC).
Bit 6
PMR36
Description
0
The P36/BUZZ pin functions as a P36 I/O pin
1
The P36/BUZZ pin functions as a BUZZ output pin
(Initial value)
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Section 10 I/O Port
Bits 5 to 2⎯P35/PWM3 to P32/PWM0 Pin Switching (PMR35 to PMR32): PMR35 to PMR32
set whether the P3n/PWMm pin is used as a P3n I/O pin or a PWMm pin for the 8-bit PWM
output.
Bit n
PMR3n
Description
0
The P3n/PWMm pin functions as a P3n I/O pin
1
The P3n/PWMm pin functions as a PWMm output pin
(Initial value)
Notes: 1. n = 5 to 2, m = 3 to 0
2. The H8S/2197S and H8S/2196S do not have PWM3 and PWM2 pin functions.
Bit 1⎯P31/SV2 Pin Switching (PMR31): PMR31 sets whether the P31/SV2 pin is used as a P31
I/O pin or an SV2 pin for the servo monitor output.
Bit 1
PMR31
Description
0
The P31/SV2 pin functions as a P31 I/O pin
1
The P31/SV2 pin functions as an SV2 output pin
(Initial value)
Bit 0⎯P30/SV1 Pin Switching (PMR30): PMR30 sets whether the P30/SV1 pin is used as a P30
I/O pin or an SV1 pin for servo monitor output.
Bit 0
PMR30
Description
0
The P30/SV1 pin functions as a P30 I/O pin
1
The P30/SV1 pin functions as an SV1 output pin
Rev.2.00 Jan. 15, 2007 page 206 of 1174
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(Initial value)
Section 10 I/O Port
Port Control Register 3 (PCR3)
Bit :
Initial value :
R/W :
7
PCR37
6
PCR36
5
PCR35
4
PCR34
3
PCR33
2
PCR32
1
PCR31
0
PCR30
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Port control register 3 (PCR3) controls the I/Os of pins P37 to P30 of port 3 in a unit of bit.
When PCR3 is set to 1, the corresponding P37 to P30 pins become output pins, and when it is set
to 0, they become input pins. When the relevant pin is set to a general I/O by PMR3, settings of
PCR3 and PDR3 become valid.
PCR3 is an 8-bit write-only register. When PCR3 is read, 1 is read. When reset, PCR3 is
initialized to H'00.
Bits 7 to 0⎯Pin 37 to P30 Pin Switching (PCR37 to PCR30)
Bit n
PCR3n
Description
0
The P3n pin functions as an input pin
1
The P3n pin functions as an output pin
Note:
(Initial value)
n = 7 to 0
Port Data Register 3 (PDR3)
Bit :
Initial value :
R/W :
7
PDR37
6
PDR36
5
PDR35
4
PDR34
3
PDR33
2
PDR32
1
PDR31
0
PDR30
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port data register 3 (PDR3) stores the data for the pins P37 to P30 of port 3. When PCR3 is 1
(output), the PDR3 values are directly read if port 3 is read. Accordingly, the pin states are not
affected. When PCR3 is 0 (input), the pin states are read if port 3 is read.
PDR3 is an 8-bit read/write enable register. When reset, PDR3 is initialized to H'00.
Rev.2.00 Jan. 15, 2007 page 207 of 1174
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Section 10 I/O Port
MOS Pull-Up Select Register 3 (PUR3)
Bit :
Initial value :
R/W :
7
PUR37
6
PUR36
5
PUR35
4
PUR34
3
PUR33
2
PUR32
1
PUR31
0
PUR30
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
MOS pull-up selector register 3 (PUR3) controls the ON and OFF of the MOS pull-up transistor
of port 3. Only the pin whose corresponding bit of PCR3 was set to 0 (input) becomes valid. If the
corresponding bit of PCR3 is set to 1 (output), the corresponding bit of PUR3 becomes invalid and
the MOS pull-up transistor is turned off.
PUR3 is an 8-bit read/write enable register. When reset, PUR3 is initialized to H'00.
Bits 7 to 0⎯P37 to P30 MOS Pull-Up Control (PUR37 to PUR30)
Bit n
PCR3n
Description
0
The P3n pin has no MOS pull-up transistor
1
The P3n pin has a MOS pull-up transistor
Note:
10.5.3
(Initial value)
n = 7 to 0
Pin Functions
This section describes the port 3 pin functions and their selection methods.
P37/TMO: P37/TMO is switched as shown below according to the PMR37 bit in PMR3 and the
PCR37 bit in PCR3.
PMR37
PCR37
Pin Function
0
0
P37 input pin
1
P37 output pin
*
TMO output pin
1
Legend: * Don’t care
Rev.2.00 Jan. 15, 2007 page 208 of 1174
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Section 10 I/O Port
P36/BUZZ: P36/BUZZ is switched as shown below according to the PMR36 bit in PMR3 and the
PCR36 bit in PCR3.
PMR36
PCR36
Pin Function
0
0
P36 input pin
1
P36 output pin
*
BUZZ output pin
1
Legend: * Don’t care
P35/PWM3: P35/PWM3 is switched as shown below according to the PMR3n bit in PMR3 and
the PCR3n bit in PCR3.
PMR35
PCR35
Pin Function
0
0
P35 input pin
1
P35 output pin
*
PWM3 output pin
1
Legend: * Don’t care
Note:
The H8S/2197S and H8S/2196S do not have PWM3 pin function.
P34/PWM2: P34/PWM2 is switched as shown below according to the PMR34 bit in PCR3 and
the PCR34 bit in PCR3.
PMR34
PCR34
Pin Function
0
0
P34 input pin
1
P34 output pin
*
PWM2 output pin
1
Legend: * Don’t care
Note:
The H8S/2197S and H8S/2196S do not have PWM2 pin function.
P33/PWM1: P33/PWM1 is switched as shown below according to the PMR33 bit in PMR3 and
the PCR33 bit in PCR3.
PMR33
PCR33
Pin Function
0
0
P33 input pin
1
P33 output pin
*
PWM1 input pin
1
Legend: * Don’t care
Rev.2.00 Jan. 15, 2007 page 209 of 1174
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Section 10 I/O Port
P32/PWM0: P32/PWM0 is switched as shown below according to the PMR32 bit in PMR3 and
the PCR32 bit in PCR.
PMR32
PCR32
Pin Function
0
0
P32 input pin
1
P32 output pin
*
PWM0 output pin
1
P31/SV2: P31/SV2 is switched as shown below according to the PMR31 bit in PMR3 and the
PCR31 bit in PCR3.
PMR31
PCR3
Pin Function
0
0
P31 input pin
1
P31 output pin
*
SV2 output pin
1
P30/SV1: P30/SV1 is switched as shown below according to the PMR30 bit in PMR3 and the
PCR30 bit in PCR3.
PMR30
PCR30
Pin Function
0
0
P30 input pin
1
P30 output pin
*
SV1 output pin
1
Legend: * Don’t care
10.5.4
Pin States
Table 10.13 shows the port 3 pin states in each operation mode.
Table 10.13 Port 3 Pin States
Pins
Reset
Active
Sleep
Standby
Watch
Subactive
Subsleep
P37/TMO
P36/BUZZ
P35/PWM3
to
P32/PWM0
P31/SV2
P30/SV1
Highimpedance
Operation
Holding
Highimpedance
Highimpedance
Operation
Holding
Rev.2.00 Jan. 15, 2007 page 210 of 1174
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Section 10 I/O Port
10.6
Port 4
10.6.1
Overview
Port 4 is an 8-bit I/O port. Table 10.14 shows the port 4 configuration.
Port 4 consists of pins that are used both as standard I/O ports (P47 to P40) and output compare
output (FTOA, FTOB), input capture input (FTIA, FTIB, FTIC, FTID) or 14-bit PWM output
(PWM14). It is switched by port mode register 4 (PMR4), timer output compare control register
(TOCR), and port control register 4 (PCR4).
Table 10.14 Port 4 Configuration
Port
Function
Port 4
Alternative Function
P47 (standard I/O port)
RPTRG (realtime output port trigger input)
P46 (standard I/O port)
FTOB (timer X1 output compare output)
P45 (standard I/O port)
FTOA (timer X1 output compare output)
P44 (standard I/O port)
FTID (timer X1 input capture input)
P43 (standard I/O port)
FTIC (timer X1 input capture input)
P42 (standard I/O port)
FTIB (timer X1 input capture input)
P41 (standard I/O port)
FTIA (timer X1 input capture input)
P40 (standard I/O port)
PWM14 (14-bit PWM output)
Note: The H8S/2197S and H8S/2196S do not have PWM14, FTIA, FTIB, FTIC, FTID, FTOA, and
FTOB pin functions.
10.6.2
Register Configuration
Table 10.15 shows the port 4 register configuration.
Table 10.15 Port 4 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Port mode register 4
PMR4
R/W
Byte
H'7E
H'FFDB
Port control register 4
PCR4
W
Byte
H'00
H'FFD4
Port data register 4
PDR4
R/W
Byte
H'00
H'FFC4
Note:
*
Lower 16 bits of the address.
Rev.2.00 Jan. 15, 2007 page 211 of 1174
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Section 10 I/O Port
Port Mode Register 4 (PMR4)
Bit :
Initial value :
R/W :
7
PMR47
6
—
5
—
4
—
3
—
2
—
1
—
0
PMR40
0
1
1
1
1
1
1
0
R/W
—
—
—
—
—
—
R/W
Port mode register 4 (PMR4) controls switching of the P47/RPTRG pin and the P40/PWM14 pin
function. The switchings of the P46/FTOB and P45/FTOA functions are controlled by TOCR. See
section 16, Timer X1. The FTIA, FTIB, FTIC, and FTID inputs always function.
PMR4 is an 8-bit read/write enable register. When reset, PMR4 is initialized to H'7E.
Because the RPTRG input always function, the alternative pin need always be set to the high or
low level regardless of the active mode and low power consumption mode. Note that the pin level
must not reach an intermediate level.
Because the FTIA, FTIB, FTIC, and FTID inputs always function, each input uses the input edge
to the alternative general I/O pins P44, P43, P42, and P41 as input signals.
Bit 7⎯P47/RPTRG Pin Switching (PMR47): PMR47 sets whether the P47/RPTRG pin is used
as a P40 I/O pin or a RPTRG pin for the realtime output port trigger input.
Bit 7
PMR47
Description
0
The P47/RPTRG pin functions as a P47 I/O pin
1
The P47/RPTRG pin functions as a RPTRG I/O pin
(Initial value)
Bits 6 to 1⎯Reserved Bits: Reserved bits. When the bits are read, 1 is always read. The write
operation is invalid.
Bit 0⎯P40/PWM14 Pin Switching (PMR40): PMR40 sets whether the P40/PWM14 pin is used
as a P40 I/O pin or a PWM14 pin for the 14-bit PWM square wave output.
Bit 0
PMR40
Description
0
The P40/PWM14 pin functions as a P40 I/O pin
1
The P40/PWM14 pin functions as a PWM14 output pin
Note: The H8S/2197S and H8S/2196S do not have PWM14 pin function.
Rev.2.00 Jan. 15, 2007 page 212 of 1174
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(Initial value)
Section 10 I/O Port
Port Control Register 4 (PCR4)
Bit :
Initial value :
R/W :
7
PCR47
6
PCR46
5
PCR45
4
PCR44
3
PCR43
2
PCR42
1
PCR41
0
PCR40
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Port control register 4 (PCR4) controls the I/Os of pins P47 to P40 of port 4 in a unit of bit.
When PCR4 is set to 1, the corresponding P47 to P40 pins become output pins, and when it is set
to 0, they become input pins. When the relevant pin is set to a general I/O by PMR4, settings of
PCR4 and PDR4 become valid.
PCR4 is an 8-bit write-only register. When PCR4 is read, 1 is read. When reset, PCR4 is
initialized to H'00.
Bits 7 to 0⎯P47 to P40 Pin Switching (PCR47 to PCR40)
Bit n
PCR4n
Description
0
The P4n pin functions as an input pin
1
The P4n pin functions as an output pin
Note:
(Initial value)
n = 7 to 0
Port Data Register 4 (PDR4)
Bit :
Initial value :
R/W :
7
PDR47
6
PDR46
5
PDR45
4
PDR44
3
PDR43
2
PDR42
1
PDR41
0
PDR40
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port data register 4 (PDR4) stores the data for the pins P47 to P40 of port 4. When PCR4 is 1
(output), the PDR4 values are directly read if port 4 is read. Accordingly, the pin states are not
affected. When PCR4 is 0 (input), the pin states are read if port 4 is read.
PDR4 is an 8-bit read/write enable register. When reset, PDR4 is initialized to H'00.
Rev.2.00 Jan. 15, 2007 page 213 of 1174
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Section 10 I/O Port
10.6.3
Pin Functions
This section describes the port 4 pin functions and their selection methods.
P47/RPTRG: P47/RPTRG is switched as shown below according to the PMR47 bit in PMR4 and
the PMR47 bit in PMR4 and the PCR47 bit in PCR4.
PMR47
PCR47
Pin Function
0
0
P47 input pin
1
P47 output pin
*
RPTRG input pin
1
Legend: * Don’t care
P46/FTOB: P46/FTOB is switched as shown below according to the PCR46 bit in PCR4 and the
OEB bit in TOCR.
OEB
PCR46
Pin Function
0
0
P46 input pin
1
P46 output pin
*
FTOB output pin
1
Legend: * Don’t care
Note:
The H8S/2197S and H8S/2196S do not have FTOB pin function.
P45/FTOA: P45/FTOA is switched as shown below according to the PCR45 bit in PCR4 and the
OEA bit in TOCR.
OEA
PCR45
Pin Function
0
0
P45 input pin
1
P45 output pin
*
FTOA output pin
1
Legend: * Don’t care
Note:
The H8S/2197S and H8S/2196S do not have FTOA pin function.
Rev.2.00 Jan. 15, 2007 page 214 of 1174
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Section 10 I/O Port
P44/FTID: P44/FTID is switched as shown below according to the PCR44 bit in PCR4.
PCR44
Pin Function
0
P44 input pin
1
P44 output pin
FTID input pin
Note: The H8S/2197S and H8S/2196S do not have FTID pin function.
P43/FTIC: P43/FTIC is switched as shown below according to the PCR43 bit in PCR4.
PCR43
Pin Function
0
P43 input pin
1
P43 output pin
FTIC input pin
Note: The H8S/2197S and H8S/2196S do not have FTIC pin function.
P42/FTIB: P42/FTIB is switched as shown below according to the PCR42 bit in PCR4.
PCR42
Pin Function
0
P42 input pin
1
P42 output pin
FTIB input pin
Note: The H8S/2197S and H8S/2196S do not have FTIB pin function.
P41/FTIA: P41/FTIA is switched as shown below according to the PCR41 bit in PCR4.
PCR41
Pin Function
0
P41 input pin
1
P41 output pin
FTIA input pin
Note: The H8S/2197S and H8S/2196S do not have FTIA pin function.
P40/PWM14: P40/PWM14 is switched as shown below according to the PMR40 bit in PMR4 and
the PCR40 bit in PCR4.
PMR40
PCR40
Pin Function
0
0
P40 input pin
1
P40 output pin
*
PWM14 input pin
1
Legend: * Don’t care
Note:
The H8S/2197S and H8S/2196S do not have PWM14 pin function.
Rev.2.00 Jan. 15, 2007 page 215 of 1174
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Section 10 I/O Port
10.6.4
Pin States
Table 10.16 shows the port 4 pin states in each operation mode.
Table 10.16 Port 4 Pin States
Pins
Reset
Active
Sleep
Standby
Watch
Subactive
Subsleep
P47/RPTRG
P46/FTOB
P45/FTOA
P44/FTID
P43/FTIC
P42/FTIB
P41/FTIA
P40/PWM14
Highimpedance
Operation
Holding
Highimpedance
Highimpedance
Operation
Holding
Note: If the RPTRG input pin is set, the pin level must be set to the high or low level regardless of
the active mode or low power consumption mode. Note that the pin level must not reach an
intermediate level.
Because the FTIA, FTIB, FTIC, and FTID inputs always function, the alternative pin need be
set to the high or low level regardless of the active mode and low power consumption
mode.
Rev.2.00 Jan. 15, 2007 page 216 of 1174
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Section 10 I/O Port
10.7
Port 6
10.7.1
Overview
Port 6 is an 8-bit I/O port. Table 10.17 shows the port 6 configuration. Port 6 is a large current I/O
port.
The sink current is 20 mA maximum (VOL = 1.7 V) and four pins can be turned on at the same
time. Port 6 consists of pins that are used as large current I/O ports (P67 to 60) and realtime output
ports (RP7 to RP0). It is switched by port mode register 6 (PMR6), port mode register A (PMRA),
and port control register 6 (PCR6).
The realtime output function can instantaneously switch the output data by an external or internal
trigger port.
Table 10.17 Port 6 Configuration
Port
Function
Alternative Function
Port 6
P67 (large current I/O port)
RP7/TMBI (timer B event input)
P66 (large current I/O port)
RP6/ADTRG (A/D conversion start external
trigger input)
P65 (large current I/O port)
RP5 (realtime output port pin)
P64 (large current I/O port)
RP4 (realtime output port pin)
P63 (large current I/O port)
RP3 (realtime output port pin)
P62 (large current I/O port)
RP2 (realtime output port pin)
P61 (large current I/O port)
RP1 (realtime output port pin)
P60 (large current I/O port)
RP0 (realtime output port pin)
Rev.2.00 Jan. 15, 2007 page 217 of 1174
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Section 10 I/O Port
10.7.2
Register Configuration
Table 10.18 shows the port 6 register configuration.
Table 10.18 Port 6 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Port mode register 6
PMR6
R/W
Byte
H'00
H'FFDD
Port mode register A
PMRA
R/W
Byte
H'3F
H'FFD9
Port control register 6
PCR6
W
Byte
H'00
H'FFD6
Port data register 6
PDR6
R/W
Byte
H'00
H'FFC6
Realtime output trigger
select register 1
RTPSR1
R/W
Byte
H'00
H'FFE5
Realtime output trigger
edge select register
2
RTPEGR*
R/W
Byte
H'FC
H'FFE4
Port control register slave 6 PCRS6
⎯
Byte
H'00
⎯
Port data register slave 6
⎯
Byte
H'00
⎯
PDRS6
Notes: 1. Lower 16 bits of the address.
2. RTPEGR is also used by port 7.
Port Mode Register 6 (PMR6)
Bit :
Initial value :
R/W :
7
PMR67
6
PMR66
5
PMR65
4
PMR64
3
PMR63
2
PMR62
1
PMR61
0
PMR60
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port mode register 6 (PMR6) controls switching of each pin function of port 6. The switching is
specified in units of bits.
PMR6 is an 8-bit read/write enable register. When reset, PMR6 is initialized to H'00.
Bits 7 to 0⎯P67/RP7 to P60/RP0 Pin Switching (PMR67 to PMR60): PMR67 to PMR60 set
whether the P6n/RPn pin is used as a P6n I/O pin or an RPn pin for the realtime output port.
Bit n
PMR6n
Description
0
The P6n/RPn pin functions as a P6n I/O pin
1
The P6n/RPn pin functions as an RPn output pin
Note:
n = 7 to 0
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(Initial value)
Section 10 I/O Port
Port Mode Register A (PMRA)
Bit :
Initial value :
R/W :
7
PMRA7
6
PMRA6
5
—
4
—
3
—
2
—
1
—
0
—
0
R/W
0
R/W
1
—
1
—
1
—
1
—
1
—
1
—
Port mode register A (PMRA) switches the pin functions in port 6. Switching is specified in a unit
of bit. PMRA is an 8-bit read/write register.
When reset, PMRA is initialized to H'3F.
Bit 7⎯P67/RP7/TMBI Pin Switching (PMRA7): PMRA7 can be used as a P6n I/O pin or a
TMBI pin for timer B event input.
Bit 7
PMRA7
Description
0
P67/RP7/TMBI pin functions as a P67/RP7 I/O pin
1
P67/RP7/TMBI pin functions as a TMBI pin
(Initial value)
Bit 6⎯Timer B Event Input Edge Switching (PMRA6): PMRA6 selects the TMBI edge sense.
Bit 6
PMRA6
Description
0
Timer B event input detects falling edge
1
Timer B event input detects rising edge
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Section 10 I/O Port
Port Control Register 6 (PCR6)
Bit :
Initial value :
R/W :
7
PCR67
6
PCR66
5
PCR65
4
PCR64
3
PCR63
2
PCR62
1
PCR61
0
PCR60
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Port control register 6 (PCR6) selects the general I/O of port 6 and controls the realtime output in
a unit of bit together with PMR6.
When PMR6 = 0, the corresponding P67 to P60 pins become general output pins if PCR6 is set to
1, and they become general input pins if it is set to 0.
When PMR6 = 1, PCR6 controls the corresponding RP7 to RP0 realtime output pins. For details,
see section 10.7.4, Operation.
PCR6 is an 8-bit write-only register. When PCR6 is read, 1 is read. When reset, PCR6 is
initialized to H'00.
PMR6
PCR6
Bit n
Bit n
PMR6n
PCR6n
Description
0
0
The P6n/RPn pin functions as a P6n general I/O input pin
(Initial value)
1
The P6n/RPn pin functions as a P6n general output pin
*
The P6n/RPn pin functions as an RPn realtime output pin
1
Legend: * Don’t care
Note:
n = 7 to 0
Port Data Register 6 (PDR6)
Bit :
Initial value :
R/W :
7
PDR67
6
PDR66
5
PDR65
4
PDR64
3
PDR63
2
PDR62
1
PDR61
0
PDR60
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port data register 6 (PDR6) stores the data for the pins P67 to P60 of port 6.
For PMR6 = 0, when PCR6 is 1 (output), the PDR6 values are directly read if port 6 is read.
Accordingly, the pin states are not affected. When PCR6 is 0 (input), the pin states are read if port
6 is read.
For PMR6 = 1, port 6 becomes a realtime output pin. For details, see section 10.7.4, Operation.
PDR6 is an 8-bit read/write enable register. When reset, PDR6 is initialized to H'00.
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Section 10 I/O Port
Realtime Output Trigger Select Register (RTPSR1)
Bit :
Initial value :
R/W :
1
0
2
4
3
7
6
5
RTPSR17 RTPSR16 RTPSR15 RTPSR14 RTPSR13 RTPSR12 RTPSR11 RTPSR10
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
The realtime output trigger select register (RTPSR1) sets whether the external trigger (RPTRG pin
input) or the internal trigger (HSW) is used as an trigger input for the realtime output in a unit of
bit. For the internal trigger HSW, see section 26.4, HSW (Head-switch) Timing Generator.
RTPSR1 is an 8-bit read/write enable register. When reset, RTPSR1 is initialized to H'00.
Bits 7 to 0⎯RP7 to RP0 Trigger Switching
Bit n
RTPSR1n
Description
0
Selects the external trigger (RPTRG pin input) as a trigger input
1
Selects the internal trigger (HSW) a trigger input
Note:
(Initial value)
n = 7 to 0
Real Time Output Trigger Edge Select Register (RTPEGR)
Bit :
7
—
6
—
5
—
4
—
3
—
2
—
Initial value :
R/W :
1
—
1
—
1
—
1
—
1
—
1
—
1
0
RTPEGR1 RTPEGR0
0
R/W
0
R/W
The realtime output trigger edge select register (RTPEGR) specifies the edge sense of the external
or internal trigger input for the realtime output.
RTPEGR is an 8-bit read/write enable register. When reset, RTPEGR is initialized to H'FC.
Bits 7 to 2⎯Reserved Bits: Reserved bits. When the bits are read, 1 is always read. The write
operation is invalid.
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Section 10 I/O Port
Bits 1 and 0⎯Realtime Output Trigger Edge Select (RTPEGR1, RTPEGR0): RTPEGR1 and
RTPEGR0 select the edge sense of the external or internal trigger input for the realtime output.
Bit 1
Bit 0
RTPEGR1
RTPEGR0
Description
0
0
Inhibits a trigger input
1
Selects the rising edge of a trigger input
0
Selects the falling edge of a trigger input
1
Selects both the leading and falling edges of a trigger input
1
10.7.3
(Initial value)
Pin Functions
This section describes the port 6 pin functions and their selection methods.
P67/RP7/TMBI: P67/RP7/TMBI is switched as shown below according to the PMRA7 bit in
PMRA, PMR67 bit in PMR6, and PCR67 bit in PCR6.
Output Value
Value When PDR6n
Was Read
P67 input pin
⎯
P67 pin
P67 output pin
PDR67
1 2
Hi-Z* *
PDR67
PMRA7
PMR67
PCR67
0
0
0
1
0
RP7 output pin
1
Pin Function
PDRS67*
1
1
*
0
TMBI input pin
1
⎯
PDR67
2
P67 pin
PDR67
Notes: 1. Hi-Z: High impedance
2. When PMR67 = 1 (realtime output pin), indicates the state after the PCR67 setup value
has been transferred to PCRS67 by a trigger input.
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Section 10 I/O Port
P66/RP6/ADTRG: P66/RP6/ADTRG is switched as shown below according to the PMR66 bit in
PMR6 and PCR66 bit in PCR6. The ADTRG pin function switching is controlled by the ADTSR.
For details, refer to section 24, A/D converter.
PMR66
PCR66
Pin Function
Output Value
Value When PDR66 Was Read
0
0
P66 input pin
⎯
P66 pin
1
P66 output pin
PDR66
0
RP6 output pin
PDR66
1 2
Hi-Z* *
1
PDR66
2
PDRS66*
1
Notes: 1. Hi-Z: High impedance
2. When PMR66 = 1 (realtime output pin), indicates the state after the PCR66 setup value
has been transferred to PCRS66 by a trigger input.
P65/RP5 to P60/RPD: P65/RP5 to P60/RPD are switched below according to the PMRAn bit in
PMRA, PMR6n bit in PMR6, and PCR6n bit in PCR6.
PMR6n
PCR6n
Pin Function
Output Value
Value When PDR6n Was Read
0
0
P6n input pin
⎯
P6n pin
1
P6n output pin
PDR6n
PDR6n
1
0
RPn output pin
Hi-Z* *
PDR6n
1
RPn output pin
PDRS6n*
1 2
2
Notes: n = 5 to 0
1. Hi-Z: High impedance
2. When PMR6n = 1 (realtime output pin), indicates the state after the PCR6n setup value
has been transferred to PCRS6n by a trigger input.
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Section 10 I/O Port
10.7.4
Operation
Port 6 can be used as a realtime output port or general I/O output port by PMR6. Port 6 functions
as a realtime output port when PMR6 = 1 and as a general I/O port when PMR6 = 0. The operation
per port 6 function is shown below. (See figure 10.2.)
RTPEGR write
Internal trigger
HSW
External trigger
RPTRG
CK
RTPEGR
Selection
circuit
RTPSR write
CK
RTPSR1
Internal data bus
RMR6 write
CK
PMR6
RDR6 write
CK
CK
PDR6
RDRS6
P6/RP
RDR6 read
Selection
circuit
RCR6 write
CK
CK
PCR6
PCRS6
Legend:
PMR6 : Port mode register 6
RTPSR1 : Realtime output trigger select register
PCR6 : Port control register 6
RTPEGR : Realtime output trigger edge select register
PDR6 : Port data register 6
HSW
PCRS6 : Port control register slave 6
RPTRG : External trigger pin
: Internal trigger signal
PDRS6 : Port data register slave 6
Figure 10.2 Port 6 Function Block Diagram
Rev.2.00 Jan. 15, 2007 page 224 of 1174
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Section 10 I/O Port
• Operation of the Realtime Output Port (PMR6 = 1)
When PMR6 is 1, it operates as a realtime output port. When a trigger is input, the PDR6 data
is transferred to PDRS6 and the PCR6 is transferred data to PCRS6, respectively. In this case,
when PCRS6 is 1, the PDRS6 data of the corresponding bit is output to the RP pin. When
PCRS6 is 0, the RP pin of the corresponding bit is output to the high-impedance state. In other
words, the pin output state (high or low) or high-impedance state can instantaneously be
switched by a trigger input.
Adversely, when PDR6 is read, the PDR6 values are read regardless of the PCR6 and PCRS6
values.
• Operation of the general I/O port (PMR6 = 0)
When PMR6 is 0, it operates as a general I/O port. When data is written to PDR6, the same
data is also written to PDRS6. Accordingly, because both PDR6 and PDRS6 and both PCR6
and PCRS6 can be handled as one register, respectively, they can be used in the same way as a
normal general I/O port. In other words, if PCR6 is 1, the PDR6 data of the corresponding bit
is output to the P6 pin. If PCR6 is 0, the P6 pin of the corresponding bit becomes an input.
Adversely, assuming that PDR6 is read, the PDR6 values are read when PCR6 is 1 and the pin
values are read when PCR6 is 0.
10.7.5
Pin States
Table 10.19 shows the port 6 pin states in each operation mode.
Table 10.19 Port 6 Pin States
Pins
Reset
Active
Sleep
Standby
Watch
Subactive
Subsleep
P67/RP7/TMBI
P66/RP6/ADTRG
P65/RP5
to
P60/RP0
Highimpedance
Operation
Holding
Highimpedance
Highimpedance
Operation
Holding
Note: If the TMBI and ADTRG input pins are set, the pin level must be set to the high or low level
regardless of the active mode or low power consumption mode. Note that pin level must not
reach an intermediate level.
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Section 10 I/O Port
10.8
Port 7
10.8.1
Overview
Port 7 is an 8-bit I/O port. Table 10.20 shows the port 7 configuration.
Port 7 consists of pins that are used both as standard I/O ports (P77 to P70), HSW timing
generation circuit (programmable pattern generator: PPG) outputs (PPG7 to PPG0), and realtime
output port (RPB to RP8). It is switched by port mode register 7 (PMR7) and port control register
7 (PCR7).
For the programmable generator (PPG), see section 26.4, HSW (Head-switch) Timing Generator.
Table 10.20 Port 7 Configuration
Port
Function
Alternative Function
Port 7
P77 (standard I/O port)
PPG7 (HSW timing output)
RPB (realtime output port)
P76 (standard I/O port)
PPG6 (HSW timing output)
RPA (realtime output port)
P75 (standard I/O port)
PPG5 (HSW timing output)
RP9 (realtime output port)
P74 (standard I/O port)
PPG4 (HSW timing output)
RP8 (realtime output port)
P73 (standard I/O port)
PPG3 (HSW timing output)
P72 (standard I/O port)
PPG2 (HSW timing output)
P71 (standard I/O port)
PPG1 (HSW timing output)
P70 (standard I/O port)
PPG0 (HSW timing output)
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Section 10 I/O Port
10.8.2
Register Configuration
Table 10.21 shows the port 7 register configuration.
Table 10.21 Port 7 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Port mode register 7
PMR7
R/W
Byte
H'00
H'FFDE
Port mode register B
PMRB
R/W
Byte
H'0F
H'FFDA
Port control register 7
PCR7
W
Byte
H'00
H'FFD7
Port data register 7
PDR7
R/W
Byte
H'00
H'FFC7
Realtime output trigger
select register 2
RTPSR2
R/W
Byte
H'0F
H'FFE6
Realtime output trigger
edge select register
RTPEGR
R/W
Byte
H'FC
H'FFE4
Port control register slave 7 PCRS7
⎯
Byte
H'00
⎯
Port data register slave 7
⎯
Byte
H'00
⎯
Note:
*
PDRS7
Lower 16 bits of the address.
Port Mode Register 7 (PMR7)
Bit :
Initial value :
R/W :
7
PMR77
6
PMR76
5
PMR75
4
PMR74
3
PMR73
2
PMR72
1
PMR71
0
PMR70
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port mode register 7 (PMR7) controls switching of each pin function of port 7. The switching is
specified in a unit of bit.
PMR7 is an 8-bit read/write enable register. When reset, PMR7 is initialized to H'00.
Bits 7 to 0⎯P77/PPG7 to P70/PPG0 Pin Switching (PMR77 to PMR70): PMR77 to PMR70
set whether the P7n/PPGn pin is used as a P7n I/O pin or a PPGn pin for the HSW timing
generation circuit output.
Bit n
PMR7n
Description
0
The P7n/PPGn pin functions as a P7n I/O pin
1
The P7n/PPGn pin functions as a PPGn output pin
Note:
(Initial value)
n = 7 to 0
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Section 10 I/O Port
Port Mode Register B (PMRB)
Bit :
Initial value :
R/W :
7
PMRB7
6
PMRB6
5
PMRB5
4
PMRB4
3
—
2
—
1
—
0
—
0
R/W
0
R/W
0
R/W
0
R/W
1
—
1
—
1
—
1
—
Port mode register B (PMRB) controls switching of each pin function of port 7. The switching is
specified in a unit of bit.
PMRB is an 8-bit read/write enable register. When reset, PMRB is initialized to H'0F.
Bits 7 to 4⎯P77/RPB to P74/RP8 Pin Switching (PMRB7 to PMRB4): P77/RPB to P74/RP8
set whether the P7n/RPm pin is used as a P7n I/O pin or a RPm pin for the realtime output port. (n
= 7 to 4 and m = B, A, 9, or 8)
Bit n
PMRBn
Description
0
P7n/RPm pin functions as a P7n I/O pin
1
P7n/RPm pin functions as a RPm I/O pin
Note:
(Initial value)
n = 7 to 4 and m = B, A, 9, and 8
Bits 3 to 0⎯Reserved Bits: Reserved bits. When the bits are read, 1 is always read. The write
operation is invalid.
Port Control Register 7 (PCR7)
Bit :
Initial value :
R/W :
7
PCR77
6
PCR76
5
PCR75
4
PCR74
3
PCR73
2
PCR72
1
PCR71
0
PCR70
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Port control register 7, together with PMRB, enable the general-purpose input/output of port 7 and
controls realtime output in bit units.
For details, refer to section 10.8.4. Operation.
PCR7 is an 8-bit write-only register. When the PCR7 is read, 1 is always read. When reset, PCR7
is initialized to H'00.
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Section 10 I/O Port
Bits 7 to 0⎯P77 to P70 Pin I/O Switching (PCR77 to PCR70)
PMRB
PCR7
Bitn
Bitn
PMRBn
PCR7n
Description
0
0
P7n/RPm pin functions as a P7n general input pin
1
P7n/RPm pin functions as a P7n general output pin
*
P7n/RPm pin functions as a RPm realtime output pin
1
(Initial Value)
Legend: * Don’t care
Note:
n = 7 to 4 and m = B, A, 9, and 8
Port Data Register 7 (PDR7)
Bit :
Initial value :
R/W :
7
PDR77
6
PDR76
5
PDR75
4
PDR74
3
PDR73
2
PDR72
1
PDR71
0
PDR70
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port data register 7 (PDR7) stores the data for the pins P77 to P70 of port 7.
If PCR7 is 1 (output) when PMRB = 0, the PDR7 values are directly read when port 7 is read.
Accordingly, the pin states are not affected. When PCR7 is 0 (input), the pin states are read if port
7 is read. When PMRB = 1, port 7 pin functions as a realtime output pin. For details, refer to
section 10.8.4, Operation.
PDR7 is an 8-bit read/write enable register. When reset, PDR7 is initialized to H'00.
Realtime Output Trigger Select Register 2 (RTPSR2)
Bit :
Initial value :
R/W :
4
7
6
5
RTPSR27 RTPSR26 RTPSR25 RTPSR24
0
R/W
0
R/W
0
R/W
0
R/W
3
—
2
—
1
—
0
—
1
—
1
—
1
—
1
—
Realtime output trigger select register (RTPSR2) selects whether to use an external trigger
(RPTRG pin input) or internal trigger (HSW) for the realtime output trigger input by specifying a
unit of bit. For details on internal trigger HSW, refer to section 26.4, HSW (Head-switch) Timing
Generator.
RTPSR2 is an 8-bit read/write enable register.
When reset, RTPSR2 is initialized to H'0F.
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Section 10 I/O Port
Bits 7 to 4⎯RPB to RP8 Pin Trigger Switching (RTPSR27 to RTPSR24)
Bit7
RTPSR2n
Description
0
Selects external trigger (RPTRG pin input) for trigger input
1
Note:
(Initial value)
Selects internal trigger (HSW) for trigger input
n = 7 to 4
Realtime Output Trigger Edge Selection Register (RTPEGR)
Bit :
7
—
6
—
5
—
4
—
3
—
2
—
Initial value :
R/W :
1
—
1
—
1
—
1
—
1
—
1
—
1
0
RTPEGR1 RTPEGR0
0
R/W
0
R/W
The realtime output trigger edge selection register (RTPEGR) specifies the sensed edge(s) of
external or internal trigger input for realtime output.
RTPEGR is an 8-bit readable/writable register. In a reset, RTPEGR is initialized to H'FC.
Bits 7 to 2⎯Reserved: These bits are always read as 1 and cannot be modified.
Bits 1 and 0⎯Realtime Output Trigger Edge Select (RTPEGR1, RTPEGR0): These bits
select the sensed edge(s) of external or internal trigger input for realtime output.
Bit 1
Bit 0
RTPEGR1
RTPEGR0
Description
0
0
Disables trigger input
1
Selects trigger input rising edge
0
Selects trigger input falling edge
1
Selects trigger input rising and falling edges
1
Rev.2.00 Jan. 15, 2007 page 230 of 1174
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(Initial value)
Section 10 I/O Port
10.8.3
Pin Functions
This section describes the port 7 pin functions and their selection methods.
P77/PPG7/RPB to P74/PPG4/RP8: P77/PPG7/RPB to P74/PPG4/RP8 are switched as shown
below according to the PMRBn bit in PMRB and the PCR7n bit in PCR7.
PMRBn
PMR7n
PCR7n
Pin Function
Output Value
Value Returned when
PDR7n is Read
0
0
0
P7n input pin
⎯
P7n pin
1
P7n output pin
PDR7n
PDR7n
0
PPGn output pin
PPGn
P7n pin
RPm output pin
1
Hi-Z*
0
1
1
1
*
0
PDR7n
PDR7n
1
PDRS7n*
1
Legend:
Hi-Z: High impedance
* Don’t care
Notes: n = 7 to 4, m = B, A, 9, 8
1. When PMRBn = 1 (realtime output pin), the state indicated is that after the PCR7n set
value has been transferred to PCRS7n by trigger input.
P73/PPG3 to P70/PPG0: P73/PPG3 to P70/PPG0 are switched as shown below according to the
PMR7n bit in PMR7 and the PCR7n bit in PCR7.
PMR7n
PCR7n
Pin Function
Output Value
Value Returned when PDR7n
Is Read
0
0
P7n input pin
⎯
P7n pin
1
P7n output pin
PDR7n
PDR7n
0
PPGn output pin
PPGn
P7n pin
1
1
Note:
PDR7n
n = 3 to 0
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Section 10 I/O Port
10.8.4
Operation
Port 7 can be used by the PMRB as a realtime output port or an I/O port.
Port 7 functions as a realtime output port when PMRB = 1 and functions as an I/O port when
PMRB = 0. Figure 10.3 show the block diagram of port 7.
Internal
trigger HSW
RTPEGR write
External trigger
RPTRG
CK
RTPEGR
RTPSR2 write
Select
CK
RTPSR2
Internal data bus
PMRA write
CK
PMRB
PDR7 write
CK
CK
PDR7
P7/RP
PDRS7
PDR7 read
Select
PCR7 write
CK
CK
PCR7
PCRS7
Legend:
PMRB:
PCR7:
PDR7:
PCRS7:
PDRS7:
Port mode register B
Port control register 7
Port data register 7
Port control register slave 7
Port data register slave 7
RTPSR2:
RTPEGR:
HSW:
RPTRG:
Realtime output trigger select register
Realtime output trigger edge select register
Internal trigger signal
External trigger pin
Figure 10.3 Block Diagram of Port 7
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Section 10 I/O Port
Port 7 functions as follows:
1. Realtime output port function (PMRB = 1)
Port function as a realtime output port when PMRB is 1. After a trigger input, the PDR7 data is
transferred to PDRS7 and PCR7 data is transferred to PCRS7. In this case, when PCRS7 is 1,
the PDRS7 data of the corresponding bit is output from the RP pin. When PCRS7 is 0, the RP
pin of the corresponding bit enters high-impedance state. In other words, the realtime output
port function can instantaneously switch the pin output state (High or Low) or high-impedance
by a trigger input.
2. I/O port function (PMRB = 0)
Port 7 functions as an I/O port when PMRB is 0. After data is written to PDR7, the same data
is written to PDRS7. After data is written to PCR7, the same data is written to PCRS7. Since
PDR7 and PDRS7, and PCR7 and PCRS7 can be used as one register, the registers can be used
as the I/O ports. In other words, if PCR7 is 1, the PDR7 data of the corresponding bit is output
from the P7 pin. If PCR is 0, the P7 pin of the corresponding bit is an input pin. If PD7 is read,
the PDR7 value is read when PCR7 is 1 and the pin value is read when PCR7 is 0.
10.8.5
Pin States
Table 10.22 shows the port 7 pin states in each operation mode.
Table 10.22 Port 6 Pin States
Pins
Reset
Active
Sleep
Standby
Watch
Subactive Subsleep
P77/PPG7/RPB HighOperation Holding HighHighOperation Holding
to
impedance
impedance impedance
P74/PPG4/RP8
P73/PPG3
to
P70/PPG0
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Section 10 I/O Port
10.9
Port 8
10.9.1
Overview
Port 8 is an 8-bit I/O port. Table 10.23 shows the port 8 configuration.
Port 8 consists of pins that are used both as standard-current I/O ports (P87 to P80) and an external
CTL signal input (EXCTL), a pre-amplifier output result signal input (COMP), color signal
outputs (R, G, and B), a pre-amplifier output selection signal output (H.Amp SW), a control signal
output for processing color signal (C.Rotary), a DPG signal input (DPG), a capstan external sync
signal input (EXCAP), an OSD character display position output (YB0), an OSD character data
output (YC0), and an external reference signal input (EXTTRG). It is switched by port mode
register 8 (PMR8), port mode register C (PMRC), and port control register 8 (PCR8).
Table 10.23 Port 8 Configuration
Port
Function
Alternative Function
Port 8
P87 (standard I/O port)
DPG signal input
P86 (standard I/O port)
External reference signal input
P85 (standard I/O port)
Pre-amplifier output result signal input
Color signal output
P84 (standard I/O port)
Pre-amplifier output selection signal output
Color signal output
P83 (standard I/O port)
Control signal output for processing color signal
Color signal output
P82 (standard I/O port)
External CTL signal input
P81 (standard I/O port)
Capstan external sync signal input
OSD character display position output
P80 (standard I/O port)
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OSD character data output
Section 10 I/O Port
10.9.2
Register Configuration
Table 10.24 shows the port 8 register configuration.
Table 10.24 Port 8 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Port mode register 8
PMR8
R/W
Byte
H'00
H'FFDF
Port mode register C
PMRC
R/W
Byte
H'C5
H'FFE0
Port control register 8
PCR8
W
Byte
H'00
H'FFD8
Port data register 8
PDR8
R/W
Byte
H'00
H'FFC8
Note:
*
Lower 16 bits of the address.
Port Mode Register 8 (PMR8)
Bit :
Initial value :
R/W :
7
PMR87
6
PMR86
5
PMR85
4
PMR84
3
PMR83
2
PMR82
1
PMR81
0
PMR80
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port mode register 8 (PMR8) controls switching of each pin function of port 8. The switching is
specified in a unit of bit.
PMR8 is an 8-bit read/write enable register. When reset, PMR8 is initialized to H'00.
If the EXCTL, COMP, DPG and EXTTRG input pins are set, the pin level need always be set to
the high or low level regardless of the active mode and low power consumption mode. Note that
the pin level must not reach an intermediate level.
Bit 7⎯P87/DPG Pin Switching (PMR87): PMR87 sets whether the P87/DPG pin is used as a
P87 I/O pin or a DPG signal input pin.
Bit 7
PMR87
Description
0
P87/DPG pin functions as a P87 I/O pin
(Drum control signals are input as an overlapped signal)
1
(Initial value)
P87/DPG pin functions as a DPG input pin
(Drum control signals are input as separate signals)
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Section 10 I/O Port
Bit 6⎯P86/EXTTRG Pin Switching (PMR86): PMR86 sets whether the P86/EXTTRG pin is
used as a P86 I/O pin or an external trigger signal input pin.
Bit 6
PMR86
Description
0
P86/EXTTRG pin functions as a P86 I/O pin
1
P86/EXTTRG pin functions as a EXTTRG input pin
(Initial value)
Bit 5⎯P85/COMP Pin Switching (PMR85): PMR85 sets whether the P85/COMP pin is used as
a P85 I/O pin or a COMP input pin of the preamplifier output result signal.
Bit 5
PMR85
Description
0
P85/COMP pin functions as a P85 I/O pin
1
P85/COMP pin functions as a COMP input pin
(Initial value)
Bit 4⎯P84/H.Amp SW Pin Switching (PMR84): PMR84 sets whether the P84/H.Amp SW pin
is used as a P84 I/O pin or H.Amp SW pin of the preamplifier output select signal output.
Bit 4
PMR84
Description
0
P84/H.Amp SW pin functions as a P84 I/O pin
1
P84/H.Amp SW pin functions as a H.Amp SW output pin
(Initial value)
Bit 3⎯P83/C. Rotary Pin Switching (PMR83): PMR83 sets whether the P83/C. Rotary pin is
used as a P83 I/O pin or a C.Rotary pin of a control signal output for processing color signal.
Bit 3
PMR83
Description
0
P83/C.Rotary pin functions as a P83 I/O pin
1
P83/C.Rotary pin functions as a C.Rotary output pin
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(Initial value)
Section 10 I/O Port
Bit 2⎯P82/EXCTL Pin Switching (PMR82): PMR82 sets whether the P82/EXCTL pin
functions as a P82 I/O pin or a EXCTL input pin of external CTL signal input.
Bit 2
PMR82
Description
0
P82/EXCTL pin functions as a P82 I/O pin
1
P82/EXCTL pin functions as a EXCTL input pin
(Initial value)
Bit 1⎯P81/EXCAP Pin Switching (PMR81): PMR81 sets whether the P81/EXCAP pin
functions as a P81 I/O pin or a EXCAP pin of capstan external synchronous signal input.
Bit 1
PMR81
Description
0
P81/EXCAP pin functions as a P81 I/O pin
1
P81/EXCAP pin functions as a EXCAP input pin
(Initial value)
Bit 0⎯P80/YCO Pin Switching (PMR80): PMR80 sets whether the P80/YCO pin functions as a
P80 I/O pin or a YCO pin of OSD character data output.
Bit 0
PMR80
Description
0
P80/YCO pin functions as a P80 I/O pin
1
P80/YCO pin functions as a YCO output pin
(Initial value)
Port Mode Register C (PMRC)
Bit :
7
—
6
—
5
PMRC5
4
PMRC4
3
PMRC3
2
—
1
PMRC1
0
—
Initial value :
R/W :
1
—
1
—
0
R/W
0
R/W
0
R/W
1
—
0
R/W
1
—
Port mode register C (PMRC) controls switching of each pin function of port 8. The switching is
specified in a unit of a bit.
PMRC is an 8-bit read/write enable register. When reset, PMRC is initialized to H'C5.
Bits 7, 6, 2, and 0⎯Reserved Bits: Reserved bits. When the bits are read, 1 is always read. The
write operation is invalid.
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Section 10 I/O Port
Bit 5⎯P85/B Pin Switching (PMRC5): PMRC5 sets whether to use the P85/B pin as a P85 I/O
pin or a B pin of the OSD color signal output.
Bit 5
PMRC5
Description
0
P85/B pin functions as a P85 pin
1
P85/B pin functions as a B output pin
(Initial value)
Bit 4⎯P84/G Pin Switching (PMRC4): PMRC4 sets whether to use the P84/G pin as a P84 I/O
pin or a G pin of the OSD color signal output.
Bit 4
PMRC4
Description
0
P84/G pin functions as a P84 I/O pin
1
P84/G pin functions as a G output pin
(Initial value)
Bit 3⎯P83/R Pin Switching (PMRC3): PMRC3 sets whether to use the P83/R pin as a P83 I/O
pin or a R pin of the OSD color signal output.
Bit 3
PMRC3
Description
0
P83/R pin functions as a P83 I/O pin
1
P83/R pin functions as a R output pin
(Initial value)
Bit 1⎯P81/YBO Pin Switching (PMRC1): PMRC1 sets whether to use the P81/YBO pin as a
P81 I/O pin or a YBO pin of the OSD character display position output.
Bit7
PMR1
Description
0
P81/YBO pin functions as a P81 I/O pin
1
P81/YBO pin functions as a YBO output pin
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(Initial value)
Section 10 I/O Port
Port Control Register 8 (PCR8)
Bit :
Initial value :
R/W :
7
PCR87
6
PCR86
5
PCR85
4
PCR84
3
PCR83
2
PCR82
1
PCR81
0
PCR80
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Port control register 8 (PCR8) controls I/O of pins P87 to P80 of port 8. The I/O is specified in a
unit of bit.
When PCR8 is set to 1, the corresponding P87 to P80 pins become output pins, and when it is set
to 0, they become input pins.
When the pins are set as general I/O pins, the settings of PCR8 and PDR8 become valid.
PCR8 is an 8-bit write-only register. When PCR8 is read, 1 is read. When reset PCR8 is initialized
to H'00.
Bits 7 to 0⎯P87 to P80 Pin I/O Switching
Bit n
PCR8n
Description
0
P8n pin functions as an input pin
1
P8n pin functions as an output pin
Note:
(Initial value)
n = 7 to 0
Port Data Register 8 (PDR8)
Bit :
Initial value :
R/W :
7
PDR87
6
PDR86
5
PDR85
4
PDR84
3
PDR83
2
PDR82
1
PDR81
0
PDR80
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port data register 8 (PDR8) stores the data of pins P87 to P80 port 8. When PCR is 1 (output), the
pin states are read is port 8 is read. Accordingly, the pin states are not affected. When PCR8 is 0
(input), the pin states are read it port 8 is read.
PDR8 is an 8-bit read/write enable register. When reset, PDR8 is initialized to H'00.
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Section 10 I/O Port
10.9.3
Pin Functions
This section describes the port 8 pin functions and their selection methods.
P87/DPG: P87/DPG is switched as shown below according to the PMR87 bit in PMR8 and
PCR87 bit in PCR8.
PMR87
PCR87
Pin Function
0
0
P87 input pin
1
P87 output pin
*
DPG input pin
1
Legend: * Don’t care
P86/EXTTRG: P86/EXTTRG is switched as shown below according to the PMR86 bit in PMR8
and PCR86 bit in PCR8.
PMR86
PCR86
Pin Function
0
0
P86 input pin
1
P86 output pin
*
EXTTRG input pin
1
Legend: * Don’t care
P85/COMP/B: P85/COMP/B is switched as shown below according to the PMR85 bit in PMR8,
PMRC5 bit in PMRC, and PCR85 bit in PCR8.
PMRC5
PMR85
PCR85
Pin Function
0
0
0
P85 input pin
1
P85 output pin
*
1
*
COMP input pin
1
0
*
B output pin
Legend: * Don’t care
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Section 10 I/O Port
P84/H.Amp SW/G: P84/H.Amp SW/G is switched as shown below according to the PMR84 bit
in PMR8, PMRC4 bit in PMRC, and PCR84 bit in PCR8.
PMRC4
PMR84
PCR84
Pin Function
0
0
0
P84 input pin
1
P84 output pin
*
1
*
H.Amp SW output pin
1
0
*
G output pin
Legend: * Don’t care
P83/C.Rotary/R: P83/C.Rotary/R is switched as shown below according to the PMR83bit in
PMR8, PMRC3 bit in PMRC, and PCR83 bit in PCR8.
PMRC3
PMR83
PCR83
Pin Function
0
0
0
P83 input pin
1
P83 output pin
*
1
*
C.Rotary output pin
1
0
*
R output pin
Legend: * Don’t care
P82/EXCTL: P82/EXCTL is switched as shown below according to the PMR82 bit in PMR8 and
PCR82 bit in PCR8.
PMR82
PCR82
Pin Function
0
0
P82 input pin
1
P82 output pin
*
EXCTL input pin
1
Legend: * Don’t care
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Section 10 I/O Port
P81/EXCAP/YBO: P81/EXCAP/YBO is switched as shown below according to the PMR81 bit
in PMR8, PMRC1 bit in PMRC, and PCR81 bit in PCR8.
PMRC1
PMR81
PCR81
Pin Function
0
0
0
P81 input pin
1
P81 output pin
*
1
*
EXCAP output pin
1
0
*
YBO output pin
Legend: * Don’t care
P80/YCO: P80/YCO is switched as shown below according to the PMR80 bit in PMR8 and
PCR80 bit in PCR
PMR80
PCR80
Pin Function
0
0
P80 input pin
1
P80 output pin
1
*
YCO output pin
Legend: * Don’t care
10.9.4
Pin States
Table 10.25 shows the port 8 pin states in each operation mode.
Table 10.25 Port 8 Pin States
Pins
Reset
Active
Sleep
Standby
Watch
Subactive Subsleep
P87/DPG
P86/EXTTRG
P85/COMP/B
P84/H.Amp SW/G
P83/C.Rotary/R
P82/EXCTL
P81/EXCAP/YB0
P80/YCO
Highimpedance
Operation
Holding
Highimpedance
Highimpedance
Operation
Holding
Notes: 1. If the EXCTL, COMP, DPG, and EXTTRG input pins are set, the pin level need always
be set to the high or low level regardless of the active mode and low power
consumption mode. Note that the pin level must not reach an intermediate level.
2. As the DPG always functions, a high or low pin level must be input to the multiplexed
pins regardless of whether active mode or power-down mode is in effect.
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Section 11 Timer A
Section 11 Timer A
11.1
Overview
Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a 32.768-kHz
crystal oscillator.
11.1.1
Features
Features of timer A are as follows:
• Choices of eight different types of internal clocks (φ/16384, φ/8192, φ/4096, φ/1024, φ/512,
φ/256, φ/64 and φ/16) are available for your selection.
• Four different overflowing cycles (1 s, 0.5 s, 0.25 s, and 0.03125 s) are selectable as a clock
timer. (When using a 32.768-kHz crystal oscillator.)
• Requests for interrupt will be output when the counter overflows.
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Section 11 Timer A
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of timer A.
TMA
Prescaler W
(PSW)
1/4
φw/128
÷128*
÷256*
÷64*
φ/16384, φ/8192,
φ/4096, φ/1024,
φ/512, φ/256,
φ/64, φ/16
÷8*
TCA
Prescaler S
(PSS)
System
φ
clock
Overflowing of
the interval
timer
Interrupting
circuit
Internal data bus
32-kHz φw
Crystal oscillator
Interrupt
requests
Prescaler unit
Legend:
TMA : Timer mode register A
TCA : Timer counter A
Note: * Selectable only when the prescaler W output (φw/128) is working as the input clock to the TCA.
Figure 11.1 Block Diagram of Timer A
11.1.3
Register Configuration
Table 11.1 shows the register configuration of timer A.
Table 11.1 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Timer mode register A
TMA
R/W
Byte
H'30
H'FFBA
Timer counter A
TCA
R
Byte
H'00
H'FFBB
Note:
*
Lower 16 bits of the address.
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Section 11 Timer A
11.2
Register Descriptions
11.2.1
Timer Mode Register A (TMA)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
TMAOV
TMAIE
—
—
TMA3
TMA2
TMA1
TMA0
0
0
1
1
0
0
0
0
R/W
—
—
R/W
R/W
R/W
R/W
R/(W)*
Note: * Only 0 can be written to clear the flag.
The timer mode register A (TMA) works to control the interrupts of timer A and to select the input
clock.
TMA is an 8-bit read/write register. When reset, the TMA will be initialized to H'30.
Bit 7⎯Timer A Overflow Flag (TMAOV): This is a status flag indicating the fact that the TCA
is overflowing (H'FF → H'00).
Bit 7
TMAOV
Description
0
[Clearing condition]
(Initial value)
When 0 is written to the TMAOV flag after reading the TMAOV flag under the status
where TMAOV = 1
1
[Setting condition]
When the TCA overflows
Bit 6⎯Enabling Interrupt of the Timer A (TMAIE): This bit works to permit/prohibit
occurrence of interrupt of the Timer A (TMAI) when the TCA overflows and when the TMAOV
of the TMA is set to 1.
Bit 6
TMAIE
Description
0
Prohibits occurrence of interrupt of the Timer A (TMAI)
1
Permits occurrence of interrupt of the Timer A (TMAI)
(Initial value)
Bits 5 and 4⎯Reserved: These bits cannot be modified and are always read as 1.
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Section 11 Timer A
Bit 3⎯Selection of the Clock Source and Prescaler (TMA3): This bit works to select the PSS
or PSW as the clock source for the Timer A.
Bit 3
TMA3
Description
0
Selects the PSS as the clock source for the Timer A
1
Selects the PSW as the clock source for the Timer A
(Initial value)
Bits 2 to 0⎯Clock Selection (TMA2 to TMA0): These bits work to select the clock to input to
the TCA. In combination with the TMA3 bit, the choices are as follows:
Bit 3
Bit 2
Bit 1
Bit 0
TMA3
TMA2
TMA1
TMA0
Prescaler Division Ratio (Interval Timer)
or Overflow Cycle (Time Base)
Operation
Mode
0
0
0
0
PSS, φ/16384 (Initial value)
1
PSS, φ/8192
Interval
timer mode
0
PSS, φ/4096
1
PSS, φ/1024
0
PSS, φ/512
1
PSS, φ/256
0
PSS, φ/64
1
PSS, φ/16
0
1s
1
0.5 s
0
0.25 s
1
0.03125 s
0
Works to clear the PSW and TCA to H'00
1
1
0
1
1
0
0
1
1
0
1
1
0
1
Note: φ = f osc
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Clock time
base mode
Section 11 Timer A
11.2.2
Timer Counter A (TCA)
Bit :
7
6
5
4
3
2
1
0
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
Initial value :
0
0
0
0
0
0
0
0
R/W :
R
R
R
R
R
R
R
R
The timer counter A (TCA) is an 8-bit up-counter that counts up on inputs from the internal clock.
The inputting clock can be selected by TMA3 to TMA0 bits of the TMA
When the TCA overflows, the TMAOV bit of the TMA is set to 1.
The TCA can be cleared by setting the TMA3 and TMA2 bits of the TMA to 11.
The TCA is always readable. When reset, the TCA will be initialized into H'00.
11.2.3
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
R/W :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP15 bit is set to 1, the Timer A stops its operation at the ending point of the bus
cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode.
When reset, the MSTPCR will be initialized into H'FFFF.
Bit 7⎯Module Stop (MSTP15): This bit works to designate the module stop mode for the Timer
A.
MSTPCRH
Bit 7
MSTP15
Description
0
Cancels the module stop mode of the Timer A
1
Sets the module stop mode of the Timer A
(Initial value)
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Section 11 Timer A
11.3
Operation
Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a 32.768-kHz
crystal oscillator.
11.3.1
Operation as the Interval Timer
When the TMA3 bit of the TMA is cleared to 0, timer A works as an 8-bit interval timer.
After reset, the TCA is cleared to H'00 and as the TMA3 bit is cleared to 0, the Timer A continues
counting up as the interval counter without interrupts right after resetting.
As the operation clock for timer A, selection can be made from eight different types of internal
clocks being output from the PSS by the TMA2 to TMA0 bits of the TMA.
When the clock signal is input after the reading of the TCA reaches H'FF, timer A overflows and
the TMAOV bit of the TMA will be set to 1. An interrupt occurs when the TMAIE bit of the TMA
is 1.
When overflowing occurs, the reading of the TCA returns to H'00 before resuming counting up.
Consequently, it works as the interval timer to produce overflow outputs periodically at every 256
input clocks.
11.3.2
Operation as Clock Timer
When the TMA3 bit of the TMA is set to 1, timer A works as a time base for the clock.
As the overflow cycles for timer A, selection can be made from four different types by counting
the clock being output from the PSW by the TMA1 bit and TMA0 bit of the TMA.
11.3.3
Initializing the Counts
When the TMA3 and TMA2 bits are set to 11, the PSW and TCA will be cleared to H'00 to come
to a stop.
At this state, writing 10 to the TMA3 bit and TMA2 bit makes timer A start counting from H'00 in
the time base mode for clocks.
After clearing the PSW and TCA using the TMA3 and TMA2 bits, writing 00 or 01 to the TMA3
bit and TMA2 bit to make timer A start counting from H'00 in the interval timer mode. However,
the period to the first count is not constant, since the PSS is not cleared.
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Section 12 Timer B
Section 12 Timer B
12.1
Overview
Timer B is an 8-bit up-counter. Timer B is equipped with two different types of functions namely,
the interval function and the auto reloading function.
12.1.1
Features
• Seven different types of internal clocks (φ/16384, φ/4096, φ/1024, φ/512, φ/128, φ/32, and φ/8)
or an of external clock can be selected.
• When the counter overflows, a interrupt request will be issued.
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of timer B.
TMB
Clock sources
φ/4096
TCB
φ/1024
Overflowing
φ/512
φ/128
Re-loading
φ/32
φ/8
TMBI
TLB
Internal data bus
φ/16384
Interrupting
circuit
Legend:
TMB
TCB
TLB
TMBI
: Timer mode register B
: Timer counter B
: Timer re-loading register B
: Event input terminal of the Timer B
Timer B
Interrupt requests
Figure 12.1 Block Diagram of Timer B
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Section 12 Timer B
12.1.3
Pin Configuration
Table 12.1 shows the pin configuration of timer B.
Table 12.1 Pin Configuration
Name
Abbrev.
I/O
Function
Event inputs to timer B
TMBI
Input
Event input pin for inputs to the TCB
12.1.4
Register Configuration
Table 12.2 shows the register configuration of timer B.
The TCB and TLB are being allocated to the same address. Reading or writing determines the
accessing register.
Table 12.2 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Timer mode register B
TMB
R/W
Byte
H'18
H'D110
Timer counter B
TCB
R
Byte
H'00
H'D111
Timer load register B
TLB
W
Byte
H'00
H'D111
Port mode register A
PMRA
R/W
Byte
H'3F
H'FFD9
Note:
*
Lower 16 bits of the address.
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Section 12 Timer B
12.2
Register Descriptions
12.2.1
Timer Mode Register B (TMB)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
TMB17
TMBIF
TMBIE
—
—
TMB12
TMB11
TMB10
0
0
0
1
1
0
0
0
R/W
R/(W)*
R/W
—
—
R/W
R/W
R/W
Note: * Only 0 can be written to clear the flag.
The TMB is an 8-bit read/write register which works to control the interrupts, to select the auto
reloading function and to select the input clock.
When reset, the TMB is initialized to H'18.
Bit 7⎯Selecting the Auto Reloading Function (TMB17): This bit works to select the auto
reloading function of the Timer B.
Bit 7
TMB17
Description
0
Selects the interval function
1
Selects the auto reloading function
(Initial value)
Bit 6⎯Interrupt Requesting Flag for the Timer B (TMBIF): This is an interrupt requesting
flag for the Timer B. It indicates the fact that the TCB is overflowing.
Bit 6
TMBIF
Description
0
[Clearing condition]
(Initial value)
When 0 is written after reading 1
1
[Setting condition]
When the TCB overflows
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Section 12 Timer B
Bit 5⎯Enabling Interrupt of the Timer B (TMBIE): This bit works to permit/prohibit
occurrence of interrupt of timer B when the TCB overflows and when the TMBIF is set to 1.
Bit 5
TMBIE
Description
0
Prohibits interrupt of timer B
1
Permits interrupt of timer B
(Initial value)
Bits 4 and 3⎯Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0⎯Clock Selection (TMB12 to TMB10): These bits work to select the clock to input to
the TCB. Selection of the rising edge or the falling edge is workable with the external event
inputs.
Bit 2
Bit 1
Bit 0
TMB12
TMB11
TMB10
Descriptions
0
0
0
Internal clock: Counts at φ/16384
0
0
1
Internal clock: Counts at φ/4096
0
1
0
Internal clock: Counts at φ/1024
0
1
1
Internal clock: Counts at φ/512
1
0
0
Internal clock: Counts at φ/128
1
0
1
Internal clock: Counts at φ/32
1
1
0
Internal clock: Counts at φ/8
1
1
1
Counts at the rising edge and the falling edge of external
event inputs (TMBI)*
Note:
*
(Initial value)
The edge selection for the external event inputs is made by setting the PMRA6 of the
port mode register A (PMRA). See section 12.2.4, Port Mode Register A (PMRA).
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Section 12 Timer B
12.2.2
Timer Counter B (TCB)
Bit :
7
6
5
4
3
2
1
0
TCB17
TCB16
TCB15
TCB14
TCB13
TCB12
TCB11
TCB10
Initial value :
0
0
0
0
0
0
0
0
R/W :
R
R
R
R
R
R
R
R
The TCB is an 8-bit readable register which works to count up by the internal clock inputs and
external event inputs. The input clock can be selected by the TMB12 to TMB10 of the TMB.
When the TCB overflows (H'FF → H'00 or H'FF → TLB setting), a interrupt request of the Timer
B will be issued.
When reset, the TCB is initialized to H'00.
12.2.3
Timer Load Register B (TLB)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
TLB17
TLB16
TLB15
TLB14
TLB13
TLB12
TLB11
TLB10
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
The TLB is an 8-bit write only register which works to set the reloading value of the TCB.
When the reloading value is set to the TLB, the value will be simultaneously loaded to the TCB
and the TCB starts counting up from the set value. Also, during an auto reloading operation, when
the TCB overflows, the value of the TLB will be loaded to the TCB. Consequently, the
overflowing cycle can be set within the range of 1 to 256 input clocks.
When reset, the TLB is initialized to H'00.
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Section 12 Timer B
12.2.4
Port Mode Register A (PMRA)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
PMRA7
PMRA6
—
—
—
—
—
—
1
1
1
1
—
—
0
0
1
1
R/W
R/W
—
—
—
—
The port mode register A (PMRA) works to changeover the pin functions of the port 6 and to
designate the edge sense of the event inputs of timer B (TMBI).
The PMRA is an 8-bit read/write register. When reset, the PMRA will be initialized to H'3F.
See section 10.7, Port 6 for other information than bit 6.
Bit 6⎯Selecting the Edges of the Event Inputs to the Timer B (PMRA6): This bit works to
select the input edge sense of the TMBI pins.
Bit 6
PMRA6
Description
0
Detects the falling edge of the event inputs to the Timer B
1
Detects the rising edge of the event inputs to the Timer B
Rev.2.00 Jan. 15, 2007 page 254 of 1174
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(Initial value)
Section 12 Timer B
12.2.5
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
R/W :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP14 bit is set to 1, the Timer B stops its operation at the ending point of the bus
cycle to shift to the module stop mode. For more information, see section 4.5, Module stop mode.
When reset, the MSTPCR is initialized to H'FFFF.
Bit 6⎯Module Stop (MSTP14): This bit works to designate the module stop mode for the Timer
B.
MSTPCRH
Bit 6
MSTP14
Description
0
Cancels the module stop mode of the Timer B
1
Sets the module stop mode of the Timer B
(Initial value)
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Section 12 Timer B
12.3
Operation
12.3.1
Operation as the Interval Timer
When the TMB17 bit of the TMB is set to 0, timer B works as an 8-bit interval timer.
When reset, since the TCB is cleared to H'00 and as the TMB17 bit is cleared to 0, timer B
continues counting up as the interval timer without interrupts right after resetting.
As the clock source for timer B, selection can be made from seven different types of internal
clocks being output from the prescaler unit by the TMB12 to TMB10 bits of the TMB or an
external clock through the TMBI input pin can be chosen instead.
When the clock signal is input after the reading of the TCB reaches H'FF, timer B overflows and
the TMBIF bit of the TMB will be set to 1. At this time, when the TMBIE bit of the TMB is 1,
interrupt occurs.
When overflowing occurs, the reading of the TCB returns to H'00 before resuming counting up.
When a value is set to the TLB while the interval timer is in operation, the value which has been
set to the TLB will be loaded to the TCB simultaneously.
12.3.2
Operation as the Auto Reload Timer
When the TMB17 of the TMB is set to 1, the Timer B works as an 8-bit auto reload timer.
When a reload value is set in the TLB, the value is loaded onto the TCB at the same time, and the
TCB starts counting up from the value.
When the clock signal is input after the reading of the TCB reaches H'FF, timer B overflows and
the TLB value is loaded onto the TCB, then the TCB continues counting up from the loaded value.
Accordingly, overflow interval can be set within the range of 1 to 256 clocks depending on the
TLB value.
Clock source and interrupts in the auto reload operation are the same as those in the interval
operation. When the TLB value is re-set while the auto reload timer is in operation, the value
which has been set to the TLB will be loaded onto the TCB simultaneously.
12.3.3
Event Counter
Timer B works as an event counter using the TMBI pin as the event input pin. When the TMB12
to TMB10 are set to 111, the external event will be selected as the clock source and the TCB
counts up at the leading edge or the trailing edge of the TMBI pin inputs.
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Section 13 Timer J
Section 13 Timer J
13.1
Overview
Timer J consists of twin counters. It carries different operation modes such as reloading and event
counting.
13.1.1
Features
Timer J consists of an 8-bit reloading timer and an 8-bit/16-bit selectable reloading timer. It has
various functions as listed below. The two timers can be used separately, or they can be connected
together to operate as a single timer.
• Reloading timers
• Event counters
• Remote-controlled transmissions
• Takeup/Supply reel pulse division
13.1.2
Block Diagram
Figure 13.1 is a block diagram of timer J. Timer J consists of two reload timers namely, TMJ-1
and TMJ-2.
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Clock sources
IRQ1
φ/4
φ/256
φ/512
8/16
Rev.2.00 Jan. 15, 2007 page 258 of 1174
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Reloading
register
TLJ
ST
Synchronization
PS11,10
Figure 13.1 Block Diagram of Timer J
REMOout : TMJ-2 toggle output
(Remote controller
transmission data)
TGL
: TMJ-2 toggle flag
: Timer output/Remote controller output changeover
: Expansion function switching
EXN
: 8-bit/16-bit operation changeover
: Starting the remote controlled operation
T/R
8/16
ST
T/R
TLK : Timer load register K
: TMJ-1 input clock selection
PS22, 21,20 : TMJ-2 input clock selection
PS11,10
TMO
TCK : Timer counter K
TLJ : Timer load register J
: TMJ-1 timer output
Edge
detection
TMO
Toggle
TGL
BUZZ
PS22, 21,20
EXN
REMOout
TCJ : Timer counter J
: Buzzer output
Internal data bus
Reloading register
(Burst/space
width register
TLK
Reloading
TCK Underflow
Down-counter
(8/16-bit)
TMJ-2
BUZZ
Output
Control
Monitor
Output
Control
TMO
Legend:
Note: * At the Low level under the timer mode.
*
Reloading
Under
flow
φ/4096
φ/8192
PB/REC-CTL
DVCTL
TCA7
BUZZ
TCJ
Downcounter (8-bit)
TMJ-1
Toggle
Clock sources
IRQ2
φ/2048
φ/64
φ/128 φ/16384
φ/1024
Interrupt request
by the TMJ2I
Interrupt request
by the TMJ1I
TMJ-2
Interrupting circuit
TMJ-1
Interrupting circuit
Section 13 Timer J
Section 13 Timer J
13.1.3
Pin Configuration
Table 13.1 shows the pin configuration of timer J.
Table 13.1 Pin Configuration
Name
Abbrev.
I/O
Function
Event input pin
IRQ1
Input
Event inputs to the TMJ-1
Event input pin
IRQ2
Input
Event inputs to the TMJ-2
13.1.4
Register Configuration
Table 13.2 shows the register configuration of timer J.
The TCJ and TLJ or the TCK and TLK are being allocated to the same address respectively.
Reading or writing determines the accessing register.
Table 13.2 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
2
Address*
Timer mode register J
TMJ
R/W
Byte
H'00
H'D13A
Byte
H'09
H'D13B
Byte
H'3F
H'D13C
Timer J control register
TMJC
R/W
Timer J status register
TMJS
R/(W)*
Timer counter J
TCJ
R
Byte
H'FF
H'D139
Timer counter K
TCK
R
Byte
H'FF
H'D138
Timer load register J
TLJ
W
Byte
H'FF
H'D139
Timer load register K
TLK
W
Byte
H'FF
H'D138
1
Notes: 1. Only 0 can be written to clear the flag.
2. Lower 16 bits of the address.
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Section 13 Timer J
13.2
Register Descriptions
13.2.1
Timer Mode Register J (TMJ)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
PS11
PS10
ST
8/16
PS21
PS20
TGL
T/R
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
The timer mode register J (TMJ) works to select the inputting clock for the TMJ-1 and TMJ-2 and
to set the operation mode.
The TMJ is an 8-bit register and bit 1 is for read only. All the remaining bits are applicable to
read/write.
When reset, the TMJ is initialized to H'00.
Under all other modes than the remote controlling mode, writing into the TMJ works to initialize
the counters (TCJ and TCK) to H'FF.
Bits 7 and 6⎯Selecting the Inputting Clock to the TMJ-1 (PS11, PS10): These bits work to
select the clock to input to the TMJ-1. When the external clock is selected, the counted edge
(rising or falling) can also be selected.
Bit 7
Bit 6
PS11
PS10
Description
0
0
Counting by the PSS, φ/512
1
Counting by the PSS, φ/256
0
Counting by the PSS, φ/4
1
Counting at the rising edge or the falling edge of the external clock
inputs (IRQ1)*
1
Note:
*
(Initial value)
The edge selection for the external clock inputs is made by setting the IRQ edge select
register (IEGR). See section 6.2.4, IRQ Edge Select Register (IEGR) for more
information.
When using an external clock under the remote controlling mode, set the opposite edge
with the IRQ1 and the IRQ2 when using an external clock under the remote controlling
mode. (When IRQ1 falling, select IRQ2 rising and when IRQ1 rising, select IRQ2 falling)
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Section 13 Timer J
Bit 5⎯Starting the Remote Controlled Operation (ST): This bit works to start the remote
controlled operations.
When this bit is set to 1, clock signal is supplied to the TMJ-1 to start signal transmissions.
When this bit is cleared to 0, clock supply stops to discontinue the operation. The ST bit will be
valid under the remote controlling mode, namely, when bit 0 (T/R bit) is 1 and bit 4 (8/16 bit) is 0.
Under other modes than the remote controlling mode, it will be fixed to 0. When a shift to the low
power consumption mode is made during remote controlled operation, the ST bit will be cleared to
0. When resuming operation after returning to the active mode, write 1.
Bit 5
ST
Description
0
Works to stop clock signal supply to the TMJ-1 under the remote controlling mode
(Initial value)
1
Works to supply clock signal to the TMJ-1 under the remote controlling mode
Bit 4⎯Switching Over Between 8-bit/16-bit Operations (8/16): This bit works to choose if
using timer J as two units of 8-bit timer/counter or if using it as a single unit of 16-bit
timer/counter. Even under 16-bit operations, TMJ1I interrupt requests from the TMJ-1 will be
valid.
Bit 4
8/16
Description
0
Makes the TMJ-1 and TMJ-2 operate separately
1
Makes the TMJ-1 and TMJ-2 operate altogether as 16-bit timer/counter
(Initial value)
Bits 3 and 2⎯Selecting the Inputting Clock for the TMJ-2 (PS21, PS20): These bits, together
with the PS22 bit in the timer J control register (TMJC), work to select the clock for the TMJ-2.
When the external clock is selected, the counted edge (rising or falling) can also be selected. For
details, refer to section 13.2.2, Timer J Control Register (TMJC).
Bit 1⎯TMJ-2 Toggle Flag (TGL): This flag indicates the toggled status of the underflowing
with the TMJ-2. Reading only is workable.
It will be cleared to 0 under the low power consumption mode.
Bit 1
TGL
Description
0
The toggle output of the TMJ-2 is 0
1
The toggle output of the TMJ-2 is 1
(Initial value)
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Section 13 Timer J
Bit 0⎯Switching Over Between Timer Output/Remote Controlling Output (T/R): This bit
works to select if using the timer outputs from the TMJ-1 as the output signal through the TMO
pin or if using the toggle outputs (remote controlled transmission data) from the TMJ-2 as the
output signal through the TMO pin.
Bit 0
T/R
Description
0
Timer outputs from the TMJ-1
1
Toggle outputs from the TMJ-2 (remote controlled transmission data)
(Initial value)
Selecting the Operation Mode
The operating mode of timer J is determined by bit 3 (EXN) of the timer J control register (TMJC)
and bits 4 (8/16) and 0 (T/R) of the timer mode register J (TMJ).
TMJC
TMJ
Bit 3
Bit 4
Bit 0
EXN
8/16
T/R
Description
0
0
0
8-bit timer + 16-bit timer
1
1
Remote-controlling mode (TMJ-2 works as a 16-bit timer)
1
*
24-bit timer
0
0
Two 8-bit timers
1
Remote-controlling mode (TMJ-2 works as an 8-bit timer)
*
16-bit timer
1
(Initial value)
Legend: * Don’t care
Writing to the TMJ in timer mode initializes the counters (TCJ and TCK) (H'FF). Consequently,
write to the reloading registers (TLJ an TLK) after finishing settings with the TMJ.
Under the remote controlling mode, although the TLJ and the TLK will not be initialized even
when writing is made into the TMJ, follow the sequence listed below when starting a remote
controlling operation:
1. Make setting to the remote controlling mode with the TMJ.
2. Write the data into the TLJ and TLK.
3. Start the remote controlled operation by use of the TMJ. (ST bit = 1).
Even under 16-bit operations, TMJ1I interrupt requests from the TMJ-1 will be valid.
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Section 13 Timer J
13.2.2
Timer J Control Register (TMJC)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
BUZZ1
BUZZ0
MON1
MON0
EXN
TMJ2IE
TMJ1IE
PS22
0
0
0
0
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The timer J control register (TMJC) works to select the buzzer output frequency and to control
permission/prohibition of interrupts.
The TMJC is an 8-bit read/write register.
When reset, the TMJC is initialized to H'09.
Bits 7 and 6⎯Selecting the Buzzer Output (BUZZ1, BUZZ0): These bits work to select if
using the buzzer outputs as the output signal through the BUZZ pin or if using the monitor signals
as the output signal through the BUZZ pin.
When setting is made to the monitor signals, choose the monitor signal using the MON1 bit and
MON0 bit.
Bit 7
Bit 6
BUZZ1
BUZZ0
Description
0
0
φ/4096
1
φ/8192
0
Works to output monitor signals
1
Works to output BUZZ signals from timer J
1
Frequency when
φ = 10 MHz
(Initial value)
2.44 kHz
1.22 kHz
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Section 13 Timer J
Bits 5 and 4⎯Selecting the Monitor Signals (MON1, MON0): These bits work to select the
type of signals being output through the BUZZ pin for monitoring purpose. These settings are
valid only when the BUZZ1 and BUZZ0 bits are being set to 10.
When PB-CTL or REC-CTL is chosen, signal duties will be output as they are.
In case of DVCTL signals, signals from the CTL dividing circuit will be toggled before being
output. Signal waveforms divided by the CTL dividing circuit into n-divisions will further be
divided into halves. (Namely, 2n divisions, 50% duty waveform).
In case of TCA7, Bit 7 of the counter of the Timer A will be output. (50% duty)
When prescaler W is being used with the Timer A, 1 Hz outputs are available.
Bit 5
Bit 4
MON1
MON0
Description
0
0
PB or REC-CTL
1
DVCTL
*
Outputs TCA7
1
(Initial value)
Legend: * Don’t care
Bit 3⎯Expansion Function Control Bit (EXN): This bit enables or disables the expansion
function of TMJ-2. When the expansion function is enabled, TMJ-2 works as a 16-bit counter, and
further input clock sources and types can be selected.
Bit 3
EXN
Description
0
Enables the TMJ-2 expansion function
1
Disables the TMJ-2 expansion function
(Initial value
Bit 2⎯Enabling Interrupt of the TMJ2I (TMJ2IE): This bit works to permit/prohibit
occurrence of TMJ2I interrupt of the TMJS in 1-set of the TMJ2I.
Bit 2
TMJ2IE
Description
0
Prohibits occurrence of TMJ2I interrupt
1
Permits occurrence of TMJ2I interrupt
Rev.2.00 Jan. 15, 2007 page 264 of 1174
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(Initial value)
Section 13 Timer J
Bit 1⎯Enabling Interrupt of the TMJ1I (TMJ1IE): This bit works to permit/prohibit
occurrence of TMJ1I interrupt of the TMJS in 1-set of the TMJ1I.
Bit 1
TMJ1IE
Description
0
Prohibits occurrence of TMJ1I interrupt
1
Permits occurrence of TMJ1I interrupt
(Initial value)
Bit 0⎯TMJ-2 Input Clock Selection (PS22): This bit, together with the PS21 and PS20 bits of
the timer mode register J (TMJ), selects the TMJ-2 input clock source.
TMJC
Bit 3
Bit 0
TMJ
Bit 3
Bit 2
EXN
PS22
PS21
PS20
Description
0
1
0
0
PSS; count at φ/128
1
PSS; count at φ/64
0
Count at TMJ-1 underflow
1
External clock (IRQ2); count at rising or falling edge*
1
1
1
0
*
*
Reserved
1
0
0
PSS; count at φ/16384
1
PSS; count at φ/2048
0
Count at TMJ-1 underflow
1
External clock (IRQ2); count at rising or falling edge*
0
PSS; count at φ/1024
1
PSS; count at φ/1024
0
Count at TMJ-1 underflow
1
1
External clock (IRQ2); count at rising or falling edge*
1
0
0
1
(Initial value)
1
Legend: * Don’t care
Note: 1. The external clock edge can be selected by the IRQ edge select register (IEGR). For
details, refer to section 6.2.4, IRQ Edge Select Registers (IEGR).
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Section 13 Timer J
13.2.3
Timer J Status Register (TMJS)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
TMJ2I
TMJ1I
—
—
—
—
—
—
0
0
1
1
1
1
1
1
R/(W)*
R/(W)*
—
—
—
—
—
—
Note: * Only 0 can be written to clear the flag.
The timer J status register (TMJS) works to indicate issuance of the interrupt request of timer J.
The TMJS is an 8-bit read/write register. When reset, the TMJS is initialized to H'3F.
Bit 7⎯TMJ2I Interrupt Requesting Flag (TMJ2I): This is the TMJ2I interrupt requesting flag.
This flag is set out when the TMJ-2 underflows.
Bit 7
TMJ2I
Description
0
[Clearing condition]
(Initial value)
When 0 is written after reading 1
1
[Setting condition]
When the TMJ-2 underflows
Bit 6⎯TMJ1I Interrupt Requesting Flag (TMJ1I): This is the TMJ1I interrupt requesting flag.
This flag is set out when the TMJ-1 underflows.
TMJ1I interrupt requests will also be made under a 16-bit operation.
Bit 6
TMJ1I
Description
0
[Clearing condition]
When 0 is written after reading 1
1
[Setting condition]
When the TMJ-1 underflows
Bits 5 to 0⎯Reserved: These bits cannot be modified and are always read as 1.
Rev.2.00 Jan. 15, 2007 page 266 of 1174
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(Initial value)
Section 13 Timer J
13.2.4
Timer Counter J (TCJ)
7
6
5
4
3
2
1
0
TDR17
TDR16
TDR15
TDR14
TDR13
TDR12
TDR11
TDR10
Initial value :
1
1
1
1
1
1
1
1
R/W :
R
R
R
R
R
R
R
R
Bit :
The timer counter J (TCJ) is an 8-bit readable down-counter which works to count down by the
internal clock inputs or external clock inputs. The inputting clock can be selected by the PS11 and
PS10 bits of the TMJ. TCJ values can be readout always. Nonetheless, when the EXN bit in TMJC
and the 8/16 bit in TMJ are both set to 1, (means when setting is made to 16-bit operation),
reading is possible under the word command only.
At this time, the TCK of the TMJ-2 can be read by the upper 8 bits and the TCJ can be read by the
lower 8 bits. When the EXN bit in TMJC is 0, TCJ can be read only in byte units.
When the TCJ underflows (H'00 → Reloading value), regardless of the operation mode setting of
the 8/16 bit, the TMJ1I bit of the TMJS will be set to 1 bit. The TCJ and TLJ are being allocated
to the same address.
When reset, the TCJ is initialized to H'FF.
13.2.5
Timer Counter K (TCK)
7
6
5
4
3
2
1
0
TDR27
TDR26
TDR25
TDR24
TDR23
TDR22
TDR21
TDR20
Initial value :
1
1
1
1
1
1
1
1
R/W :
R
R
R
R
R
R
R
R
Bit :
The timer counter K (TCK) is an 8-bit or a 16-bit readable down-counter which works to count
down by the internal clock inputs or external clock inputs. The inputting clock can be selected by
the EXN and PS22 bits of the TMJC, and the PS21 and PS20 bits of the TMJ. TCK values can be
readout always. Nonetheless, when the EXN bit in TMJC and the 8/16 bit in TMJ are both set to 1,
(means when setting is made to 16-bit operation), reading is possible under the word command
only.
At this time, the TCK can be read by the upper 8 bits and the TCJ of the TMJ-1 can be read by the
lower 8 bits. When the EXN bit in TMJC is 0, TCK works as a 16-bit counter and can be read only
in word units.
When the TCK underflows (H'00 → Reloading value), the TMJ2I bit of the TMJS will be set to 1.
The TCK and TLK are being allocated to the same address.
When reset, the TCK is initialized to H'FF.
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Section 13 Timer J
13.2.6
Timer Load Register J (TLJ)
7
6
5
4
3
2
1
0
TLR17
TLR16
TLR15
TLR14
TLR13
TLR12
TLR11
TLR10
Initial value :
1
1
1
1
1
1
1
1
R/W :
W
W
W
W
W
W
W
W
Bit :
The timer load register J (TLJ) is an 8-bit write only register which works to set the reloading
value of the TCJ.
When the reloading value is set to the TLJ, the value will be simultaneously loaded to the TCJ and
the TCJ starts counting down from the set value. Also, during an auto reloading operation, when
the TCJ underflows, the value of the TLJ will be loaded to the TCJ. Consequently, the
underflowing cycle can be set within the range of 1 to 256 input clocks. Nonetheless, when the
EXN bit in TMJC and the 8/16 bit in TMJ are both set to 1, (means when setting is made to 16-bit
operation), writing is possible under the word command only.
At this time, the upper 8 bits can be written into the TLK of the TMJ-2 and the lower 8 bits can be
written into the TLJ. When the EXN bit in TMJC is 0, TLJ can be written to only in byte units; an
8-bit reload value is written to TLJ.
The TLJ and TCJ are being allocated to the same address.
When reset, the TLJ is initialized to H'FF.
13.2.7
Timer Load Register K (TLK)
Bit :
7
6
5
4
3
2
1
0
TLR27
TLR26
TLR25
TLR24
TLR23
TLR22
TLR21
TLR20
Initial value :
1
1
1
1
1
1
1
1
R/W :
W
W
W
W
W
W
W
W
The timer load register K (TLK) is an 8-bit or a 16-bit write only register which works to set the
reloading value of the TCK.
When the reloading value is set to the TLK, the value will be simultaneously loaded to the TCK
and the TCK starts counting down from the set value. Also, during an auto reloading operation,
when the TCK underflows, the value of the TLK will be loaded to the TCK. Consequently, the
underflowing cycle can be set within the range of 1 to 256 input clocks. Nonetheless, when the
EXN bit in TMJC and the 8/16 bit in TMJ are both set to 1, (means when setting is made to 16-bit
operation), writing is possible under the word command only. At this time, the upper 8 bits can be
written into the TLK and the lower 8 bits can be written into the TLJ of the TMJ-1. When the
EXN bit in TMJC is 0, TLK can be written to only in word units; a 16-bit reload value is written
to TLK. The TLK and TCK are being allocated to the same address.
When reset, the TLK is initialized to H'FF.
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Section 13 Timer J
13.2.8
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP13 bit is set to 1, timer J stops its operation at the ending point of the bus cycle to
shift to the module stop mode. For more information, see section 4.5, Module Stop Mode.
When reset, the MSTPCR is initialized to H'FFFF.
Bit 5⎯Module Stop (MSTP13): This bit works to designate the module stop mode for the Timer
J.
MSTPCRH
Bit 5
MSTP13
Description
0
Cancels the module stop mode of timer J
1
Sets the module stop mode of timer J
(Initial value)
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Section 13 Timer J
13.3
Operation
13.3.1
8-bit Reload Timer (TMJ-1)
The TMJ-1 is an 8-bit reload timer. As the clock source, dividing clock or edge signals through the
IRQ1 pin are being used. By selecting the edge signals through the IRQ1 pin, it can also be used
as an event counter. While it is working as an event counter, its reloading function is workable
simultaneously. When data are written into the reloading register, these data will be written into
the counters (event counter, timer counter) simultaneously. Also, when the event counter
underflows, the event counter value is reset to the reload register value, and a TMJ1I interrupt
request occurs. Every time the counter underflows, the output level toggles. This output can be
used as a buzzer or the carrier frequency at remote-controlled transmission by selecting an
appropriate divided clock.
The TMJ-1 and TMJ-2, in combination, can be used as a 16-bit or a 24-bit reload timer.
Nonetheless, when they are being used, in combination, as a 16-bit timer, word command only is
valid and the TCK works as the down counter for the upper 8 bits and the TCJ works as the down
counter for the lower 8 bits, means a reloading register of total 16 bits.
When data are written into a 16-bit reloading register, the same data will be written into the 16-bit
down counter.
Also, when the 16-bit down counter underflow signals, the data of the 16-bit reloading register
will be reloaded into the down counter. When the EXN bit of TMJC is set to 0, the expansion
function of TMJ-2 is enabled, that is, TMJ-2 works as a 16-bit reloading timer, and it can be
connected to TMJ-1 to be a 24-bit reloading timer. In this case, TCK works as the upper 16-bit
part and TCJ works as the lower 8-bit part of a 24-bit down counter, and TLK works as the upper
16-bit part and TLJ works as the lower 8-bit part of a 24-bit reloading register.
Even when they are making a 16-bit or a 24-bit operation, the TMJ1I interrupt requests of the
TMJ-1 and BUZZER outputs are effective. In case these functions are not necessary, make them
invalid by programming.
The TMJ-1 and TMJ-2, in combination, can be used for remote controlled data transmission.
Regarding the remote controlled data transmission, see section 13.3.3, Remote Controlled Data
Transmission.
13.3.2
8-bit Reload Timer (TMJ-2)
The TMJ-2 is an 8-bit or a 16-bit down-counting reload timer. As the clock source, dividing clock,
edge signals through the IRQ2 pin or the underflow signals from the TMJ-1 are being used. By
selecting the edge signals through the IRQ2 pin, it can also be used as an event counter. While it is
working as an event counter, its reloading function is workable simultaneously.
When data are written into the reloading register, these data will be written into the counter
simultaneously. Also, when the counter underflows, reloading will be made to the data counter of
Rev.2.00 Jan. 15, 2007 page 270 of 1174
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Section 13 Timer J
the reloading register.
When the counter underflows, TMJ2I interrupt requests will be issued.
The TMJ-2 and TMJ-1, in combination, can be used as a 16-bit or a 24-bit reload timer. For more
information on the 16-bit or 24-bit reload timer, see section 13.3.1, 8-bit Reload Timer (TMJ-1).
The TMJ-2 and TMJ-1, in combination, can be operated by remote controlled data transmission.
Regarding the remote controlled data transmission, see section 13.3.3, Remote Controlled Data
Transmission.
13.3.3
Remote Controlled Data Transmission
The Timer J is capable of making remote controlled data transmission. The carrier frequencies for
the remote controlled data transmission can be generated by the TMJ-1 and the burst width
duration and the space width duration can be setup by the TMJ-2.
The data having been written into the reloading register TMJ-1 and into the burst/space duration
register (TLK) of the TMJ-2 will be loaded to the counter at the same time as the remote
controlled data transmission starts. (Remote controlled data transmission starting bit (ST) ← 1)
While remote controlled data transmission is being made, the contents of the burst/space duration
register will be loaded to the counter only while reloading is being made by underflow signals.
Even when a writing is made to the burst/space duration register while remote controlled data
transmission is being made, reloading operation will not be made until an underflow signal is
issued. The TMJ-2 issues TMJ2I interrupt requests by the underflow signals. The TMJ-1 performs
normal reloading operation (including the TMJ1I interrupt requests).
Figure 13.2 shows the output waveform for the remote controlled data transmission function.
When a shift to the low power consumption mode is effected while remote controlled data
transmission is being made, the ST bit will be cleared to 0. When resuming the remote controlled
data transmission after returning to the active mode, write 1.
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Section 13 Timer J
TMJ-1 can generate
the carrier frequencies
Remote controlled data
transmission outputs
Burst width
Space width
TMJ-2 toggle output
=1
Setting the remote
controlled mode
Setting the burst width
Setting the
space width
ST bit ← 1
Underflow
Burst width
TMJ-2 toggle output
=0
TMJ-2 toggle
output = 1
Setting the
burst width
Setting the
space width
Underflow
Figure 13.2 Remote Controlled Data Transmission Output Waveform
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REJ09B0329-0200
Underflow
Remote controlled data
transmission output
TMO
REMOout
UDF
TMJ-2
TMO
(BUZZ)
UDF
TMJ-1
Section 13 Timer J
Figure 13.3 Timer Output Timing
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Section 13 Timer J
When the Timer J is set to the remote controlled operation mode, since the start bit (ST) is being
set or cleared in synchronization with the inputting clock to the TMJ-2, a delay upto a cycle of the
inputting clock at the maximum occurs, namely, after the ST bit has been set to 1 until the remote
controlled data transmission starts. Consequently, when the TLK is updated during the period after
setting the ST bit to 1 until the next cycle of the inputting clock comes, the initial burst width will
be changed as shown in figure 13.4.
Therefore, when making remote controlled data transmission, determine 1/0 of the TGL bit at the
time of the first burst width control operation without fail. (Or, set the space width to the TLK
after waiting for a cycle of the inputting clock.)
After that, operations can be continued by interrupts.
Similarly, pay attention to the control works when ending remote controlled data transmission.
Example:
1) Set the burst width with the TLK.
2) ST bit ← 1.
3) Execute the procedure 4) if the TGL flag = 1.
4) Set the space width with the TLK under the status where the TGL flag = 1.
5) Make TMJ-2 interrupt.
6) Set the burst width with the TLK.
:
n) After making TMJ-2 interrupt, make setting of the ST ← 0 under the status where the TGL
flag = 0.
Inputting clock
to the TMJ-2
Interrupt
Interrupt
TGL flag
ST ← 1
TLK setting
(Burst width)
(B)
Burst width
according to (B)
Remote controlled data
transmission starts here.
Delay
Space width
according to (S)
ST ← 0
Delay
The period during which the
space width settig can be
made. (S)
If an updating is made with the
TLK during this period, the burst
width will be changed.
Stopping the remote controlled
data transmission
Figure 13.4 Controls of the Remote Controlled Data Transmission
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Section 13 Timer J
13.3.4
TMJ-2 Expansion Function
The TMJ-2 expansion function is enabled by setting the EXN bit in the timer J control register
(TMJC) to 0. This function makes TMJ-2, which usually works as an 8-bit counter, work as a 16bit counter. When this function is selected, timer counter K (TCK) and timer load register K
(TLK) must be accessed as follows:
TCK Read: To read TCK, use the word-length MOV instruction. In this case, the upper 8 bits of
TCK are read out to the lower byte of the on-chip data bus, and the lower 8 bits are read out to the
upper byte of the on-chip data bus. That is, when MOV.W @TCK, Rn is executed, the lower 8
bits of TCK are stored in RnH and the upper 8 bits are stored in RnL.
TLK Write: To write to TLK, use the word-length MOV instruction. In this case, the upper 8 bits
are written to the lower byte of TLK, and the lower 8 bits are written to the upper byte of TLK.
That is, when MOV.W Rn, @TLK is executed, the RnH data is written to the lower byte of TLK,
and the RnL data is written to the upper byte of TLK.
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Section 13 Timer J
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Section 14 Timer L
Section 14 Timer L
14.1
Overview
Timer L is an 8-bit up/down counter using the control pulses or the CFG division signals as the
clock source.
14.1.1
Features
Features of timer L are as follows:
• Two types of internal clocks (φ/128 and φ/64), DVCFG2 (CFG division signal 2), PB and
REC-CTL (control pulses) are available for your selection.
⎯ When the PB-CTL is not available, such as when reproducing un-recorded tapes, tape
count can be made by the DVCFG2.
⎯ Selection of the rising edge or the falling edge is workable with the CTL pulse counting.
• Interrupts occur when the counter overflows or underflows and at occurrences of compare
match clear.
• Capable to switch over between the up-counting and down-counting functions with the
counter.
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Section 14 Timer L
14.1.2
Block Diagram
Figure 14.1 shows a block diagram of timer L.
LMR
Internal clock
φ/128
φ/64
Read
LTC
PB and
REC-CTL
OVF/UDF
Internal data bus
DVCFG2
Reloading
Match clear
Comparator
Interrupting
circuit
RCR
Write
Legend:
DVCFG2 : Division signal 2 of the CFG
PB and REC-CTL : Control pluses necessary when making
reproduction and storage
LMR : Timer L mode register
LTC : Linear time counter
RCR : Reload/compare match register
OVF : Overflow
UDF : Underflow
Figure 14.1 Block Diagram of Timer L
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Interrupt request
Section 14 Timer L
14.1.3
Register Configuration
Table 14.1 shows the register configuration of timer L. The linear time counter (LTC) and the
reload compare patch register (RCR) are being allocated to the same address.
Reading or writing determines the accessing register.
Table 14.1 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Timer L mode register
LMR
R/W
Byte
H'30
H'D112
Linear time counter
LTC
R
Byte
H'00
H'D113
Reload/compare match
register
RCR
W
Byte
H'00
H'D113
Note:
*
Lower 16 bits of the address.
Rev.2.00 Jan. 15, 2007 page 279 of 1174
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Section 14 Timer L
14.2
Register Descriptions
14.2.1
Timer L Mode Register (LMR)
Bit :
Initial value :
7
6
5
4
3
2
1
0
LMIF
LMIE
—
—
LMR3
LMR2
LMR1
LMR0
0
0
1
1
0
0
0
0
R/W
—
—
R/W
R/W
R/W
R/W
R/W : R /(W)*
Note: * Only 0 can be written to clear the flag.
The timer L mode register A (LMR) is an 8-bit read/write register which works to control the
interrupts, to select between up-counting and down-counting and to select the clock source. When
reset, the LMR is initialized to H'30.
Bit 7⎯Timer L Interrupt Requesting Flag (LMIF): This is the Timer L interrupt requesting
flag. It indicates occurrence of overflow or underflow of the LTC or occurrence of compare match
clear.
Bit 7
LMIF
Description
0
[Clearing condition]
(Initial value)
When 0 is written after reading 1
1
[Setting condition]
When the LTC overflows, underflows or when compare match clear has occurred
Bit 6⎯Enabling Interrupt of the Timer L (LMIE): When the LTC overflows, underflows or
when compare match clear has occurred, then LMIF is set to 1, this bit works to permit/prohibit
the occurrence of an interrupt of timer L.
Bit 6
LMIE
Description
0
Prohibits occurrence of interrupt of Timer L
1
Permits occurrence of interrupt of Timer L
(Initial value)
Bits 5 and 4⎯Reserved: These bits cannot be modified and are always read as 1.
Bit 3⎯Up-Count/Down-Count Control (LMR3): This bit is for selection if timer L is to be
controlled to the up-counting function or down-counting function.
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Section 14 Timer L
1. When Controlled to the Up-Counting Function
⎯ When any other values than H'00 are input to the RCR, the LTC will be cleared to H'00
before starting counting up. When the LTC value and the RCR value match, the LTC will
be cleared to H'00. Also, interrupt requests will be issued by the match signal. (Compare
match clear function)
⎯ When H'00 is set to the RCR, the counter makes 8-bit interval timer operation to issue a
interrupt request when overflowing occurs. (Interval timer function)
2. When Controlled to the Down-Counting Function
⎯ When a value is set to the RCR, the set value is reloaded to the LTC and counting down
starts from that value. When the LTC underflows, the value of the RCR will be reloaded to
the LTC. Also, when the LTC underflows, a interrupt request will be issued. (Auto reload
timer function)
Bit 3
LMR3
Description
0
Controlling to the up-counting function
1
Controlling to the down-counting function
(Initial value)
Bits 2 to 0⎯Clock Selection (LMR2 to LMR0): The bits LMR2 to LMR0 work to select the
clock to input to timer L. Selection of the leading edge or the trailing edge is workable for
counting by the PB and the REC-CTL.
Bit 2
Bit 1
Bit 0
LMR2
LMR1
LMR0
Description
0
0
0
Counts at the rising edge of the PB and REC-CTL
(Initial value)
1
Counts at the falling edge of the PB and REC-CTL
1
*
Counts the DVCFG2
0
*
Counts at φ/128 of the internal clock
1
*
Counts at φ/64 of the internal clock
1
Legend: * Don't care.
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Section 14 Timer L
14.2.2
Linear Time Counter (LTC)
Bit :
7
6
5
4
3
2
1
0
LTC7
LTC6
LTC5
LTC4
LTC3
LTC2
LTC1
LTC0
Initial value :
0
0
0
0
0
0
0
0
R/W :
R
R
R
R
R
R
R
R
The linear time counter (LTC) is a readable 8-bit up/down-counter. The inputting clock can be
selected by the LMR2 to LMR0 bits of the LMR.
When reset, the LTC is initialized to H'00.
14.2.3
Reload/Compare Match Register (RCR)
Bit :
7
6
5
4
3
2
1
0
RCR7
RCR6
RCR5
RCR4
RCR3
RCR2
RCR1
RCR0
Initial value :
0
0
0
0
0
0
0
0
R/W :
W
W
W
W
W
W
W
W
The reload/compare match register (RCR) is an 8-bit write only register.
When timer L is being controlled to the up-counting function, when a compare match value is set
to the RCR, the LTC will be cleared at the same time and the LTC will then start counting up from
the initial value (H'00).
While, when the Timer L is being controlled to the down-counting function, when a reloading
value is set to the RCR, the same value will be loaded to the LTC at the same time and the LTC
will then start counting up from said value. Also, when the LTC underflows, the value of the RCR
will be reloaded to the LTC.
When reset, the RCR is initialized to H'00.
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Section 14 Timer L
14.2.4
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP12 bit is set to 1, timer L stops its operation at the ending point of the bus cycle to
shift to the module stop mode. For more information, see section 4.5, Module Stop Mode.
When reset, the MSTPCR is initialized to H'FFFF.
Bit 4⎯Module Stop (MSTP12): This bit works to designate the module stop mode for timer L.
MSTPCRH
Bit 4
MSTP12
Description
0
Cancels the module stop mode of timer L
1
Sets the module stop mode of timer L
(Initial value)
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Section 14 Timer L
14.3
Operation
Timer L is an 8-bit up/down counter.
The inputting clock for Timer L can be selected by the LMR2 to LMR0 bits of the LMR from the
choices of the internal clock (φ/128 and φ/64), DVCDG2, PB and REC-CTL.
Timer L is provided with three different types of operation modes, namely, the compare match
clear mode when controlled to the up-counting function, the auto reloading mode when controlled
to the down-counting function and the interval timer mode.
Respective operation modes and operation methods will be explained below.
14.3.1
Compare Match Clear Operation
When the LMR3 bit of the LMR is cleared to 0, timer L will be controlled to the up-counting
function.
When any other values than H'00 are written into the RCR, the LTC will be cleared to H'00
simultaneously before starting counting up.
Figure 14.2 shows RCR writing and LTC clearing timing. When the LTC value and the RCR
value match (compare match), the LTC readings will be cleared to H'00 to resume counting from
H'00.
Figure 14.3 indicated on the next page shows the compare match clear timing.
1 state
φ
Write signal
N
RCR
H' 00
LTC
Figure 14.2 RCR Writing and LTC Clearing Timing Chart
Rev.2.00 Jan. 15, 2007 page 284 of 1174
REJ09B0329-0200
Section 14 Timer L
φ
PB-CTL
Count-up
signal
Compare match
clear signal
RCR
LTC
N
N-1
N
H' 00
Interrupt
request
Figure 14.3 Compare Match Clearing Timing Chart
(In case the rising edge of the PB-CTL is selected)
14.3.2
Auto-Reload Operation
When 1 is written in bit LMR3 of LMR, LTC enters down-counting control mode.
When a reload value is written in RCR, LTC is reloaded with the same value and starts counting
down from that value. Figure 14.4 shows the timing of the writing and reloading of RCR.
At underflow, LTC is reloaded with the RCR value. Figure 14.5 shows the reload timing.
1 state
φ
Write
signal
RCR
N
LTC
N
Figure 14.4 Timing of Writing and Reloading of RCR
Rev.2.00 Jan. 15, 2007 page 285 of 1174
REJ09B0329-0200
Section 14 Timer L
φ
PB-CTL
Count-down
signal
Reload
underflow
RCR
N
LTC
H'01
H'00
N
Interrupt
request
Figure 14.5 Reload Timing (Rising Edge of PB-CTL Selected)
14.3.3
Interval Timer Operation
When bit LMR3 is cleared to 0 in LMR, the timer L enters up-counting control mode.
If H'00 is written in RCR, compare-match operations are not carried out. The counter functions as
an interval timer (up-counter).
14.3.4
Interrupt Request
The timer L generates an interrupt request when any of the following occurs:
• Compare-match clear under up-counting control
• Underflow under down-counting control
• Overflow or underflow when the reload/compare-match register (RCR) value is H'00
Rev.2.00 Jan. 15, 2007 page 286 of 1174
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Section 14 Timer L
14.4
Typical Usage
Figure 14.6 shows a typical usage of the timer L.
H'FF
Value written
in RCR
H'00
*
*
LTC = RCR
Underflow
Compare match clear
(reload)
Value other than H'00
written in RCR under
Down-counting control
up-counting control
(1 written in bit LMR3)
(Record, playback,
fast-forward, etc.)
*
Underflow
(reload)
(Rewind, reverse, etc.)
Note: * A downward-pointing arrow indicates an interrupt request.
Figure 14.6 Typical Usage of Linear Time Counter
14.5
Reload Timer Interrupt Request Signal
The timer counters with reload registers generate an underflow or overflow in the last cycle before
being decremented or incremented. The underflow or overflow generates a reload signal and an
interrupt request signal.
If the value in the reload register is rewritten at the same time as the underflow or overflow (at the
reload timing), an interrupt request is generated and the counter is reloaded at the same time.
When rewriting the reload value in order to avoid an interrupt, leave an ample timing margin
around the write to the reload register.
Rev.2.00 Jan. 15, 2007 page 287 of 1174
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Section 14 Timer L
Figure 14.7 shows a sample timing diagram of contention between an underflow and the rewriting
of the reload register.
1 Bus
cycle
φ
Write
Reload
register
Counter
H'zz
H'01
H'nn
H'00
H'nn
H'nn-1
Reload: disabled by write
UDF
IRR
Legend:
Write: Reload register rewrite signal
Reload: Reload signal
Counter underflow
UDF:
Interrupt request signal
IRR:
Figure 14.7 Contention between Reload Timer Underflow and
Rewriting of Reload Register
Rev.2.00 Jan. 15, 2007 page 288 of 1174
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Section 15 Timer R
Section 15 Timer R
15.1
Overview
Timer R consists of triple 8-bit down-counters. It carries VCR mode identification function and
slow tracking function in addition to the reloading function and event counter function.
15.1.1
Features
The Timer R consists of triple 8-bit reloading timers. By combining the functions of three units of
reloading timers/counters and by combining three units of timers, it can be used for the following
applications:
• Applications making use of the functions of three units of reloading timers.
• For identification of the VCR mode.
• For reel controls.
• For acceleration and braking of the capstan motor when being applied to intermittent
movements.
• Slow tracking mono-multi applications.
15.1.2
Block Diagram
Timer R consists of three units of reload timer counters, namely, two units of reload timer
counters equipped with capturing function (TMRU-1 and TMRU-2) and a unit of reload timer
counter (TMRU-3).
Figure 15.1 is a block diagram of timer R.
Rev.2.00 Jan. 15, 2007 page 289 of 1174
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Rev.2.00 Jan. 15, 2007 page 290 of 1174
REJ09B0329-0200
Figure 15.1 Block Diagram of Timer R
Clock
selection
(2 bits)
PS31,30
Reloading register
(8 bits)
TMRL3
TMRU-3
Down-counter
(8 bits)
Capture register
(8 bits)
*1
Underflow
Under
flow
Reloading register
(8 bits)
Down-counter
(8 bits)
TMRU-1
*2
TMRCP1
RLD/
CAP
TMRL1
S
R Q
TMRL2
Under
flow
CLR2
R
AC/BR
Res
SLW
CAPF
CP/
SLM
Res
braking
Acceleration
Acceleration/
braking
Q
S
CFG mask F/F
Resetting
Available/
Not
available
Capture register
(8 bits)
TMRCP2
Down-counter
(8 bits)
TMRU-2
Reloading register
(8 bits)
PS21,20
Clock
selection
(2 bits)
Internal bus
LAT
Latch
clock
selection
Clock source
φ /64
φ /128
φ /256
Reloading
Available/
not
available
RLD
Internal bus
RLCK
Reloading
clock
selection
Interrupting circuit
TMRI3
Interrupt
request
TMRI1
Interrupt
request
TMRI2
Interrupt request
Notes: 1. When the DVCTL is being used as the clock source, reloading will be made when the counter underflows and when
the dividing clock is being used as the clock source, reloading will be made by the DVCTL.
2. When the LAT bit = 0, the capture signal against the TMRU-1 will not be output.
DVCTL
Clock sources
φ /1024
φ /2048
φ /4096
External signals
IRQ3
CFG↑
Clock sources
φ /4
φ /256
φ /512
CPS
PS11,10
Clock
selection
(2 bits)
Section 15 Timer R
Section 15 Timer R
15.1.3
Pin Configuration
Table 15.1 shows the pin configuration of timer R.
Table 15.1 Pin Configuration
Name
Abbrev.
I/O
Function
Input capture inputting pin
IRQ3
Input
Input capture inputting for the Timer R
15.1.4
Register Configuration
Table 15.2 shows the register configuration of timer R.
Table 15.2 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address
Timer R mode register 1
TMRM1
R/W
Byte
H'00
H'D118
Timer R mode register 2
TMRM2
R/W
Byte
H'00
H'D119
Timer R control/status
register
TMRCS
R/W
Byte
H'03
H'D11F
Timer R capture register 1
TMRCP1
R
Byte
H'FF
H'D11A
Timer R capture register 2
TMRCP2
R
Byte
H'FF
H'D11B
Timer R load register 1
TMRL1
W
Byte
H'FF
H'D11C
Timer R load register 2
TMRL2
W
Byte
H'FF
H'D11D
Timer R load register 3
TMRL3
W
Byte
H'FF
H'D11E
Note: Memories of respective registers will be preserved even under the low power consumption
mode. Nonetheless, the CAPF flag and SLW flag of the TMRM2 will be cleared to 0.
Rev.2.00 Jan. 15, 2007 page 291 of 1174
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Section 15 Timer R
15.2
Register Descriptions
15.2.1
Timer R Mode Register 1 (TMRM1)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
CLR2
AC/BR
RLD
RLCK
PS21
PS20
RLD/CAP
CPS
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The timer R mode register 1 (TMRM1) works to control the acceleration and braking processes
and to select the inputting clock for the TMRU-2. This is an 8-bit read/write register.
When reset, the TMRM1 is initialized to H'00.
Bit 7⎯Selecting Clearing/Not Clearing of TMRU-2 (CLR2): This bit is used for selecting if
the TMRU-2 counter reading is to be cleared or not as it is captured.
Bit 7
CLR2
Description
0
TMRU-2 counter reading is not to be cleared as soon as it is captured. (Initial value)
1
TMRU-2 counter reading is to be cleared as soon as it is captured
Bit 6⎯Acceleration/Braking Processing (AC/BR): This bit works to control occurrences of
interrupt requests to detect completion of acceleration or braking while the capstan motor is
making intermittent revolutions.
For more information, see section 15.3.6, Acceleration and Braking Processes of the Capstan
Motor.
Bit 6
AC/BR
Description
0
Braking
1
Acceleration
Rev.2.00 Jan. 15, 2007 page 292 of 1174
REJ09B0329-0200
(Initial value)
Section 15 Timer R
Bit 5⎯Using/Not Using the TMRU-2 for Reloading (RLD): This bit is used for selecting if the
TMRU-2 reload function is to be turned on or not.
Bit 5
RLD
Description
0
Not using the TMRU-2 as the reload timer
1
Using the TMRU-2 as the reload timer
(Initial value)
Bit 4⎯Reloading Timing for the TMRU-2 (RLCK): This bit works to select if the TMRU-2 is
reloading by the CFG or by underflowing of the TMRU-2 counter. This choice is valid only when
the bit 5 (RLD) is being set to 1.
Bit 4
RLCK
Description
0
Reloading at the rising edge of the CFG
1
Reloading by underflowing of the TMRU-2
(Initial value)
Bits 3 and 2⎯Clock Source for the TMRU-2 (PS21, PS20): These bits work to select the
inputting clock to the TMRU-2.
Bit 3
Bit 2
PS21
PS20
0
0
Counting by underflowing of the TMRU-1
1
Counting by the PSS, φ/256
0
Counting by the PSS, φ/128
1
Counting by the PSS, φ/64
1
Description
(Initial value)
Bit 1⎯Operation Mode of the TMRU-1 (RLD/CAP): This bit works to select if the operation
mode of the TMRU-1 is reload timer mode or capture timer mode.
Under the capture timer mode, reloading operation will not be made. Also, the counter reading
will be cleared as soon as capture has been made.
Bit 1
RLD/CAP
Description
0
The TMRU-1 works as the reloading timer
1
The TMRU-1 works as the capture timer
(Initial value)
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Section 15 Timer R
Bit 0⎯Capture Signals of the TMRU-1 (CPS): In combination with the LAT bit (Bit 7) of the
TMRM2, this bit works to select the capture signals of the TMRU-1. This bit becomes valid when
the LAT bit is being set to 1. It will also become valid when the RLD/CAP bit (Bit 1) is being set
to 1. Nonetheless, it will be invalid when the RLD/CAP bit (Bit 1) is being set to 0.
Bit 0
CPS
Description
0
Capture signals at the rising edge of the CFG
1
Capture signals at the edge of the IRQ3
15.2.2
(Initial value)
Timer R Mode Register 2 (TMRM2)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
LAT
PS11
PS10
PS31
PS30
CP/SLM
CAPF
SLW
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)*
R/(W)*
The timer R mode register 2 (TMRM2) is an 8-bit read/write register which works to identify the
operation mode and to control the slow tracking processing.
When reset, the TMRM2 is initialized to H'00.
Note: * The CAPF bit and the SLW bit, respectively, works to latch the interrupt causes and
writing 0 only is valid. Consequently, when these bits are being set to 1, respective
interrupt requests will not be issued. Therefore, it is necessary to check these bits
during the course of the interrupt processing routine to have them cleared.
Also, priority is given to the set and, when an interrupt cause occur while the a clearing
command (BCLR, MOV, etc.) is being executed, the CAPF bit and the SLW bit will
not be cleared respectively and it thus becomes necessary to pay attention to the
clearing timing.
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Section 15 Timer R
Bit 7⎯Capture Signals of the TMRU-2 (LAT): In combination with the CPS bit (Bit 0) of the
TMRM1, this bit works to select the capture signals of the TMRU-2.
TMRM2
TMRM1
Bit 7
Bit 0
LAT
CPS
Description
0
*
Captures when the TMRU-3 underflows
1
0
Captures at the rising edge of the CFG
1
Captures at the edge of the IRQ3
(Initial value)
Legend: * Don't care.
Bits 6 and 5⎯Clock Source for the TMRU-1 (PS11, PS10): These bits work to select the
inputting clock to the TMRU-1.
Bit 6
Bit 5
PS11
PS10
Description
0
0
Counting at the rising edge of the CFG
1
Counting by the PSS, φ/4
0
Counting by the PSS, φ/256
1
Counting by the PSS, φ/512
1
(Initial value)
Bits 4 and 3⎯Clock Source for the TMRU-3 (PS31, PS30): These bits work to select the
inputting clock to the TMRU-3.
Bit 4
Bit 3
PS31
PS30
Description
0
0
Counting at the rising edge of the DVCTL from the dividing circuit.
(Initial value)
1
Counting by the PSS, φ/4096
0
Counting by the PSS, φ/2048
1
Counting by the PSS, φ/1024
1
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Section 15 Timer R
Bit 2⎯Interrupt Causes (CP/SLM): This bit works to select the interrupt causes for the TMRI3.
Bit 2
CP/SLM
Description
0
Makes interrupt requests upon the capture signals of the TMRU-2 valid (Initial value)
1
Makes interrupt requests upon ending of the slow tracking mono-multi valid
Bit 1⎯Capture Signal Flag (CAPF): This is a flag being set out by the capture signal of the
TMRU-2. Although both reading/writing are possible, 0 only is valid for writing.
Also, priority is being given to the set and, when the capture signal and writing 0 occur
simultaneously, this flag bit remains being set to 1 and the interrupt request will not be issued and
it is necessary to be attentive about this fact.
When the CP/SLM bit (bit 2) is being set to 1, this CAPF bit should always be set to 0.
The CAPF flag is cleared to 0 under the low power consumption mode.
Bit 1
CAPF
Description
0
[Clearing condition]
(Initial value)
When 0 is written after reading 1
1
[Setting condition]
At occurrences of the TMRU-2 capture signals while the CP/SLM bit is set to 0
Bit 0⎯Slow Tracking Mono-multi Flag (SLW): This is a flag being set out when the slow
tracking mono-multi processing ends. Although both reading/writing are possible, 0 only is valid
for writing.
Also, priority is being given to the set and, when ending of the slow tracking mono-multi
processing and writing 0 occur simultaneously, this flag bit remains being set to 1 and the interrupt
request will not be issued and it is necessary to be attentive about this fact.
When the CP/SLM bit (bit 2) is being set to 0, this SLW bit should always be set to 0.
The SLW flag is cleared to 0 under the low power consumption mode.
Bit 0
SLW
Description
0
[Clearing condition]
(Initial value)
When 0 is written after reading 1
1
[Setting condition]
When the slow tracking mono-multi processing ends while the CP/SLM bit is set to 1
Rev.2.00 Jan. 15, 2007 page 296 of 1174
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Section 15 Timer R
15.2.3
Timer R Control/Status Register (TMRCS)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
TMRI3E
TMRI2E
TMRI1E
TMRI3
TMRI2
TMRI1
—
—
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/(W)*
R/(W)*
R/(W)*
—
—
Note: * Only 0 can be written to clear the flag.
The timer R control/status register (TMRCS) works to control the interrupts of timer R.
The TMRCS is an 8-bit read/write register. When reset, the TMRCS is initialized to H'03.
Bit 7⎯Enabling the TMRI3 Interrupt (TMRI3E): This bit works to permit/prohibit occurrence
of the TMRI3 interrupt when an interrupt cause being selected by the CP/SLM bit of the TMRM2
has occurred, such as occurrences of the TMRU-2 capture signals or when the slow tracking
mono-multi processing ends, and the TMRI3 has been set to 1.
Bit 7
TMRI3E
Description
0
Prohibits occurrences of TMRI3 interrupts
1
Permits occurrences of TMRI3 interrupts
(Initial value)
Bit 6⎯Enabling the TMRI2 Interrupt (TMRI2E): This bit works to permit/prohibit occurrence
of the TMRI2 interrupt when the TMRI2 has been set to 1 by issuance of the underflow signal of
the TMRU-2 or by ending of the slow tracking mono-multi processing.
Bit 6
TMRI2E
Description
0
Prohibits occurrences of TMRI2 interrupts
1
Permits occurrences of TMRI2 interrupts
(Initial value)
Bit 5⎯Enabling the TMRI1 Interrupt (TMRI1E): This bit works to permit/prohibit occurrence
of the TMRI1 interrupt when the TMRI1 has been set to 1 by issuance of the underflow signal of
the TMRU-1.
Bit 5
TMRI1E
Description
0
Prohibits occurrences of TMRI1 interrupts
1
Permits occurrences of TMRI1 interrupts
(Initial value)
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Section 15 Timer R
Bit 4⎯TMRI3 Interrupt Requesting Flag (TMRI3): This is the TMRI3 interrupt requesting
flag.
It indicates occurrence of an interrupt cause being selected by the CP/SLM bit of the TMRM2,
such as occurrences of the TMRU-2 capture signals or ending of the slow tracking mono-multi
processing.
Bit 4
TMRI3
Description
0
[Clearing condition]
1
[Setting condition]
(Initial value)
When 0 is written after reading 1
At occurrence of the interrupt cause being selected by the CP/SLM bit of the TMRM2
Bit 3⎯TMRI2 Interrupt Requesting Flag (TMRI2): This is the TMRI2 interrupt requesting
flag.
It indicates occurrences of the TMRU-2 underflow signals or ending of the acceleration/braking
processing of the capstan motor.
Bit 3
TMRI2
Description
0
[Clearing condition]
(Initial value)
When 0 is written after reading 1
1
[Setting condition]
At occurrences of the TMRU-2 underflow signals or ending of the acceleration
/braking processing of the capstan motor
Bit 2⎯TMRI1 Interrupt Requesting Flag (TMRI1): This is the TMRI1 interrupt requesting
flag.
It indicates occurrences of the TMRU-1 underflow signals.
Bit 2
TMRI1
Description
0
[Clearing condition]
When 0 is written after reading 1.
1
[Setting condition]
When the TMRU-1 underflows.
Rev.2.00 Jan. 15, 2007 page 298 of 1174
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(Initial value)
Section 15 Timer R
Bits 1 and 0⎯Reserved: These bits cannot be modified and are always read as 1.
15.2.4
Timer R Capture Register 1 (TMRCP1)
Bit :
7
6
5
4
3
2
1
0
TMRC17 TMRC16 TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10
Initial value :
1
1
1
1
1
1
1
1
R/W :
R
R
R
R
R
R
R
R
The timer R capture register 1 (TMRCP1) works to store the captured data of the TMRU-1.
During the course of the capturing operation, the TMRU-1 counter readings are captured by the
TMRCP1 at the CFG edge or the IRQ3 edge. The capturing operation of the TMRU-1 is
performed using 16 bits, in combination with the capturing operation of the TMRU-2.
The TMRCP1 is an 8-bit read only register. When reset, the TMRCS is initialized to H'FF.
Notes: 1. When the TMRCP1 is readout while the capture signal is being received, the reading
data become unstable. Pay attention to the timing for reading out.
2. When a shift to the low power consumption mode is made while the capturing
operating is in progress, the counter reading becomes unstable. After returning to the
active mode, always write H'FF into the TMRL1 to initialize the counter.
15.2.5
Timer R Capture Register 2 (TMRCP2)
Bit :
7
6
5
4
3
2
1
0
TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20
Initial value :
1
1
1
1
1
1
1
1
R/W :
R
R
R
R
R
R
R
R
The timer R capture register 2 (TMRCP2) works to store the capture data of the TMRU-2. At each
CFG edge, IRQ3 edge, or at occurrence of underflow of the TMRU-3, the TMRU-2 counter
readings are captured by the TMRCP2.
The TMRCP2 is an 8-bit read only register. When reset, the TMRCS will be initialized into H'FF.
Notes: 1. When the TMRCP2 is readout while the capture signal is being received, the reading
data become unstable. Pay attention to the timing for reading out.
2. When a shift to the low power consumption mode is made, the counter reading
becomes unstable. After returning to the active mode, always write H'FF into the
TMRL2 to initialize the counter.
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Section 15 Timer R
15.2.6
Timer R Load Register 1 (TMRL1)
Bit :
7
6
5
4
3
2
1
0
TMR17
TMR16
TMR15
TMR14
TMR13
TMR12
TMR11
TMR10
Initial value :
1
1
1
1
1
1
1
1
R/W :
W
W
W
W
W
W
W
W
The timer R load register 1 (TMRL1) is an 8-bit write-only register which works to set the load
value of the TMRU-1.
When a load value is set to the TMRL1, the same value will be set to the TMRU-1 counter
simultaneously and the counter starts counting down from the set value. Also, when the counter
underflows during the course of the reload timer operation, the TMRL1 value will be set to the
counter.
When reset, the TMRL1 is initialized to H'FF.
15.2.7
Timer R Load Register 2 (TMRL2)
Bit :
7
6
5
4
3
2
1
0
TMR27
TMR26
TMR25
TMR24
TMR23
TMR22
TMR21
TMR20
Initial value :
1
1
1
1
1
1
1
1
R/W :
W
W
W
W
W
W
W
W
The timer R load register 2 (TMRL2) is an 8-bit write only register which works to set the load
value of the TMRU-2.
When a load value is set to the TMRL2, the same value will be set to the TMRU-2 counter
simultaneously and the counter starts counting down from the set value. Also, when the counter
underflows or a CFG edge is detected during the course of the reload timer operation, the TMRL2
value will be set to the counter.
When reset, the TMRL2 is initialized to H'FF.
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Section 15 Timer R
15.2.8
Timer R Load Register 3 (TMRL3)
Bit :
7
6
5
4
3
2
1
0
TMR37
TMR36
TMR35
TMR34
TMR33
TMR32
TMR31
TMR30
Initial value :
1
1
1
1
1
1
1
1
R/W :
W
W
W
W
W
W
W
W
The timer R load register 3 (TMRL3) is an 8-bit write only register which works to set the load
value of the TMRU-3.
When a load value is set to the TMRL3, the same value will be set to the TMRU-3 counter
simultaneously and the counter starts counting down from the set value. Also, when the counter
underflows or a DVCTL edge is detected, the TMRL2 value will be set to the counter. (Reloading
will be made by the underflowing signals when the DVCTL signal is selected as the clock source,
and reloading will be made by the DVCTL signals when the dividing clock is selected as the clock
source.)
When reset, the TMRL3 is initialized to H'FF.
15.2.9
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP11 bit is set to 1, timer R stops its operation at the ending point of the bus cycle to
shift to the module stop mode. For more information, see section 4.5, Module Stop Mode.
When reset, the MSTPCR is initialized to H'FFFF.
Bit 3⎯Module Stop (MSTP11): This bit works to designate the module stop mode for the Timer
R.
MSTPCRH
Bit 3
MSTP11
Description
0
Cancels the module stop mode of timer R
1
Sets the module stop mode of timer R
(Initial value)
Rev.2.00 Jan. 15, 2007 page 301 of 1174
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Section 15 Timer R
15.3
Operation
15.3.1
Reload Timer Counter Equipped with Capturing Function TMRU-1
TMRU-1 is a reload timer counter equipped with capturing function. It consists of an 8-bit downcounter, a reloading register and a capture register.
The clock source can be selected from among the leading edge of the CFG signals and three types
of dividing clocks. It is also selectable whether using it as a reload counter or as a capture counter.
Even when the capturing function is selected, the counter readings can be updated by writing the
values into the reloading register.
When the counter underflows, the TMRI1 interrupt request will be issued.
The initial values of the TMRU-1 counter, reloading register and capturing register are all H'FF.
• Operation of the Reload Timer
When a value is written into to the reloading register, the same value will be written into the
counter simultaneously. Also, when the counter underflows, the reloading register value will
be reloaded to the counter. The TMRU-1 is a dividing circuit for the CFG. In combination with
the TMRU-2 and TMRU-3, it can also be used for the mode identification purpose.
• Capturing Operation
Capturing operation is carried out in combination with the TMRU-2 using the combined 16
bits. It can be so programmed that the counter may be cleared by the capture signal. The CFG
edges or IRQ3 edges are used as the capture signals. It is possible to issue the TMRI3 interrupt
request by the capture signal.
In addition to the capturing function being worked out in combination with the TMRU-2, the
TMRU-1 can be used as a 16-bit CFG counter. Selecting the IRQ3 as the capture signal, the
CFG within the duration of the reel pulse being input into the IRQ3 pin can be counted by the
TMRU-1.
15.3.2
Reload Timer Counter Equipped with Capturing Function TMRU-2
TMRU-2 is a reload timer counter equipped with capturing function. It consists of an 8-bit downcounter, a reloading register and a capture register.
The clock source can be selected from among the undedrflowing signal of the TMRU-1 and three
types of dividing clocks. Also, although the reloading function is workable during its capturing
operation, equipping or not of the reloading function is selectable. Even when without-reloadingfunction is chosen, the counter reading can be updated by writing the values to the reloading
register.
When the counter underflows, the TMRI2 interrupt request will be issued.
The initial values of the TMRU-2 counter, reloading register and capturing register are all H'FF.
Rev.2.00 Jan. 15, 2007 page 302 of 1174
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Section 15 Timer R
• Operation of the Reload Timer
When a value is written into to the reloading register, the same value will be written into the
counter, simultaneously. Also, when the counter underflows or when a CFG edge is detected,
the reloading register value will be reloaded to the counter.
The TMRU-2 can make acceleration and braking work for the capstan motor using the reload
timer operation.
• Capturing Operation
Using the capture signals, the counter reading can be latched into the capturing register. As the
capture signal, you can choose from among edges of the CFG, edges of the IRQ3 or the
underflow signals of the TMRU-3. It is possible to issue the TMRI3 interrupt request by the
capture signal.
The capturing function (stopping the reloading function) of the TMRU-2, in combination with
the TMRU-1 and TMRU-3, can also be used for the mode identification purpose.
15.3.3
Reload Counter Timer TMRU-3
The reload counter timer TMRU-3 consists of an 8-bit down-counter and a reloading register. Its
clock source can be selected from between the undedrflowing signal of the counter and the edges
of the DVCTL signals. (When the DVCTL signal is selected as the clock source, reloading will be
effected by the underflowing signals and when the dividing clock is selected as the clock source,
reloading will be effected by the DVCTL signals.) The reloading signal works to reload the
reloading register value into the counter. Also, when a value is written into to the reloading
register, the same value will be written into the counter, simultaneously.
The initial values of the counter and the reloading register are H'FF.
The underflowing signals can be used as the capturing signal for the TMRU-2.
The TMRU-3 can also be used as a dividing circuit for the DVCTL. Also, in combination with the
TMRU-1 and TMRU-2 (capturing function), the TMRU-3 can be used for the mode identification
purpose. Since the divided signals of the DVCTL are being used as the clock source, CTL signals
(DVCTL) conforming to the double speed can be input when making searches. These DVCTL
signals can also be used for phase controls of the capstan motor.
Also, by selecting the dividing clock as the clock source, it is possible to make a delay with the
edges of the DVCTL to provide the slow tracking mono-multi function.
Rev.2.00 Jan. 15, 2007 page 303 of 1174
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Section 15 Timer R
15.3.4
Mode Identification
When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing
tapes, the TMRU-1 (CFG dividing circuit), TMRU-2 (capturing function/without reloading
function) and TMRU-3 (DVCTL dividing circuit) of timer R should be used.
Timer R will become to the aforementioned status after a reset.
Under the aforementioned status, the divided CFG should be written into the reloading register of
the TMRU-1 and divided DVCTL should be written into the reloading register of the TMRU-3.
When the TMRU-3 underflows, the counter value of the TMRU-2 is captured. Such capturing
register value represents the number of the CFG within the DVCTL cycle.
As aforementioned, the Timer R can work to count the number of the CFG corresponding to n
times of DVCTL's or to identify the mode being searched.
For register settings, see section 15.5.1, Mode Identification.
15.3.5
Reeling Controls
CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and
TMRU-2. Choosing the IRQ3 as the capture signal and counting the CFG within the duration of
the reel pulse being input through the IRQ3 pin affect reeling controls. For register settings, see
section 15.5.2, Reeling Controls.
15.3.6
Acceleration and Braking Processes of the Capstan Motor
When making intermittent movements such as those for slow reproductions or for still
reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan
motor. The acceleration and braking processes functions to check if the revolution of a capstan
motor has reached the prescribed rate when accelerated or braked. For this purpose, the TMRU-2
(reloading function) should be used.
When making accelerations:
• Set the AC/BR bit of the TMRM1 to acceleration (set to 1). Also, use the rising edge of the
CFG as the reloading signal.
• Set the prescribed time on the CFG frequency to determine if the acceleration has been
finished, into the reloading register.
• The TMRU-2 will work to down-count the reloading data.
• In case the acceleration has not been finished (in case the CFG signal is not input even when
the prescribed time has elapsed = underflowing of down-counting has occurred), such
underflowing works to set to CFG mask F/F (masking movement) and the reload timer will be
cleared by the CFG.
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Section 15 Timer R
• When the acceleration has been finished (when the CFG signal is input before the prescribed
time has elapsed = reloading movement has been made before the down counter underflows),
an interrupt request will be issued because of the CFG.
When making breaking:
• Set the AC/BR bit of the TMRM1 to braking (clear to 0). Also, use the rising edge of the CFG
as the reloading signal.
• Set the prescribed time on the CFG frequency to determine if the braking has been finished,
into the reloading register.
• The TMRU-2 will work to down-count the reloading data.
• If the braking has not finished (when the CFG signal is input before the prescribed time has
elapsed and reloading movement has been made before the down counter underflows), the
reload timer movement will continue.
• When the acceleration has finished (when the CFG signal is not input even when the
prescribed time has elapsed and underflowing of down-counting has occurred), interrupt
request will be issued because of the underflowing signal.
The acceleration and braking processes should be employed when making special reproductions,
in combination with the slow tracking mono-multi function outlined in section 15.3.7, Slow
Tracking Mono-Multi Function.
For register settings, see section 15.5.4, Acceleration and Braking Processes of the Capstan Motor.
15.3.7
Slow Tracking Mono-Multi Function
When performing slow reproductions or still reproductions, the braking timing for the capstan
motor is determined by use of the edge of the DVCTL signal. The slow tracking mono-multi
function works to measure the time from the rising edge of the DVCTL signal down to the desired
point to issue the interrupt request. In actual programming, this interrupt should be used to activate
the brake of the capstan motor. The TMRU-3 should be used to perform time measurements for
the slow tracking mono-multi function. Also, the braking process can be made using the TMRU-2.
Figure 15.2 shows the time series movements when a slow reproduction is being performed.
For register settings, see section 15.5.3, Slow Tracking Mono-Multi Function.
Rev.2.00 Jan. 15, 2007 page 305 of 1174
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Section 15 Timer R
Compensation for vertical vibrations
(Supplementary V-pulse)
HSW
FG acceleration detection
Accelerating the
capstan motor
Hi-Z
Acceleration
process
DVCTL↑
Interrupt
Slow tracking
mono-multi
Slow tracking
delay
Braking the
capstan motor
Forward
rotation
Braking the
drum motor
FG stopping detection
Reloading
Reverse
rotation
Braking
process
Servo
Compensation for
horizontal vibrations
Compensation for
horizontal vibrations
Frame feeds
H.AmpSW
C.Rotary
Legend:
Hi-Z : High impedance state
In case of 4-head SP mode.
In case of 2-head application, H.AmpSW and
C.Rotary should be "Low".
Figure 15.2 Time Series Movements when a Slow Reproduction
Is Being Performed
Rev.2.00 Jan. 15, 2007 page 306 of 1174
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Section 15 Timer R
15.4
Interrupt Cause
In timer R, bits TMRI1 to TMRI3 of the timer R control/status register cause interrupts. The
following are descriptions of the interrupts.
1. Interrupts caused by the underflowing of the TMRU-1 (TMRI1)
These interrupts will constitute the timing for reloading with the TMRU-1.
2. Interrupts caused by the underflowing of the TMRU-2 or by an end of the acceleration or
braking process (TMRI2)
When interrupts occur at the reload timing of the TMRU-2, clear the AC/BR
(acceleration/braking) bit of the timer R mode register 1 (TMRM1) to 0.
3. Interrupts caused by the capture signals of the TMRU-2 and by ending the slow tracking
mono-multi process (TMRI3)
Since these two interrupt causes are constituting the OR, it becomes necessary to determine
which interrupt cause is occurring using the software.
Respective interrupt causes are being set to the CAPF flag or the SLW flag of the timer R
mode register 2 (TMRM2), have the software determine which.
Since the CAPF flag and the SLW flag will not be cleared automatically, program the software
to clear them. (Writing 0 only is valid for these flags.) Unless these flags are cleared, detection
of the next cause becomes unworkable. Also, if the CP/SLM bit is changed leaving these flags
uncleared as they are, these flags will get cleared.
Rev.2.00 Jan. 15, 2007 page 307 of 1174
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Section 15 Timer R
15.5
Settings for Respective Functions
15.5.1
Mode Identification
When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing
tapes, the TMRU-1 (CFG dividing circuit), TMRU-2 (capturing function/without reloading
function) and TMRU-3 (DVCTL dividing circuit) of the timer R should be used.
Timer R will be initialized to this mode identification status after a reset.
Under this status, the divided CFG should be written into the reloading register of the TMRU-1
and divided DVCTL should be written into the reloading register of the TMRU-3. When the
TMRU-3 underflows, the counter value of the TMRU-2 is captured. Such capturing register value
represents the number of the CFG within the DVCTL cycle.
Thus, timer R can work to count the number of the CFG corresponding to n times of DVCTL's or
to identify the mode being searched.
Settings
• Setting the timer R mode register 1 (TMRM1)
⎯ CLR2 bit (bit 7) = 1: Works to clear after making the TMRU-2 capture.
⎯ RLD bit (bit 5) = 0: Sets the TMRU-2 without reloading function.
⎯ PS21 and PS20 (bits 3 and 2) = (0 and 0): The underflowing signals of the TMRU-1 are to
be used as the clock source for the TMRU-2.
⎯ RLD/CAP bit (bit 1) = 0: The TMRU-1 has been set to make the reload timer operation.
• Setting the timer R mode register 2 (TMRM2)
⎯ LAT bit (bit 7) = 0: The underflowing signals of the TMRU-3 are to be used as the capture
signal for the TMRU-2.
⎯ PS11 and PS10 (bits 6 and 5) = (0 and 0): The leading edge of the CFG signal is to be used
as the clock source for the TMRU-1.
⎯ PS31 and PS30 (bits 4 and 3) = (0 and 0): The leading edge of the DVCTL signal is to be
used as the clock source for the TMRU-3.
⎯ CP/SLM bit (bit 2) = 0: The capture signal is to work to issue the TMRI3 interrupt request.
• Setting the timer R load register 1 (TMRL1)
⎯ Set the dividing value for the CFG. The set value should become (n −1) when divided by n.
• Setting the timer R load register 3 (TMRL3)
⎯ Set the dividing value for the DVCTL. The set value should become (n −1) when divided
by n.
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Section 15 Timer R
15.5.2
Reeling Controls
CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and
TMRU-2. By choosing the IRQ3 as the capture signal, and by counting the CFG within the
duration of the reel pulse being input through the IRQ3 pin, reeling controls, etc. can be effected.
Settings
• Setting P13/IRQ3 pin as the IRQ3 pin
⎯ Set the PMR13 bit (bit 3) of the port mode register 1 (PMR1) to 1. See section 6.2.6, Port
Mode Register (PMR1).
• Setting the timer R mode register 1 (TMRM1)
⎯ CLR2 bit (bit 7) = 1: Works to clear after making the TMRU-2 capture.
⎯ PS21 and PS20 (bits 3 and 2) = (0 and 0): The underflowing signals of the TMRU-1 are to
be used as the clock source for the TMRU-2.
⎯ RLD/CAP bit (bit 1) = 1: The TMRU-1 has been set to make the capturing operation.
⎯ CPS bit (bit 0) = 1: The edge of the IRQ3 signal is to be used as the capture signal for the
TMRU-1 and TMRU-2.
• Setting the timer R mode register 2 (TMRM2)
⎯ LAT bit (bit 7) = 1: The edge of the IRQ3 signal is to be used as the capture signal for the
TMRU-1 and TMRU-2.
⎯ PS11 and PS10 (bits 6 and 5) = (0 and 0): The rising edge of the CFG signal is to be used
as the clock source for the TMRU-1.
⎯ CP/SLM bit (bit 2) = 0: The capture signal is to work to issue the TMRI3 interrupt request.
Rev.2.00 Jan. 15, 2007 page 309 of 1174
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Section 15 Timer R
15.5.3
Slow Tracking Mono-Multi Function
When performing slow reproductions or still reproductions, the braking timing for the capstan
motor is determined by use of the edge of the DVCTL signal. The slow tracking mono-multi
function works to measure the time from the leading edge of the DVCTL signal down to the
desired point to issue the interrupt request. In actual programming, this interrupt should be used to
activate the brake of the capstan motor. The TMRU-3 should be used to perform time
measurements for the slow tracking mono-multi function. Also, the braking process can be made
using the TMRU-2.
Settings
• Setting the timer R mode register 2 (TMRM2)
⎯ PS31 and PS30 (bits 4 and 3) = Other than (0, 0): The dividing clock is to be used as the
clock source for the TMRU-3.
⎯ CP/SLM bit (bit 2) = 1: The slow tracking delay signal is to work to issue the TMRI3
interrupt request.
• Setting the timer R load register 3 (TMRL3)
⎯ Set the slow tracking delay value. When the delay count is n, the set value should be
(n – 1).
⎯ Regarding the delaying duration, see figure 15.2.
Rev.2.00 Jan. 15, 2007 page 310 of 1174
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Section 15 Timer R
15.5.4
Acceleration and Braking Processes of the Capstan Motor
When making intermittent movements such as those for slow reproductions or for still
reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan
motor. The acceleration and braking processes will function to check if the revolution of a capstan
motor has reached the prescribed rate when accelerated or braked. For this purpose, the TMRU-2
(reloading function) should be used.
The acceleration and braking processes should be employed when making special reproductions,
in combination with the slow tracking mono-multi function.
Settings for the acceleration process
• Setting the timer R mode register 1 (TMRM1)
⎯ AC/BR bit (bit 6) = 1: Acceleration process
⎯ RLD bit (bit 5) = 1: The TMRU-2 is to be used as the reload timer.
⎯ RLCK bit (bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG.
⎯ PS21 and PS20 (bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the
clock source for the TMRU-2.
• Setting the timer R load register 2 (TMRL2)
⎯ Set the count reading for the duration until the acceleration process finishes. When the
count is n, the set value should be (n − 1).
⎯ Regarding the duration until the acceleration process finishes, see figure 15.2.
Settings for the braking process
• Setting the timer R mode register 1 (TMRM1)
⎯ AC/BR bit (bit 6) = 0: Braking process
⎯ RLD bit (bit 5) = 1: The TMRU-2 is to be used as the reload timer.
⎯ RLCK bit (bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG.
⎯ PS21 and PS20 (bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the
clock source for the TMRU-2.
• Setting the timer R load register 2 (TMRL2)
⎯ Set the count reading for the duration until the braking process finishes. When the count is
n, the set value should be (n – 1).
⎯ Regarding the duration until the braking process finishes, see figure 15.2.
Rev.2.00 Jan. 15, 2007 page 311 of 1174
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Section 15 Timer R
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Section 16 Timer X1
Section 16 Timer X1
Note: The Timer X1 is not (incorporated in) provided for the H8S/2197S and H8S/2196S.
16.1
Overview
Timer X1 is capable of outputting two different types of independent waveforms using a 16-bit
free running counter (FRC) as the basic means and it is also applicable to measurements of the
durations of input pulses and the cycles external clocks.
16.1.1
Features
Timer X1 has the following features:
• Four different types of counter inputting clocks.
Three different types of internal clocks (φ/4, φ/16 and φ/64) and the DVCFG.
• Two independent output comparing functions
Capable of outputting two different types of independent waveforms.
• Four independent input capturing functions
The rising edge or falling edge can be selected for use. The buffer operation can also be
designated.
• Counter clearing designation is workable.
The counter readings can be cleared by compare match A.
• Seven types of interrupt causes
Comparing match × 2 causes, input capture × 4 causes and overflow × 1 cause are available for
use and they can make respective interrupt requests independently.
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Section 16 Timer X1
16.1.2
Block Diagram
Figure 16.1 shows a block diagram of the Timer X1.
FTIA*
(HSW)
FTIB*
(VD)
FTIC*
(DVCTL)
FTID*
(NHSW)
ICRA
Input
capture
control
ICRB
ICRC
ICRD
TCRX
OCRB
Internal data bus
Comparison circuit
FRC
(DVCFG)
φ/4
φ/16
φ/64
Comparison circuit
OCRA
Output comparing output
FTOA
FTOB
TOCR
TCSRX
TIER
Legend:
TIER
TCSRX
FRC
OCRA
OCRB
TCRX
Interrupt
request × 7
: Timer interrupt enabling register
: Timer control/status register X
: Free running counter
: Output comparing register A
: Output comparing register B
: Timer control register X
TOCR
ICRA
ICRB
ICRC
ICRD
: Output comparing control register
: Input capture register A
: Input capture register B
: Input capture register C
: Input capture register D
Note: * stands for the external terminal.
( ) stands for the internal signal.
Figure 16.1 Block Diagram of Timer X1
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Section 16 Timer X1
16.1.3
Pin Configuration
Table 16.1 shows the pin configuration of timer X1.
Table 16.1 Pin Configuration
Name
Abbrev.
I/O
Function
Output comparing A output-pin
FTOA
Output
Output pin for the output comparing A
Output comparing B output-pin
FTOB
Output
Output pin for the output comparing B
Input capture A input-pin
FTIA
Input
Input-pin for the input capture A
Input capture B input-pin
FTIB
Input
Input-pin for the input capture B
Input capture C input-pin
FTIC
Input
Input-pin for the input capture C
Input capture D input-pin
FTID
Input
Input-pin for the input capture D
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Section 16 Timer X1
16.1.4
Register Configuration
Table 16.2 shows the register configuration of timer X1.
Table 16.2 Register Configuration
Name
Abbrev.
R/W
Initial Value
3
Address*
Timer interrupt enabling register
TIER
R/W
H'00
H'D100
Timer control/status register X
TCSRX
1
R/ (W)*
H'00
H'D101
Free running counter H
FRCH
R/W
H'00
H'D102
Free running counter L
FRCL
R/W
H'00
H'D103
Output comparing register AH
OCRAH
R/W
H'FF
Output comparing register AL
OCRAL
R/W
H'FF
H'D104*
2
H'D105*
Output comparing register BH
OCRBH
R/W
H'FF
Output comparing register BL
OCRBL
R/W
H'FF
H'D104*
2
H'D105*
Timer control register X
TCRX
R/W
H'00
H'D106
Timer output comparing control register
TOCR
R/W
H'00
H'D107
Input capture register AH
ICRAH
R
H'00
H'D108
Input capture register AL
ICRAL
R
H'00
H'D109
Input capture register BH
ICRBH
R
H'00
H'D10A
Input capture register BL
ICRBL
R
H'00
H'D10B
Input capture register CH
ICRCH
R
H'00
H'D10C
Input capture register CL
ICRCL
R
H'00
H'D10D
Input capture register DH
ICRDH
R
H'00
H'D10E
Input capture register DL
ICRDL
R
H'00
H'D10F
2
2
Notes: 1. Only 0 can be written to clear the flag for Bits 7 to 1. Bit 0 is readable/writable.
2. The addresses of the OCRA and OCRB are the same. Changeover between them are
to be made by use of the TOCR bit and OCRS bit.
3. Lower 16 bits of the address.
Rev.2.00 Jan. 15, 2007 page 316 of 1174
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Section 16 Timer X1
16.2
Register Descriptions
16.2.1
Free Running Counter (FRC)
Free running counter H (FRCH)
Free running counter L (FRCL)
FRC
Bit :
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FRCH
FRCL
The FRC is a 16-bit read/write up-counter which counts up by the inputting internal clock/external
clock. The inputting clock is to be selected from the CKS1 and CKS0 of the TCRX.
By the setting of the CCLRA bit of the TCSRX, the FRC can be cleared by comparing match A.
When the FRC overflows (H'FFFF → H'0000), the OVF of the TCSRX will be set to 1.
At this time, when the OVIE of the TIER is being set to 1, an interrupt request will be issued to the
CPU.
Reading/writing can be made from and to the FRC through the CPU at 8-bit or 16-bit.
The FRC is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
16.2.2
Output Comparing Registers A and B (OCRA and OCRB)
Output comparing register AH and BH (OCRAH and OCRBH)
Output comparing register AL and BL (OCRAL and OCRBL)
OCRA, OCRB
Bit :
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRAH, OCRBH
OCRAL, OCRBL
The OCR consists of twin 16-bit read/write registers (OCRA and OCRB). The contents of the
OCR are always being compared with the FRC and, when the value of these two match, the OCFA
and OCRB of the TCSRX will be set to 1. At this time, if the OCIAE and OCIB of the TIER are
Rev.2.00 Jan. 15, 2007 page 317 of 1174
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Section 16 Timer X1
being set to 1, an interrupt request will be issued to the CPU.
When performing compare matching, if the OEA and OEB of the TOCR are set to 1, the level
value set to the OLVLA and OLVLB of the TOCR will be output through the FTOA and FTOB
pins. After resetting, 0 will be output through the FTOA and FTOB pins until the first compare
matching occurs.
Reading/writing can be made from and to the OCR through the CPU at 8-bit or 16-bit.
The OCR is cleared to H'FFFF when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
16.2.3
Input Capture Registers A through D (ICRA through ICRD)
Input capture register AH to DH (ICRAH to ICRDH)
Input capture register AL to DL (ICRAL to ICRDL)
ICRA, ICRB, ICRC, ICRD
Bit :
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W :
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ICRAH, ICRBH, ICRCH, ICRDH
ICRAL, ICRBL, ICRCL, ICRDL
The ICR consists of four 16-bit read-only registers (ICRA through ICRD).
When the falling edge of the input capture input signal is detected, the value is transferred to the
ICRA through ICRD. The ICFA through ICFD of the TCSRX are set to 1 simultaneously. If the
IDIAE through IDIDE of the TCRX are all set to 1, an interrupt request will be issued to the CPU.
The edge of the input signal can be selected by setting the IEDGA through IEDGD of the TCRX.
The ICRC and ICRD can also be used as the buffer register, of the ICRA and ICRB, respectively
by setting the BUFEA and BUFEB of the TCRX to perform buffer operations. Figure 16.2 shows
the connections necessary when using the ICRC as the buffer register of the ICRA. (BUFEA = 1)
When the ICRC is used as the buffer of the ICRA, by setting IEDGA ≠ IEDGC, both of the rising
and falling edges can be designated for use. In case of IEDGA = IEDGC, either one of the rising
edge or the falling edge only is usable. Regarding selection of the input signal edge, see table 16.3.
Note: Transference from the FRC to the ICR will be performed regardless of the value of the
ICF.
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Section 16 Timer X1
IEDGA
BUFEA IEDGC
Edge detection and
capture signal
generating circuit.
FTIA
ICRC
ICRA
FRC
Figure 16.2 Buffer Operation (Example)
Table 16.3 Input Signal Edge Selection when Making Buffer Operation
IEDGA
IEDGC
Selection of the Input Signal Edge
0
0
Captures at the falling edge of the input capture input A (Initial value)
1
Captures at both rising and falling edges of the input capture input A
1
0
1
Captures at the rising edge of the input capture input A
Reading can be made from the ICR through the CPU at 8-bit or 16-bit.
For stable input capturing operation, maintain the pulse duration of the input capture input signals
at 1.5 system clock (φ) or more in case of single edge capturing and at 2.5 system clock (φ) or
more in case of both edge capturing.
The ICR is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
16.2.4
Timer Interrupt Enabling Register (TIER)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
ICIAE
ICIBE
ICICE
ICIDE
OCIAE
OCIBE
OVIE
ICSA
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The TIER is an 8-bit read/write register that controls permission/prohibition of interrupt requests.
The TIER is initialized to H'00 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
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Section 16 Timer X1
Bit 7⎯Enabling the Input Capture Interrupt A (ICIAE): This bit works to permit/prohibit
interrupt requests (ICIA) by the ICFA when the ICFA of the TCSRX is being set to 1.
Bit 7
ICIAE
Description
0
Prohibits interrupt requests (ICIA) by the ICFA
1
Permits interrupt requests (ICIA) by the ICFA
(Initial value)
Bit 6⎯Enabling the Input Capture Interrupt B (ICIBE): This bit works to permit/prohibit
interrupt requests (ICIB) by the ICFB when the ICFB of the TCSRX is being set to 1.
Bit 6
ICIBE
Description
0
Prohibits interrupt requests (ICIB) by the ICFB
1
Permits interrupt requests (ICIB) by the ICFB
(Initial value)
Bit 5⎯Enabling the Input Capture Interrupt C (ICICE): This bit works to permit/prohibit
interrupt requests (ICIC) by the ICFC when the ICFC of the TCSRX is being set to 1.
Bit 5
ICICE
Description
0
Prohibits interrupt requests (ICIC) by the ICFC
1
Permits interrupt requests (ICIC) by the ICFC
(Initial value)
Bit 4⎯Enabling the Input Capture Interrupt D (ICIDE): This bit works to permit/prohibit
interrupt requests (ICID) by the ICFD when the ICFD of the TCSRX is being set to 1.
Bit 4
ICIDE
Description
0
Prohibits interrupt requests (ICID) by the ICFD
1
Permits interrupt requests (ICID) by the ICFD
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(Initial value)
Section 16 Timer X1
Bit 3⎯Enabling the Output Comparing Interrupt A (OCIAE): This bit works to
permit/prohibit interrupt requests (OCIA) by the OCFA when the OCFA of the TCSRX is being
set to 1.
Bit 3
OCIAE
Description
0
Prohibits interrupt requests (OCIA) by the OCFA
1
Permits interrupt requests (OCIA) by the OCFA
(Initial value)
Bit 2⎯Enabling the Output Comparing Interrupt B (OCIBE): This bit works to
permit/prohibit interrupt requests (OCIB) by the OCFB when the OCFB of the TCSRX is being
set to 1.
Bit 2
OCIBE
Description
0
Prohibits interrupt requests (OCIB) by the OCFB
1
Permits interrupt requests (OCIB) by the OCFB
(Initial value)
Bit 1⎯Enabling the Timer Overflow Interrupt (OVIE): This bit works to permit/prohibit
interrupt requests (FOVI) by the OVF when the OVF of the TCSRX is being set to 1.
Bit 1
OVIE
Description
0
Prohibits interrupt requests (FOVI) by the OVF
1
Permits interrupt requests (FOVI) by the OVF
(Initial value)
Bit 0⎯Selecting the Input Capture A Signals (ICSA): This bit works to select the input capture
A signals.
Bit 0
ICSA
Description
0
Selects the FTIA pin for inputting of the input capture A signals
1
Selects the HSW for inputting of the input capture A signals
(Initial value)
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Section 16 Timer X1
16.2.5
Timer Control/Status Register X (TCSRX)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
ICFA
ICFB
ICFC
ICFD
OCFA
OCFB
OVF
CCLRA
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
Note: * Only 0 can be written to clear the flag for Bits 7 to 1.
The TCSRX is an 8-bit register which works to select counter clearing timing and to control
respective interrupt requesting signals. The TCSRX is initialized to H'00 when reset or under the
standby mode, watch mode, subsleep mode, module stop mode or subactive mode.
Meanwhile, as for the timing, see section 16.3, Operation.
The FTIA through FTID pins are for fixed inputs inside the LSI under the low power consumption
mode excluding the sleep mode. Consequently, when such shifts as active mode → low power
consumption mode → active mode are made, wrong edges may be detected depending on the pin
status or on the type of the detecting edge.
To avoid such error, clear the interrupt requesting flag once immediately after shifting to the active
mode from the low power consumption mode.
Bit 7⎯Input Capture Flag A (ICFA): This is a status flag indicating the fact that the value of
the FRC has been transferred to the ICRA by the input capture signals.
When the BUFEA of the TCRX is being set to 1, the ICFA indicates the status that the FRC value
has been transferred to the ICRA by the input capture signals and that the ICRA value before
being updated has been transferred to the ICRC.
This flag should be cleared by use of of the software. Such setting should only be made by use of
the hardware. It is not possible to make this setting using a software.
Bit 7
ICFA
Description
0
[Clearing condition]
(Initial value)
When 0 is written into the ICFA after reading the ICFA under the setting of ICFA = 1
1
[Setting condition]
When the value of the FRC has been transferred to the ICRA by the input capture
signals
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Section 16 Timer X1
Bit 6⎯Input Capture Flag B (ICFB): This status flag indicates the fact that the value of the
FRC has been transferred to the ICRB by the input capture signals.
When the BUFEB of the TCRX is being set to 1, the ICFB indicates the status that the FRC value
has been transferred to the ICRB by the input capture signals and that the ICRB value before being
updated has been transferred to the ICRC.
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make this setting using a software.
Bit 6
ICFB
Description
0
[Clearing condition]
(Initial value)
When 0 is written into the ICFB after reading the ICFB under the setting of ICFB = 1
1
[Setting condition]
When the value of the FRC has been transferred to the ICRB by the input capture
signals
Bit 5⎯Input Capture Flag C (ICFC): This status flag indicates the fact that the value of the
FRC has been transferred to the ICRC by the input capture signals.
When an input capture signal occurs while the BUFEA of the TCRX is being set to 1, although the
ICFC will be set out, data transference to the ICRC will not be performed.
Therefore, in buffer operation, the ICFC can be used as an external interrupt by setting the ICICE
bit to 1.
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make this setting using a software.
Bit 5
ICFC
Description
0
[Clearing condition]
(Initial value)
When 0 is written into the ICFC after reading the ICFC under the setting of ICFC = 1
1
[Setting condition]
When the input capture signal has occurred
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Section 16 Timer X1
Bit 4⎯Input Capture Flag D (ICFD): This status flag indicates the fact that the value of the
FRC has been transferred to the ICRD by the input capture signals.
When an input capture signal occurs while the BUFEB of the TCRX is being set to 1, although the
ICFD will be set out, data transference to the ICRD will not be performed.
Therefore, in buffer operation, the ICFD can be used as an external interrupt by setting the ICIDE
bit to 1.
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make this setting using a software.
Bit 4
ICFD
Description
0
[Clearing condition]
(Initial value)
When 0 is written into the ICFD after reading the ICFD under the setting of ICFD = 1
1
[Setting condition]
When the input capture signal has occurred
Bit 3⎯Output Comparing Flag A (OCFA): This status flag indicates the fact that the FRC and
the OCRA have come to a comparing match.
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make this setting using a software.
Bit 3
OCFA
Description
0
[Clearing condition]
(Initial value)
When 0 is written into the OCFA after reading the OCFA under the setting of OCFA =
1
1
[Setting condition]
When the FRC and the OCRA have come to the comparing match
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Section 16 Timer X1
Bit 2⎯Output Comparing Flag B (OCFB): This status flag indicates the fact that the FRC and
the OCRB have come to a comparing match.
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make this setting using a software.
Bit 2
OCFB
Description
0
[Clearing condition]
(Initial value)
When 0 is written into the OCFB after reading the OCFB under the setting of OCFB =
1
1
[Setting condition]
When the FRC and the OCRB have come to the comparing match
Bit 1⎯Timer Over Flow (OVF): This is a status flag indicating the fact that the FRC
overflowed. (H'FFFF → H'0000).
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make this setting using a software.
Bit 1
OVF
Description
0
[Clearing condition]
(Initial value)
When 0 is written into the OVF after reading the OVF under the setting of OVF = 1
1
[Setting condition]
When the FRC value has become H'FFFF → H'0000
Bit 0⎯Counter Clearing (CCLRA): This bit works to select if or not to clear the FRC by
occurrence of comparing match A (matching signal of the FRC and OCRA).
Bit 0
CCLRA
Description
0
Prohibits clearing of the FRC by occurrence of comparing match A
1
Permits clearing of the FRC by occurrence of comparing match A
(Initial value)
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Section 16 Timer X1
16.2.6
Timer Control Register X (TCRX)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
IEDGA
IEDGB
IEDGC
IEDGD
BUFEA
BUFEB
CKS1
CKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The TCRX is an 8-bit read/write register that selects the input capture signal edge, designates the
buffer operation, and selects the inputting clock for the FRC.
The TCRX is initialized to H'00 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
Bit 7⎯Input Capture Signal Edge Selection A (IEDGA): This bit works to select the rising
edge or falling edge of the input capture signal A (FTIA).
Bit 7
IEDGA
Description
0
Captures the falling edge of the input capture signal A
1
Captures the rising edge of the input capture signal A
(Initial value)
Bit 6⎯Input Capture Signal Edge Selection B (IEDGB): This bit works to select the rising
edge or falling edge of the input capture signal B (FTIB).
Bit 6
IEDGB
Description
0
Captures the falling edge of the input capture signal B
1
Captures the rising edge of the input capture signal B
(Initial value)
Bit 5⎯Input Capture Signal Edge Selection C (IEDGC): This bit works to select the rising
edge or falling edge of the input capture signal C (FTIC). However, when the DVCTL has been
selected as the signal for the input capture signal edge selection C, this bit will not influence the
operation.
Bit 5
IEDGC
Description
0
Captures the falling edge of the input capture signal C
1
Captures the rising edge of the input capture signal C
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(Initial value)
Section 16 Timer X1
Bit 4⎯Input Capture Signal Edge Selection D (IEDGD): This bit works to select the rising
edge or falling edge of the input capture signal D (FTID).
Bit 4
IEDGD
Description
0
Captures the falling edge of the input capture signal D
1
Captures the rising edge of the input capture signal D
(Initial value)
Bit 3⎯Buffer Enabling A (BUFEA): This bit works to select whether or not to use the ICRC as
the buffer register for the ICRA.
Bit 3
BUFEA
Description
0
Not using the ICRC as the buffer register for the ICRA
1
Using the ICRC as the buffer register for the ICRA
(Initial value)
Bit 2⎯Buffer Enabling B (BUFEB): This bit works to select whether or not to use the ICRD as
the buffer register for the ICRB.
Bit 2
BUFEB
Description
0
Not using the ICRD as the buffer register for the ICRB
1
Using the ICRD as the buffer register for the ICRB
(Initial value)
Bits 1 and 0⎯Clock Select (CKS1, CKS0): These bits work to select the inputting clock to the
FRC from among three types of internal clocks and the DVCFG.
The DVCFG is the edge detecting pulse selected by the CFG dividing timer.
Bit 1
Bit 0
CKS1
CKS0
Description
0
0
Internal clock: Counts at φ/4
0
1
Internal clock: Counts at φ/16
1
0
Internal clock: Counts at φ/64
1
1
DVCFG: The edge detecting pulse selected by the CFG dividing timer
(Initial value)
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Section 16 Timer X1
16.2.7
Timer Output Comparing Control Register (TOCR)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
ICSB
ICSC
ICSD
OCRS
OEA
OEB
OLVLA
OLVLB
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The TOCR is an 8-bit read/write register that select input capture signals and output comparing
output level, permits output comparing outputs, and controls switching over of the access of the
OCRA and OCRB. See section 16.2.4, Timer Interrupt Enabling Register (TIER) regarding the
input capture inputs A.
The TOCR is initialized to H'00 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
Bit 7⎯Selecting the Input Capture B Signals (ICSB): This bit works to select the input capture
B signals.
Bit 7
ICSB
Description
0
Selects the FTIB pin for inputting of the input capture B signals
1
Selects the VD as the input capture B signals
(Initial value)
Bit 6⎯Selecting the Input Capture C Signals (ICSC): This bit works to select the input capture
C signals. The DVCTL is the edge detecting pulse selected by the CTL dividing timer.
Bit 6
ICSC
Description
0
Selects the FTIC pin for inputting of the input capture C signals
1
Selects the DVCTL as the input capture C signals
(Initial value)
Bit 5⎯Selecting the Input Capture D Signals (ICSD): This bit works to select the input capture
D signals.
Bit 5
ICSD
Description
0
Selects the FTID pin for inputting of the input capture D signals
1
Selects the NHSW as the input capture D signals
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(Initial value)
Section 16 Timer X1
Bit 4⎯Selecting the Output Comparing Register (OCRS): The addresses of the OCRA and
OCRB are the same. The OCRS works to control which register to choose when reading/writing
this address. The choice will not influence the operation of the OCRA and OCRB.
Bit 4
OCRS
Description
0
Selects the OCRA register
1
Selects the OCRB register
(Initial value)
Bit 3⎯Enabling the Output A (OEA): This bit works to control the output comparing A signals.
Bit 3
OEA
Description
0
Prohibits the output comparing A signal outputs
1
Permits the output comparing A signal outputs
(Initial value)
Bit 2⎯Enabling the Output B (OEB): This bit works to control the output comparing B signals.
Bit 2
OEB
Description
0
Prohibits the output comparing B signal outputs
1
Permits the output comparing B signal outputs
(Initial value)
Bit 1⎯Output Level A (OLVLA): This bit works to select the output level to output through the
FTOA pin by use of the comparing match A (matching signal between the FRC and OCRA).
Bit 1
OLVLA
Description
0
Low level
1
High level
(Initial value)
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Section 16 Timer X1
Bit 0⎯Output Level B (OLVLB): This bit works to select the output level to output through the
FTOB pin by use of the comparing match B (matching signal between the FRC and OCRB).
Bit 0
OLVLB
Description
0
Low level
1
High level
16.2.8
(Initial value)
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The MSTPCR consists of twin 8-bit read/write registers that control the module stop mode.
When the MSTP10 bit is set to 1, the Timer X1 stops its operation at the ending point of the bus
cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode.
When reset, the MSTPCR is initialized to H'FFFF.
Bit 2⎯Module Stop (MSTP10): This bit works to designate the module stop mode for timer X1.
MSTPCRH
Bit 2
MSTP10
Description
0
Cancels the module stop mode of the Timer X1
1
Sets the module stop mode of the Timer X1
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(Initial value)
Section 16 Timer X1
16.3
Operation
16.3.1
Operation of Timer X1
• Output Comparing Operation
Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting clock
can be selected from among three different types of internal clocks or the external clock by
setting the CKS1 and CKS0 of the TCRX.
The contents of the FRC are always being compared with the OCRA and OCRB and, when the
value of these two match, the level set by the the OLVLA and OLVLB of the TOCR is output
through the FTOA pin and FTOB pin.
After resetting, 0 will be output through the FTOA and FTOB pins until the first compare
matching occurs.
Also, when the CCLRA of the TCSRX is being set to 1, the FRC will be cleared to H'0000
when the comparing match A occurs.
• Input Capturing Operation
Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting clock
can be selected from among three different types of internal clocks or the external clock by
setting the CKS1 and CKS0 of the TCRX.
The inputs are transferred to the IEDGA through IEDGD of the TCRX through the FTIA
through FTID pins and, at the same time, the ICFA through ICFD of the TCSRX are set to 1.
At this time, if the ICIAE through ICIED of the TIER are being set to 1, due interrupt request
will be issued to the CPU.
When the BUFEA and BUFEB of the TCRX are set to 1, the ICRC and ICRD work as the
buffer register, respectively, of the ICRA and ICRB. When the edge selected by setting the
IEDGA through IEDGD of the TCRX is input through the FTIA and FTIB pins, the value at
the time of the FRC is transferred to the ICRA and ICRB and, at the same time, the values of
the ICRA and ICRB before updating are transferred to the ICRC and ICRD. At this time, when
the ICFA and ICFB are being set to 1 and if the ICIAE and ICIBE of the TIER are being set to
1, due interrupt request will be issued to the CPU.
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Section 16 Timer X1
16.3.2
Counting Timing of the FRC
The FRC is counted up by the inputting clock. By setting the CKS1 and CKS0 of the TCRX, the
inputting clock can be selected from among three different types of clocks (φ/4, φ/16 and φ/64)
and the DVCFG.
• Internal Clock Operation
By setting the CKS1 and CKS0 bits of the TCRX, three types of internal clocks (φ/4, φ/16 and
φ/64), generated by dividing the system clock (φ) can be selected. Figure 16.3 shows the
timing chart.
φ
Internal clock
FRC input
clock
FRC
N−1
N
N+1
Figure 16.3 Count Timing for Internal Clock Operation
• DVCFG Clock Operation
By setting the CKS1 and CKS0 bits of the TCRX to 1, DVCFG clock input can be selected.
The DVCFG clock makes counting by use of the edge detecting pulse being selected by the
CFG dividing timer.
Figure 16.4 shows the timing chart.
φ
CFG
DVCFG
FRC input
clock
FRC
N
N+1
Figure 16.4 Count Timing for CFG Clock Operation
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Section 16 Timer X1
16.3.3
Output Comparing Signal Outputting Timing
When a comparing match occurs, the output level having been set by the OLVL of the TOCR is
output through the output comparing signal outputting pins (FTOA and FTOB).
Figure 16.5 shows the timing chart for the output comparing signal outputting A.
φ
FRC
N
OCRA
N
N+1
N+1
N
N
Comparing match
signal
↓ Clearing*
OLVLA
FTOA
Output comparing
signal outputting
A pin
Note: * Execution of the command is to be designated by the software.
Figure 16.5 Output Comparing Signal Outputting A Timing
16.3.4
FRC Clearing Timing
The FRC can be cleared when the comparing match A occurs. Figure 16.6 shows the timing chart.
φ
Comparing match
A signal
FRC
N
H' 0000
Figure 16.6 Clearing Timing by Occurrence of the Comparing Match A
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Section 16 Timer X1
16.3.5
Input Capture Signal Inputting Timing
• Input Capture Signal Inputting Timing
As for the input capture signal inputting, rising or falling edge is selected by settings of the
IEDGA through IEDGD bits of the TCRX.
Figure 16.7 shows the timing chart when the rising edge is selected (IEDGA through IEDGD =
1).
φ
Input capture signal
inputting pin
Input capture signal
Figure 16.7 Input Capture Signal Inputting Timing (under Normal State)
• Input Capture Signal Inputting Timing when Making Buffer Operation
Buffer operation can be made using the ICRC or ICRD as the buffer of the ICRA or ICRB.
Figure 16.8 shows the input capture signal inputting timing chart in case both of the rising and
falling edges are designated (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and IEDGC = 1),
using the ICRC as the buffer register for the ICRA (BUFEA = 1).
φ
FTIA
Input capture
signal
FRC
n
n+1
N
ICRA
M
n
n
N
ICRC
m
M
M
n
Figure 16.8 Input Capture Signal Inputting Timing Chart under the Buffer Mode
(under Normal State)
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Section 16 Timer X1
Even when the ICRC or ICRD is used as the buffer register, the input capture flag will be set up
corresponding to the designated edge change of respective input capture signals.
For example, when using the ICRC as the buffer register for the ICRA, when an edge change
having been designated by the IEDGC bit is detected with the input capture signals C and if the
ICIEC bit is duly set, an interrupt request will be issued.
However, in this case, the FRC value will not be transferred to the ICRC.
16.3.6
Input Capture Flag (ICFA through ICFD) Setting Up Timing
The input capture signal works to set the ICFA through ICFD to 1 and, simultaneously, the FRC
value is transferred to the corresponding ICRA through ICRD. Figure 16.9 shows the timing chart.
φ
Input capture
signal
ICFA to ICFD
FRC
N
ICRA to ICRD
N
Figure 16.9 ICFA through ICFD Setting Up Timing
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Section 16 Timer X1
16.3.7
Output Comparing Flag (OCFA and OCFB) Setting Up Timing
The OCFA and OCFB are being set to 1 by the comparing match signal being output when the
values of the OCRA, OCRB and FRC match. The comparing match signal is generated at the last
state of the value match (the timing of the FRC's updating the matching count reading).
After the values of the OCRA, OCRB and FRC match, up until the count up clock signal is
generated, the comparing match signal will not be issued. Figure 16.10 shows the OCFA and
OCFB setting timing chart.
φ
FRC
N
OCRA, OCRB
N
N+1
Comparing match
signal
OCFA, OCFB
Figure 16.10 OCF Setting Up Timing
16.3.8
Overflow Flag (CVF) Setting Up Timing
The OVF is set to when the FRC overflows (H'FFFF → H'0000). Figure 16.11 shows the timing
chart.
φ
FRC
H'FFFF
H'0000
Overflowing
signal
OVF
Figure 16.11 OVF Setting Up Timing
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Section 16 Timer X1
16.4
Operation Mode of Timer X1
Table 16.4 indicated below shows the operation mode of Timer X1.
Table 16.4 Operation Mode of Timer X1
Operation Mode Reset
Active
Sleep
Watch Subactive
Standby
Subsleep
Module
Stop
FRC
Reset
Functions
Functions
Reset
Reset
Reset
Reset
Reset
OCRA, OCRB
Reset
Functions
Functions
Reset
Reset
Reset
Reset
Reset
ICRA to ICRD
Reset
Functions
Functions
Reset
Reset
Reset
Reset
Reset
TIER
Reset
Functions
Functions
Reset
Reset
Reset
Reset
Reset
TCRX
Reset
Functions
Functions
Reset
Reset
Reset
Reset
Reset
TOCR
Reset
Functions
Functions
Reset
Reset
Reset
Reset
Reset
TCSRX
Reset
Functions
Functions
Reset
Reset
Reset
Reset
Reset
16.5
Interrupt Causes
Total seven interrupt causes exist with Timer X1, namely, ICIA through ICID, OCIA, OCIB and
FOVI. Table 16.5 lists the contents of interrupt causes. Interrupt requests can be permitted or
prohibited by setting interrupt enabling bits of the TIER. Also, independent vector addresses are
allocated to respective interrupt causes.
Table 16.5 Interrupt Causes of Timer X1
Abbreviations of the Interrupt Causes
Priority Degree
Contents
ICIA
Interrupt request by the ICFA
High
ICIB
Interrupt request by the ICFB
ICIC
Interrupt request by the ICFC
ICID
Interrupt request by the ICFD
OCIA
Interrupt request by the OCFA
OCIB
Interrupt request by the OCFB
FOVI
Interrupt request by the OVF
Low
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Section 16 Timer X1
16.6
Exemplary Uses of Timer X1
Figure 16.12 shows an example of outputting at optional phase difference of the pulses of the 50%
duty. For this setting, follow the procedures listed below.
1. Set the CCLRA bit of the TCSRX to 1.
2.
Each time a comparing match occurs, the OLVLA bit and the OLVLB bit are reversed by use
of the software.
H'FFFF
FRC
Clearing the
counter
OCRA
OCRB
H'0000
FTOA
FTOB
Figure 16.12 Pulse Outputting Example
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Section 16 Timer X1
16.7
Precautions when Using Timer X1
Pay great attention to the fact that the following competitions and operations occur during
operation of timer X1.
16.7.1
Competition between Writing and Clearing with the FRC
When a counter clearing signal is issued under the T2 state where the FRC is under the writing
cycle, writing into the FRC will not be effected and the priority will be given to clearing of the
FRC.
Figure 16.13 shows the timing chart.
Writing cycle with the FRC
T1
T2
φ
Address
FRC address
Internal writing
signal
Counter clearing
signal
FRC
N
H'0000
Figure 16.13 Competition between Writing and Clearing with the FRC
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Section 16 Timer X1
16.7.2
Competition between Writing and Counting Up with the FRC
When a counting up cause occurs under the T2 state where the FRC is under the writing cycle, the
counting up will not be effected and the priority will be given to count writing.
Figure 16.14 shows the timing chart.
Writing cycle with the FRC
T1
T2
φ
Address
FRC address
Internal writing
signal
Inputting clock
to the FRC
FRC
N
M
Writing data
Figure 16.14 Competition between Writing and Counting Up with the FRC
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Section 16 Timer X1
16.7.3
Competition between Writing and Comparing Match with the OCR
When a comparing match occurs under the T2 state where the OCRA and OCRB are under the
writing cycle, the priority will be given to writing of the OCR and the comparing match signal will
be prohibited.
Figure 16.15 shows the timing chart.
Writing cycle with the OCR
T1
T2
φ
Address
OCR address
Internal writing
signal
FRC
N
OCR
N
N+1
M
Writing data
Comparing match
signal
Will be prohibited
Figure 16.15 Competition between Writing and Comparing Match with the OCR
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Section 16 Timer X1
16.7.4
Changing Over the Internal Clocks and Counter Operations
Depending on the timing of changing over the internal clocks, the FRC may count up. Table 16.6
shows the relations between the timing of changing over the internal clocks (Re-writing of the
CKS1 and CKS0) and the FRC operations.
When using an internal clock, the counting clock is being generated detecting the falling edge of
the internal clock dividing the system clock (φ). For this reason, like Item No. 3 of table 16.6,
count clock signals are issued deeming the timing before the changeover as the falling edge to
have the FRC to count up.
Also, when changing over between an internal clock and the external clock, the FRC may count
up.
Table 16.6 Changing Over the Internal Clocks and the FRC Operation
No.
1
Rewriting Timing for
the CKS1 and CKS0
FRC Operation
Low → low level
changeover
Clock before
the changeover
Clock after
the changeover
Count
clock
FRC
N
N+1
Rewriting of the CKS1 and CKS0
2
Low → High level
changeover
Clock before
the changeover
Clock after
the changeover
Count
clock
FRC
N
N+1
N+2
Rewriting of the CKS1 and CKS0
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Section 16 Timer X1
No.
3
Rewriting Timing for
the CKS1 and CKS0
FRC Operation
High → low level
changeover
Clock before
the changeover
Clock after
the changeover
*
Count
clock
FRC
N
N+1
N+2
Rewriting of the CKS1 and CKS0
4
High → high level
changeover
Clock before
the changeover
Clock after
the changeover
Count
clock
FRC
N
N+1
N+2
Rewriting of the CKS1 and CKS0
Note:
*
The count clock signals are issued determining the changeover timing as the falling
edge to have the FRC to count up.
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Section 16 Timer X1
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Section 17 Watchdog Timer (WDT)
Section 17 Watchdog Timer (WDT)
17.1
Overview
This LSI has an on-chip watchdog timer with one channel (WDT) for monitoring system
operation. The WDT outputs an overflow signal if a system crash prevents the CPU from writing
to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an
internal reset signal or internal NMI interrupt signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer mode, an interval timer interrupt is generated each time the counter overflows.
17.1.1
Features
WDT features are listed below.
• Switchable between watchdog timer mode and interval timer mode
⎯ WOVI interrupt generation in interval timer mode
• Internal reset or internal interrupt generated when the timer counter overflows
⎯ Choice of internal reset or NMI interrupt generation in watchdog timer mode
• Choice of 8 counter input clocks
⎯ Maximum WDT interval: system clock period × 131072 × 256
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Section 17 Watchdog Timer (WDT)
17.1.2
Block Diagram
Figure 17.1 shows block diagram of WDT.
WOVI
(Interrupt request signal)
Internal NMI
interrupt request signal
Interrupt
control
Overflow
Clock
·
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
select
Reset
control
Internal reset signal*
WTCNT
WTCSR
Module bus
WDT
Legend:
WTCSR : Timer control/status register
WTCNT : Timer counter
Note: * The internal reset signal can be generated by means of a register setting.
Figure 17.1 Block Diagram of WDT
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Bus
interface
Internal bus
Internal clock
source
Section 17 Watchdog Timer (WDT)
17.1.3
Register Configuration
The WDT has two registers, as described in table 17.1. These registers control clock selection,
WDT mode switching, the reset signal, etc.
Table 17.1 WDT Registers
Address*
1
Abbrev.
R/W
Initial Value
2
Write*
Read
Watchdog timer
control/status register
WTCSR
3
R/ (W)*
H'00
H'FFBC
H'FFBC
Watchdog timer counter
WTCNT
R/W
H'00
H'FFBC
H'FFBD
System control register
SYSCR
R/W
H'09
H'FFE8
H'FFE8
Name
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 17.2.4, Notes on Register Access.
3. Only 0 can be written in bit 7, to clear the flag.
17.2
Register Descriptions
17.2.1
Watchdog Timer Counter (WTCNT)
Bit :
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W :
WTCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in WTCSR, WTCNT starts counting pulses generated from the
internal clock source selected by bits CKS2 to CKS0 in WTCSR. When the count overflows
(changes from H'FF to H'00), the OVF flag in WTCSR is set to 1.
WTCNT is initialized to H'00 by a reset, or when the TME bit is cleared to 0.
Note: * WTCNT is write-protected by a password to prevent accidental overwriting. For details
see section 17.2.4, Notes on Register Access.
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Section 17 Watchdog Timer (WDT)
17.2.2
Watchdog Timer Control/Status Register (WTCSR)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
OVF
WT/IT
TME
—
RST/NMI
CKS2
CKS1
CKS0
0
0
0
0
0
0
0
0
R/(W)*
R/W
R/W
—
R/W
R/W
R/W
R/W
Note: * Only 0 can be written to clear the flag.
WTCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to
be input to WTCNT, and the timer mode.
WTCSR is initialized to H'00 by a reset.
Note: * WTCSR is write-protected by a password to prevent accidental overwriting. For details
see section 17.2.4, Notes on Register Access.
Bit 7⎯Overflow Flag (OVF): A status flag that indicates that WTCNT has overflowed from
H'FF to H'00.
Bit 7
OVF
Description
0
[Clearing conditions]
(Initial value)
1. Write 0 in the TME bit
2. Read WTCSR when OVF = 1*, then write 0 in OVF
1
[Setting condition]
When WTCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset
Note:
*
When OVF is polled and the interval timer interrupt is disabled, OVF=1 must be read at
least twice.
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Section 17 Watchdog Timer (WDT)
Bit 6⎯Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
(WOVI) when WTCNT overflows. If used as a watchdog timer, the WDT generates a reset or
NMI interrupt when WTCNT overflows.
Bit 6
WT/IT
Description
0
Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when
WTCNT overflows
(Initial value)
1
Watchdog timer mode: Sends the CPU a reset or NMI interrupt request when
WTCNT overflows
Bit 5⎯Timer Enable (TME): Selects whether WTCNT runs or is halted.
Bit 5
TME
Description
0
WTCNT is initialized to H'00 and halted
1
WTCNT counts
(Initial value)
Bit 4⎯Reserved: This bit should not be set to 1.
Bit 3⎯Reset or NMI (RST/NMI): Specifies whether an internal reset or NMI interrupt is
requested on WTCNT overflow in watchdog timer mode.
Bit 3
RST/NMI
Description
0
An NMI interrupt request is generated
1
An internal reset request is generated
(Initial value)
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Section 17 Watchdog Timer (WDT)
Bits 2 to 0⎯Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source,
obtained by dividing the system clock (φ) for input to WTCNT.
WDT Input Clock Selection
Bit 2
Bit 1
Bit 0
Description
CSK2
CSK1
CSK0
Clock
Overflow Period* (when φ = 10 MHz)
0
0
0
φ/2 (Initial value)
51.2 μs
1
φ/64
1.6 ms
0
φ/128
3.3 ms
1
φ/512
13.1 ms
0
φ/2048
52.4 ms
1
φ/8192
209.7 ms
0
φ/32768
838.9 ms
1
φ/131072
3.36 s
1
1
0
1
Note:
17.2.3
*
The overflow period is the time from when WTCNT starts counting up from H'00 until
overflow occurs.
System Control Register (SYSCR)
Bit :
7
6
5
4
3
2
1
0
—
—
INTM1
INTM0
XRST
—
—
—
Initial value :
0
0
0
0
1
0
0
1
R/W :
—
—
R
R/W
R
—
—
—
Only bit 3 is described here. For details on functions not related to the watchdog timer, see
sections 3.2.2 and 6.2.1, System Control Register (SYSCR), and the descriptions of the relevant
modules.
Bit 3⎯External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a
read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow.
Bit 3
XRST
Description
0
Reset is generated by watchdog timer overflow
1
Reset is generated by external reset input
Rev.2.00 Jan. 15, 2007 page 350 of 1174
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(Initial value)
Section 17 Watchdog Timer (WDT)
17.2.4
Notes on Register Access
The watchdog timer's WTCNT and WTCSR registers differ from other registers in being more
difficult to write to. The procedures for writing to and reading these registers are given below.
• Writing to WTCNT and WTCSR
These registers must be written to by a word transfer instruction. They cannot be written to
with byte transfer instructions.
Figure 17.2 shows the format of data written to WTCNT and WTCSR. WTCNT and WTCSR
both have the same write address. For a write to WTCNT, the upper byte of the written word
must contain H'5A and the lower byte must contain the write data. For a write to WTCSR, the
upper byte of the written word must contain H'A5 and the lower byte must contain the write
data. This transfers the write data from the lower byte to WTCNT or WTCSR.
<WTCNT write>
15
Address : H'FFBC
8 7
H'5A
0
0
Write data
<WTCSR write>
15
Address : H'FFBC
0
8 7
H'A5
0
Write data
Figure 17.2 Format of Data Written to WTCNT and WTCSR
• Reading WTCNT and WTCSR
These registers are read in the same way as other registers. The read addresses are H'FFBC for
WTCSR, and H'FFBD for WTCNT.
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Section 17 Watchdog Timer (WDT)
17.3
Operation
17.3.1
Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/IT and TME bits in WTCSR to 1. Software
must prevent WTCNT overflows by rewriting the WTCNT value (normally by writing H'00)
before overflow occurs. This ensures that WTCNT does not overflow while the system is
operating normally. If WTCNT overflows without being rewritten because of a system crash or
other error, the chip is reset, or an NMI interrupt is generated, for 518 system clock periods (518
φ). This is illustrated in figure 17.3.
An internal reset request from the watchdog timer and reset input from the RES pin are handled
via the same vector. The reset source can be identified from the value of the XRST bit in SYSCR.
If a reset caused by an input signal from the RES pin and a reset caused by WDT overflow occur
simultaneously, the RES pin reset has priority, and the XRST bit in SYSCR is set to 1.
WTCNT value
Overflow
H'FF
Time
H'00
WT/IT = 1
TME = 1
H'00 written
to WTCNT
OVF = 1*
WT/IT = 1 H'00 written
TME = 1 to WTCNT
Internal reset
generated
Internal reset
signal
518 system clock period
Legend:
WT/IT : Timer mode select bit
TME : Timer enable bit
Note: * Cleared to 0 by an internal reset when OVF is set to 1. XRST is cleared to 0.
Figure 17.3 Operation in Watchdog Timer Mode (when Reset)
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Section 17 Watchdog Timer (WDT)
17.3.2
Interval Timer Operation
To use the WDT as an interval timer, clear the WT/IT bit in WTCSR to 0 and set the TME bit to
1. An interval timer interrupt (WOVI) is generated each time WTCNT overflows, provided that
the WDT is operating as an interval timer, as shown in figure 17.4. This function can be used to
generate interrupt requests at regular intervals.
WTCNT value
Overflow
H'FF
Overflow
Overflow
Overflow
Time
H'00
WT/IT = 0
TME = 1
WOVI
WOVI
WOVI
WOVI
WOVI : Interval timer interrupt request generation
Figure 17.4 Operation in Interval Timer Mode
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Section 17 Watchdog Timer (WDT)
17.3.3
Timing of Setting of Overflow Flag (OVF)
The OVF bit in WTCSR is set to 1 if WTCNT overflows during interval timer operation. At the
same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 17.5.
If NMI request generation is selected in watchdog timer mode, when WTCNT overflows the OVF
bit in WTCSR is set to 1 and at the same time an NMI interrupt is requested.
CK
WTCNT
H'FF
H'00
Overflow signal
(internal signal)
OVF
Figure 17.5 Timing of OVF Setting
17.4
Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in WTCSR. OVF must
be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is
selected in watchdog timer mode, an overflow generates an NMI interrupt request.
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Section 17 Watchdog Timer (WDT)
17.5
Usage Notes
17.5.1
Contention between Watchdog Timer Counter (WTCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a WTCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 17.6 shows this operation.
WTCNT write cycle
T2
T1
Internal φ
Internal address
Internal write
signal
WTCNT input
clock
WTCNT
N
M
Counter write data
Figure 17.6 Contention between WTCNT Write and Increment
17.5.2
Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in WTCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
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Section 17 Watchdog Timer (WDT)
17.5.3
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, correct operation cannot be guaranteed. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
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Section 18 8-Bit PWM
Section 18 8-Bit PWM
18.1
Overview
The 8-bit PWM incorporates 4 channels of the duty control method (H8S/2197S and H8S/2196S:
2 channels). Its outputs can be used to control a reel motor or loading motor.
18.1.1
Features
• Conversion period: 256-state
• Duty control method
18.1.2
Block Diagram
Figure 18.1 shows a block diagram of the 8-bit PWM (1 channel).
Internal data bus
PW8CR
PWMn
Polarity
specification
PWRn
R
Match signal
Comparator
Q
S
OVF
27
Free-running counter (FRC)
20
φ
Legend:
PWRn
: 8-bit PWM data register n
PW8CR : 8-bit PWM control register
PWMn
: 8-bit PWM square-wave output pin n
OVF
: Overflow signal from FRC lower 8-bit
Note:
n = 3 to 0 (H8S/2197S and H8S/2196S: n = 1 and 0)
Figure 18.1 Block Diagram of 8-Bit PWM (1 channel)
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Section 18 8-Bit PWM
18.1.3
Pin Configuration
Table 18.1 shows the 8-bit PWM pin configuration.
Table 18.1 Pin Configuration
Name
Abbrev.
I/O
Function
8-bit PWM square-wave output pin 0
PWM0
Output
8-bit PWM square-wave output 0
8-bit PWM square-wave output pin 1
PWM1
Output
8-bit PWM square-wave output 1
8-bit PWM square-wave output pin 2
PWM2
Output
8-bit PWM square-wave output 2
8-bit PWM square-wave output pin 3
PWM3
Output
8-bit PWM square-wave output 3
18.1.4
Register Configuration
Table 18.2 shows the 8-bit PWM register configuration.
Table 18.2 8-Bit PWM Registers
Name
Abbrev.
R/W
Size
Initial Value
Address*
8-bit PWM data register 0
PWR0
W
Byte
H'00
H'D126
8-bit PWM data register 1
PWR1
W
Byte
H'00
H'D127
8-bit PWM data register 2
PWR2
W
Byte
H'00
H'D128
8-bit PWM data register 3
PWR3
W
Byte
H'00
H'D129
8-bit PWM control register
PW8CR
R/W
Byte
H'F0
H'D12A
Port mode register 3
PMR3
R/W
Byte
H'00
H'FFD0
Note:
*
Lower 16 bits of the address.
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Section 18 8-Bit PWM
18.2
Register Descriptions
18.2.1
8-bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3)
PWR0
Bit :
Initial value :
R/W :
7
PW07
6
PW06
5
PW05
4
PW04
3
PW03
2
PW02
1
PW01
0
PW00
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
7
PW17
6
PW16
5
PW15
4
PW14
3
PW13
2
PW12
1
PW11
0
PW10
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
7
PW27
6
PW26
5
PW25
4
PW24
3
PW23
2
PW22
1
PW21
0
PW20
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
7
PW37
6
PW36
5
PW35
4
PW34
3
PW33
2
PW32
1
PW31
0
PW30
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
PWR1
Bit :
Initial value :
R/W :
PWR2
Bit :
Initial value :
R/W :
PWR3
Bit :
Initial value :
R/W :
8-bit PWM data registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3) control the duty cycle at 8bit PWM pins. The data written in PWR0, PWR1, PWR2 and PWR3 correspond to the high-level
width of one PWM output waveform cycle (256 states).
When data is set in PWR0, PWR1, PWR2 and PWR3, the contents of the data are latched in the
PWM waveform generators, updating the PWM waveform generation data.
PWR0, PWR1, PWR2 and PWR3 are 8-bit write-only registers. When read, all bits are always
read as 1.
PWR0, PWR1, PWR2 and PWR3 are initialized to H'00 by a reset.
Note: The H8S/2197S and H8S/2196S do not have PWR2 and PWR3.
Rev.2.00 Jan. 15, 2007 page 359 of 1174
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Section 18 8-Bit PWM
18.2.2
8-bit PWM Control Register (PW8CR)
Bit :
7
—
6
—
5
—
4
—
3
PWC3
2
PWC2
1
PWC1
0
PWC0
Initial value :
R/W :
1
—
1
—
1
—
1
—
0
R/W
0
R/W
0
R/W
0
R/W
The 8-bit PWM control register (PW8CR) is an 8-bit readable/writable register that controls PWM
functions. PW8CR is initialized to H'F0 by a reset.
Bits 7 to 4⎯Reserved: These bits cannot be modified and are always read as 1.
Bits 3 to 0⎯Output Polarity Select (PWC3 to PWC0): These bits select the output polarity of
PWMn pin between positive or negative (reverse).
Bit n
PWCn
Description
0
PWMn pin output has positive polarity
1
PWMn pin output has negative polarity
(Initial value)
Note: n = 3 to 0 (H8S/2197S and H8S/2196S: n = 1 and 0).
18.2.3
Port Mode Register 3 (PMR3)
Bit :
Initial value :
R/W :
7
PMR37
6
PMR36
5
PMR35
4
PMR34
3
PMR33
2
PMR32
1
PMR31
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PMR30
0
R/W
The port mode register 3 (PMR3) controls function switching of each pin in the port 3. Switching
is specified for each bit.
The PMR3 is a 8-bit readable/writable register and is initialized to H'00 by a reset.
For bits other than 5 to 2, see section 10.5, Port 3.
Rev.2.00 Jan. 15, 2007 page 360 of 1174
REJ09B0329-0200
Section 18 8-Bit PWM
Bits 5 to 2⎯P35/PWM3 to P32/PWM0 Pin Switching (PMR35 to PMR32): These bits set
whether the P3n/PWMm pin is used as I/O pin or it is used as 8-bit PWM output PWMm pin.
Bit n
PMR3n
Description
0
P3n/PMWm pin functions as P3n I/O pin
1
P3n/PMWm pin functions as PWMm output pin
(Initial value)
Note: n = 5 to 2, m = 3 to 0. The H8S/2197S and H8S/2196S do not have PWM2 and PWM3 pin
functions.
18.2.4
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode.
When MSTP4 bit is set to 1, the 8-bit PWM stops its operation upon completion of the bus cycle
and transits to the module stop mode. For details, see section 4.5, Module Stop Mode.
The MSTPCR is initialized to H'FFFF by a reset.
Bit 4⎯Module Stop (MSTP4): This bit sets the module stop mode of the 8-bit PWM.
MSTPCRL
Bit 4
MSTP4
Description
0
8-bit PWM module stop mode is released
1
8-bit PWM module stop mode is set
(Initial value)
Rev.2.00 Jan. 15, 2007 page 361 of 1174
REJ09B0329-0200
Section 18 8-Bit PWM
18.3
8-Bit PWM Operation
The 8-bit PWM outputs PWM pulses having a cycle length of 256 states and a pulse width
determined by the data registers (PWR).
The output PWM pulse can be converted to a DC voltage through integration in a low-pass filter.
Figure 18.2 shows the output waveform example of 8-bit PWM. The pulse width (Twidth) can be
obtained by the following expression:
Twidth = (1/φ) × (PWR setting value)
FRC lower
8-bit value
H'FF
PWRn setting
value
H'00
PWRn pin
output
(Positive
polarity)
(n = 3 to 0)
Pulse width
T width
Pulse width
T width
T width
T width
(Negative
polarity)
Pulse cycle
(256 states)
Pulse cycle
(256 states)
Figure 18.2 8-bit PWM Output Waveform (Example)
Rev.2.00 Jan. 15, 2007 page 362 of 1174
REJ09B0329-0200
Section 19 12-Bit PWM
Section 19 12-Bit PWM
19.1
Overview
The 12-bit PWM incorporates 2 channels of the pulse pitch control method and functions as the
drum and capstan motor controller.
19.1.1
Features
Two on-chip 12-bit PWM signal generators are provided to control motors. These PWMs use the
pulse-pitch control method (periodically overriding part of the output). This reduces lowfrequency components in the pulse output, enabling a quick response without increasing the clock
frequency. The pitch of the PWM signal is modified in response to error data (representing lead or
lag in relation to a preset speed and phase).
Rev.2.00 Jan. 15, 2007 page 363 of 1174
REJ09B0329-0200
Section 19 12-Bit PWM
19.1.2
Block Diagram
Figure 19.1 shows a block diagram of the 12-bit PWM (1 channel). The PWM signal is generated
by combining quantizing pulses from a 12-bit pulse generator with quantizing pulses derived from
the contents of a data register. Low-frequency components are reduced because the two quantizing
pulses have different frequencies. The error data is represented by an unsigned 12-bit binary
number.
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
Counter
Pulse generator
Output control circuit
CAPPWM
or
DRMPWM
PWM data register
PWM control register
Error data
Internal data bus
Digital filter
circuit
DFUCR*
Legend:
CAPPWM
: Capstan mix pin
DRMPWM
: Drum mix pin
Note: * Refer to section 26, Servo Circuits.
Figure 19.1 Block Diagram of 12-Bit PWM (1 channel)
Rev.2.00 Jan. 15, 2007 page 364 of 1174
REJ09B0329-0200
PTON CP/DP
Section 19 12-Bit PWM
19.1.3
Pin Configuration
Table 19.1 shows the 12-bit PWM pin configuration.
Table 19.1 Pin Configuration
Name
Abbrev.
I/O
Function
Capstan mix
CAPPWM
Output
12-bit PWM square-wave output
Drum mix
DRMPWM
19.1.4
Register Configuration
Table 19.2 shows the 12-bit PWM register configuration.
Table 19.2 12-Bit PWM Registers
Name
Abbrev.
R/W
Size
Initial Value
Address*
12-bit PWM control register
CPWCR
W
Byte
H'42
H'D07B
DPWCR
W
Byte
H'42
H'D07A
CPWDR
R/W
Word
H'F000
H'D07C
DPWDR
R/W
Word
H'F000
H'D078
12-bit PWM data register
Note:
*
Lower 16 bits of the address.
Rev.2.00 Jan. 15, 2007 page 365 of 1174
REJ09B0329-0200
Section 19 12-Bit PWM
19.2
Register Descriptions
19.2.1
12-Bit PWM Control Registers (CPWCR, DPWCR)
CPWCR
Bit :
Initial value :
R/W :
7
CPOL
6
CDC
5
CHiZ
4
CH/L
3
CSF/DF
2
CCK2
1
CCK1
0
CCK0
0
W
1
W
0
W
0
W
0
W
0
W
1
W
0
W
DPWCR
Bit :
Initial value :
R/W :
7
DPOL
6
DDC
5
DHiZ
4
DH/L
3
DSF/DF
2
DCK2
1
DCK1
0
DCK0
0
W
1
W
0
W
0
W
0
W
0
W
1
W
0
W
CPWCR is the PWM output control register for the capstan motor. DPWCR is the PWM output
control register for the drum motor. Both are 8-bit writable registers.
CPWCR and DPWCR are initialized to H'42 by a reset, or when in a power-down state except for
active medium-speed mode.
Bit 7⎯Polarity Invert (POL): This bit can invert the polarity of the modulated PWM signal for
noise suppression and other purposes. This bit is invalid when fixed output is selected (when bit
DC is set to 1).
Bit 7
POL
Description
0
Output with positive polarity
1
Output with inverted polarity
(Initial value)
Bit 6⎯Output Select (DC): Selects either PWM modulated output, or fixed output controlled by
the pin output bits (bits 5 and 4).
Rev.2.00 Jan. 15, 2007 page 366 of 1174
REJ09B0329-0200
Section 19 12-Bit PWM
Bits 5 and 4⎯PWM Pin Output (Hi-Z, H/L): When bit DC is set to 1, the 12-bit PWM output
pins (CAPPWM, DRMPWM) output a value determined by the Hi-Z and H/L bits. The output is
not affected by bit POL.
In power-down modes, the 12-bit PWM circuit and pin statuses are retained. Before making a
transition to a power-down mode, first set bits 6 (DC), 5 (Hi-Z), and 4 (H/L) of the 12-bit PWM
control registers (CPWCR and DPWCR) to select a fixed output level. Choose one of the
following settings:
Bit 6
Bit 5
Bit 4
DC
Hi-Z
H/L
Output state
1
0
0
Low output
1
High output
1
*
High-impedance
*
*
Modulation signal output
0
(Initial value)
Legend: * Don't care
Bit 3⎯Output Data Select (SF/DF): Selects whether the data to be converted to PWM output is
taken from the data register or from the digital filter circuit.
Bit 3
SF/DF
Description
0
Modulation by error data from the digital filter circuit
1
Modulation by error data written in the data register
(Initial value)
Note: When PWMs output data from the digital filter circuit, the data consisting of the speed and
phase filtering results are modulated by PWMs and output from the CAPPWM and
DRMPWM pins. However, it is possible to output only drum phase filter results from
CAPPWM pin and only capstan phase filter result from DRMPWM pin, by DFUCR settings
of the digital filter circuit. See section 26.11, Digital Filters.
Rev.2.00 Jan. 15, 2007 page 367 of 1174
REJ09B0329-0200
Section 19 12-Bit PWM
Bits 2 to 0⎯Carrier Frequency Select (CK2 to CK0): Selects the carrier frequency of the PWM
modulated signal. Do not set them to 111.
Bit 2
Bit 1
Bit 0
CK2
CK1
CK0
Description
0
0
0
φ2
1
φ4
0
φ8
1
φ16
1
1
0
1
19.2.2
(Initial value)
0
φ32
1
φ64
0
φ128
1
(Do not set)
12-Bit PWM Data Registers (DPWDR, CPWDR)
CPWDR
Bit :
Initial value :
R/W :
15
14
13
12
—
—
—
—
11
10
9
8
7
6
5
4
3
2
1
0
CPWDR11 CPWDR10 CPWDR9 CPWDR8 CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11
10
9
8
7
6
5
4
3
DPWDR
Bit : 15
14
13
12
—
—
—
—
Initial value : 1
R/W : —
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
1
0
DPWDR11 DPWDR10 DPWDR9 DPWDR8 DPWDR7 DPWDR6 DPWDR5 DPWDR4 DPWDR3 DPWDR2 DPWDR1 DPWDR0
The 12-bit PWM data registers (DPWDR and CPWDR) are 12-bit readable/writable registers in
which the data to be converted to PWM output is written.
The data in these registers is converted to PWM output only when bit SF/DF of the corresponding
control register is set to 1. When the SF/DF bit is 0, the error data from the digital filter circuit is
written in the data register, and then modulated by PWM. At this time, the error data from the
digital filter circuit can be monitored by reading the data register.
These registers can be accessed by word only, and cannot be accessed by byte. Byte access gives
unassured results.
Rev.2.00 Jan. 15, 2007 page 368 of 1174
REJ09B0329-0200
Section 19 12-Bit PWM
Both registers are initialized to H'F000 by a reset or in a power-down state except for active
medium speed mode.
19.2.3
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode.
When MSTP1 bit is set to 1, the 12-bit PWM stops its operation upon completion of the bus cycle
and transits to the module stop mode. For details, see section 4.5, Module Stop Mode.
The MSTPCR is initialized to H'FFFF by a reset.
Bit 1⎯Module Stop (MSTP1): This bit sets the module stop mode of the 12-bit PWM.
MSTPCRL
Bit 1
MSTP1
Description
0
12-bit PWM and servo circuit module stop mode is released
1
12-bit PWM and servo circuit module stop mode is set
(Initial value)
Rev.2.00 Jan. 15, 2007 page 369 of 1174
REJ09B0329-0200
Section 19 12-Bit PWM
19.3
Operation
19.3.1
Output Waveform
The PWM signal generator combines the error data with the output from an internal pulse
generator to produce a pulse-width modulated signal.
When Vcc/2 is set as the reference value, the following conditions apply:
1. When the motor is running at the correct speed and phase, the PWM signal is output with a
50% duty cycle.
2. When the motor is running behind the correct speed or phase, it is corrected by periodically
holding part of the PWM signal low. The part held low depends on the size of the error.
3. When the motor is running ahead of the correct speed or phase, it is corrected by periodically
holding part of the PWM signal high. The part held high depends on the size of the error.
When the motor is running at the correct speed and phase, the error data is a 12-bit value
representing 1/2 (1000 0000 0000), and the PWM output has the same frequency as the selected
division clock.
After the error data has been converted into a PWM signal, the PWM signal can be smoothed into
a DC voltage by an external low-pass filter (LPF). The smoothe error data can be used to control
the motor.
Figure 19.2 shows sample waveform outputs.
The 12-bit PWM pin outputs a low-level signal upon reset, in power-down mode or at modulestop.
Rev.2.00 Jan. 15, 2007 page 370 of 1174
REJ09B0329-0200
C13
C12
C11
C10
PWM data register
Pwr3 2 1 0
"L"
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Corresponds to Pwr0 = 1
Corresponds to Pwr1 = 1
Corresponds to Pwr2 = 1
Pulse Generator
Corresponds to Pwr3 = 1
Counter
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 1
2
3
4
5
6
7
8
9 10 11 12
Section 19 12-Bit PWM
Figure 19.2 Sample Waveform Output by 12-Bit PWM (4 Bits)
Rev.2.00 Jan. 15, 2007 page 371 of 1174
REJ09B0329-0200
Section 19 12-Bit PWM
Rev.2.00 Jan. 15, 2007 page 372 of 1174
REJ09B0329-0200
Section 20 14-Bit PWM
Section 20 14-Bit PWM
Note: The 14-Bit PWM is not (incorporated in) provided for the H8S/2197S and H8S/2196S.
20.1
Overview
The 14-bit PWM is a pulse division type PWM that can be used for electronic tuner control, etc.
20.1.1
Features
Features of the 14-bit PWM are given below:
• Choice of two conversion periods
A conversion period of 32768/φ with a minimum modulation width of 2/φ, or a conversion
period of 16384/φ with a minimum modulation width of 1/φ, can be selected.
• Pulse division method for less ripple
Rev.2.00 Jan. 15, 2007 page 373 of 1174
REJ09B0329-0200
Section 20 14-Bit PWM
20.1.2
Block Diagram
Figure 20.1 shows a block diagram of the 14-bit PWM.
Internal data bus
PWCR
PWDRL
PWDRU
φ/4
PWM waveform
generator
φ/2
PWM14
Legend:
PWCR : PWM control register
PWDRL : PWM data register L
PWDRU: PWM data register U
PWM14 : PWM14 output pin
Figure 20.1 Block Diagram of 14-Bit PWM
20.1.3
Pin Configuration
Table 20.1 shows the 14-bit PWM pin configuration.
Table 20.1 Pin Configuration
Name
Abbrev.
I/O
Function
PWM 14-bit square-wave output pin
PWM14*
Output
14-bit PWM square-wave output
Note:
*
This pin also functions as P40 general I/O pin. When using this pin, set the pin function
by the port mode register 4 (PMR4). For details, see section 10.6, Port 4.
Rev.2.00 Jan. 15, 2007 page 374 of 1174
REJ09B0329-0200
Section 20 14-Bit PWM
20.1.4
Register Configuration
Table 20.2 shows the 14-bit PWM register configuration.
Table 20.2 14-Bit PWM Registers
Name
Abbrev.
R/W
Size
Initial Value
Address*
PWM control register
PWCR
R/W
Byte
H'FE
H'D122
PWM data register U
PWDRU
W
Byte
H'C0
H'D121
PWM data register L
PWDRL
W
Byte
H'00
H'D120
Note:
Lower 16 bits of the address.
*
20.2
Register Descriptions
20.2.1
PWM Control Register (PWCR)
Bit :
7
—
6
—
5
—
4
—
3
—
2
—
1
—
0
PWCR0
Initial value :
R/W :
1
—
1
—
1
—
1
—
1
—
1
—
1
—
0
R/W
The PWM control register (PWCR) is an 8-bit read/write register that controls the 14-bit PWM
functions. PWCR is initialized to H'FE by a reset.
Bits 7 to 1⎯Reserved: These bits cannot be modified and are always read as 1.
Bit 0⎯Clock Select (PWCR0): Selects the clock supplied to the 14-bit PWM.
Bit 0
PWCR0
Description
0
The input clock is φ/2 (tφ = 2/φ)
(Initial value)
The conversion period is 16384/φ, with a minimum modulation width of 1/φ
1
The input clock is φ/4 (tφ = 4/φ)
The conversion period is 32768/φ, with a minimum modulation width of 2/φ
Note: t/φ: Period of PWM clock input
Rev.2.00 Jan. 15, 2007 page 375 of 1174
REJ09B0329-0200
Section 20 14-Bit PWM
20.2.2
PWM Data Registers U and L (PWDRU, PWDRL)
PWDRU
Bit :
7
—
6
—
Initial value :
R/W :
1
—
1
—
5
4
3
2
1
0
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
0
W
0
W
0
W
0
W
0
W
0
W
PWDRL
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
PWM data registers U and L (PWDRU and PWDRL) indicate high level width in one PWM
waveform cycle.
PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU
and the lower 8 bits to PWDRL. The value written in PWDRU and PWDRL gives the total highlevel width of one PWM waveform cycle. Both PWDRU and PWDRL are accessible by byte
access only. Word access gives unassured results.
When 14-bit data is written in PWDRU and PWDRL, the contents are latched in the PWM
waveform generator and the PWM waveform generation data is updated. When writing the 14-bit
data, follow these steps:
1. Write the lower 8 bits to PWDRL.
2. Write the upper 6 bits to PWDRU.
Write the data first to PWDRL and then to PWDRU.
PWDRU and PWDRL are write-only registers. When read, all bits always read 1.
PWDRU and PWDRL are initialized to H'C000 by a reset.
Rev.2.00 Jan. 15, 2007 page 376 of 1174
REJ09B0329-0200
Section 20 14-Bit PWM
20.2.3
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The module stop control register (MSTPCR) consists of two 8-bit readable/writable registers that
control the module stop mode functions.
When the MSTP5 bit is set to 1, the 14-bit PWM operation stops at the end of the bus cycle and a
transition is made to module stop mode. For details, see section 4.5, Module Stop Mode.
MSTPCR is initialized to H'FFFF by a reset.
Bit 5⎯Module Stop (MSTP5): Specifies the module stop mode of the 14-bit PWM.
MSTPCRL
Bit 5
MSTP5
Description
0
14-bit PWM module stop mode is released
1
14-bit PWM module stop mode is set
(Initial value)
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Section 20 14-Bit PWM
20.3
14-Bit PWM Operation
When using the 14-bit PWM, set the registers in this sequence:
1. Set bit PWM40 to 1 in port mode register 4 (PMR4) so that pin P40/PWM14 is designated for
PWM output.
2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either
32768/φ (PWCR0 = 1) or 16384/φ (PWCR0 = 0).
3. Set the output waveform data in PWM data registers U and L (PWDRU, PWDRL). Be sure to
write byte data first to PWDRL and then to PWDRU. When the data is written in PWDRU, the
contents of these registers are latched in the PWM waveform generator, and the PWM
waveform generation data is updated in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 20.2. The total high-level width
during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be
expressed as follows:
TH = (data value in PWDRU and PWDRL + 64) × tφ/2
where to is the period of PWM clock input: 2/φ (bit PWCR0 = 0) or 4/φ (bit PWCR0 = 1).
If the data value in PWDRU and PWDRL is from H'3FC0 to H'3FFF, the PWM output stays high.
When the data value is H'C000, TH is calculated as follows:
TH = 64 × tφ/2 = 32 ⋅ tφ
1 conversion period
t f1
t H1
t f2
t H2
t f63
t H3
t H63
t f64
t H64
T H = t H1 + t H2 + t H3 + ... + t H64
t f1 = t f2 = t f3 = ... = t f64
Figure 20.2 Waveform Output by 14-Bit PWM
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Section 21 Prescalar Unit
Section 21 Prescalar Unit
21.1
Overview
The prescalar unit (PSU) has a 18-bit free running counter (FRC) that uses φ as a clock source and
a 5-bit counter that uses φW as a clock source.
21.1.1
Features
• Prescalar S (PSS)
Generates frequency division clocks that are input to peripheral functions.
• Prescalar W (PSW)
When a timer A is used as a clock time base, the PSW frequency-divides subclocks and
generates input clocks.
• Stable oscillation wait time count
During the return from the low power consumption mode excluding the sleep mode, the FRC
counts the stable oscillation wait time.
• 8-bit PWM
The lower 8 bits of the FRC is used as 8-bit PWM cycle and duty cycle generation counters.
(Conversion cycle: 256 states)
• 8-bit input capture by IC pins
Catches the 8 bits of 2 to 2 of the FRC according to the edge of the IC pin for remote control
receiving.
15
8
• Frequency division clock output
Can output the frequency division clock for the system clock or the frequency division clock
for the subclock from the frequency division clock output pin (TMOW).
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Section 21 Prescalar Unit
21.1.2
Block Diagram
Figure 21.1 shows a block diagram of the prescalar unit.
PWM3
PWM2
PWM1
PWM0
Stable oscillation
wait time count output
Prescalar S
φ/131072 to φ/2
MSB
217
6 bits
212
27
20
8 bits
LSB
18-bit free running counter (FRC)
215
28
8 bits
IC pin
Interrupt
request
φ/32
φ/16
φ/8
φw/32
ICR1
φ/4
φw/16
TMOW
pin
φw/8
Prescalar W
φw/128
φw/4
MSB
5-bit counter
PCSR
Internal data bus
Legend:
ICR1 : Input capture register 1
PCSR : Prescalar unit control/status register
IC
: Input capture input pin
TMOW : Frequency division clock output pin
Figure 21.1 Block Diagram of Prescalar Unit
Rev.2.00 Jan. 15, 2007 page 380 of 1174
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φ
LSB
Section 21 Prescalar Unit
21.1.3
Pin Configuration
Table 21.1 shows the pin configuration of the prescalar unit.
Table 21.1 Pin Configuration
Name
Abbrev.
I/O
Function
Input capture input
IC
Input
Prescalar unit input capture input pin
Frequency division clock
output
TMOW
Output
Prescalar unit frequency division clock
output pin
21.1.4
Register Configuration
Table 21.2 shows the register configuration of the prescalar unit.
Table 21.2 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address*
Input capture register 1
ICR1
R
Byte
H'00
H'D12C
Prescalar unit control/status
register
PCSR
R/W
Byte
H'08
H'D12D
Note:
*
Lower 16 bits of the address.
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Section 21 Prescalar Unit
21.2
Registers
21.2.1
Input Capture Register 1 (ICR1)
Bit :
Initial value :
R/W :
7
ICR17
6
ICR16
5
ICR15
4
ICR14
3
ICR13
2
ICR12
1
ICR11
0
ICR10
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
15
8
Input capture register 1 (ICR1) captures 8-bit data of 2 to 2 of the FRC according to the edge of
the IC pin.
ICR1 is an 8-bit read-only register. The write operation becomes invalid. The ICR1 values are
undefined until the first capture is generated after the mode has been set to the standby mode,
watch mode, subactive mode, and subsleeve mode. When reset, ICR1 is initialized to H'00.
21.2.2
Prescalar Unit Control/Status Register (PCSR)
Bit :
Initial value :
R/W :
7
ICIF
6
ICIE
5
ICEG
4
NCon/off
3
—
2
DCS2
1
DCS1
0
DCS0
0
R/(W)*
0
R/W
0
R/W
0
R/W
1
—
0
R/W
0
R/W
0
R/W
Note: * Only 0 can be written to clear the flag.
The prescalar unit control/status register (PCSR) controls the input capture function and selects the
frequency division clock that is output from the TMOW pin.
PCSR is an 8-bit read/write enable register. When reset, PCSR is initialized to H'08.
Bit 7⎯Input Capture Interrupt Flag (ICIF): Input capture interrupt request flag. This indicates
that the input capture was performed according to the edge of the IC pin.
Bit 7
ICIF
Description
0
[Clear condition]
(Initial value)
When 0 is written after 1 has been read
1
[Set condition]
When the input capture was performed according to the edge of the IC pin
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Section 21 Prescalar Unit
Bit 6⎯Input Capture Interrupt Enable (ICIE): When ICIF was set to 1 by the input capture
according to the edge of the IC pin, ICIE enables and disables the generation of an input capture
interrupt.
Bit 6
ICIE
Description
0
Disables the generation of an input capture interrupt
1
Enables the generation of an input capture interrupt
(Initial value)
Bit 5⎯IC Pin Edge Select (ICEG): ICEG selects the input edge sense of the IC pin.
Bit 5
ICEG
Description
0
Detects the falling edge of the IC pin input
1
Detects the rising edge of the IC pin input
(Initial value)
Bit 4⎯Noise Cancel ON/OFF (NCon/off): NCon/off selects enable/disable of the noise cancel
function of the IC pin. For the noise cancel function, see section 21.3, Noise Cancel Circuit.
Bit 4
NCon/off
Description
0
Disables the noise cancel function of the IC pin
1
Enables the noise cancel function of the IC pin
(Initial value)
Bit 3⎯Reserved: This bit cannot be modified and is always read as 1.
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Section 21 Prescalar Unit
Bits 2 to 0⎯Frequency Division Clock Output Select (DCS2 to DCS0): DCS2 to DCS0 select
eight types of frequency division clocks that are output from the TMOW pin.
Bit 2
Bit 1
Bit 0
DCS2
DCS1
DCS0
Description
0
0
0
Outputs PSS, φ/32
1
Outputs PSS, φ/16
0
Outputs PSS, φ/8
1
Outputs PSS, φ/4
0
Outputs PSW, φW/32
1
Outputs PSW, φW/16
0
Outputs PSW, φW/8
1
Outputs PSW, φW/4
1
1
0
1
21.2.3
(Initial value)
Port Mode Register 1 (PMR1)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
PMR17
PMR16
PMR15
PMR14
PMR13
PMR12
PMR11
PMR10
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching
is specified in a unit of bit.
PMR1 is an 8-bit read/write enable register. When reset, PMR1 is initialized to H'00. For details,
refer to Port Mode Register 1 in section 10.3.2 Register Configuration.
Bit 7⎯P17/TMOW Pin Switching (PMR17): PMR17 sets whether the P17/TMOW pin is used
as a P17 I/O pin or a TMOW pin for division clock output.
Bit 7
PMR17
Description
0
The P17/TMOW pin functions as a P17 I/O pin
1
The P17/TMOW pin functions as a TMOW output function
Rev.2.00 Jan. 15, 2007 page 384 of 1174
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(Initial value)
Section 21 Prescalar Unit
Bit 6⎯P16/IC Pin Switching (PMR16): PMR16 sets whether the P16/IC pin is used as a P16 I/O
pin or an IC pin for the input capture input of the prescalar unit.
Bit 6
PMR16
Description
0
The P16/IC pin functions as a P16 I/O pin
1
The P16/IC pin functions as an IC input function
21.3
(Initial value)
Noise Cancel Circuit
The IC pin has a built-in a noise cancel circuit. The circuit can be used for noise protection such as
remote control receiving. The noise cancel circuit samples the input values of the IC pin twice at
an interval of 256 states. If the input values are different, they are assumed to be noise.
The IC pin can specify enable/disable of the noise cancel function according to the bit 4
(NCon/off) of the prescalar unit control/status register (PCSR).
21.4
Operation
21.4.1
Prescalar S (PSS)
The PSS is a 17-bit counter that uses the system clock (φ=fosc) as an input clock and generates the
frequency division clocks (φ/131072 to φ/2) of the peripheral function. The low-order 17 bits of
the 18-bit free running counter (FRC) correspond to the PSS. The FRC is incremented by one
clock. The PSS output is shared by the timer and serial communication interface (SCI), and the
frequency division ratio can independently be set by each built-in peripheral function.
When reset, the FRC is initialized to H'00000, and starts increment after reset has been released.
Because the system clock oscillator is stopped in standby mode, watch mode, subactive mode, and
subsleep mode, the PSS operation is also stopped. In this case, the FCR is also initialized to
H'00000.
The FRC cannot be read and written from the CPU.
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Section 21 Prescalar Unit
21.4.2
Prescalar W (PSW)
PSW is a counter that uses the subclock as an input clock. The PSW also generates the input clock
of the timer A. In this case, the timer A functions as a clock time base.
When reset, the PSW is initialized to H'00, and starts increment after reset has been released. Even
if the mode has been shifted to the standby mode*, watch mode*, subactive mode*, and subsleep
mode*, the PSW continues the operation as long as the clocks are supplied by the X1 and X2 pins.
The PSW can also be initialized to H'00 by setting the TMA3 and TMA2 bits of the timer mode
register A (TMA) to 11.
Note: * When the timer A is in module stop mode, the operation is stopped.
Figure 21.2 shows the supply of the clocks to the peripheral function by the PSS and PSW.
φ/131072 to φ/2
OSC1
OSC2
System fosc
clock
oscillator
X1
Subclock
oscillator
X2
(fx)
φw
System
clock
duty
correction
circuit
φ
Subclock
frequency
dividers
(1/2, 1/4, and 1/8)
Prescalar S
Intermediate
speed clock
frequency divider
φw/4
Timer
SCI
TMOW pin
φw/128
Prescalar W
System clock
selection
Timer A
CPU
ROM
RAM
Peripheral register
I/O port
Figure 21.2 Clock Supply
21.4.3
Stable Oscillation Wait Time Count
For the count of the stable oscillation stable wait time during the return from the low power
consumption mode excluding the sleep mode, see section 4, Power-Down State.
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Section 21 Prescalar Unit
21.4.4
8-bit PWM
This 8-bit PWM controls the duty control PWM signal in the conversion cycle 256 states. It counts
7
0
the cycle and the duty cycle at 2 to 2 of the FRC. It can be used for controlling reel motors and
loading motors. For details, see section 18, 8-Bit PWM.
21.4.5
8-bit Input Capture Using IC Pin
This function catches the 8-bit data of 2 to 2 of the FRC according to the edge of the IC pin. It
can be used for remote control receiving.
For the edge of the IC pin, the rising and falling edges can be selected.
The IC pin has a built-in noise cancel circuit. See section 21.3, Noise Cancel Circuit.
An interrupt request is generated due to the input capture using the IC pin.
15
8
Note: Rewriting the ICEG bit, NCon/off bit, or PMR16 bit is incorrectly recognized as edge
detection according to the combinations between the state and detection edge of the IC pin
and the ICIF bit may be set after up to 384φ seconds.
21.4.6
Frequency Division Clock Output
The frequency division clock can be output from the TMOW pin. For the frequency division
clock, eight types of clocks can be selected according to the DCS2 to DCS0 bits in PCSR.
The clock in which the system clock was frequency-divided is output in active mode and sleep
mode and the clock in which the subclock was frequency-divided is output in active mode*, sleep
mode*, and subactive mode.
Note: * When timer A is in module stop mode, no clock is output.
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Section 21 Prescalar Unit
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Section 22 Serial Communication Interface 1 (SCI1)
Section 22 Serial Communication Interface 1 (SCI1)
22.1
Overview
The serial communication interface (SCI) can handle both asynchronous and clocked synchronous
serial communication. A function is also provided for serial communication between processors
(multiprocessor communication function).
22.1.1
Features
SCI1 features are listed below.
• Choice of asynchronous or synchronous serial communication mode
⎯ Asynchronous mode
• Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character
Serial data communication can be carried out with standard asynchronous
communication chips such as a Universal Asynchronous Receiver/Transmitter (UART)
or Asynchronous Communication Interface Adapter (ACIA)
• A multiprocessor communication function is provided that enables serial data
communication with a number of processors
• Choice of 12 serial data transfer formats
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Multiprocessor bit: 1 or 0
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the SI1 pin level directly in case of a
framing error
⎯ Clock synchronous mode
• Serial data communication is synchronized with a clock
Serial data communication can be carried out with other chips that have a synchronous
communication function
• One serial data transfer format
Data length: 8 bits
• Receive error detection: Overrun errors detected
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Section 22 Serial Communication Interface 1 (SCI1)
• Full-duplex communication capability
⎯ The transmitter and receiver are mutually independent, enabling transmission and reception
to be executed simultaneously
⎯ Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data
• Built-in baud rate generator allows any bit rate to be selected
• Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK1 pin
• Four interrupt sources
⎯ Four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive
error) that can issue requests independently
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Section 22 Serial Communication Interface 1 (SCI1)
22.1.2
Block Diagram
Module data bus
RDR1
TDR1
SCMR1
BRR1
SSR1
SCR1
SI1
RSR1
TSR1
SO1
Parity generation
SMR1
Transmission/
reception
control
Internal data bus
Bus interface
Figure 22.1 shows a block diagram of the SCI.
φ
Baud rate
generator
φ/4
φ/16
φ/64
Clock
Parity check
External clock
SCK1
Legend:
RSR1
RDR1
TSR1
TDR1
SMR1
SCR1
SSR1
SCMR1
BRR1
TEI
TXI
RXI
ERI
: Receive shift register 1
: Receive data register 1
: Transmit shift register 1
: Transmit data register 1
: Serial mode register 1
: Serial control register 1
: Serial status register 1
: Serial interface mode register 1
: Bit rate register 1
Figure 22.1 Block Diagram of SCI
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Section 22 Serial Communication Interface 1 (SCI1)
22.1.3
Pin Configuration
Table 22.1 shows the serial pins used by the SCI.
Table 22.1 SCI Pins
Channel
Pin Name
Symbol
I/O
Function
1
Serial clock pin 1
SCK1
I/O
SCI1 clock input/output
Receive data pin 1
SI1
Input
SCI1 receive data input
Transmit data pin 1
SO1
Output
SCI1 transmit data output
22.1.4
Register Configuration
The SCI1 has the internal registers shown in table 22.2. These registers are used to specify
asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the
transmitter/receiver.
Table 22.2 SCI Registers
Channel
1
Common
Name
Abbrev.
R/W
1
Initial Value Address*
Serial mode register 1
SMR1
R/W
H'00
H'D148
Bit rate register 1
BRR1
R/W
H'FF
H'D149
Serial control register 1
SCR1
R/W
H'00
H'D14A
Transmit data register 1
TDR1
R/W
H'FF
H'D14B
Serial status register 1
SSR1
R/(W)*
H'84
H'D14C
Receive data register 1
RDR1
R
H'00
H'D14D
Serial interface mode register 1
SCMR1
R/W
H'F2
H'D14E
Module stop control register
MSTPCRH
R/W
H'FF
H'FFEC
MSTPCRL
R/W
H'FF
H'FFED
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
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2
Section 22 Serial Communication Interface 1 (SCI1)
22.2
Register Descriptions
22.2.1
Receive Shift Register 1 (RSR1)
Bit :
7
6
5
4
3
2
1
0
R/W :
—
—
—
—
—
—
—
—
RSR1 is a register used to receive serial data.
The SCI sets serial data input from the SI1 pin in RSR1 in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to RDR automatically.
RSR1 cannot be directly read or written to by the CPU.
22.2.2
Receive Data Register 1 (RDR1)
Bit :
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W :
R
R
R
R
R
R
R
R
RDR1 is a register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received serial data from RSR1
to RDR1 where it is stored, and completes the receive operation. After this, RSR1 is receiveenabled.
Since RSR1 and RDR1 function as a double buffer in this way, continuous receive operations can
be performed.
RDR1 is a read-only register, and cannot be written to by the CPU.
RDR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
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Section 22 Serial Communication Interface 1 (SCI1)
22.2.3
Transmit Shift Register 1 (TSR1)
Bit :
7
6
5
4
3
2
1
0
R/W :
—
—
—
—
—
—
—
—
TSR1 is a register used to transmit serial data.
To perform serial data transmission, the SCI first transfers transmit data from TDR1 to TSR1, then
sends the data to the SO1 pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from TDR1 to
TSR1, and transmission started, automatically. However, data transfer from TDR1 to TSR1 is not
performed if the TDRE bit in SSR1 is set to 1.
TSR1 cannot be directly read or written to by the CPU.
22.2.4
Transmit Data Register 1 (TDR1)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDR1 is an 8-bit register that stores data for serial transmission.
When the SCI detects that TSR1 is empty, it transfers the transmit data written in TDR1 to TSR1
and starts serial transmission. Continuous serial transmission can be carried out by writing the next
transmit data to TDR1 during serial transmission of the data in TSR1.
TDR1 can be read or written to by the CPU at all times.
TDR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
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Section 22 Serial Communication Interface 1 (SCI1)
22.2.5
Serial Mode Register 1 (SMR1)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMR1 is an 8-bit register used to set the SCI's serial transfer format and select the baud rate
generator clock source.
SMR1 can be read or written to by the CPU at all times.
SMR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7⎯Communication Mode (C/A): Selects asynchronous mode or clock synchronous mode as
the SCI operating mode.
Bit 7
C/A
Description
0
Asynchronous mode
1
Clock synchronous mode
(Initial value)
Bit 6⎯Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR
Description
0
8-bit data
7-bit data*
1
Note:
*
(Initial value)
When 7-bit data is selected, the MSB (bit 7) of TDR1 is not transmitted, and LSBfirst/MSB-first selection is not available.
Rev.2.00 Jan. 15, 2007 page 395 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
Bit 5⎯Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In synchronous mode, or when a
multiprocessor format is used, parity bit addition and checking is not performed, regardless of the
PE bit setting.
Bit 5
PE
Description
0
Parity bit addition and checking disabled
1
Parity bit addition and checking enabled*
Note:
*
(Initial value)
When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by the O/E bit.
Bit 4⎯Parity Mode (O/E): Selects either even or odd parity for use in parity addition and
checking.
The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, when parity
bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is
used.
Bit 4
O/E
Description
0
Even parity*
2
Odd parity*
1
1
(Initial value)
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is even. In reception, a
check is performed to see if the total number of 1 bits in the receive character plus the
parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check
is performed to see if the total number of 1 bits in the receive character plus the parity
bit is odd.
Rev.2.00 Jan. 15, 2007 page 396 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
Bit 3⎯Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP
bit setting is invalid since stop bits are not added.
Bit 3
STOP
Description
0
1 stop bit*
1
2 stop bits*
1
(Initial value)
2
Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character
before it is sent.
2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2⎯Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in
asynchronous mode; it is invalid in synchronous mode.
For details of the multiprocessor communication function, see section 22.3.3, Multiprocessor
Communication Function.
Bit 2
MP
Description
0
Multiprocessor function disabled
1
Multiprocessor format selected
(Initial value)
Rev.2.00 Jan. 15, 2007 page 397 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
Bits 1 and 0⎯Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the
baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the
setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 22.2.8, Bit Rate Register 1 (BRR1).
Bit 1
Bit 0
CKS1
CKS0
Description
0
0
φ clock
1
φ/4 clock
0
φ/16 clock
1
φ/64 clock
1
22.2.6
(Initial value)
Serial Control Register 1 (SCR1)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR1 is a register that performs enabling or disabling of SCI transfer operations, serial clock
output in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR1 can be read or written to by the CPU at all times.
SCR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7⎯Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt
(TXI) request generation when serial transmit data is transferred from TDR1 to TSR1 and the
TDRE flag in SSR1 is set to 1.
Bit 7
TIE
Description
0
Transmit-data-empty interrupt (TXI) request disabled*
1
Transmit-data-empty interrupt (TXI) request enabled
Note:
*
(Initial value)
TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,
then clearing it to 0, or clearing the TIE bit to 0.
Rev.2.00 Jan. 15, 2007 page 398 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
Bit 6⎯Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI)
request and receive-error interrupt (ERI) request generation when serial receive data is transferred
from RSR1 to RDR1 and the RDRF flag in SSR1 is set to 1.
Bit 6
RIE
Description
0
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request
disabled*
(Initial value)
1
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request
enabled
Note:
*
RXI and ERI interrupt request cancellation can be performed by reading 1 from the
RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.
Bit 5⎯Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5
TE
Description
0
Transmission disabled*
2
Transmission enabled*
1
1
(Initial value)
Notes: 1. The TDRE flag in SSR1 is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to TDR1 and the
TDRE flag in SSR1 is cleared to 0.
SMR1 setting must be performed to decide the transmission format before setting the
TE bit to 1.
Bit 4⎯Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4
RE
Description
0
Reception disabled*
2
Reception enabled*
1
1
(Initial value)
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode.
SMR1 setting must be performed to decide the reception format before setting the RE
bit to 1.
Rev.2.00 Jan. 15, 2007 page 399 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
Bit 3⎯Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in
SMR1 set to 1.
The MPIE bit setting is invalid in clock synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupts disabled (normal reception performed)
(Initial value)
[Clearing conditions]
1. When the MPIE bit is cleared to 0
2. When data with MPB = 1 is received
Multiprocessor interrupts enabled*
1
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR1 are disabled until data with the
multiprocessor bit set to 1 is received.
Note:
*
When receive data including MPB = 0 is received, receive data transfer from RSR1 to
RDR1, receive error detection, and setting of the RDRF, FER, and ORER flags in
SSR1, is not performed. When receive data with MPB = 1 is received, the MPB bit in
SSR1 is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and
ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag
setting is enabled.
Bit 2⎯Transmit End Interrupt Enable (TEIE): Enables or disables transmit-end interrupt
(TEI) request generation if there is no valid transmit data in TDR when the MSB is transmitted.
Bit 2
TEIE
Description
0
Transmit-end interrupt (TEI) request disabled*
Transmit-end interrupt (TEI) request enabled*
1
Note:
*
(Initial value)
TEI cancellation can be performed by reading 1 from the TDRE flag in SSR1, then
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Rev.2.00 Jan. 15, 2007 page 400 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
Bits 1 and 0⎯Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or
the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of
external clock operation (CKE1 = 1). Note that the SCI's operating mode must be decided using
SMR1 before setting the CKE1 and CKE0 bits.
For details of clock source selection, see table 22.9.
Bit 1
Bit 0
CKE1
CKE0
Description
0
0
Asynchronous mode
Internal clock/SCK1 pin functions as I/O
1
port*
Clock synchronous mode Internal clock/SCK1 pin functions as serial
1
clock output*
1
Asynchronous mode
Internal clock/SCK1 pin functions as clock
2
output*
Clock synchronous mode Internal clock/SCK1 pin functions as serial
clock output
1
0
Asynchronous mode
External clock/SCK1 pin functions as clock
3
input*
Clock synchronous mode External clock/SCK1 pin functions as serial
clock input
Asynchronous mode
External clock/SCK1 pin functions as clock
3
input*
Clock synchronous mode External clock/SCK1 pin functions as serial
clock input
Notes: 1. Initial value.
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
Rev.2.00 Jan. 15, 2007 page 401 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
22.2.7
Serial Status Register 1 (SSR1)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
1
0
0
0
0
1
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Note: * Only 0 can be written to clear the flag.
SSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SSR1 is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7⎯Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR1 to TSR1 and the next serial data can be written to TDR1.
Bit 7
TDRE
Description
0
[Clearing condition]
When 0 is written in TDRE after reading TDRE = 1
1
[Setting conditions]
(Initial value)
1. When the TE bit in SCR1 is 0
2. When data is transferred from TDR1 to TSR1 and data can be written to TDR1
Rev.2.00 Jan. 15, 2007 page 402 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
Bit 6⎯Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR1.
Bit 6
RDRF
Description
0
[Clearing condition]
1
[Setting condition]
(Initial value)
When 0 is written in RDRF after reading RDRF = 1
When serial reception ends normally and receive data is transferred from RSR1 to
RDR1
Note: RDR1 and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR1 is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Bit 5⎯Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5
ORER
Description
0
[Clearing condition]
(Initial value)*
1
When 0 is written in ORER after reading ORER = 1*
1
1
[Setting condition]
2
When the next serial reception is completed while RDRF = 1*
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR1 is
cleared to 0.
2. The receive data prior to the overrun error is retained in RDR1, and the data received
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
Rev.2.00 Jan. 15, 2007 page 403 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
Bit 4⎯Framing Error (FER): Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
Bit 4
FER
Description
0
[Clearing condition]
(Initial value)
1
When 0 is written in FER after reading FER = 1*
1
[Setting condition]
When the SCI checks the stop bit at the end of the receive data when reception
2
ends, and the stop bit is 0*
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR1 is
cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit
is not checked. If a framing error occurs, the receive data is transferred to RDR1 but the
RDRF flag is not set. Also, subsequent serial reception cannot be continued while the
FER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
Bit 3⎯Parity Error (PER): Indicates that a parity error occurred during reception using parity
addition in asynchronous mode, causing abnormal termination.
Bit 4
PER
Description
0
[Clearing condition]
(Initial value)
1
When 0 is written in PER after reading PER = 1*
1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit does
2
not match the parity setting (even or odd) specified by the O/E bit in SMR1*
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR1 is
cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR1 but the RDRF flag is not
set. Also, subsequent serial reception cannot be continued while the PER flag is set to
1. In synchronous mode, serial transmission cannot be continued, either.
Rev.2.00 Jan. 15, 2007 page 404 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
Bit 2⎯Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of
the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2
TEND
Description
0
[Clearing condition]
When 0 is written in TDRE after reading TDRE = 1
1
[Setting conditions]
(Initial value)
1. When the TE bit in SCR1 is 0
2. When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit
character
Bit 1⎯Multiprocessor Bit (MPB): When reception is performed using a multiprocessor format
in asynchronous mode, MPB stores the multiprocessor bit in the receive data.
MPB is a read-only bit, and cannot be modified.
Bit 1
MPB
Description
0
[Clearing condition]
(Initial value)
When data with a 0 multiprocessor bit is received*
1
[Setting condition]
When data with a 1 multiprocessor bit is received
Note:
*
Retains its previous state when the RE bit in SCR1 is cleared to 0 with multiprocessor
format.
Bit 0⎯Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting,
and in synchronous mode.
Bit 0
MPBT
Description
0
Data with a 0 multiprocessor bit is transmitted
1
Data with a 1 multiprocessor bit is transmitted
(Initial value)
Rev.2.00 Jan. 15, 2007 page 405 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
22.2.8
Bit Rate Register 1 (BRR1)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR1.
BRR1 can be read or written to by the CPU at all times.
BRR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Table 22.3 shows sample BRR1 settings in asynchronous mode, and table 22.4 shows sample
BRR1 settings in synchronous mode.
Rev.2.00 Jan. 15, 2007 page 406 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
Table 22.3 BRR1 Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency φ (MHz)
Bit Rate
(bits/s)
2
2.097152
2.4576
3
n
N
Error (%)
n
N
Error (%) n
N
Error (%) n
N
Error (%)
110
1
141
0.03
1
148
−0.04
1
174
−0.26
1
212
0.03
150
1
103
0.16
1
108
0.21
1
127
0.00
1
155
0.16
300
0
207
0.16
0
217
0.21
0
255
0.00
1
77
0.16
600
0
103
0.16
0
108
0.21
0
127
0.00
0
155
0.16
1200
0
51
0.16
0
54
−0.71
0
63
0.00
0
77
0.16
2400
0
25
0.16
0
26
1.12
0
31
0.00
0
38
0.16
4800
0
12
0.16
0
13
−2.54
0
15
0.00
0
19
−2.40
9600
⎯
⎯
⎯
0
6
−2.54
0
7
0.00
0
9
−2.40
19200
⎯
⎯
⎯
⎯
⎯
⎯
0
3
0.00
0
4
−2.40
31250
0
1
0.00
⎯
⎯
⎯
0
⎯
⎯
0
2
0.00
38400
⎯
⎯
⎯
⎯
⎯
⎯
0
1
0.00
⎯
⎯
⎯
Operating Frequency φ (MHz)
Bit Rate
(bits/s)
3.6864
4
4.9152
5
n
N
Error (%)
n
N
Error (%)
n
N
Error (%) n
N
Error (%)
110
2
64
0.69
2
70
0.03
2
86
0.31
2
88
−0.25
150
1
191
0.00
1
207
0.16
1
255
0.00
2
64
0.16
300
1
95
0.00
1
103
0.16
1
127
0.00
1
129 0.16
600
0
191
0.00
0
207
0.16
0
255
0.00
1
64
1200
0
95
0.00
0
103
0.16
0
127
0.00
0
129 0.16
2400
0
47
0.00
0
51
0.16
0
63
0.00
0
64
0.16
4800
0
23
0.00
0
25
0.16
0
31
0.00
0
32
−1.38
9600
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.70
19200
0
5
0.00
⎯
⎯
⎯
0
7
0.00
0
7
1.70
31250
⎯
⎯
⎯
0
3
0.00
0
4
−1.73
0
4
0.00
38400
0
2
0.00
⎯
⎯
⎯
0
3
0.00
0
3
1.70
0.16
Rev.2.00 Jan. 15, 2007 page 407 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
Operating Frequency φ (MHz)
Bit Rate
(bits/s)
6
6.144
7.3728
8
n
N
Error (%)
n
N
Error (%)
n
N
Error (%) n
N
Error (%)
110
2
106
−0.44
2
108
0.08
2
130
−0.07
2
141
0.03
150
2
77
0.16
2
79
0.00
2
95
0.00
2
103
0.16
300
1
155
0.16
1
159
0.00
1
191
0.00
1
207
0.16
600
1
77
0.16
1
79
0.00
1
95
0.00
1
103
0.16
1200
0
155
0.16
0
159
0.00
0
191
0.00
0
207
0.16
2400
0
77
0.16
0
79
0.00
0
95
0.00
0
103
0.16
4800
0
38
0.16
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
−2.40
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
−2.40
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.34
⎯
⎯
⎯
0
7
0.00
38400
0
4
−2.40
0
4
0.00
0
5
0.00
⎯
⎯
⎯
Operating Frequency φ (MHz)
Bit Rate
(bits/s)
9.8304
n
N
10
Error (%)
n
N
Error (%)
110
2
174
−0.26
2
177
−0.25
150
2
127
0.00
2
129
0.16
300
1
255
0.00
2
64
0.16
600
1
127
0.00
1
129
0.16
1200
0
255
0.00
1
64
0.16
2400
0
127
0.00
0
129
0.16
4800
0
63
0.00
0
64
0.16
9600
0
31
0.00
0
32
−1.38
19200
0
15
0.00
0
15
1.70
31250
0
9
−1.73
0
9
0.00
38400
0
7
0.00
0
7
1.70
Rev.2.00 Jan. 15, 2007 page 408 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
Table 22.4 BRR1 Settings for Various Bit Rates (Synchronous Mode)
Operating Frequency φ (MHz)
2
4
8
Bit Rate
(bits/s)
n
N
n
N
110
3
70
⎯
⎯
250
2
124
2
500
1
249
1k
1
2.5 k
10
n
N
n
N
249
3
124
⎯
⎯
2
124
2
249
⎯
⎯
124
1
249
2
124
⎯
⎯
0
199
1
99
1
199
1
249
5k
0
99
0
199
1
99
1
124
10 k
0
49
0
99
0
199
0
249
25 k
0
19
0
39
0
79
0
99
50 k
0
9
0
19
0
39
0
49
100 k
0
4
0
9
0
19
0
24
250 k
0
1
0
3
0
7
0
9
500 k
0
0*
0
1
0
3
0
4
0
0*
0
1
0
0*
1M
2.5 M
5M
Legend:
Blank: Cannot be set.
⎯:
Can be set, but there will be a degree of error.
*:
Continuous transfer is not possible.
Note: As far as possible, the setting should be made so that the error is no more than 1%.
Rev.2.00 Jan. 15, 2007 page 409 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
The BRR1 setting is found from the following equations.
• Asynchronous mode:
N=
φ
64 × 22n −1× B
× 10 6 − 1
• Synchronous mode:
φ
8 × 22n −1 × B
N=
× 106 − 1
Where
B:
Bit rate (bits/s)
N:
BRR1 setting for baud rate generator (0 ≤ N ≤ 255)
φ:
Operating frequency (MHz)
n:
Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SMR1 Setting
n
Clock
CKS1
CKS0
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
The bit rate error in asynchronous mode is found from the following equation:
Error (%) =
φ × 106
{ (N + 1) × B × 64 × 22n −1
−1
} × 10
Table 22.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 22.6
and 22.7 show the maximum bit rates with external clock input.
Rev.2.00 Jan. 15, 2007 page 410 of 1174
REJ09B0329-0200
Section 22 Serial Communication Interface 1 (SCI1)
Table 22.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum Bit Rate (bits/s)
n
N
2
62500
0
0
2.097152
65536
0
0
2.4576
76800
0
0
3
93750
0
0
3.6864
115200
0
0
4
125000
0
0
4.9152
153600
0
0
5
156250
0
0
6
187500
0
0
6.144
192000
0
0
7.3728
230400
0
0
8
250000
0
0
9.8304
307200
0
0
10
312500
0
0
Rev.2.00 Jan. 15, 2007 page 411 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
Table 22.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.5000
31250
2.097152
0.5243
32768
2.4576
0.6144
38400
3
0.7500
46875
3.6864
0.9216
57600
4
1.0000
62500
4.9152
1.2288
76800
5
1.2500
78125
6
1.5000
93750
6.144
1.5360
96000
7.3728
1.8432
115200
8
2.0000
125000
9.8304
2.4576
153600
10
2.5000
156250
Table 22.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.3333
333333.3
4
0.6667
666666.7
6
1.0000
1000000.0
8
1.3333
1333333.3
10
1.6667
1666666.7
Rev.2.00 Jan. 15, 2007 page 412 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
22.2.9
Serial Interface Mode Register 1 (SCMR1)
Bit :
7
6
5
4
3
2
1
0
—
—
—
—
SDIR
SINV
—
SMIF
Initial value :
1
1
1
1
0
0
1
0
R/W :
—
—
—
—
R/W
R/W
—
R/W
SCMR1 is an 8-bit readable/writable register used to select SCI functions.
SCMR1 is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 to 4⎯Reserved: These bits cannot be modified and are always read as 1.
Bit 3⎯Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.
Bit 3
SDIR
Description
0
TDR1 contents are transmitted LSB-first
(Initial value)
Receive data is stored in RDR1 LSB-first
1
TDR1 contents are transmitted MSB-first
Receive data is stored in RDR1 MSB-first
Bit 2⎯Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not
affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in
SMR1.
Bit 2
SINV
Description
0
TDR1 contents are transmitted without modification
(Initial value)
Receive data is stored in RDR1 without modification
1
TDR1 contents are inverted before being transmitted
Receive data is stored in RDR1 in inverted form
Bit 1⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 0⎯Reserved: 1 should not be written in this bit.
Rev.2.00 Jan. 15, 2007 page 413 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
22.2.10 Module Stop Control Register (MSTPCR)
MSTPCRL
MSTPCRH
Bit :
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8
Initial value :
1
1
1
1
1
1
1
1
7
6
5
MSTP7 MSTP6 MSTP5
1
1
1
4
3
2
1
MSTP4 MSTP3 MSTP2 MSTP1
1
1
1
1
0
MSTP0
1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When bit MSTP8 is set to 1, SCI1 operation stops at the end of the bus cycle and a transition is
made to module stop mode. For details, see section 4.5, Module Stop Mode.
MSTPCR is initialized to H'FFFF by a reset.
Bit 0⎯Module Stop (MSTP8): Specifies the SCI1 module stop mode.
MSTPCRH
Bit 0
MSTP8
Description
0
SCI1 module stop mode is cleared
1
SCI1 module stop mode is set
Rev.2.00 Jan. 15, 2007 page 414 of 1174
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(Initial value)
Section 22 Serial Communication Interface 1 (SCI1)
22.3
Operation
22.3.1
Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and synchronous mode in which
synchronization is achieved with clock pulses.
Selection of asynchronous or synchronous mode and the transmission format is made using SMR1
as shown in table 22.8. The SCI clock is determined by a combination of the C/A bit in SMR1 and
the CKE1 and CKE0 bits in SCR1, as shown in table 22.9.
• Asynchronous Mode
⎯ Data length: Choice of 7 or 8 bits
⎯ Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the
combination of these parameters determines the transfer format and character length)
⎯ Detection of framing, parity, and overrun errors, and breaks, during reception
⎯ Choice of internal or external clock as SCI clock source
• When internal clock is selected:
The SCI operates on the baud rate generator clock and a clock with the same frequency
as the bit rate can be output
• When external clock is selected:
A clock with a frequency of 16 times the bit rate must be input (the built-in baud rate
generator is not used)
• Clock Synchronous Mode
⎯ Transfer format: Fixed 8-bit data
⎯ Detection of overrun errors during reception
⎯ Choice of internal or external clock as SCI clock source
• When internal clock is selected:
The SCI operates on the baud rate generator clock and a serial clock is output off-chip
• When external clock is selected:
The built-in baud rate generator is not used, and the SCI operates on the input serial
clock
Rev.2.00 Jan. 15, 2007 page 415 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
Table 22.8 SMR1 Settings and Serial Transfer Format Selection
SMR1 Settings
SCI Transfer Format
Bit 7
Bit 6
Bit 2
Bit 5
Bit 3
C/A
CHR
MP
PE
STOP
Mode
Data
Length
Multiprocessor Bit
Parity
Bit
Stop Bit
Length
0
0
0
0
0
Asynchronous mode
8-bit
data
No
No
1 bit
1
1
2 bits
Yes
0
1
1
0
2 bits
0
7-bit
data
1
No
Yes
1
1
1
⎯
⎯
⎯
0
⎯
1
⎯
0
⎯
1
⎯
⎯
1 bit
2 bits
1
0
1 bit
2 bits
0
1
1 bit
Asynchronous mode
(multiprocessor
format)
8-bit
data
Yes
No
2 bits
1 bit
7-bit
data
8-bit
Clock
synchronous data
mode
1 bit
2 bits
No
Table 22.9 SMR1 and SCR1 Settings and SCI Clock Source Selection
SMR1 SCR1 Setting
Bit 7
Bit 1
Bit 0
C/A
CKE1
CKE0
Mode
Clock Source
SCK Pin Function
0
0
0
Asynchronous
mode
Internal
SCI does not use SCK pin
1
1
SCI Transfer Clock
0
Outputs clock with same frequency
as bit rate
External
Inputs clock with frequency of 16
times the bit rate
Internal
Outputs serial clock
External
Inputs serial clock
1
1
0
0
1
1
Clock
synchronous
mode
0
1
Rev.2.00 Jan. 15, 2007 page 416 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
22.3.2
Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial communication is thus carried out with synchronization established on a character-bycharacter basis.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 22.2 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level).
In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in
reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the
length of one bit, so that the transfer data is latched at the center of each bit.
Idle state
(mark state)
1
Serial
data
LSB
0
D0
MSB
D1
D2
D3
D4
D5
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
D6
D7
1
0/1
Parity
bit
1
1
Stop
bit(s)
1 bit,
1 or 2 bits
or none
One unit of transfer data (character or frame)
Figure 22.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
Rev.2.00 Jan. 15, 2007 page 417 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
• Data Transfer Format
Table 22.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected by settings in SMR1.
Table 22.10 Serial Transfer Formats (Asynchronous Mode)
SMR1 Settings
Serial Transfer Format and Frame Length
CHR
PE
MP
STOP
1
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
Legend:
S:
Start bit
STOP:
Stop bit
P:
Parity bit
MPB: Multiproccesor bit
Rev.2.00 Jan. 15, 2007 page 418 of 1174
REJ09B0329-0200
2
3
4
5
6
7
8
9
10
11
12
Section 22 Serial Communication Interface 1 (SCI1)
• Clock
Either an internal clock generated by the built-in baud rate generator or an external clock input
at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit
in SMR1 and the CKE1 and CKE0 bits in SCR1. For details of SCI clock source selection, see
table 22.9.
When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit
rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is at the center of each transmit data bit, as shown in figure 22.3.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 22.3 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode)
Rev.2.00 Jan. 15, 2007 page 419 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
• Data Transfer Operations
⎯ SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then
initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be
cleared to 0 before making the change using the following procedure. When the TE bit is
cleared to 0, the TDRE flag is set to 1 and TSR1 is initialized. Note that clearing the RE bit
to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the
contents of RDR1.
When an external clock is used the clock should not be stopped during operation, including
initialization, since operation is uncertain.
Figure 22.4 shows a sample SCI initialization flowchart.
Start initialization
[1] Set the clock selection in SCR1.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR1 settings are made.
Clear TE and RE bits in SCR1 to 0
Set CKE1 and CKE0 bits in SCR1
(TE, RE bits 0)
[1]
Set data transfer format
in SMR1 and SCMR1
[2]
Set value in BRR1
[3]
Wait
No
[2] Set the data transfer format in SMR1 and
SCMR1.
[3] Write a value corresponding to the bit rate
to BRR1. This is not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set the
TE bit or RE bit in SCR1 to 1. Also set the
RIE, TIE, TEIE, and MPIE bits.
Setting the TE and RE bits enables the
SO1 and SI1 pins to be used.
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR1 to 1,
and set RIE, TIE, TEIE,
and MPIE bits
[4]
<Initialization completed>
Figure 22.4 Sample SCI Initialization Flowchart
Rev.2.00 Jan. 15, 2007 page 420 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
⎯ Serial Data Transmission (Asynchronous Mode)
Figure 22.5 shows a sample flowchart for serial transmission.
The following procedure should be used for serial data transmission.
[1]
Initialization
Start transmission
Read TDRE flag in SSR1
[1]
No
[1] SCI initialization:
The SO1 pin is automatically designated as
the transmit data output pin.
[2] SCI status check and transmit data write:
Read SSR and check that the TDRE flag is
set to 1, then write transmit data to TDR1
and clear the TDRE flag to 0.
[3] Serial transmission continuation procedure:
To continue serial transmission, read 1
from the TDRE flag to confirm that writing is
possible, then write data to TDR1, and then
clear the TDRE flag to 0.
TDRE = 1
Yes
Write transmit data to TDR1 and
clear TDRE flag in SSR to 0
[4] Break output at the end of serial
transmission:
To output a break in serial transmission, set
PCR for the port corresponding to the SO1
pin to 1, clear PDR to 0, then clear the TE
bit in SCR1 to 0.
No
All data transmitted?
Yes
[3]
Read TEND flag in SSR1
No
TEND = 1
Yes
No
Break output?
[4]
Yes
Clear PDR to 0
and set PCR to 1
Clear TE bit in SCR1 to 0
< End >
Figure 22.5 Sample Serial Transmission Flowchart
Rev.2.00 Jan. 15, 2007 page 421 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written
to TDR1, and transfers the data from TDR1 to TSR1.
2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
The serial transmit data is sent from the SO1 pin in the following order.
a. Start bit:
One 0-bit is output.
b. Transmit data:
8-bit or 7-bit data is output in LSB-first order.
c. Parity bit or multiprocessor bit:
One parity bit (even or odd parity), or one multiprocessor bit is output.
A format in which neither a parity bit nor a multiprocessor bit is output can also be
selected.
d. Stop bit(s):
One or two 1-bits (stop bits) are output.
e. Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, the data is transferred from TDR1 to TSR1, the stop bit is
sent, and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the stop bit is sent, and then the
mark state is entered in which 1 is output continuously. If the TEIE bit in SCR1 is set to 1 at
this time, a TEI interrupt request is generated.
Rev.2.00 Jan. 15, 2007 page 422 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
Figure 22.6 shows an example of the operation for transmission in asynchronous mode.
1
Data
Start
bit
0
D0
D1
Parity Stop
bit
bit
D7
0/1
1
Data
Start
bit
0
D0
D1
Parity
bit
D7
0/1
Stop
bit
1
Idle state
1
(mark state)
TDRE
TEND
TXI interrupt Data written to TDR1 and
request
TDRE flag cleared to 0
generated
in TXI interrupt handling
routine
TXI interrupt request
generated
TEI interrupt request
generated
1 frame
Figure 22.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev.2.00 Jan. 15, 2007 page 423 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
⎯ Serial Data Reception (Asynchronous Mode)
Figures 22.7 and 22.8 show sample flowcharts for serial reception.
The following procedure should be used for serial data reception.
[1] SCI initialization:
The SI1 pin is automatically designated as
the receive data input pin.
[1]
Initialization
Start reception
Read ORER, PER,
FER flags in SSR1
[2]
Yes
PER ∨ FER ∨ ORER = 1
[3]
No
Error handling
[2][3] Receive error handling and break
detection:
If a receive error occurs, read the ORER,
PER, and FER flags in SSR1 to identify the
error. After performing the appropriate
error handling, ensure that the ORER,
PER, and FER flags are all cleared to 0.
Reception cannot be resumed if any of
these flags are set to 1. In the case of a
framing error, a break can be detected by
reading the value of the input port
corresponding to the SI1 pin.
(Continued on next page)
Read RDRF flag in SSR1
[4]
No
RDRF = 1
[4] SCI status check and receive data read:
Read SSR1 and check that RDRF = 1, then
read the receive data in RDR1 and clear
the RDRF flag to 0. Transition of the RDRF
flag from 0 to 1 can also be identified by an
RXI interrupt.
[5] Serial reception continuation procedure:
To continue serial reception, before the
stop bit for the current frame is received,
read the RDRF flag, read RDR1, and clear
the RDRF flag to 0.
Yes
Read receive data in RDR1, and clear
RDRF flag in SSR1 to 0
No
All data received?
[5]
Yes
Clear RE bit in SCR1 to 0
< End >
Figure 22.7 Sample Serial Reception Data Flowchart (1)
Rev.2.00 Jan. 15, 2007 page 424 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
[3]
Error handling
No
ORER = 1
Yes
Overrun error handling
No
FER = 1
Yes
Yes
Break?
No
Framing error handling
Clear RE bit in SCR1 to 0
No
PER = 1
Yes
Parity error handling
Clear ORER, PER, and FER
flags in SSR1 to 0
< End >
Figure 22.8 Sample Serial Reception Data Flowchart (2)
Rev.2.00 Jan. 15, 2007 page 425 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
In serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in RSR1 in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks.
a. Parity check:
The SCI checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set in the O/E bit in SMR1.
b. Stop bit check:
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
c. Status check:
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be
transferred from RSR1 to RDR1.
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored
in RDR1.
If a receive error* is detected in the error check, the operation is as shown in table 22.11.
4. If the RIE bit in SCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full
interrupt (RXI) request is generated.
Also, if the RIE bit in SCR1 is set to 1 when the ORER, PER, or FER flag changes to 1, a
receive-error interrupt (ERI) request is generated.
Note: * Subsequent receive operations cannot be performed when a receive error has occurred.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be
cleared to 0.
Table 22.11 Receive Errors and Conditions for Occurrence
Receive Error
Abbrev.
Occurrence Condition
Data Transfer
Overrun error
ORER
When the next data reception is
completed while the RDRF flag
in SSR1 is set to 1
Receive data is not transferred
from RSR1 to RDR1
Framing error
FER
When the stop bit is 0
Receive data is transferred
from RSR1 to RDR1
Parity error
PER
When the received data differs
from the parity (even or odd) set
in SMR1
Receive data is transferred
from RSR1 to RDR1
Rev.2.00 Jan. 15, 2007 page 426 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
Figure 22.9 shows an example of the operation for reception in asynchronous mode.
1
Data
Start
bit
0
D0
D1
Parity Stop
bit
bit
D7
0/1
1
Data
Start
bit
0
D0
D1
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
RDRF
FER
RXI interrupt RDR1 data read
and RDRF flag
request
cleared to 0 in
generation
RXI interrupt
handling routine
ERI interrupt request
generated by framing
error
1 frame
Figure 22.9 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
22.3.3
Multiprocessor Communication Function
The multiprocessor communication function performs serial communication using a
multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous
mode. Use of this function enables data transfer to be performed among a number of processors
sharing transmission lines.
When multiprocessor communication is carried out, each receiving station is addressed by a
unique ID code.
The serial communication cycle consists of two component cycles: an ID transmission cycle
which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used
to differentiate between the ID transmission cycle and the data transmission cycle.
The transmitting station first sends the ID of the receiving station with which it wants to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added.
The receiving station skips the data until data with a 1 multiprocessor bit is sent.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID does
not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this
way, data communication is carried out among a number of processors.
Figure 22.10 shows an example of inter-processor communication using a multiprocessor format.
Rev.2.00 Jan. 15, 2007 page 427 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
1. Data Transfer Format
There are four data transfer formats.
When a multiprocessor format is specified, the parity bit specification is invalid.
For details, see table 22.10.
2. Clock
See the section on asynchronous mode.
Transmitting
station
Serial communication line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'AA
H'01
(MPB = 1)
ID transmission cycle:
receiving station
specification
(MPB = 0)
Data transmission cycle:
data transmission to
receiving station
specified by ID
Legend:
MPB : Multiprocessor bit
Figure 22.10 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
3. Data Transfer Operations
a. Multiprocessor Serial Data Transmission
Figure 22.11 shows a sample flowchart for multiprocessor serial data transmission.
The following procedure should be used for multiprocessor serial data transmission.
Rev.2.00 Jan. 15, 2007 page 428 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
[1]
Initialization
Start transmission
Read TDRE flag in SSR1
[2]
[1] SCI initialization:
The SO1 pin is automatically designated as
the transmit data output pin.
[2] SCI status check and transmit data write:
Read SSR1 and check that the TDRE flag
is set to 1, then write transmit data to
TDR1. Set the MPBT bit in SSR1 to 0 or 1.
Finally, clear the TDRE flag to 0.
No
TDRE = 1
[3] Serial transmission continuation procedure:
To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR1,
and then clear the TDRE flag to 0.
Yes
Write transmit data to TDR1
and set MPBT bit in SSR1
[4] Break output at the end of serial
transmission:
To output a break in serial transmission, set
the port PCR to 1, clear PDR to 0, then
clear the TE bit in SCR1 to 0.
Clear TDRE flag to 0
No
Transmission end?
[3]
Yes
Read TEND flag in SSR1
No
TEND = 1
Yes
No
Break output?
[4]
Yes
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR1 to 0
< End >
Figure 22.11 Sample Multiprocessor Serial Transmission Flowchart
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Section 22 Serial Communication Interface 1 (SCI1)
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written
to TDR1, and transfers the data from TDR1 to TSR1.
2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
The serial transmit data is sent from the SO2 pin in the following order.
a. Start bit:
One 0-bit is output.
b. Transmit data:
8-bit or 7-bit data is output in LSB-first order.
c. Multiprocessor bit
One multiprocessor bit (MPBT value) is output.
d. Stop bit(s):
One or two 1-bits (stop bits) are output.
e. Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, data is transferred from TDR1 to TSR1, the stop bit is sent,
and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the stop bit is sent, and then the
mark state is entered in which 1 is output continuously. If the TEIE bit in SCR1 is set to 1 at
this time, a transmit-end interrupt (TEI) request is generated.
Rev.2.00 Jan. 15, 2007 page 430 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
Figure 22.12 shows an example of SCI operation for transmission using a multiprocessor format.
1
0
Multiprocessor Stop
bit
bit
Data
Start
bit
D0
D1
D7
0/1
1
0
Multiprocessor Stop
bit
bit 1
Data
Start
bit
D0
D1
D7
0/1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt Data written to TDR1 and
TDRE flag cleared to 0
request
in TXI interrupt handling
general
routine
TXI interrupt request
generated
TEI interrupt
request
generated
1 frame
Figure 22.12 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
b. Multiprocessor Serial Data Reception
Figures 22.13 and 22.14 show sample flowcharts for multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
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Section 22 Serial Communication Interface 1 (SCI1)
Initialization
[1]
Start reception
Set MPIE bit in SCR1 to 1
[2]
Read ORER and FER flags in SSR1
FER ∨ ORER = 1
Yes
No
Read RDRF flag in SSR1
[3]
[1] SCI initialization:
The SI1 pin is automatically designated as
the receive data input pin.
[2] ID reception cycle:
Set the MPIE bit in SCR1 to 1.
[3] SCI status check, ID reception and
comparison:
Read SSR1 and check that the RDRF flag
is set to 1, then read the receive data in
RDR1 and compare it with this station's ID.
If the data is not this station's ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
If the data is this station's ID, clear the
RDRF flag to 0.
No
RDRF = 1
[4] SCI status check and data reception:
Read SSR1 and check that the RDRF flag
is set to 1, then read the data in RDR1.
Yes
Read receive data in RDR1
No
This station's ID?
Yes
Read ORER and FER flags in SSR1
FER ∨ ORER = 1
Yes
[5] Receive error handling and break
detectioon:
If a receive error occurs, read the ORER
and FER flags in SSR1 to identify the error.
After performing the appropriate error
handling, ensure that the ORER and FER
flags are both cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can
be detected by reading the SI1 in value.
No
Read RDRF flag in SSR1
[4]
No
RDRF = 1
Yes
Read receive data in RDR1
No
All data received?
[5]
Error handling
Yes
Clear RE bit in SCR1 to 0
(Continued on
next page)
< End >
Figure 22.13 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 22 Serial Communication Interface 1 (SCI1)
[5]
Error handling
No
ORER = 1
Yes
Overrun error handling
No
FER = 1
Yes
Yes
Break?
No
Framing error handling
Clear RE bit in SCR1 to 0
Clear ORER, PER, and FER
flags in SSR1 to 0
< End >
Figure 22.14 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 22 Serial Communication Interface 1 (SCI1)
Figure 22.15 shows an example of SCI operation for multiprocessor format reception.
1
Data (ID1)
Start
bit
0
Stop
MPB bit
D0
D1
D7
1
1
Data (Data 1)
Start
bit
0
Stop
MPB bit
D0
D1
D7
0
1
1 Idle state
(mark state)
MPIE
RDRF
RDR1
value
ID1
MPIE = 0
RXI interrupt
request (multiprocessor
interrupt)
generated
RDR1 data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
If not this station's
ID, MPIE bit is set
to 1 again
RXI interrupt request
is not generated, and
RDR1 retains its state
(a) Data does not match station's ID
1
Data (ID2)
Start
bit
0
Stop
MPB bit
D0
D1
D7
1
1
Data (Data 2)
Start
bit
0
Stop
MPB bit
D0
D1
D7
0
1
1 Idle state
(mark state)
MPIE
RDRF
RDR1
value
ID1
MPIE = 0
ID2
RXI interrupt
request (multiprocessor
interrupt)
generated
RDR1 data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
Matches this station's
ID, so reception continues,
and data is received in RXI
interrupt handling routine
(b) Data matches station's ID
Figure 22.15 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Rev.2.00 Jan. 15, 2007 page 434 of 1174
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Data2
MPIE bit set
to 1 again
Section 22 Serial Communication Interface 1 (SCI1)
22.3.4
Operation in Synchronous Mode
In synchronous mode, data is transmitted or received in synchronization with clock pulses, making
it suitable for high-speed serial communication.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication by use of a common clock. Both the transmitter and the receiver also have a
double-buffered structure, so that data can be read or written during transmission or reception,
enabling continuous data transfer.
Figure 22.16 shows the general format for synchronous serial communication.
One unit of transfer data (character or frame)
*
*
Synchronous
clock
MSB
LSB
Serial
data
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Don't care
Bit 7
Don't care
Note: * High except in continuous transfer
Figure 22.16 Data Format in Synchronous Communication
In synchronous serial communication, data on the transmission line is output from one falling edge
of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock.
In synchronous serial communication, one character consists of data output starting with the LSB
and ending with the MSB. After the MSB is output, the transmission line holds the MSB state.
In synchronous mode, the SCI receives data in synchronization with the rising edge of the serial
clock.
• Data Transfer Format
A fixed 8-bit data format is used.
No parity or multiprocessor bits are added.
Rev.2.00 Jan. 15, 2007 page 435 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
• Clock
Either an internal clock generated by the built-in baud rate generator or an external serial clock
input at the SCK pin can be selected, according to the setting of the C/A bit in SMR1 and the
CKE1 and CKE0 bits in SCR1. For details on SCI clock source selection, see table 22.9.
When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. When only receive operations are performed, however, the
serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform
receive operations in units of one character, select an external clock as the clock source.
• Data Transfer Operations
⎯ SCI Initialization (Synchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then
initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be
cleared to 0 before making the change using the following procedure. When the TE bit is
cleared to 0, the TDRE flag is set to 1 and TSR1 is initialized. Note that clearing the RE bit
to 0 does not change the settings of the RDRF, PER, FER, and ORER flags, or the contents
of RDR1.
Figure 22.17 shows a sample SCI initialization flowchart.
Rev.2.00 Jan. 15, 2007 page 436 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
[1] Set the clock selection in SCR1. Be sure to
clear bits RIE, TIE, TEIE, and MPIE, TE
and RE, to 0.
Start initialization
Clear TE and RE bits in SCR1 to 0
[2] Set the data transfer format in SMR1 and
SCMR1.
Set CKE1 and CKE0 bits in
SCR1 (TE, RE bits 0)
[1]
Set data transfer format
in SMR1 and SCMR1
[2]
Set value in BRR1
[3]
[3] Write a value corresponding to the bit rate
to BRR1. This is not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set the
TE bit or RE bit in SCR1 to 1.
Also set the RIE, TIE, TEIE, and MPIE bits.
Setting the TE and RE bits enables the
SO1 and SI1 pins to be used.
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR1 to 1,
and set RIE, TIE, TEIE, and MPIE
bits
[4]
<Transfer start>
Note: For simultaneous data transmit and receive operations, the TE and RE bits must be cleared
to 0 or set to 1 simultaneously.
Figure 22.17 Sample SCI Initialization Flowchart
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Section 22 Serial Communication Interface 1 (SCI1)
⎯ Serial Data Transmission (Synchronous Mode)
Figure 22.18 shows a sample flowchart for serial transmission.
The following procedure should be used for serial data transmission.
[1]
Initialization
Start transmission
Read TDRE flag in SSR1
[2]
No
[1] SCI initialization:
The SO1 pin is automatically designated as
the transmit data output pin.
[2] SCI status check and transmit data write:
Read SSR1 and check that the TDRE flag
is set to 1, then write transmit data to TDR1
and clear the TDRE flag to 0.
[3] Serial transmission continuation procedure:
To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR1,
and then clear the TDRE flag to 0.
TDRE = 1
Yes
Write transmit data to TDR1 and
clear TDRE flag in SSR1 to 0
No
All data transmitted?
[3]
Yes
Read TEND flag in SSR1
No
TEND = 1
Yes
Clear TE bit in
SCR1 to 0
< End >
Figure 22.18 Sample Serial Transmission Flowchart
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Section 22 Serial Communication Interface 1 (SCI1)
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written
to TDR1, and transfers the data from TDR1 to TSR1.
2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is
generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an
external clock has been specified, data is output synchronized with the input clock.
The serial transmit data is sent from the SO1 pin starting with the LSB (bit 0) and ending with
the MSB (bit 7).
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR1 to TSR1, and serial
transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the MSB (bit 7) is sent, and the
SO1 pin maintains its state.
If the TEIE bit in SCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is
generated.
4. After completion of serial transmission, the SCK pin is held in a constant state.
Figure 22.19 shows an example of SCI operation in transmission.
Transfer
direction
Synchronous
clock
Serial
data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request
generated
Data written to TDR1
and TDRE flag cleared
to 0 in TXI interrupt
handling routine
TXI interrupt
request
generated
TEI interrupt
request
generated
1 frame
Figure 22.19 Example of SCI Operation in Transmission
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Section 22 Serial Communication Interface 1 (SCI1)
⎯ Serial Data Reception (Synchronous Mode)
Figure 22.20 shows a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
When changing the operating mode from asynchronous to synchronous, be sure to check
that the ORER, PER, and FER flags are all cleared to 0.
The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor
receive operations will be possible.
Rev.2.00 Jan. 15, 2007 page 440 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
Initialization
[1]
[1] SCI initialization:
The SI1 pin is automatically designated as
the receive data input pin.
Start reception
[2]
Read ORER flag in SSR1
Yes
ORER = 1
No
[2][3] Receive error handling:
IF a receive error occurs, read the ORER
flag in SSR1, and after performing the
appropriate error handling, clear the ORER
flag to 0. Transfer cannot be resumed if
the ORER flag is set to 1.
[3]
Error handling
(Continued below)
Read RDRF flag in SSR1
[4] SCI status check and receive data read:
Read SSR1 and check that the RDRF flag
is set to 1, then read the receive data in
RDR1 and clear the RDRF flag to 0.
Transition of the RDRF flag from 0 to 1 can
also be identified by and RXI interrupt.
[4]
[5] Serial reception continuation procedure:
To continue serial reception, before the
MSB (bit 7) of the current frame is received,
finish reading the RDRF flag, reading
RDR1, and clearing the RDRF flag to 0.
No
RDRF = 1
Yes
Read receive data in RDR1,
and clear RDRF flag in SSR1 to 0
No
All data received?
[5]
Yes
Clear RE bit in SCR1 to 0
< End >
[3]
Error handling
Overrun error handling
Clear ORER flag in
SSR1 to 0
< End >
Figure 22.20 Sample Serial Reception Flowchart
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Section 22 Serial Communication Interface 1 (SCI1)
In serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with serial clock input or output.
2. The received data is stored in RSR1 in LSB-to-MSB order.
After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be
transferred from RSR1 to RDR1.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR1. If a
receive error is detected in the error check, the operation is as shown in table 22.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
3. If the RIE bit in SCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full
interrupt (RXI) request is generated.
Also, if the RIE bit in SCR1 is set to 1 when the ORER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
Figure 22.21 shows an example of SCI operation in reception.
Synchronous
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt
request
generated
RDR1 data read and
RDRF flag cleared to 0
in RXI interrupt
handling routine
RXI interrupt
request
generated
ERI interrupt request
generated by
overrun error
1 frame
Figure 22.21 Example of SCI Operation in Reception
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Section 22 Serial Communication Interface 1 (SCI1)
⎯ Simultaneous Serial Data Transmission and Reception (Synchronous Mode)
Figure 22.22 shows a sample flowchart for simultaneous serial transmit and receive
operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations.
Initialization
[1] SCI initialization:
The SO1 pin is designated as the transmit
data output pin, and the SI1 pin is
designated as the receive data input pin,
enabling simultaneous transmit and receive
operations.
[1]
Start transfer
Read TDRE flag in SSR1
[2]
No
[2] SCI status check and transmit data write:
Read SSR1 and check that the TDRE flag
is set to 1, then write transmit data to TDR1
and clear the TDRE flag to 0.
Transition of the TDRE flag from 0 to 1 can
also be identified by a TXI interrupt.
TDRE = 1
Yes
Write transmit data to TDR1 and
clear TDRE flag in SSR1 to 0
Read ORER flag in SSR1
ORER = 1
No
Read RDRF flag in SSR1
Yes
[3]
Error handling
[4]
No
RDRF = 1
Yes
Read receive data in RDR1, and
clear RDRF flag in SSR1 to 0
No
All data received?
Yes
Clear TE and RE
bits in SCR1 to 0
< End >
[5]
[3] Receive error handling:
If a receive error occurs, read the ORER
flag in SSR1, and after performing the
appropriate error handling, clear the ORER
flag to 0. Transmission/reception cannot
be resumed if the ORER flag is set to 1.
[4] SCI status check and receive data read:
Read SSR1 and check that the RDRF flag
is set to 1, then read the receive data in
RDR1 and clear the RDRF flag to 0.
Transition of the RDRF flag from 0 to 1 can
also be identified by an RXI interrupt.
[5] Serial transmission/reception continuation
procedure:
To continue serial transmission/reception,
before the MSB (bit 7) of the current frame
is received, finish reading the RDRF flag,
reading RDR1, and clearing the RDRF flag
to 0. Also before the MSB (bit 7) of the
current frame is transmitted, read 1 from
the TDRE flag to confirm that writing is
possible, then write data to TDR1 and clear
the TDRE flag to 0.
Note: When switching from transmit or receive operation
to simultaneous transmit and receive operations, first
clear the TE bit and RE bit to 0, then set both these
bits to 1 simultaneously.
Figure 22.22 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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Section 22 Serial Communication Interface 1 (SCI1)
22.4
SCI Interrupts
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)
request. Table 22.12 shows the interrupt sources and their relative priorities. Individual interrupt
sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR1. Each kind of
interrupt request is sent to the interrupt controller independently.
When the TDRE flag in SSR1 is set to 1, a TXI interrupt request is generated. When the TEND
flag in SSR1 is set to 1, a TEI interrupt request is generated.
When the RDRF flag in SSR1 is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR1 is set to 1, an ERI interrupt request is generated.
Table 22.12 SCI Interrupt Sources
Channel
Interrupt Source
Description
Priority
1
ERI
Interrupt by receive error (ORER, FER, or PER)
High
RXI
Interrupt by receive data register full (RDRF)
TXI
Interrupt by transmit data register empty (TDRE)
TEI
Interrupt by transmit end (TEND)
Low
The TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt will have priority for acceptance,
and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be
accepted in this case.
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Section 22 Serial Communication Interface 1 (SCI1)
22.5
Usage Notes
The following points should be noted when using the SCI.
• Relation between Writes to TDR1 and the TDRE Flag
The TDRE flag in SSR1 is a status flag that indicates that transmit data has been transferred
from TDR1 to TSR1. When the SCI transfers data from TDR1 to TSR1, the TDRE flag is set
to 1.
Data can be written to TDR1 regardless of the state of the TDRE flag. However, if new data is
written to TDR1 when the TDRE flag is cleared to 0, the data stored in TDR1 will be lost since
it has not yet been transferred to TSR1. It is therefore essential to check that the TDRE flag is
set to 1 before writing transmit data to TDR1.
• Operation when Multiple Receive Errors Occur Simultaneously
If a number of receive errors occur at the same time, the state of the status flags in SSR1 is as
shown in table 22.13. If there is an overrun error, data is not transferred from RSR1 to RDR1,
and the receive data is lost.
Table 22.13 State of SSR1 Status Flags and Transfer of Receive Data
SSR1 Status Flags
RDRF
ORER
FER
PER
Receive Data Transfer
RSR1 to RDR1
Receive Error Status
1
1
0
0
X
Overrun error
0
0
1
0
Framing error
0
0
0
1
Parity error
1
1
1
0
X
Overrun error + framing error
1
1
0
1
X
Overrun error + parity error
0
0
1
1
1
1
1
1
Notes:
Framing error + parity error
X
Overrun error + framing error
+ parity error
: Receive data is transferred from RSR1 to RDR1.
X: Receive data is not transferred from RSR1 to RDR1.
• Break Detection and Processing
When framing error (FER) detection is performed, a break can be detected by reading the SI1
pin value directly. In a break, the input from the SI1 pin becomes all 0s, and so the FER flag is
set, and the parity error flag (PER) may also be set.
Note that, since the SCI continues the receive operation after receiving a break, even if the
FER flag is cleared to 0, it will be set to 1 again.
Rev.2.00 Jan. 15, 2007 page 445 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
• Sending a Break
The SO1 pin has a dual function as an I/O port whose direction (input or output) is determined
by PDR and PCR. This can be used to send a break.
Between serial transmission initialization and setting of the TE bit to 1, the mark state is
replaced by the value of PDR (the pin does not function as the SO1 pin until the TE bit is set to
1). Consequently, PCR and PDR for the port corresponding to the SO1 pin are first set to 1.
To send a break during serial transmission, first clear PDR to 0, then clear the TE bit to 0.
When the TE bit is cleared to 0, the transmitter is initialized regardless of the current
transmission state, the SO1 pin becomes an I/O port, and 0 is output from the SO1 pin.
• Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1,
even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission.
Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
• Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the
transfer rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and
performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock. This is illustrated in figure 22.23.
16 clocks
8 clocks
7
0
15 0
7
15 0
Internal basic
clock
Receive data
Start bit
D0
Synchronization
sampling timing
Data sampling
timing
Figure 22.23 Receive Data Sampling Timing in Asynchronous Mode
Rev.2.00 Jan. 15, 2007 page 446 of 1174
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D1
Section 22 Serial Communication Interface 1 (SCI1)
Thus the reception margin in asynchronous mode is given by formula (1) below.
1
M = | (0.5 –
) – (L – 0.5) F –
2N
| D – 0.5 |
N
(1 + F) | × 100%
... Formula (1)
Where M
N
D
L
F
: Reception margin (%)
: Ratio of bit rate to clock (N = 16)
: Clock duty (D = 0 to 1.0)
: Frame length (L = 9 to 12)
: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by
formula (2) below.
When D = 0.5 and F = 0,
M = (0.5 –
1
2 × 16
) × 100%
= 46.875%
... Formula (2)
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
• Operation in Case of Mode Transition
⎯ Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode, standby mode, watch mode, subactive mode, or subsleep mode transition.
TSR1, TDR1, and SSR1 are reset. The output pin states in module stop mode, standby
mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and
becomes high-level output after the relevant mode is cleared. If a transition is made during
transmission, the data being transmitted will be undefined. When transmitting without
changing the transmit mode after the relevant mode is cleared, transmission can be started
by setting TE to 1 again, and performing the following sequence: SSR1 read → TDR1
write → TDRE clearance. To transmit with a different transmit mode after clearing the
relevant mode, the procedure must be started again from initialization. Figure 22.24 shows
a sample flowchart for mode transition during transmission. Port pin states are shown in
figures 22.25 and 22.26.
Rev.2.00 Jan. 15, 2007 page 447 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
⎯ Reception
Receive operation should be stopped (by clearing RE to 0) before making a module stop
mode, standby mode, watch mode, subactive mode, or subsleep mode transition. RSR1,
RDR1, and SSR1 are reset. If a transition is made without stopping operation, the data
being received will be invalid. To continue receiving without changing the reception mode
after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a
different receive mode, the procedure must be started again from initialization.
Figure 22.27 shows a sample flowchart for mode transition during reception.
<Transmission>
No
All data
transmitted?
[1]
Yes
Read TEND flag in SSR1
[2] If TIE and TEIE are set to 1, clear
them to 0 in the same way.
No
TEND = 1
[1] Data being transmitted is interrupted.
After exiting software standby mode,
etc., normal CPU transmission is
possible by setting TE to 1, reading
SSR1, writing TDR1, and clearing
TDRE to 0.
Yes
TE = 0
[3] Includes module stop mode, watch
mode, subactive mode, and subsleep
mode.
[2]
Transition to standby
mode, etc.
[3]
Exit from standby
mode, etc.
Change
operating mode?
No
Yes
Initialization
TE = 1
<Start of transmission>
Figure 22.24 Sample Flowchart for Mode Transition during Transmission
Rev.2.00 Jan. 15, 2007 page 448 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
Transition
to standby
End of
transmission
Start of transmission
Exit from
standby
TE bit
Port input/output
SCK1 output pin
SO1 output pin Port input/output
High output
Port
Start
Stop
Port input/output
Port
SCI TxD output
High output
SCI TxD
output
Figure 22.25 Asynchronous Transmission Using Internal Clock
Start of transmission
End of
transmission
Transition
to standby
Exit from
standby
TE bit
Port input/output
SCK1 output pin
SO1 output pin Port input/output
Last TxD bit held
Marking output
Port
SCI TxD output
Port input/output
Port
High output*
SCI TxD
output
Note: * Initialized by software standby.
Figure 22.26 Synchronous Transmission Using Internal Clock
Rev.2.00 Jan. 15, 2007 page 449 of 1174
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Section 22 Serial Communication Interface 1 (SCI1)
<Reception>
Read RDRF flag in SSR1
RDRF = 1
No
[1]
[1] Receive data being received
becomes invalid.
[2]
[2] Includes module stop mode,
watch mode, subactive mode,
and subsleep mode.
Yes
Read receive data in RDR1
RE = 0
Transition to standby
mode, etc.
Exit from standby
mode, etc.
Change
operating mode?
No
Yes
Initialization
RE = 1
<Start of reception>
Figure 22.27 Sample Flowchart for Mode Transition during Reception
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2
Section 23 I C Bus Interface (IIC)
2
Section 23 I C Bus Interface (IIC)
23.1
Overview
2
This LSI incorporates a 2-channel I C bus interface (H8S/2197S and H8S/2196S: 1 channel).
2
2
The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus)
2
interface functions. The register configuration that controls the I C bus differs partly from the
Philips configuration, however.
2
Each I C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer
data, saving board and connector space.
23.1.1
Features
• Selection of addressing format or non-addressing format
⎯ I C bus format: addressing format with acknowledge bit, for master/slave operation
2
⎯ Serial format: non-addressing format without acknowledge bit, for master operation only
• Conforms to Philips I C bus interface (I C bus format)
2
2
• Two ways of setting slave address (I C bus format)
2
• Start and stop conditions generated automatically in master mode (I C bus format)
2
• Selection of acknowledge output levels when receiving (I C bus format)
2
• Automatic loading of acknowledge bit when transmitting (I C bus format)
2
• Wait function in master mode (I C bus format)
2
⎯ A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
• Wait function in slave mode (I C bus format)
2
⎯ A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
• Three interrupt sources
⎯ Data transfer end (including transmission mode transition with I C bus format and address
reception after loss of master arbitration)
2
⎯ Address match: when any slave address matches or the general call address is received in
2
slave receive mode (I C bus format)
⎯ Stop condition detection
• Selection of 16 internal clocks (in master mode)
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2
Section 23 I C Bus Interface (IIC)
• Direct bus drive (with SCL and SDA pins)
⎯ Four pins P26/SCL0, P25/SDA0, P24/SCL1 and P23/SDA1 (normally CMOS pins)
function as NMOS-only outputs when the bus drive function is selected.
23.1.2
Block Diagram
2
Figure 23.1 shows a block diagram of the I C bus interface.
Figure 23.2 shows an example of I/O pin connections to external circuits. I/O pins are driven only
by NMOS and apparently function as NMOS open-drain outputs. However, applicable voltages to
input pins depend on the power (Vcc) voltage of this LSI.
PS
SCL
Noise
canceller
ICCR
Clock
control
ICMR
Bus state
decision
circuit
SDA
ICSR
Arbitration
decision
circuit
ICDRT
Output data
control
circuit
ICDRS
Internal data bus
φ
ICDRR
Noise
canceler
Address
comparator
SAR, SARX
Legend:
ICCR
ICMR
ICSR
ICDR
SAR
SARX
PS
Interrupt
generator
: I2C control register
: I2C mode register
: I2C status register
: I2C data register
: Slave address register
: Slave address register X
: Prescaler
2
Figure 23.1 Block Diagram of I C Bus Interface
Rev.2.00 Jan. 15, 2007 page 452 of 1174
REJ09B0329-0200
Interrupt
request
2
Section 23 I C Bus Interface (IIC)
VCC
SCLin
SCL
SCL
SDA
SDA
SCLout
SDAin
SCLin
This LSI
SCL
SDA
(Master)
SCL
SDA
SDAout
SCLin
SCLout
SCLout
SDAin
SDAin
SDAout
SDAout
(Slave 1)
(Slave 2)
2
Figure 23.2 I C Bus Interface Connections (Example: This Chip as Master)
23.1.3
Pin Configuration
2
Table 23.1 summarizes the input/output pins used by the I C bus interface.
2
Table 23.1 I C Bus Interface Pins
Channel
Name
Abbrev.* I/O
0
Serial clock pin
SCL0
Input/output IIC0 serial clock input/output
Serial data pin
SDA0
Input/output IIC0 serial data input/output
Formatless serial clock pin
SYNCI
Input
Serial clock pin
SCL1
Input/output IIC1 serial clock input/output
Serial data pin
SDA1
Input/output IIC1 serial data input/output
1
Notes: *
Function
IIC0 formatless serial clock input
In this section, channel numbers in the abbreviated register names are omitted; SCL0
and SCL1 are collectively referred to as SCL, and SDA0 and SDA1 as SDA.
Channel 0 is not provided (incorporated in) for the H8S/2197S and H8S/2196S.
Rev.2.00 Jan. 15, 2007 page 453 of 1174
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2
Section 23 I C Bus Interface (IIC)
23.1.4
Register Configuration
2
Table 23.2 summarizes the registers of the I C bus interface.
Table 23.2 Register Configuration
Abbrev.
R/W
Initial Value
1
Address*
2
ICCR0
R/W
H'01
H'D0E8
2
ICSR0
R/W
H'00
H'D0E9
2
ICDR0
R/W
⎯
I C bus mode register
2
ICMR0
R/W
H'00
2
H'D0EE*
2
H'D0EF*
Slave address register
SAR0
R/W
H'00
H'D0EF*
Second slave address register
SARX0
R/W
H'01
H'D0EE*
2
ICCR1
R/W
H'01
H'D158
2
ICSR1
R/W
H'00
H'D159
2
ICDR1
R/W
⎯
I C bus mode register
ICMR1
R/W
H'00
2
H'D15E*
2
H'D15F*
Slave address register
SAR1
R/W
H'00
H'D15F*
Second slave address register
SARX1
R/W
H'01
2
H'D15E*
DDC switch register
DDCSWR
R/W
H'0F
H'D0E5
Module stop control register
MSTPCRH R/W
H'FF
H'FFEC
MSTPCRL
H'FF
H'FFED
Channel
Name
0*
I C bus control register
3
I C bus status register
I C bus data register
1
I C bus control register
I C bus status register
I C bus data register
2
0 and 1
Notes: 1. Lower 16 bits of the address.
2
2. The registers that can be read from or written to depend on the ICE bit in the I C bus
control register. The slave address registers can be accessed when ICE = 0, and the
2
I C bus mode registers can be accessed when ICE = 1.
3. Channel 0 is not provided (incorporated in) for the H8S/2197S and H8S/2196S.
Rev.2.00 Jan. 15, 2007 page 454 of 1174
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2
2
2
2
Section 23 I C Bus Interface (IIC)
23.2
Register Descriptions
23.2.1
I C Bus Data Register (ICDR)
2
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
ICDR7
ICDR6
ICDR5
ICDR4
ICDR3
ICDR2
ICDR1
ICDR0
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICDRR
7
6
5
4
3
2
1
0
ICDRR7
ICDRR6
ICDRR5
ICDRR4
ICDRR3
ICDRR2
ICDRR1
ICDRR0
Initial value :
—
—
—
—
—
—
—
—
R/W :
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
ICDRS7
ICDRS6
ICDRS5
ICDRS4
ICDRS3
ICDRS2
ICDRS1
ICDRS0
Initial value :
—
—
—
—
—
—
—
—
R/W :
—
—
—
—
—
—
—
—
7
6
5
4
3
2
1
0
Bit :
ICDRS
Bit :
ICDRT
Bit :
ICDRT7
ICDRT6
ICDRT5
ICDRT4
ICDRT3
ICDRT2
ICDRT1
ICDRT0
Initial value :
—
—
—
—
—
—
—
—
R/W :
W
W
W
W
W
W
W
W
TDRE, RDRF (Internal flag)
—
—
TDRE
RDRF
Initial value :
0
0
R/W :
—
—
Bit :
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or
written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the
Rev.2.00 Jan. 15, 2007 page 455 of 1174
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2
Section 23 I C Bus Interface (IIC)
three registers are performed automatically in coordination with changes in the bus state, and
affect the status of internal flags such as TDRE and RDRF.
2
After transmission/reception of one frame of data using ICDRS, if the I C bus is in transmit mode
and the next data is in ICDRT (the TDRE flag is 0), data is transferred automatically from ICDRT
2
to ICDRS. After transmission/reception of one frame of data using ICDRS, if the I C bus is in
receive mode and no previous data remains in ICDRR (the RDRF flag is 0), data is transferred
automatically from ICDRS to ICDRR.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
ICDR is assigned to the same address as SARX, and can be written and read only when the ICE
bit is set to 1 in ICCR.
The value of ICDR is undefined after a reset.
The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the
TDRE and RDRF flags affects the status of the interrupt flags.
TDRE
Description
0
The next transmit data is in ICDR (ICDRT), or transmission cannot be started
[Clearing conditions]
(Initial value)
1. When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1)
2. When a stop condition is detected in the bus line state after a stop condition is
2
issued with the I C bus format or serial format selected
2
3. When a stop condition is detected with the I C bus format selected
4. In receive mode (TRS = 0)
(A 0 write to TRS during transfer is valid after reception of a frame containing an
acknowledge bit)
1
The next transmit data can be written in ICDR (ICDRT)
[Setting conditions]
1. In transmit mode (TRS = 1), when a start condition is detected in the bus line
2
state after a start condition is issued in master mode with the I C bus format or
serial format selected
2. In transmit mode (TRS = 1) when formatless transfer is selected
3. When data is transferred from ICDRT to ICDRS
(Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is
empty)
4. When a switch is made from receive mode (TRS = 0) to transmit mode (TRS = 1)
after detection of a start condition
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Section 23 I C Bus Interface (IIC)
RDRF
Description
0
The data in ICDR (ICDRR) is invalid
(Initial value)
[Clearing condition]
When ICDR (ICDRR) receive data is read in receive mode
1
The ICDR (ICDRR) receive data can be read
[Setting condition]
When data is transferred from ICDRS to ICDRR
(Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and
RDRF = 0)
23.2.2
Slave Address Register (SAR)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SAR is assigned to the same
address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SAR is initialized to H'00 by a reset.
Bits 7 to 1⎯Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,
2
differing from the addresses of other slave devices connected to the I C bus.
Bit 0⎯Format Select (FS): Used together with the FSX bit in SARX and the SW bit in
DDCSWR to select the communication format.
• I C bus format: addressing format with acknowledge bit
2
• Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
• Formatless transfer (only for channel 0): non-addressing with or without an acknowledge bit
and without detection of start or stop condition, for slave mode only.
The FS bit also specifies whether or not SAR slave address recognition is performed in slave
mode.
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Section 23 I C Bus Interface (IIC)
DDCSWR
Bit 6
SAR
Bit 0
SARX
Bit 0
SW
FS
FSX
Operating Mode
0
0
0
I C bus format
1
I C bus format
2
•
1
0
1
•
SAR slave address recognized
•
SARX slave address ignored
0
0
1
1
0
1
Note:
*
(Initial value)
2
I C bus format
•
SAR slave address ignored
•
SARX slave address recognized
Synchronous serial format
•
1
SAR and SARX slave addresses recognized
2
SAR and SARX slave addresses ignored
Formatless transfer (start and stop conditions are not
detected)
•
With acknowledge bit
Formatless transfer* (start and stop conditions are not
detected)
•
Without acknowledge bit
Do not use this setting when automatically switching the mode from formatless transfer
2
to I C bus format by setting DDCSWR.
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Section 23 I C Bus Interface (IIC)
23.2.3
Second Slave Address Register (SARX)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
FSX
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the same
address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.
Bits 7 to 1⎯Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to
2
SVAX0, differing from the addresses of other slave devices connected to the I C bus.
Bit 0⎯Format Select X (FSX): Used together with the FX bit in SAR and the SW bit in
DDCSWR to select the communication format.
• I C bus format: addressing format with acknowledge bit
2
• Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
• Formatless transfer: non-addressing with or without an acknowledge bit and without detection
of start or stop condition, for slave mode only.
The FSX bit also specifies whether or not SARX slave address recognition is performed in slave
mode. For details, see the description of the FS bit in section 23.2.2, Slave Address Register
(SAR).
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Section 23 I C Bus Interface (IIC)
23.2.4
2
I C Bus Mode Register (ICMR)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
MLS
WAIT
CKS2
CKS1
CKS0
BC2
BC1
BC0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the master mode transfer clock frequency and
the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and
read only when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'00 by a reset.
Bit 7⎯MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or
LSB-first.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
2
Do not set this bit to 1 when the I C bus format is used.
Bit 7
MLS
Description
0
MSB-first
1
LSB-first
Rev.2.00 Jan. 15, 2007 page 460 of 1174
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(Initial value)
2
Section 23 I C Bus Interface (IIC)
Bit 6⎯Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data
2
and the acknowledge bit, in master mode with the I C bus format. When WAIT is set to 1, after the
fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins
(with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred
consecutively with no wait inserted.
The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the
WAIT setting.
The setting of this bit is invalid in slave mode.
Bit 6
WAIT
Description
0
Data and acknowledge bits transferred consecutively
1
Wait inserted between data and acknowledge bits
(Initial value)
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Section 23 I C Bus Interface (IIC)
Bits 5 to 3⎯Transfer Clock Select (CKS2 to CKS0): These bits, together with the IICX1 bit
(for channel 1) or IICX0 bit (for channel 0) in STCR, select the serial clock frequency in master
mode. They should be set according to the required transfer rate.
STCR
Bits 5, 6
Bit 5
Bit 4
Bit 3
IICX
CKS2
CKS1
CKS0
Clock
φ = 8 MHz
φ = 10 MHz
0
0
0
0
φ/28
286 kHz
357 kHz
1
φ/40
200 kHz
250 kHz
0
φ/48
167 kHz
208 kHz
1
φ/64
125 kHz
156 kHz
0
φ/80
100 kHz
125 kHz
1
φ/100
80.0 kHz
100 kHz
0
φ/112
71.4 kHz
89.3 kHz
1
φ/128
62.5 kHz
78.1 kHz
0
φ/56
143 kHz
179 kHz
1
φ/80
100 kHz
125 kHz
0
φ/96
83.3 kHz
104 kHz
1
φ/128
62.5 kHz
78.1 kHz
0
φ/160
50.0 kHz
62.5 kHz
1
φ/200
40.0 kHz
50.0 kHz
0
φ/224
35.7 kHz
44.6 kHz
1
φ/256
31.3 kHz
39.1 kHz
1
1
0
1
1
0
0
1
1
0
1
Rev.2.00 Jan. 15, 2007 page 462 of 1174
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Transfer Rate
2
Section 23 I C Bus Interface (IIC)
Bits 2 to 0⎯Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be
2
transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0),
the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made
during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000,
the setting should be made while the SCL line is low.
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the end of a data transfer, including the acknowledge bit.
Bit 2
Bit 1
Bit 0
Bits/Frame
BC2
BC1
BC0
Synchronous Serial Format
I C Bus Format
0
0
0
8
9 (Initial value)
1
1
2
0
2
3
1
3
4
0
4
5
1
5
6
0
6
7
1
7
8
1
1
0
1
2
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Section 23 I C Bus Interface (IIC)
2
23.2.5
I C Bus Control Register (ICCR)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
ICE
IEIC
MST
TRS
ACKE
BBSY
IRIC
SCP
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)*
W
Note: * Only 0 can be written to clear the flag.
2
ICCR is an 8-bit readable/writable register that enables or disables the I C bus interface, enables or
disables interrupts, selects master or slave mode and transmission or reception, enables or disables
2
acknowledgement, confirms the I C bus interface bus status, issues start/stop conditions, and
performs interrupt flag confirmation.
ICCR is initialized to H'01 by a reset.
2
2
Bit 7⎯I C Bus Interface Enable (ICE): Selects whether or not the I C bus interface is to be
used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer
operations are enabled. When ICE is cleared to 0, the IIC stops and its internal status is initialized.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can
be accessed when ICE is 1.
Bit 7
ICE
Description
0
I C bus interface module disabled, with SCL and SDA signal pins set to port function
The internal status of the IIC is initialized
SAR and SARX can be accessed
(Initial value)
1
I C bus interface module enabled for transfer operations (pins SCL and SDA are
driving the bus)
ICMR and ICDR can be accessed
2
2
2
2
Bit 6⎯I C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I C
bus interface to the CPU.
Bit 6
IEIC
Description
0
Interrupts disabled
1
Interrupts enabled
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(Initial value)
2
Section 23 I C Bus Interface (IIC)
Bits 5 and 4⎯Master/Slave Select (MST) and Transmit/Receive Select (TRS): MST selects
2
whether the I C bus interface operates in master mode or slave mode.
2
TRS selects whether the I C bus interface operates in transmit mode or receive mode.
2
In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode. In slave receive mode with the addressing
format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to
the R/W bit in the first frame after a start condition.
Modification of the TRS bit during transfer is deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.
Bit 5
Bit 4
MST
TRS
Description
0
0
Slave receive mode
1
Slave transmit mode
0
Master receive mode
1
Master transmit mode
1
(Initial value)
Bit 5
MST
Description
0
Slave mode
(Initial value)
[Clearing conditions]
1. When 0 is written by software
2
2. When bus arbitration is lost after transmission is started in I C bus format master
mode
1
Master mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing condition 2)
2. When 1 is written in MST after reading MST = 0 (in case of clearing condition 2)
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Section 23 I C Bus Interface (IIC)
Bit 4
TRS
Description
0
Receive mode
(Initial value)
[Clearing conditions]
1. When 0 is written by software (in cases other than setting condition 3)
2. When 0 is written in TRS after reading TRS = 1 (in case of setting condition 3)
2
3. When bus arbitration is lost after transmission is started in I C bus format master
mode
4. When the SW bit in DDCSWR changes from 1 to 0
1
Transmit mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing conditions 3)
2. When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3)
2
3. When a 1 is received as the R/W bit of the first frame in I C bus format slave
mode
Bit 3⎯Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the
2
acknowledge bit returned from the receiving device when using the I C bus format is to be ignored
and continuous transfer is performed, or transfer is to be aborted and error handling, etc.,
performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received
acknowledge bit is not indicated by the ACKB bit, which is always 0.
When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data
transmission, regardless of the value of the acknowledge bit. When the ACKE bit is 1, the TDRE,
IRIC, and IRTR flags are set on completion of data transmission when the acknowledge bit is 0,
and the IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1.
Depending on the receiving device, the acknowledge bit may be significant, in indicating
completion of processing of the received data, for instance, or may be fixed at 1 and have no
significance.
Bit 3
ACKE
Description
0
The value of the acknowledge bit is ignored, and continuous transfer is performed
(Initial value)
1
If the acknowledge bit is 1, continuous transfer is interrupted
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Section 23 I C Bus Interface (IIC)
2
Bit 2⎯Bus Busy (BBSY): The BBSY flag can be read to check whether the I C bus (SCL, SDA)
is busy or free. In master mode, this bit is also used to issue start and stop conditions.
A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting
BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition,
clearing BBSY to 0.
To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a stop condition, use a MOV instruction to
write 0 in BBSY and 0 in SCP.
2
It is not possible to write to BBSY in slave mode; the I C bus interface must be set to master
transmit mode before issuing a start condition. MST and TRS should both be set to 1 before
writing 1 in BBSY and 0 in SCP.
Bit 2
BBSY
Description
0
Bus is free
(Initial value)
[Clearing condition]
When a stop condition is detected
1
Bus is busy
[Setting condition]
When a start condition is detected
2
2
Bit 1⎯I C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I C bus interface has
issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave
address or general call address is detected in slave receive mode, when bus arbitration is lost in
master transmit mode, and when a stop condition is detected. IRIC is set at different times
depending on the FS bit in SAR and the WAIT bit in ICMR. See section 23.3.6, IRIC Setting
Timing and SCL Control. The conditions under which IRIC is set also differ depending on the
setting of the ACKE bit in ICCR.
IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.
When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously
without CPU intervention.
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Section 23 I C Bus Interface (IIC)
Bit 1
IRIC
Description
0
Waiting for transfer, or transfer in progress
(Initial value)
[Clearing condition]
When 0 is written in IRIC after reading IRIC = 1
(1)
Interrupt requested
[Setting conditions]
•
•
•
•
2
I C bus format master mode
1. When a start condition is detected in the bus line state after a start condition
is issued
(when the TDRE flag is set to 1 because of first frame transmission)
2. When a wait is inserted between the data and acknowledge bit when WAIT =
1
3. At the end of data transfer
(at the rise of the 9th transmit/receive clock pulse, or at the fall of the 8th
transmit/receive clock pulse when using wait insertion)
4. When a slave address is received after bus arbitration is lost
(when the AL flag is set to 1)
5. When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
2
I C bus format slave mode
1. When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1)
and at the end of data transfer up to the subsequent retransmission start
condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
2. When the general call address is detected
(when FS = 0 and the ADZ flag is set to 1)
and at the end of data transfer up to the subsequent retransmission start
condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
3. When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
4. When a stop condition is detected
(when the STOP or ESTP flag is set to 1)
Synchronous serial format
1. At the end of data transfer
(when the TDRE or RDRF flag is set to 1)
2. When a start condition is detected with serial format selected
When a condition, other than the above, that sets the TDRE or RDRF flag to 1 is
detected
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Section 23 I C Bus Interface (IIC)
2
When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The
IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a
retransmission start condition or stop condition after a slave address (SVA) or general call address
2
match in I C bus format slave mode.
Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set.
The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in
continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the
specified number of ICDR reads or writes have been completed.
Table 23.3 shows the relationship between the flags and the transfer states.
Note: * This LSI does not incorporate DTC.
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Section 23 I C Bus Interface (IIC)
Table 23.3 Flags and Transfer States
MST
TRS
BBSY ESTP STOP IRTR
AASX AL
AAS
ADZ
ACKB State
1/0
1/0
0
0
0
0
0
0
0
0
0
Idle state (flag
clearing required)
1
1
0
0
0
0
0
0
0
0
0
Start condition
issuance
1
1
1
0
0
1
0
0
0
0
0
Start condition
established
1
1/0
1
0
0
0
0
0
0
0
0/1
Master mode wait
1
1/0
1
0
0
1
0
0
0
0
0/1
Master mode
transmit/receive end
0
0
1
0
0
0
1/0
1
1/0
1/0
0
Arbitration lost
0
0
1
0
0
0
0
0
1
0
0
SAR match by first
frame in slave mode
0
0
1
0
0
0
0
0
1
1
0
General call address
match
0
0
1
0
0
0
1
0
0
0
0
SARX match
0
1/0
1
0
0
0
0
0
0
0
0/1
Slave mode
transmit/receive end
(except after SARX
match)
0
0
1/0
1
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
Slave mode
transmit/receive end
(after SARX match)
0
1/0
0
1/0
1/0
0
0
0
0
0
0/1
Stop condition
detected
Bit 0⎯Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop
conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP.
This bit is always read as 1. If 1 is written, the data is not stored.
Bit 0
SCP
Description
0
Writing 0 issues a start or stop condition, in combination with the BBSY flag
1
Reading always returns a value of 1
Writing is ignored
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(Initial value)
2
Section 23 I C Bus Interface (IIC)
23.2.6
2
I C Bus Status Register (ICSR)
Bit :
7
6
5
4
3
2
1
0
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
Initial value :
R/W :
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
Note: * Only 0 can be written to clear the flag.
ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge
confirmation and control.
ICSR is initialized to H'00 by a reset.
Bit 7⎯Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been
2
detected during frame transfer in I C bus format slave mode.
Bit 7
ESTP
Description
0
No error stop condition
(Initial value)
[Clearing conditions]
1. When 0 is written in ESTP after reading ESTP = 1
2. When the IRIC flag is cleared to 0
1
•
2
In I C bus format slave mode: Error stop condition detected
[Setting condition]
When a stop condition is detected during frame transfer
•
In other modes: No meaning
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Section 23 I C Bus Interface (IIC)
Bit 6⎯Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been
2
detected after completion of frame transfer in I C bus format slave mode.
Bit 6
STOP
Description
0
No normal stop condition
(Initial value)
[Clearing conditions]
1. When 0 is written in STOP after reading STOP = 1
2. When the IRIC flag is cleared to 0
•
1
2
In I C bus format slave mode: Error stop condition detected
[Setting condition]
When a stop condition is detected after completion of frame transfer
•
In other modes:No meaning
2
Bit 5⎯I C Bus Interface Continuous Transmission/Reception Interrupt Request Flag
2
(IRTR): Indicates that the I C bus interface has issued an interrupt request to the CPU, and the
source is completion of reception/transmission of one frame in continuous transmission/reception
for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1
at the same time.
IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by
reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically
when the IRIC flag is cleared to 0.
Note: * This LSI does not incorporate DTC.
Bit 5
IRTR
Description
0
Waiting for transfer, or transfer in progress
(Initial value)
[Clearing conditions]
1. When 0 is written in IRTR after reading IRTR = 1
2. When the IRIC flag is cleared to 0
1
Continuous transfer state
[Setting conditions]
•
In I C bus interface slave mode: When the TDRE or RDRF flag is set to 1 when
AASX = 1
•
In other modes: When the TDRE or RDRF flag is set to 1
2
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Section 23 I C Bus Interface (IIC)
2
Bit 4⎯Second Slave Address Recognition Flag (AASX): In I C bus format slave receive mode,
this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in
SARX.
AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is
also cleared automatically when a start condition is detected.
Bit 4
AASX
Description
0
Second slave address not recognized
(Initial value)
[Clearing conditions]
1. When 0 is written in AASX after reading AASX = 1
2. When a start condition is detected
3. In master mode
1
Second slave address recognized
[Setting condition]
When the second slave address is detected in slave receive mode while FSX=0
Bit 3⎯Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The
2
I C bus interface monitors the bus. When two or more master devices attempt to seize the bus at
2
nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL
to 1 to indicate that the bus has been taken by another master.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 3
AL
Description
0
Bus arbitration won (Initial value)
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in AL after reading AL = 1
1
Arbitration lost
[Setting conditions]
1. If the internal SDA and SDA pin disagree at the rise of SCL in master transmit
mode
2. If the internal SCL line is high at the fall of SCL in master transmit mode
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Section 23 I C Bus Interface (IIC)
2
Bit 2⎯Slave Address Recognition Flag (AAS): In I C bus format slave receive mode, this flag is
set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the
general call address (H'00) is detected.
AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 2
AAS
Description
0
Slave address or general call address not recognized
(Initial value)
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in AAS after reading AAS = 1
3. In master mode
1
Slave address or general call address recognized
[Setting condition]
When the slave address or general call address is detected when FS = 0 in slave
receive mode
2
Bit 1⎯General Call Address Recognition Flag (ADZ): In I C bus format slave receive mode,
this flag is set to 1 if the first frame following a start condition is the general call address (H'00).
ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 1
ADZ
Description
0
General call address not recognized
(Initial value)
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in ADZ after reading ADZ = 1
3. In master mode
1
General call address recognized
[Setting condition]
If the general call address is detected when FSX = 0 or FS = 0 is selected in the
slave receive mode.
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Section 23 I C Bus Interface (IIC)
Bit 0⎯Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the
receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In
receive mode, after data has been received, the acknowledge data set in this bit is sent to the
transmitting device.
When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line
(returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal
software is read.
Bit 0
ACKB
Description
0
Receive mode: 0 is output at acknowledge output timing
(Initial value)
Transmit mode: Indicates that the receiving device has acknowledged the data (signal
is 0)
1
Receive mode: 1 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has not acknowledged the data
(signal is 1)
23.2.7
Serial/Timer Control Register (STCR)
Bit :
7
6
5
4
3
2
1
0
—
IICX1
IICX0
—
FLSHE
OSROME
—
—
Initial value :
0
0
0
0
0
0
0
0
R/W :
—
R/W
R/W
—
R/W
R/W
—
—
STCR is an 8-bit readable/writable register that controls the IIC operating mode.
STCR is initialized to H'00 by a reset.
Bit 7⎯Reserved: This bit cannot be modified and is always read as 0.
2
Bits 6 and 5⎯I C Transfer Select 1, 0 (IICX1, IICX0): These bits, together with bits CKS2 to
2
CKS0 in ICMR of IIC, select the transfer rate in master mode. For details, see section 23.2.4, I C
Bus Mode Register (ICMR).
Bit 3⎯Flash Memory Control Resister Enable (FLSHE): This bit selects the control resister of
the flash memory. For details, refer to section 7.3.5, Serial/Timer Control Resister (STCR).
Bit 2⎯OSD ROM Enable (OSROME): This bit controls the OSD ROM. For details, refer to
section 7, ROM.
Bits 4, 1, and 0⎯Reserved: These bits cannot be modified and are always read as 0.
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Section 23 I C Bus Interface (IIC)
23.2.8
DDC Switch Register (DDCSWR)
Bit :
7
6
5
4
3
2
1
0
SWE*3
SW*3
IE*3
IF*3
CLR3
CLR2
CLR1
CLR0
0
0
0
0
1
1
1
1
R/W
R/W
R/W
R/(W)*1
W*2
W*2
W*2
W*2
Initial value :
R/W :
Notes: 1. Only 0 can be written to clear the flag.
2. Always read as 1.
3. These bits are not provided (incorporated in) for the H8S/2197S and H8S/2196S.
DDCSWR is an 8-bit read/write register that controls automatic format switching for IIC channel
0 and IIC internal latch clearing. DDCSWR is initialized to H'0F by a reset or in hardware standby
mode.
Bit 7⎯DDC Mode Switch Enable (SWE): Enables or disables automatic switching from
2
formatless transfer to I C bus format transfer for IIC channel 0.
Bit 7
SWE
Description
0
Disables automatic switching from formatless transfer to I C bus format transfer for
IIC channel 0.
(Initial value)
1
Enables automatic switching from formatless transfer to I C bus format transfer for
IIC channel 0.
2
2
2
Bit 6⎯DDC Mode Switch (SW): Selects formatless transfer or I C bus format transfer for IIC
channel 0.
Bit 6
SW
Description
0
I C bus format is selected for IIC channel 0.
2
[Clearing conditions]
1. When 0 is written by software
2. When an SCL falling edge is detected when SWE = 1
1
Formatless transfer is selected for IIC channel 0.
[Setting condition]
When 1 is written after SW = 0 is read
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(Initial value)
2
Section 23 I C Bus Interface (IIC)
Bit 5⎯DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to
the CPU when the format for IIC channel 0 is automatically switched.
Bit 5
IE
Description
0
Disables an interrupt at automatic format switching
1
Enables an interrupt at automatic format switching
(Initial value)
Bit 4⎯DDC Mode Switch Interrupt Flag (IF): Indicates the interrupt request to the CPU when
the format for IIC channel 0 is automatically switched.
Bit 4
IF
Description
0
Interrupt has not been requested
(Initial value)
[Clearing condition]
When 0 is written after IF = 1 is read
1
Interrupt has been requested
[Setting condition]
When an SCL falling edge is detected when SWE = 1
Bits 3 to 0⎯IIC Clear 3 to 0 (CLR3 to CLR0): Control the IIC0 and IIC1 initialization. These
are write-only bits and are always read as 1.
Writing to these bits generates a clearing signal for the internal latch circuit which initializes the
IIC status.
The data written to these bits are not held. When initializing the IIC, be sure to use the MOV
instruction to write to all the CLR3 to CLR0 bits at the same time; do not use bit manipulation
instructions such as BCLR.
When reinitializing the module status, the CLR3 to CLR0 bits must be rewritten.
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Section 23 I C Bus Interface (IIC)
Bit 3
Bit 2
Bit 1
Bit 0
CLR3
CLR2
CLR1
CLR0
Description
0
0
⎯
⎯
The setting is invalid
1
0
0
The setting is invalid
1
IIC0 internal latch cleared
0
IIC1 internal latch cleared
1
IIC0 and IIC1 internal latches cleared
⎯
This setting is invalid
1
1
⎯
⎯
23.2.9
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
R/W :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the corresponding bit in MSTPCR is set to 1, operation of the corresponding IIC channel is
halted at the end of the bus cycle, and a transition is made to module stop mode. For details, see
section 4.5, Module Stop Mode.
MSTPCR is initialized to H'FFFF by a reset. It is not initialized in standby mode.
MSTPCRL Bit 7⎯Module Stop (MSTP7): Specifies the module stop mode for IIC channel 0.
MSTPCRL
Bit 7
MSTP7
Description
0
Module stop mode for IIC channel 0 is cleared
1
Module stop mode for IIC channel 0 is set
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Section 23 I C Bus Interface (IIC)
MSTPCRL Bit 6⎯Module Stop (MSTP6): Specifies the module stop mode for IIC channel 1.
MSTPCRL
Bit 6
MSTP6
Description
0
Module stop mode for IIC channel 1 is cleared
1
Module stop mode for IIC channel 1 is set
23.3
Operation
23.3.1
I C Bus Data Format
2
(Initial value)
2
2
The I C bus interface has serial and I C bus formats.
2
The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures
23.3(1) and (2). The first frame following a start condition always consists of 8 bits. Formatless
transfer can be selected only for IIC channel 0. The formatless transfer data is shown in figure
23.3 (3).
The serial format is a non-addressing format with no acknowledge bit. This is shown in figure
23.4.
2
Figure 23.5 shows the I C bus timing.
The symbols used in figures 23.3 to 23.5 are explained in table 23.4.
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Section 23 I C Bus Interface (IIC)
(1) FS = 0 or FSX = 0
S
1
SLA
7
R/W
1
A
1
DATA
n
A
1
A/A
1
1
P
1
m
Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = 1 or above)
(2) Start condition transmission, FS = 0 or FSX = 0
S
1
SLA
7
R/W
1
A
1
DATA
n1
1
A/A
1
S
1
SLA
7
R/W
1
m1
A
1
A/A
1
DATA
n2
1
P
1
m2
Upper: Transfer bit count (n1 and n2 = 1 to 8)
Lower: Transfer frame count (m1 and m2 = 1 or above)
(3) Formatless (IIC channel 0 only, FS = 0 or FSX = 0)
DATA
8
A
1
DATA
n
A
1
A/A
1
1
Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = 1 or above)
m
2
2
Figure 23.3 I C Bus Data Formats (I C Bus Formats)
FS = 1 and FSX = 1
S
DATA
DATA
P
1
8
n
1
1
m
Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = 1 or above)
2
Figure 23.4 I C Bus Data Format (Serial Format)
SDA
SCL
S
1-7
8
9
SLA
R/W
A
1-7
8
DATA
2
9
A
Figure 23.5 I C Bus Timing
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1-7
DATA
8
9
A/A
P
2
Section 23 I C Bus Interface (IIC)
2
Table 23.4 I C Bus Data Format Symbols
Symbol
Description
S
Start condition. The master device drives SDA from high to low while SCL is hig
SLA
Slave address, by which the master device selects a slave device
R/W
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
A
Acknowledge. The receiving device (the slave in master transmit mode, or the
master in master receive mode) drives SDA low to acknowledge a transfer
DATA
Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first
or LSB-first format is selected by bit MLS in ICMR
P
Stop condition. The master device drives SDA from low to high while SCL is high
23.3.2
Master Transmit Operation
2
In I C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal. The transmission procedure and
operations synchronize with the ICDR writing are described below.
[1] Set bit ICE in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX in
STCR, according to the operating mode.
[2] Read the BBSY flag in ICCR to confirm that the bus is free.
[3] Set bits MST and TRS to 1 in ICCR to select master transmit mode.
[4] Write 1 to BBSY and 0 to SCP. This changes SDA from high to low when SCL is high, and
generates the start condition.
[5] Then IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt
request is sent to the CPU.
[6] Write the data (slave address + R/W) to ICDR. After the start condition instruction has been
issued and the start condition has been generated, write data to ICDR. If this procedure is not
2
followed, data may not be output correctly. With the I C bus format (when the FS bit in SAR
or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7bit slave address and transmit/receive direction. As indicating the end of the transfer, and so
the IRIC flag is cleared to 0. After writing ICDR, clear IRIC immediately not to execute other
interrupt handling routine. If one frame of data has been transmitted before the IRIC clearing,
it can not be determine the end of transmission. The master device sequentially sends the
transmission clock and the data written to ICDR using the timing shown in figure 23.6. The
selected slave device (i.e. the slave device with the matching slave address) drives SDA low at
the 9th transmit clock pulse and returns an acknowledge signal.
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Section 23 I C Bus Interface (IIC)
[7] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
[8] Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has
not acknowledged (ACKB bit is 1), operate the step [12] to end transmission, and retry the
transmit operation.
[9] Write the transmit data to ICDR. As indicating the end of the transfer, and so the IRIC flag is
cleared to 0. After writing ICDR, clear IRIC immediately not to execute other interrupt
handling routine. The master device sequentially sends the transmission clock and the data
written to ICDR. Transmission of the next frame is performed in synchronization with the
internal clock.
[10] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
[11] Read the ACKB bit in ICSR and confirm ACKB is cleared to 0. When there is data to be
transmitted, go to the step [9] to continue next transmission. When the slave device has not
acknowledged (ACKB bit is set to 1), operate the step [12] to end transmission.
[12] Clear the IRIC flag to 0. And write 0 to BBSY and SCP in ICCR. This changes SDA from
low to high when SCL is high, and generates the stop condition.
Start condition
Geberation
SCL
(master output)
1
SDA
(master output)
bit 7
2
bit 6
3
bit 5
4
bit 4
5
bit 3
6
bit 2
Slave address
SDA
(slave output)
7
bit 1
8
9
2
bit 7
bit 0
R/W
1
[7]
bit 6
Data 1
A
[5]
IRIC
IRTR
ICDR
Note: Data write
timing in ICDR
ICDR Writing
prohibited
Data 1
address + R/W
ICDR Writing
enable
User processing [4] Write BBSY = 1
and SCP = 0
(start condition
issuance)
[6] ICDR write
[6] IRIC clear
These processes are executed continuously.
[9] ICDR write [9] IRIC clear
These processes are executed continuously.
Figure 23.6 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0)
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Section 23 I C Bus Interface (IIC)
23.3.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns an
2
acknowledge signal. The slave device transmits data. I C bus interface module consists of the data
buffers of ICDRR and ICDRS, so data can be received continuously in master receive mode. For
this construction, when stop condition issuing timing delayed, it may occurs the internal
contention between stop condition issuance and SCL clock output for next data receiving, and then
the extra SCL clock would be outputted automatically or the SDA line would be held to low. And
2
for I C bus interface system, the acknowledge bit must be set to 1 at the last data receiving, so the
change timing of ACKB bit in ICSR should be controlled by software. To take measures against
these problems, the wait function should be used in master receive mode. The reception procedure
and operations with the wait function in master receive mode are described below.
[1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode, and set the
WAIT bit in ICMR to 1. Also clear the ACKB bit in ICSR to 0 (acknowledge data setting).
[2] When ICDR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. In order to detect wait operation,
set the IRIC flag in ICCR must be cleared to 0. After reading ICDR, clear IRIC immediately
not to execute other interrupt handling routine. If one frame of data has been received before
the IRIC clearing, it can not be determine the end of reception.
[3] The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. If the IEIC bit in ICCR has
been set to 1, an interrupt request is sent to the CPU. SCL is automatically fixed low in
synchronization with the internal clock until the IRIC flag clearing. If the first frame is the last
receive data, execute step [10] to halt reception.
[4] Clear the IRIC flag to release from the Wait State. The master device outputs the 9th clock and
drives SDA at the 9th receive clock pulse to return an acknowledge signal.
[5] When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in ICSR
are set to 1 at the rise of the 9th receive clock pulse. The master device outputs SCL clock to
receive next data.
[6] Read ICDR.
[7] Clear the IRIC flag to detect next wait operation. From clearing of the IRIC flag to negation of
a wait as described in step [4] (and [9]) to clearing of the IRIC flag as described in steps [5],
[6], and [7], must be performed within the time taken to transfer one byte.
[8] The IRIC flags set to 1 at the fall of the 8th receive clock pulse. SCL is automatically fixed low
in synchronization with the internal clock until the IRIC flag clearing. If this frame is the last
receive data, execute step [10] to halt reception.
[9] Clear the IRIC flag in ICCR to cancel wait operation. The master device outputs the 9th clock
and drives SDA at the 9th receive clock pulse to return an acknowledge signal. Data can be
received continuously by repeating step [5] to [9].
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Section 23 I C Bus Interface (IIC)
[10] Set the ACKB bit in ICSR to 1 so as to return “No acknowledge” data. Also set the TRS bit
to 1 to switch from receive mode to transmit mode.
[11] Clear IRIC flag to 0 to release from the Wait State.
[12] When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
receive clock pulse.
[13] Clear the WAIT bit to 0 to switch from wait mode to no wait mode. Read ICDR and the IRIC
flag to 0. Clearing of the IRIC flag should be after the WAIT = 0.
[14] Clear the BBSY bit and SCP bit to 0. This changes SDA from low to high when SCL is high,
and generates the stop condition.
Master transmit mode
Master receive mode
SCL
(master output)
9
1
2
3
4
5
6
7
8
SDA
(slave output)
A
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Data 1
9
[3]
SDA
(master output)
[5]
1
2
Bit7
Bit6
3
4
5
Bit5
Bit4
Bit3
Data 2
A
IRIC
IRTR
ICDR
User processing
Data 1
[2] IRIC clearance
[1] TRS cleared to 0 [2] ICDR read
(dummy read)
WAIT set to 1
ACKB cleared to 0
[4] IRC clearance
These processes are executed continuously.
[6] ICDR read
(Data 1)
[7] IRIC clearance
These processes are executed continuously.
Figure 23.7 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)
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Section 23 I C Bus Interface (IIC)
SCL
(master output)
8
SDA
(slave output)
Bit0
Data 2
9
[8]
SDA
(master output)
1
2
3
4
5
6
7
8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Data 3
[5]
9
1
2
Bit7
[8]
A
Bit6
Data 4
[5]
A
IRIC
IRTR
ICDR
User processing
Data 1
[9] IRIC clearance
Data 2
[6] ICDR read
(Data 2)
[7] IRIC clearance
Data 3
[9] IRIC Clearance
These processes are executed continuously.
[6] ICDR read
(Data 3)
[7] IRIC clearance
These processes are executed continuously.
Figure 23.8 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1) Continued
23.3.4
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The receive procedure and operations in slave receive
mode are described below.
1. Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according to
the operating mode.
2. A start condition output by the master device sets the BBSY flag to 1 in ICCR.
3. After the slave device detects the start condition, if the first frame matches its slave address, it
functions as the slave device designated as the master device. If the 8th bit data (R/W) is 0,
TRS bit in ICCR remains 0 and executes slave receive operation.
4. At the ninth clock pulse of the receive frame, the slave device drives SDA low to acknowledge
the transfer. At the same time, the IRIC flag is set to 1 in ICCR. If IEIC is 1 in ICCR, a CPU
interrupt is requested. If the RDRF internal flag is 0, it is set to 1 and continuous reception is
performed. If the RDRF internal flag is 1, the slave device holds SCL low from the fall of the
receive clock until it has read the data in ICDR.
5. Read ICDR and clear IRIC to 0 in ICCR. At this time, the RDRF flag is cleared to 0.
Steps 4 and 5 can be repeated to receive data continuously. When a stop condition is detected (a
low-to-high transition of SDA while SCL is high), the BBSY flag is cleared to 0 in ICCR.
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Section 23 I C Bus Interface (IIC)
Start condition
issurance
SCL
(Master output)
1
2
3
4
5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
6
7
8
9
1
2
Bit 7
Bit 6
SCL
(Slave output)
SDA
(Master output)
Slave address
SDA
(Slave output)
Bit 2
Bit 1
Bit 0
R/W
Data 1
[4]
A
RDRF
IRIC
Interrupt request
generated
ICDRS
Address + R/W
ICDRR
User processing
Address + R/W
[5] Read ICDR
[5] Clear IRIC
Figure 23.9 Example of Timing in Slave Receive Mode (MLS = ACKB = 0)
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Section 23 I C Bus Interface (IIC)
SCL
(Master output)
7
8
Bit 1
Bit 0
9
1
2
3
4
5
6
7
8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
SCL
(Slave output)
SDA
(Master output)
Data 1
SDA
(Slave output)
Bit 7
Bit 6
[4]
[4]
Data 2
A
A
RDRF
IRIC
Interrupt
request
generated
ICDRS
Data 1
ICDRR
Data 1
User processing
[5] Read ICDR
Interrupt
request
generated
Data 2
Data 2
[5] Clear IRIC
Figure 23.10 Example of Timing in Slave Receive Mode (MLS = ACKB = 0)
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Section 23 I C Bus Interface (IIC)
23.3.5
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, and the master device outputs
the transmit clock and returns an acknowledge signal. The transmit procedure and operations in
slave transmit mode are described below.
1. Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according to
the operating mode.
2. After the slave device detects a start condition, if the first frame matches its slave address, at
the ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the
same time, the IRIC flag is set to 1 in ICCR, and if the IEIC bit in ICCR is set to 1 at this time,
an interrupt request is sent to the CPU. If the eighth data bit (R/W) is 1, the TRS bit is set to 1
in ICCR, automatically causing a transition to slave transmit mode. The slave device holds
SCL low from the fall of the transmit clock until data is written in ICDR.
3. Clear the IRIC flag to 0, then write data in ICDR. The written data is transferred to ICDRS,
and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. Clear IRIC to 0,
then write the next data in ICDR. The slave device outputs the written data serially in step with
the clock output by the master device, with the timing shown in figure 23.11.
4. When one frame of data has been transmitted, at the rise of the ninth transmit clock pulse IRIC
is set to 1 in ICCR. If the TDRE internal flag is 1, the slave device holds SCL low from the fall
of the transmit clock until data is written in ICDR. The master device drives SDA low at the
ninth clock pulse to acknowledge the data. The acknowledge signal is stored in the ACKB bit
in ICSR, and can be used to check whether the transfer was carried out normally. If TDRE
internal flag is set to 0, the data written in ICDR is transferred to ICDRS, then transmission
starts and TDRE internal flag and IRIC and IRTR flags are all set to 1 again.
5. To continue transmitting, clear IRIC to 0, then write the next transmit data in ICDR. At this
time, the TDRE internal flag is cleared to 0.
Steps 4 and 5 can be repeated to transmit continuously. To end the transmission, write H'FF in
ICDR so that the SDA may be freed on the slave side. When a stop condition is detected (a low-tohigh transition of SDA while SCL is high), the BBSY flag will be cleared to 0 in ICCR.
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Section 23 I C Bus Interface (IIC)
Slave receive mode
SCL
(Master output)
8
Slave transmit mode
9
1
2
3
4
5
6
7
8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
1
2
Bit 7
Bit 6
SCL
(Slave output)
SDA
(Slave output)
Bit 7
A
SDA
(Master output) R/W
Bit 6
Data 1
[2]
Data 2
A
TDRE
IRIC
Interrupt
request
generated
ICDRT
Data 1
ICDRS
User
processing
[3]
Interrupt
request
generated
Interrupt
request
generated
Data 2
Data 1
[3] Clear IRIC
[3] Write ICDR
Data 2
[3] Write ICDR
[5] Clear IRIC
[5] Write ICDR
Figure 23.11 Example of Timing in Slave Transmit Mode (MLS = 0)
23.3.6
IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 23.12 shows the IRIC set timing and SCL control.
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Section 23 I C Bus Interface (IIC)
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait)
SCL
SDA
7
8
9
1
7
8
A
1
IRIC
User
processing
Clear
IRIC
Write to ICDR (transmit) or
read ICDR (receive)
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted)
SCL
SDA
8
9
1
8
A
1
IRIC
User
processing
Clear IRIC
Clear IRIC Write to ICDR (transmit) or
read ICDR (receive)
(c) When FS = 1 and FSX = 1 (synchronous serial format)
SCL
SDA
7
8
1
7
8
1
IRIC
User
processing
Clear IRIC
Write to ICDR (transmit) or
read ICDR (receive)
Figure 23.12 IRIC Setting Timing and SCL Control
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Section 23 I C Bus Interface (IIC)
23.3.7
2
Automatic Switching from Formatless Transfer to I C Bus Format Transfer
Setting the SW bit in DDCSWR to 1 selects the IIC0 formatless transfer operation. When an SCL
2
falling edge is detected, the operating mode automatically switches from formatless transfer to I C
bus format transfer (slave mode). For automatic switching to be possible, the following four
conditions must be observed:
2
1. The same data pin (SDA) is used in common for formatless transfer and I C bus format
transfer.
2
2. Separate clock pins are used for formatless transfer and I C bus format transfer (SYNC1 for
2
formatless, and SCL for I C bus format)
3. The SCL pin is kept high during formatless transfer.
2
4. Register bits other than the TRS bit in ICCR are set to appropriate values so that I C bus
format transfer can be performed.
2
The operating mode is automatically switched from formatless transfer to I C bus format transfer
when an SCL falling edge is detected and the SW bit in DDCSWR is automatically cleared to 0.
2
To switch the mode from I C bus format transfer to formatless transfer, set the SW bit to 1 by
software.
2
During formatless transfer, do not modify the bits that control the I C bus interface operating
2
mode, such as the MSL or TRS bit. When switching from the I C bus format transfer to formatless
transfer, specify the formatless transfer direction (transmit or receive) by setting or clearing the
2
TRS bit, then set the SW bit to 1. After the automatic switching from formatless transfer to I C bus
format transfer (slave mode), the TRS bit is automatically cleared to 0 to enter the slave address
receive wait state.
2
If an SCL falling edge is detected during formatless transfer, the I C does not wait for the stop
condition but switches the operating mode immediately.
Note: The IIC0 is not provided (incorporated in) for the H8S/2197S and H8S/2196S.
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Section 23 I C Bus Interface (IIC)
23.3.8
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 23.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
SCL or SDA
input signal
C
C
Q
D
Latch
D
Q
Match
detector
Latch
Internal SCL
or SDA signal
System clock
period
Sampling
clock
Figure 23.13 Block Diagram of Noise Canceler
23.3.9
Sample Flowcharts
2
Figures 23.14 to 23.17 show sample flowcharts for using the I C bus interface in each mode.
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Section 23 I C Bus Interface (IIC)
Start
[1] Initialize
Initialize
[2] Test the status of the SCL and SDA lines.
Read BBSY in ICCR
No
BBSY = 0?
Yes
[3] Select master transmit mode.
Set MST = 1 and
TRS = 1 in ICCR
[4] Start condition issuance
Write BBSY = 1
and SCP = 0 in ICCR
[5] Wait for a start condition generation
Read IRIC in ICCR
No
IRIC = 1?
[6] Set transmit data for the first byte (slave
address + R/W).
(After writing ICDR, clear IRIC
immediately)
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
[7] Wait for 1 byte to be transmitted.
IRIC = 1?
Yes
Read ACKB in ICSR
ACKB = 0?
No
[8] Test the acknowledge bit, transferred from
slave device.
Yes
Transmit mode?
No
Master receive mode
Yes
Write transmit data in ICDR
Clear IRIC in ICCR
[9] Set transmit data for the second and
subsequent bytes.
(After writing ICDR, clear IRIC
immediately)
Read IRIC in ICCR
No
[10] Wait for 1 byte to be transmitted.
IRIC = 1?
Yes
Read ACKB in ICSR
[11] Test for end of transfer
No
End of transmission
or ACKB = 1?
Yes
Clear IRIC in ICCR
[12] Stop condition issuance
Write BBSY = 0
and SCP = 0 in ICCR
End
Figure 23.14 Flowchart for Master Transmit Mode (Example)
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Section 23 I C Bus Interface (IIC)
Master receive mode
Set TRS = 0 in ICCR
[1] Select receive mode
Set WAIT = 1 in ICMR
Set ACKB = 0 in ICSR
[2] Start receiving. The first read is a dummy
read. After reading ICDR, please clear
IRIC immediately.
Read ICDR
Clear IRIC in ICCR
[3] Wait for 1 byte to be received.
(8th clock falling edge)
Read IRIC in ICCR
No
IRIC = 1?
Yes
Last receive ?
Yes
No
No
Clear IRIC in ICCR
[4] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
Read IRIC in ICCR
[5] Wait for 1 byte to be received.
(9th clock risig edge)
IRIC = 1?
Yes
[6] Read the received data.
Read ICDR
No
Clear IRIC in ICCR
[7] Clear IRIC
Read IRIC in ICCR
[8] Wait for the next data to be received.
(8th clock falling edge)
IRIC = 1?
Yes
Yes
Last receive ?
No
Read IRIC in ICCR
Set ACKB = 1 in ICSR
Set TRS = 1 in ICCR
Clear IRIC in ICCR
[9] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
[10] Set ACKB = 1 so as to return No
acknowledge, or set TRS = 1 so as not
to issue Extra clock.
[11] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
Read IRIC in ICCR
No
[12] Wait for 1 byte to be received.
IRIC = 1?
Yes
Set WAIT = 0 in ICMR
Read ICDR
[13] Set WAIT = 0.
Read ICDR.
Clear IRIC.
(Note: After setting WAIT = 0, IRIC
should be cleared to 0)
Clear IRIC in ICCR
Write BBSY = 0
and SCP = 0 in ICCR
[14] Stop condition issuance.
End
Figure 23.15 Flowchart for Master Receive Mode (Example)
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Section 23 I C Bus Interface (IIC)
Start
Initialize
Set MST = 0 and
TRS = 0 in ICCR
[1]
Set ACKB = 0 in ICSR
Read IRIC flag in ICCR
No
[2]
IRIC = 1?
Yes
Read AAS and ADZ flags in ICSR
No
AAS = 1 and
ADZ = 0?
General call address processing
*Description omitted
Yes
Read TRS bit in ICCR
TRS = 0?
No
Slave transmit mode
Yes
Last receive?
Yes
No
Read ICDR
[3]
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
No
[1] Select slave receive mode.
[4]
IRIC = 1?
[2] Wait for 1 byte to be received (slave
address)
Yes
[3] Start receiving. The first read is a dummy
read.
Set ACKB = 0 in ICSR
[5]
Read ICDR
[6]
[4] Wait for the transfer to end.
[5] Set acknowledge data for the last receive.
Clear IRIC flag in ICCR
[6] Start the last receive.
Read IRIC flag in ICCR
No
[7]
[7] Wait for the transfer to end.
IRIC = 1?
[8] Read the last receive data.
Yes
Read ICDR
[8]
Clear IRIC flag in ICCR
End
Figure 23.16 Flowchart for Slave Transmit Mode (Example)
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Section 23 I C Bus Interface (IIC)
[1] Set transmit data for the second and
subsequent bytes.
Slave transmit mode
Clear IRIC in ICCR
[2] Wait for 1 byte to be transmitted.
Write transmit data in ICDR
[1]
Clear IRIC flag in ICCR
[4] Select slave receive mode.
[5] Dummy read (to release the SCL line).
Read IRIC flag in ICCR
No
[3] Test for end of transfer.
[2]
IRIC = 1?
Yes
Read ACKB bit in ICSR
No
[3]
End of transmission
(ACKB = 1)?
Yes
Set TRS = 0 in ICCR
[4]
Read ICDR
[5]
Clear IRIC flag in ICCR
End
Figure 23.17 Flowchart for Slave Receive Mode (Example)
23.3.10 Initializing Internal Status
2
2
The I C can forcibly initialize the I C internal status when a dead lock occurs during
communication. Initialization is enabled by (1) setting the CLR3 to CLR0 bits in DDCSWR, or (2)
clearing the ICE bit. For details on CLR3 to CLR0 settings, refer to section 23.2.8, DDC Switch
Register (DDCSWR).
(1) Initialized Status
This function initializes the following:
⎯ TDRE and RDRF internal flags
⎯ Transmit/receive sequencer and internal clock counter
⎯ Internal latches (wait, clock, or data output) which holds the levels output from the SCL
and SDA pins
This function does not initialize the following:
⎯ Register contents (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, and STCR)
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Section 23 I C Bus Interface (IIC)
⎯ Internal latches which holds the register read information to set or clear the flags in ICMR,
ICCR, ICSR, and DDCSWR
⎯ Bit counter (BC2 to BC0) value in ICMR
⎯ Sources of interrupts generated (interrupts that has been transferred to the interrupt
controller)
(2) Notes on Initialization
⎯ Interrupt flags and interrupt sources are not cleared; clear them by software if necessary.
⎯ Other register flags cannot be assumed to be cleared, either; clear them by software if
necessary.
⎯ When initialization is specified by the DDCSWR settings, the data written to the CLR3 to
2
CLR0 bits are not held. When initializing the I C, be sure to use the MOV instruction to
write to all the CLR3 to CLR0 bits at the same time; do not use bit manipulation
instructions such as BCLR. When reinitializing the module status, all the CLR3 to CLR0
bits must be rewritten to at the same time.
⎯ If a flag is cleared during transfer, the I C module stops transfer immediately, and releases
the control of the SCL and SDA pins. Before starting again, set the registers to appropriate
values to make a correct communication if necessary.
2
This module initializing function does not modify the BBSY bit value, but in some cases,
depending on the SCL and SDA pin status and the release timing, the signal waveforms at the
SCL and SDA pins may indicate the stop condition, and accordingly the BBSY bit may be
cleared. Other bits or flags may be affected in the same way by module initialization.
2
To avoid these problems, take the following procedure to initialize the I C:
2
1. Initialize the I C by setting the CLR3 to CLR0 bits or the ICE bit.
2. Execute a stop condition issuing instruction to clear the BBSY bit to 0 (writing 0 to BBSY and
SCP), and wait for two cycles of the transfer clock.
2
3. Initialize the I C again by setting the CLR3 to CLR0 bits or the ICE bit.
2
4. Set the registers in I C to appropriate values.
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Section 23 I C Bus Interface (IIC)
23.4
Usage Notes
1. In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that the SCL may briefly remain at a high
level immediately after BBSY is cleared to 0.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
a. Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
b. Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
3. Table 23.5 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
2
Table 23.5 I C Bus Timing (SCL and SDA Output)
Item
Symbol
Output Timing
Unit
Notes
SCL output cycle time
tSCLO
28 tcyc to 256 tcyc
ns
SCL output high pulse width
tSCLHO
0.5 tSCLO
ns
Figure 31.8
(reference)
SCL output low pulse width
tSCLLO
0.5 tSCLO
ns
SDA output bus free time
tBUFO
0.5 tSCLO –1 tcyc
ns
Start condition output hold time
tSTAHO
0.5 tSCLO –1 tcyc
ns
Retransmission start condition
output setup time
tSTASO
1 tSCLO
ns
Stop condition output setup time
tSTOSO
0.5 tSCLO +2 tcyc
ns
Data output setup time (master)
tSDASO
1 tSCLLO –3 tcyc
ns
Data output setup time (slave)
Data output hold time
Note:
*
tSDAHO
1 tSCLL –(6 tcyc or 12 tcyc*)
ns
3 tcyc
ns
6 tcyc when IICX is 0, 12 tcyc when 1.
4. SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
2
therefore depends on the system clock cycle tcyc, as shown in table 31.6. Note that the I C bus
interface AC timing specifications will not be met with a system clock frequency of less than 5
MHz.
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Section 23 I C Bus Interface (IIC)
2
5. The I C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high2
speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds
2
the time determined by the input clock of the I C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 23.6.
Table 23.6 Permissible SCL Rise Time (tsr) Values
Time Indication [ns]
2
IICX
tcyc Indication
0
7.5 tcyc
1
17.5 tcyc
I C Bus
Specification
(Max.)
φ = 8 MHz
φ = 10 MHz
Normal mode
1000
937
750
High-speed mode
300
←
←
Normal mode
1000
←
←
High-speed mode
300
←
←
2
6. The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
2
and 300 ns. The I C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in
2
table 23.5. However, because of the rise and fall times, the I C bus interface specifications may
not be satisfied at the maximum transfer rate. Table 23.7 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
2
tBUFO fails to meet the I C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 μs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
2
permits this output timing for use as slave devices connected to the I C bus.
2
tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I C bus interface
specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
2
timing permits this output timing for use as slave devices connected to the I C bus.
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Section 23 I C Bus Interface (IIC)
7. Precautions on reading ICDR at the end of master receive mode
When terminating the master receive mode, set TRS bit to 1, and select "write" for ICCR
BBSY = 0 and SCP = 0. This forces to move SDA from low to high level when SCL is at high
level, thereby generating the stop condition.
Now you can read received data from ICDR. If, however, any data is remaining on the buffer,
received data on ICDRS is not transferred to ICDR, thus you won't be able to read the second
byte data.
When it is required to read the second byte data, issue the stop condition from the master
receive state (TRS bit is 0).
Before reading data from ICDR register, make sure that BBSY bit on ICCR register is 0, stop
condition is generated and bus is made free.
If you try to read received data after the stop condition issue instruction (setting ICCR's BBSY
= 0 and SCP = 0 to write) has been executed but before the actual stop condition is generated,
clock may not be appropriately signaled when the next master sending mode is turned on.
Thus, reasonable care is needed for determining when to read the received data.
After the master receive is complete, if you want to re-write IIC control bit (such as clearing MST
bit) for switching the sending/receiving mode or modifying settings, it must be done during period
(a) indicated in figure 23.18 (after making sure ICCR register BBSY bit is cleared to 0).
Start
condition
Stop condition
(a)
SDA
Bit 0
A
SCL
8
9
Internal clock
BBSY bit
Master receive mode
ICDR read
inhibit period
The stop condition
issue instruction
(BBSY = 0 and SCP = 0
set to write) is executed
Generation of the stop
condition is checked
(BBSY = 0 is set to read)
Start condition
is issued
Figure 23.18 Precautions on Reading the Master Receive Data
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Section 23 I C Bus Interface (IIC)
8. Notes on Start Condition Issuance for Retransmission
Figure 23.19 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. After start
condition issuance is done and determined the start condition, write the transmit data to ICDR.
[1] Wait for end of 1-byte transfer
IRIC = 1 ?
No
[1]
[2] Determine wheter SCL is low
Yes
Clear IRIC in ICSR
Start condition
issuance?
[3] Issue restart condition instruction for transmission
No
Other processing
[4] Determine whether start condition is generated or not
Yes
Read SCL pin
SCL = Low ?
[2]
[5] Set transmit data (slave address + R/W)
No
Note: Program so that processing instruction [3] to [5] is
Yes
executed continuously.
Write BBSY = 1,
SCP = 0 (ICSR)
[3]
[4]
IRIC = 1 ?
No
Yes
Write transmit data to ICDR
[5]
Start condition
(retransmission)
SCL
9
SDA ACK
bit 7
IRIC
[5] ICDR write (next transmit data)
[4] IRIC determination
[3] Issue restart condition instruction
for retransmission
[2] Determination of SCL=Low
[1] IRIC determination
Figure 23.19 Flowchart and Timing of Start Condition Instruction Issuance for
Retransmission
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Section 23 I C Bus Interface (IIC)
2
9. Notes on I C Bus Interface Stop Condition Instruction Issuance
If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load
capacitance is large, or if there is a slave device of the type that drives SCL low to effect a
wait, issue the stop condition instruction after reading SCL and determining it to be low, as
shown below.
SCL
9th clock
VIH
High period secured
As waveform rise is late,
SCL is detected as low
SDA
Stop condition
IRIC
[1] Determination of SCL = low
[2] Stop condition instruction issuance
Figure 23.20 Timing of Stop Condition Issuance
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Section 23 I C Bus Interface (IIC)
2
Table 23.7 I C Bus Timing (with Maximum Influence of tSr/tSf)
Time Indication (at Maximum Transfer Rate) [ns]
Item
tcyc Indication
tSCLHO
0.5 tSCLO
(–tSr)
tSCLLO
0.5 tSCLO
(–tSf)
tBUFO
0.5 tSCLO –1 tcyc
(–tSr)
tSTAHO
0.5 tSCLO –1 tcyc
(–tSf)
tSTASO
1 tSCLO
(–tSr)
tSTOSO
0.5 tSCLO +2 tcyc
(–tSr)
tSDASO
(master)
1 tSCLLO*3 –3 tcyc
(-tSr)
tSDASO
(slave)
1 tSCLL*3–12 tcyc*2
(–tSr)
tSDAHO
3 tcyc
Normal mode
High-speed
mode
Normal mode
High-speed
mode
Normal mode
High-speed
mode
Normal mode
High-speed
mode
Normal mode
High-speed
mode
Normal mode
High-speed
mode
Normal mode
High-speed
mode
Normal mode
High-speed
mode
Normal mode
High-speed
mode
tSr/tSf
Influence
(Max.)
I2C Bus
Specification
(Min.)
φ = 8 MHz
−1000
−300
4000
600
←
←
←
←
−250
−250
4700
1300
←
←
←
←
−1000
−300
4700
1300
3875*1
825*1
3900*1
850*1
−250
−250
4000
600
4625
875
4650
900
−1000
−300
4700
600
9000
2200
9000
2200
−1000
−300
4000
600
4250
1200
4200
1150
−1000
−300
250
100
3325
625
3400
700
−1000
−300
250
100
2200
−500*1
2500
−200*1
0
0
0
0
375
↑
300
↑
φ = 10 MHz
2
Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
2
maximum transfer rate; therefore, whether or not the I C bus interface specifications are
met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL –
6 tcyc).
2
3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.).
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Section 23 I C Bus Interface (IIC)
10. Notes on WAIT Function
⎯ Conditions to cause this phenomenon
When both of the following conditions are satisfied, the clock pulse of the 9th clock could
be outputted continuously in master mode using the WAIT function due to the failure of
the WAIT insertion after the 8th clock fall.
(1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode
(2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock
and the fall of the 8th clock.
⎯ Error phenomenon
Normally, WAIT State will be cancelled by clearing the IRIC flag bit from 1 to 0 after the
fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the
7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally.
Therefore, the WAIT State will be cancelled right after WAIT insertion on 8th clock fall.
⎯ Restrictions
Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2
through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th
clock.
If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC
counter is turned to 1 or 0, please confirm the SCL pins are in L’ state after the counter
value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 23.21.)
ASD
A
SCL
9
BC2–BC0
0
Transmit/receive data
1
2
7
3
6
4
5
5
4
6
3
Transmit/receive
data
A
7
2
1
8
SCL =
‘L’ confirm
9
0
1
2
7
IRIC clear
IRIC
(operation
example)
IRIC flag clear available
IRIC flag clear available
IRIC flag clear unavailable
Figure 23.21 IRIC Flag Clear Timing on WAIT Operation
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3
6
5
When BC2-0 ≥ 2
IRIC clear
2
Section 23 I C Bus Interface (IIC)
11. Notes on ICDR Reads and ICCR Access in Slave Transmit Mode
2
In a transmit operation in the slave mode of the I C bus interface, do not read the ICDR register
or read or write to the ICCR register during the period indicated by the shaded portion in figure
23.22.
Normally, when interrupt processing is triggered in synchronization with the rising edge of the
9th clock cycle, the period in question has already elapsed when the transition to interrupt
processing takes place, so there is no problem with reading the ICDR register or reading or
writing to the ICCR register.
To ensure that the interrupt processing is performed properly, one of the following two
conditions should be applied.
(1) Make sure that reading received data from the ICDR register, or reading or writing to the
ICCR register, is completed before the next slave address receive operation starts.
(2) Monitor the BC2 to BC0 counter in the ICMR register and, when the value of BC2 to BC0
is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in
order to involve the problem period in question before reading from the ICDR register, or
reading or writing to the ICCR register.
Waveforms if
problem occurs
SDA
SCL
TRS
R/W
8
Bit 7
A
9
Address received
Data transmission
Period when ICDR reads and ICCR
reads and writes are prohibited
(6 system clock cycles)
ICDR write
Detection of 9th clock
cycle rising edge
Figure 23.22 ICDR Read and ICCR Access Timing in Slave Transmit Mode
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Section 23 I C Bus Interface (IIC)
12. Notes on TRS Bit Setting in Slave Mode
From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the
rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 23.23)
2
in the slave mode of the I C bus interface, the value set in the TRS bit in the ICCR register is
effective immediately.
However, at other times (indicated as (b) in figure 23.23) the value set in the TRS bit is put on
hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than
taking effect immediately.
This results in the actual internal value of the TRS bit remaining 1 (transmit mode) and no
acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an
address receive operation following a restart condition input with no stop condition
intervening.
When receiving an address in the slave mode, clear the TRS bit to 0 during the period
indicated as (a) in figure 23.23.
To cancel the holding of the SCL bit low by the wait function in the slave mode, clear the TRS
bit to 0 and then perform a dummy read of the ICDR register.
Restart condition
(b)
(a)
A
SDA
SCL
TRS
8
1
9
2
3
4
5
6
7
8
9
Address reception
Data transmission
TRS bit setting hold time
ICDR dummy read
TRS bit set
Detection of 9th clock
cycle rising edge
Detection of 9th clock
cycle rising edge
Figure 23.23 TRS Bit Setting Timing in Slave Mode
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Section 23 I C Bus Interface (IIC)
13. Notes on Arbitration Lost in Master Mode
2
The I C bus interface recognizes the data in transmit/receive frame as an address when
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
2
register, the I C bus interface erroneously recognizes that the address call has occurred. (See
figure 23.24.)
2
In multi-master mode, a bus conflict could happen. When The I C bus interface is operated in
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
• Arbitration is lost
• The AL flag in ICSR is set to 1
I2
C bus interface
(Master transmit mode)
S
SLA
A
R/W
DATA1
Transmit data match
Transmit timing match
Other device
(Master transmit mode)
S
SLA
A
R/W
Transmit data does not match
DATA2
A
DATA3
A
Data contention
I2C bus interface
(Slave receive mode)
S
SLA
A
R/W
• Receive address is ignored
SLA
R/W
A
DATA4
A
• Automatically transferred to slave
receive mode
• Receive data is recognized as
an address
• When the receive data matches to
the address set in the SAR or SARX
register, the I2C bus interface operates
as a slave device
Figure 23.24 Diagram of Erroneous Operation when Arbitration is Lost
2
Though it is prohibited in the normal I C protocol, the same problem may occur when the MST
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1
according to the order below.
(a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
(b) Set the MST bit to 1.
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Section 23 I C Bus Interface (IIC)
(c) To confirm that the bus was not entered to the busy state while the MST bit is being set,
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
14. Notes on Interrupt Occurrence after ACKB Reception
⎯ Conditions to cause this failure
The IRIC flag is set to 1 when both of the following conditions are satisfied.
• 1 is received as the acknowledge bit for transmit data and the ACKB bit in ICSR is set
to 1
• Rising edge of the 9th transmit/receive clock is input to the SCL pin
When the above two conditions are satisfied in slave receive mode, an unnecessary
interrupt occurs.
Figure 23.25 shows the note on interrupt occurrence in slave mode after receiving 1 as the
acknowledge bit (ACKB = 1).
(1) For the last transmit data in master transmit mode or slave transmit mode, 1 is received
as the acknowledge bit.
If the ACKE bit in ICCR is set to 1 at this time, the ACKB bit in ICSR is set to 1.
(2) After switching to slave receive mode, the start condition is input, and address
reception is performed next.
(3) Even if the received address does not match the address set in SAR or SARX, the IRIC
flag is set to 1 at the rise of the 9th transmit/receive clock, thus causing an interrupt to
occur.
Note that if the slave address matches, an interrupt is to be generated at the rise of the 9th
transmit/receive clock as normal operation, so this is not erroneous operation.
⎯ Restriction
2
In a transmit operation of the I C bus interface module, carry out the following
countermeasures.
(1) After 1 is received as the acknowledge bit for transmit data, clear the ACKE bit in
ICCR to 0 to clear the ACKB bit to 0.
(2) To enable acknowledge bit reception afterwards, set the ACKE bit to 1 again.
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Section 23 I C Bus Interface (IIC)
Master transmit mode or
slave transmit mode
Stop
condition
Slave reception mode
Start
condition
(2) Address that does not match is received.
SDA
N
SCL
8
Address
9
1
2
3
4
5
6
7
8
A
Data
9
1
2
ACKB bit
IRIC flag
Stop condition
detection
Countermeasure:
Clear the ACKE bit to 0 to clear
the ACKB bit.
(3) Unnecessary interrupt occurs
(received address is invalid).
(1) Acknowledge bit is received
and the ACKB bit is set to 1.
Figure 23.25 Note on Interrupt Occurrence in Slave Mode after ACKB = 1 Reception
15. Notes on TRS Bit Setting and ICDR Register Access
⎯ Conditions to cause this failure
Low-fixation of the SCL pins is cancelled incorrectly when the following conditions are
satisfied.
(1) Master mode
Figure 23.26 shows the notes on ICDR reading (TRS = 1) in master mode.
(1) When previously received 2-bytes data remains in ICDR unread (ICDRS are full).
(2) Reads ICDR register after switching to transmit mode (TRS = 1). (RDRF = 0 state)
(3) Sets to receive mode (TRS = 0), after transmitting Rev.1 frame of issued start
condition by master mode.
(2) Slave mode
Figure 23.27 shows the notes on ICDR writing (TRS = 0) in slave mode.
(1) Writes ICDR register in receive mode (TRS = 0), after entering the start condition
by slave mode (TDRE = 0 state).
Address match with Rev.1 frame, receive 1 by R/W bit, and switches to transmit
mode (TRS = 1).
When these conditions are satisfied, the low fixation of the SCL pins is cancelled
without ICDR register access after Rev.1 frame is transferred.
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2
Section 23 I C Bus Interface (IIC)
⎯ Restriction
Please carry out the following countermeasures when transmitting/receiving via the IIC bus
interface module.
(1) Please read the ICDR registers in receive mode, and write them in transmit mode.
(2) In receiving operation with master mode, please issue the start condition after clearing
the internal flag of the IIC bus interface module, using CLR3 to CLR0 bit of the
DDCSWR register on bus-free state (BBSY = 0).
Along with ICDRS: ICDRR transfer
Stop condition
SDA
Cancel condition of SCL =
Low fixation is set.
Start condition
Address
A
SCL
8
1
9
2
3
4
5
6
7
8
A
Data
9
1
2
3
(3) TRS = 0
TRS bit
(2) RDRF = 0
RDRF bit
ICDRS data
full
(1) ICDRS data full
ICDR read
TRS = 0 setting
Detection of 9th clock rise
(TRS = 1)
Figure 16.26 Notes on ICDR Reading with TRS = 1 Setting in Master Mode
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2
Section 23 I C Bus Interface (IIC)
Along with ICDRS: ICDRR transfer
Stop condition
Cancel condition of SCL =
Low fixation
Start condition
Address
A
SDA
SCL
8
1
9
2
3
4
A
5
6
8
7
9
Data
1
2
3
4
(2) TRS = 1
TRS bit
TDRE bit
(1) TDRE = 0
ICDR write
TRS = 0 setting
Automatic TRS = 1 setting by
receiving R/W = 1
Figure 16.27 Notes on ICDR Writing with TRS = 0 Setting in Slave Mode
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2
Section 23 I C Bus Interface (IIC)
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Section 24 A/D Converter
Section 24 A/D Converter
24.1
Overview
This LSI incorporates a 10-bit successive-approximations A/D converter that allows up to 12
analog input channels to be selected.
24.1.1
Features
A/D converter has the following features.
• 10-bit resolution
• 12 input channels
• Sample and hold function
• Choice of software, hardware (internal signal) triggering or external triggering for A/D
conversion start.
• A/D conversion end interrupt request generation
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Section 24 A/D Converter
24.1.2
Block Diagram
Figure 24.1 shows a block diagram of the A/D converter.
Internal data bus
10-bit
D/A
Successive
approximation register
Reference Voltage
AVCC
A
D
R
A
H
R
A
D
C
S
R
A
D
C
R
AVSS
A
D
T
S
R
Hardware
control
circuit
Vref
Analog multiplexer
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
ANA
ANB
ADTRG
(HSW timing generator)
+
DFG
ADTRG
Chopper type
comparator
Control circuit
φ/2
φ/4
Sample-andhold circuit
Interrupt request
Legend:
ADR : Software trigger A/D result register
AHR : Hardware trigger A/D result register
ADCR : A/D control register
ADCSR: A/D control/status register
ADTSR: A/D trigger selection register
ADTRG, DFG : Hardware trigger
ADTRG : A/D external trigger input
Figure 24.1 Block Diagram of A/D Converter
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Section 24 A/D Converter
24.1.3
Pin Configuration
Table 24.1 summarizes the input pins used by the A/D converter.
Table 24.1 A/D Converter Pins
Name
Abbrev.
I/O
Function
Analog power supply pin
AVCC
Input
Analog block power supply and A/D
conversion reference voltage
Analog ground pin
AVSS
Input
Analog block ground and A/D conversion
reference voltage
Analog input pin 0
AN0
Input
Analog input channel 0
Analog input pin 1
AN1
Input
Analog input channel 1
Analog input pin 2
AN2
Input
Analog input channel 2
Analog input pin 3
AN3
Input
Analog input channel 3
Analog input pin 4
AN4
Input
Analog input channel 4
Analog input pin 5
AN5
Input
Analog input channel 5
Analog input pin 6
AN6
Input
Analog input channel 6
Analog input pin 7
AN7
Input
Analog input channel 7
Analog input pin 8
AN8
Input
Analog input channel 8
Analog input pin 9
AN9
Input
Analog input channel 9
Analog input pin A
ANA
Input
Analog input channel A
Analog input pin B
ANB
Input
Analog input channel B
A/D external trigger input pin
ADTRG
Input
External trigger input for starting A/D
conversion
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Section 24 A/D Converter
24.1.4
Register Configuration
Table 24.2 summarizes the registers of the A/D converter.
Table 24.2 A/D Converter Registers
Name
Abbrev.
R/W
Size
Initial Value Address*
Software trigger A/D result register H
ADRH
R
Byte
H'00
H'D130
Software trigger A/D result register L
ADRL
R
Byte
H'00
H'D131
Hardware trigger A/D result register H
AHRH
R
Byte
H'00
H'D132
Hardware trigger A/D result register L
AHRL
R
Byte
H'00
H'D133
A/D control register
ADCR
R/W
Byte
H'40
H'D134
A/D control/status register
ADCSR
R (W)*
Byte
H'01
H'D135
A/D trigger selection register
ADTSR
R/W
Byte
H'FC
H'D136
Port mode register 0
PMR0
R/W
Byte
H'00
H'FFCD
1
2
Notes: 1. Only 0 can be written in bits 7 and 6, to clear the flag. Bits 3 to 1 are read-only.
2. Lower 16 bits of the address.
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Section 24 A/D Converter
24.2
Register Descriptions
24.2.1
Software-Triggered A/D Result Register (ADR)
ADRH
Bit :
15
14
13
12
11
ADRL
10
9
8
7
6
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
Initial value :
0
0
0
0
0
0
0
0
0
0
R/W :
R
R
R
R
R
R
R
R
R
R
5
4
3
2
1
0
—
—
—
—
—
—
0
—
0
—
0
—
0
—
0
—
0
—
The software-triggered A/D result register (ADR) is a register that stores the result of an A/D
conversion started by software.
The A/D-converted data is 10-bit data. Upon completion of software-triggered A/D conversion,
the 10-bit result data is transferred to ADR and the data is retained until the next softwaretriggered A/D conversion completion. The upper 8 bits of the data are stored in the upper bytes
(bits 15 to 8) of ADR, and the lower 2 bits are stored in the lower bytes (bits 7 and 6). Bits 5 to 0
are always read as 0.
ADR can be read by the CPU at any time, but the ADR value during A/D conversion is not fixed.
The upper bytes can always be read directly, but the data in the lower bytes is transferred via a
temporary register (TEMP). For details, see section 24.3, Interface to Bus Master.
ADR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop
mode, standby mode, watch mode, subactive mode and subsleep mode.
24.2.2
Hardware-Triggered A/D Result Register (AHR)
AHRH
Bit :
15
14
13
12
11
AHRL
10
9
8
7
6
AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2 AHR1 AHR0
Initial value :
0
0
0
0
0
0
0
0
0
0
R/W :
R
R
R
R
R
R
R
R
R
R
5
4
3
2
1
0
—
—
—
—
—
—
0
—
0
—
0
—
0
—
0
—
0
—
The hardware-triggered A/D result register (AHR) is a register that stores the result of an A/D
conversion started by hardware (internal signal: ADTRG and DFG) or by external trigger input
(ADTRG).
The A/D-converted data is 10-bit data. Upon completion of hardware- or external-triggered A/D
conversion, the 10-bit result data is transferred to AHR and the data is retained until the next
hardware- or external- triggered A/D conversion completion. The upper 8 bits of the data are
stored in the upper bytes (bits 15 to 8) of AHR, and the lower 2 bits are stored in the lower bytes
(bits 7 and 6). Bits 5 to 0 are always read as 0.
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Section 24 A/D Converter
AHR can be read by the CPU at any time, but the AHR value during A/D conversion is not fixed.
The upper bytes can always be read directly, but the data in the lower bytes is transferred via a
temporary register (TEMP). For details, see section 24.3, Interface to Bus Master.
AHR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop
mode, standby mode, watch mode, subactive mode and subsleep mode.
24.2.3
A/D Control Register (ADCR)
Bit :
7
CK
6
—
5
HCH1
4
HCH0
3
SCH3
2
SCH2
1
SCH1
0
SCH0
Initial value :
0
R/W
1
—
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W :
ADCR is a register that sets A/D conversion speed and selects analog input channel. When
executing ADCR setting, make sure that the SST and HST flags in ADCSR is set to 0.
ADCR is an 8-bit readable/writable register that is initialized to H'40 by a reset, and in module
stop mode, standby mode, watch mode, subactive mode and subsleep mode.
Bit 7⎯Clock Select (CK): Sets A/D conversion speed.
Bit 7
CK
Description
0
Conversion frequency is 266 states
1
Conversion frequency is 134 states
(Initial value)
Note: A/D conversion starts when 1 is written in SST, or when HST is set to 1. The conversion
period is the time from when this start flag is set until the flag is cleared at the end of
conversion. Actual sample-and-hold takes place (repeatedly) during the conversion
frequency shown in figure 24.2.
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Section 24 A/D Converter
States
Instruction execution
MOV.B
WRITE
Start flag
Conversion frequency
Conversion period (134 or 266 states)
Interrupt request flag
IRQ sampling
(CPU)
Note: IRQ sampling; When conversion ends, the start flag is cleared and the interrupt request flag is
set. The CPU recognizes the interrupt in the last execution state of an instruction,
and executes interrupt exception handling after completing the instruction.
Figure 24.2 Internal Operation of A/D Converter
Bit 6⎯Reserved: This bit cannot be modified and is always read as 1.
Bits 5 and 4⎯Hardware Channel Select (HCH1, HCH0): These bits select the analog input
channel that is converted by hardware triggering or triggering by an external input. Only channels
AN8 to ANB are available for hardware- or external-triggered conversion.
Bit 5
Bit 4
HCH1
HCH0
Analog Input Channel
0
0
AN8
1
AN9
0
ANA
1
ANB
1
(Initial value)
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Section 24 A/D Converter
Bits 3 to 0⎯Software Channel Select (SCH3 to SCH0): These bits select the analog input
channel that is converted by software triggering.
When channels AN0 to AN7 are used, appropriate pin settings must be made in port mode register
0 (PMR0). For pin settings, see section 24.2.6, Port Mode Register 0 (PMR0).
Bit 3
Bit 2
Bit 1
Bit 0
SCH3
SCH2
SCH1
SCH0
0
0
0
0
AN0
1
AN1
0
AN2
1
AN3
0
AN4
1
AN5
0
AN6
1
AN7
0
AN8
1
AN9
0
ANA
1
ANB
*
No channel selected for software-triggered
conversion
1
1
0
1
1
0
0
1
1
*
Analog Input Channel
(Initial value)
Legend: * Don't care.
Note: If conversion is started by software when SCH3 to SCH0 are set to 11**, the conversion
result is undetermined. Hardware- or external-triggered conversion, however, will be
performed on the channel selected by HCH1 and HCH0.
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Section 24 A/D Converter
24.2.4
A/D Control/Status Register (ADCSR)
Bit :
7
SEND
6
HEND
5
ADIE
4
SST
3
HST
2
BUSY
1
SCNL
0
—
Initial value :
R/W :
0
R/(W)*
0
R/(W)*
0
R/W
0
R/W
0
R
0
R
0
R
1
—
Note: * Only 0 can be written to bits 7 and 6, to clear the flag.
The A/D status register (ADCSR) is an 8-bit register that can be used to start or stop A/D
conversion, or check the status of the A/D converter.
A/D conversion starts when 1 is written in SST flag. A/D conversion can also start by setting HST
flag to 1 by hardware- or external-triggering.
For ADTRG start by HSW timing generator in hardware triggering, see section 26.4, HSW (Headswitch) Timing Generator.
When conversion ends, the converted data is stored in the software-triggered A/D result register
(ADR) or hardware-triggered A/D result register (AHR), and the SST or HST bit is cleared to 0. If
software-triggering and hardware- or external-triggering are generated at the same time, priority is
given to hardware- or external-triggering.
ADCSR is an 8-bit register which is initialized to H'01 by a reset, and in module stop mode,
standby mode, watch mode, subactive mode and subsleep mode.
Bit 7⎯Software A/D End Flag (SEND): Indicates the end of A/D conversion.
Bit 7
SEND
Description
0
[Clearing condition]
(Initial value)
0 is written after reading 1
1
[Setting condition]
Software-triggered A/D conversion has ended
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Section 24 A/D Converter
Bit 6⎯Hardware A/D End Flag (HEND): Indicates that hardware- or external-triggered A/D
conversion has ended.
Bit 6
HEND
Description
0
[Clearing condition]
(Initial value)
0 is written after reading 1
1
[Setting condition]
Hardware- or external-triggered A/D conversion has ended
Bit 5⎯A/D Interrupt Enable (ADIE): Selects enable or disable of interrupt (ADI) generation
upon A/D conversion end.
Bit 5
ADIE
Description
0
Interrupt (ADI) upon A/D conversion end is disabled
1
Interrupt (ADI) upon A/D conversion end is enabled
(Initial value)
Bit 4⎯Software A/D Start Flag (SST): Indicates or controls the start and end of softwaretriggered A/D conversion. This bit remains 1 during software-triggered A/D conversion.
When 0 is written in this bit, software-triggered A/D conversion operation can forcibly be aborted.
Bit 4
SST
Description
0
Read: Indicates that software-triggered A/D conversion has ended or been stopped
(Initial value)
Write: Software-triggered A/D conversion is aborted
1
Read: Indicates that software-triggered A/D conversion is in progress
Write: Starts software-triggered A/D conversion
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Section 24 A/D Converter
Bit 3⎯Hardware A/D Status Flag (HST): Indicates the status of hardware- or external-triggered
A/D conversion. When 0 is written in this bit, A/D conversion is aborted regardless of whether it
was hardware-triggered or external-triggered.
Bit 3
HST
Description
0
Read: Hardware- or external-triggered A/D conversion is not in progress
(Initial value)
Write: Hardware- or external-triggered A/D conversion is aborted
1
Hardware- or external-triggered A/D conversion is in progress
Bit 2⎯Busy Flag (BUSY): During hardware- or external-triggered A/D conversion, if software
attempts to start A/D conversion by writing to the SST bit, the SST bit is not modified and instead
the BUSY flag is set to 1.
This flag is cleared when the hardware-triggered A/D result register (AHR) is read.
Bit 2
BUSY
Description
0
No contention for A/D conversion
1
Indicates an attempt to execute software-triggered A/D conversion while hardwareor external-triggered A/D conversion was in progress
(Initial value)
Bit 1⎯Software-Triggered Conversion Cancel Flag (SCNL): Indicates that software-triggered
A/D conversion was canceled by the start of hardware-triggered A/D conversion.
This flag is cleared when A/D conversion is started by software.
Bit 1
SCNL
Description
0
No contention for A/D conversion
1
Indicates that software-triggered A/D conversion was canceled by the start of
hardware-triggered A/D conversion
(Initial value)
Bit 0⎯Reserved: This bit cannot be modified and is always read as 1.
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Section 24 A/D Converter
24.2.5
Trigger Select Register (ADTSR)
Bit :
7
—
6
—
5
—
4
—
3
—
2
—
1
TRGS1
0
TRGS0
Initial value :
R/W :
1
—
1
—
1
—
1
—
1
—
1
—
0
R/W
0
R/W
The trigger select register (ADTSR) selects hardware- or external-triggered A/D conversion start
factor.
ADTSR is an 8-bit readable/writable register that is initialized to H'FC by a reset, and in module
stop mode, standby mode, watch mode, subactive mode and subsleep mode.
Bits 7 to 2⎯Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0⎯Trigger Select (TRGS1, TRGS0): These bits select hardware- or externaltriggered A/D conversion start factor. Set these bits when A/D conversion is not in progress.
Bit 1
Bit 0
TRGS1
TRGS0
Description
0
0
Hardware- or external-triggered A/D conversion is disabled
(Initial value)
1
24.2.6
1
Hardware-triggered (ADTRG) A/D conversion is selected
0
Hardware-triggered (DFG) A/D conversion is selected
1
External-triggered (ADTRG) A/D conversion is selected
Port Mode Register 0 (PMR0)
Bit :
Initial value :
R/W :
7
PMR07
6
PMR06
5
PMR05
4
PMR04
3
PMR03
2
PMR02
1
PMR01
0
PMR00
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port mode register 0 (PMR0) controls switching of each pin function of port 0. Switching is
specified for each bit.
PMR0 is an 8-bit readable/writable register and is initialized to H'00 by a reset.
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Section 24 A/D Converter
Bits 7 to 0⎯P07/AN7 to P00/AN0 Pin Switching (PMR07 to PMR00): These bits set the
P0n/ANn pin as the input pin for P0n or as the ANn pin for A/D conversion analog input channel.
Bit n
PMR0n
Description
0
P0n/ANn functions as a general-purpose input port
1
P0n/ANn functions as an analog input channel
(Initial value)
Note: n = 7 to 0
24.2.7
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit :
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value :
R/W :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR consists of 8-bit readable/writable registers and performs module stop mode control.
When the MSTP2 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus
cycle and a transition is made to module stop mode. For details, see section 4.5, Module Stop
Mode.
MSTPCR is initialized to H'FFFF by a reset
Bit 2⎯Module Stop (MSTP2): Specifies the A/D converter module stop mode.
MSTPCRL
Bit 2
MSTP2
Description
0
A/D converter module stop mode is cleared
1
A/D converter module stop mode is set
(Initial value)
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Section 24 A/D Converter
24.3
Interface to Bus Master
ADR and AHR are 16-bit registers, but the data bus to the bus master is only 8 bits wide.
Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is
accessed via a temporary register (TEMP).
A data reading from ADR and AHR is performed as follows. When the upper byte is read, the
upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the CPU.
When reading ADR and AHR, always read the upper byte before the lower byte. It is possible to
read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 24.3 shows the data flow for ADR access. The data flow for AHR access is the same.
Upper byte read
Module data bus
Bus master
(H'AA)
Bus
interface
TEMP
(H'40)
ADRH
(H'AA)
ADRL
(H'40)
Lower byte read
Bus master
(H'40)
Module data bus
Bus
interface
TEMP
(H'40)
ADRH
(H'AA)
ADRL
(H'40)
Figure 24.3 ADR Access Operation (Reading H'AA40)
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Section 24 A/D Converter
24.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution.
24.4.1
Software-Triggered A/D Conversion
A/D conversion starts when software sets the software A/D start flag (SST bit) to 1. The SST bit
remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends.
Conversion can be software-triggered on any of the 12 channels provided by analog input pins
AN0 to ANB. Bits SCH3 to SCH0 in ADCR select the analog input pin used for softwaretriggered A/D conversion. Pins AN8 to ANB are also available for hardware- or external-triggered
conversion.
When conversion ends, SEND flag in ADCSR bit is set to 1. If ADIE bit in ADCSR is also set to
1, an A/D conversion end interrupt occurs.
If the conversion time or input channel selection in ADCR needs to be changed during A/D
conversion, to avoid malfunctions, first clear the SST bit to 0 to halt A/D conversion.
If software writes 1 in the SST bit to start software-triggered conversion while hardware- or
external-triggered conversion is in progress, the hardware- or external-triggered conversion has
priority and the software-triggered conversion is not executed. At this time, BUSY flag in ADCSR
is set to 1. The BUSY flag is cleared to 0 when the hardware-triggered A/D result register (AHR)
is read. If conversion is triggered by hardware while software-triggered conversion is in progress,
the software-triggered conversion is immediately canceled and the SST flag is cleared to 0, and
SCNL flag in ADCSR is set to 1. The SCNL flag is cleared when software writes 1 in the SST bit
to start conversion after the hardware-triggered conversion ends.
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Section 24 A/D Converter
24.4.2
Hardware- or External-Triggered A/D Conversion
The system contains the hardware trigger function that allows to turn on A/D conversion at a
specified timing by use of the hardware trigger (internal signals: ADTRG and DFG) and the
incoming external trigger (ADTRG). This function can be used to measure an analog signal that
varies in synchronization with an external signal at a fixed timing.
To execute hardware- or external-triggered A/D conversion, select appropriate start factor in
TRGS1 and TRGS0 bits in ADTSR. When the selected triggering occurs, HST flag in ADCSR is
set to 1 and A/D conversion starts. The HST flag remains 1 during A/D conversion, and is
automatically cleared to 0 when conversion ends. For ADTRG start by HSW timing generator in
hardware triggering, see section 26.4, HSW (Head-switch) Timing Generator. Setting of the
analog input pins on four channels from AN8 to ANB can be modified with the hardware trigger
or the incoming external trigger. Setting is done from HCH1 and HCH0 bits on ADCR. Pins AN8
to ANB are also available for software-triggered conversion.
When conversion ends, HEND flag in ADCSR is set to 1. If ADIE bit in ADCSR is also set to 1,
an A/D conversion end interrupt occurs.
If the conversion time or input channel selection in ADCR needs to be changed during A/D
conversion, to avoid malfunctions, first clear the HST flag to 0 to halt A/D conversion.
If software writes 1 in the SST bit to start software-triggered conversion while hardware- or
external-triggered conversion is in progress, the hardware- or external-triggered conversion has
priority and the software-triggered conversion is not executed. At this time, BUSY flag in ADCSR
is set to 1. The BUSY flag is cleared to 0 when the hardware-triggered A/D result register (AHR)
is read.
If conversion is triggered by hardware while software-triggered conversion is in progress, the
software-triggered conversion is immediately canceled and the SST flag is cleared to 0, and SCNL
flag in ADCSR is set to 1 (the SCNL flag is cleared when software writes 1 in the SST bit to start
conversion after the hardware-triggered conversion ends). The analog input channel changes
automatically from the channel that was undergoing software-triggered conversion (selected by
bits SCH3 to SCH0 in ADCR) to the channel selected by bits HCH1 and HCH0 in ADCR for
hardware- or external-triggered conversion. After the hardware- or external-triggered conversion
ends, the channel reverts to the channel selected by the software-triggered conversion channel
select bits in ADCR.
Hardware- or external-triggered conversion has priority over software-triggered conversion, so the
A/D interrupt-handling routine should check the SCNL and BUSY flags when it processes the
converted data.
Rev.2.00 Jan. 15, 2007 page 528 of 1174
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Section 24 A/D Converter
24.5
Interrupt Sources
When A/D conversion ends, SEND or HEND flag in ADCSR is set to 1. The A/D conversion end
interrupt (ADI) can be enabled or disabled by ADIE bit in ADCSR.
Figure 24.4 shows the block diagram of A/D conversion end interrupt.
A/D control/status register (ADCSR)
SEND
HEND
ADIE
A/D conversion end
interrupt (ADI)
To interrupt controller
Figure 24.4 Block Diagram of A/D Conversion End Interrupt
Rev.2.00 Jan. 15, 2007 page 529 of 1174
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Section 24 A/D Converter
Rev.2.00 Jan. 15, 2007 page 530 of 1174
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Section 25 Address Trap Controller (ATC)
Section 25 Address Trap Controller (ATC)
25.1
Overview
The address trap controller (ATC) is capable of generating interrupt by setting an address to trap,
when the address set appears during bus cycle.
25.1.1
Features
Address to trap can be set independently at three points.
25.1.2
Block Diagram
Figure 25.1 shows a block diagram of the address trap controller.
ATCR
TAR0
TAR1
Internal bus
Bus
interface
Modules bus
TAR2
Trap condition comparator
Interrupt request
Legend:
ATCR
TAR0 to 2
: Address trap control register
: Trap address register 0 to 2
Figure 25.1 Block Diagram of ATC
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Section 25 Address Trap Controller (ATC)
25.1.3
Register Configuration
Table 25.1 Register List
Name
Abbrev.
R/W
Initial Value
Address*
Address trap control register
ATCR
R/W
H'F8
H'FFB9
Trap address register 0
TAR0
R/W
H'F00000
H'FFB0 to H'FFB2
Trap address register 1
TAR1
R/W
H'F00000
H'FFB3 to H'FFB5
Trap address register 2
TAR2
R/W
H'F00000
H'FFB6 to H'FFB8
Note:
Lower 16 bits of the address.
*
25.2
Register Descriptions
25.2.1
Address Trap Control Register (ATCR)
Bit :
7
6
5
4
3
2
1
0
—
—
—
—
—
TRC2
TRC1
TRC0
Initial value :
1
1
1
1
1
0
0
0
R/W :
—
—
—
—
—
R/W
R/W
R/W
Bits 7 to 3⎯Reserved: These bits cannot be modified and are always read as 1.
Bit 2⎯Trap Control 2 (TRC2): Sets ON/OFF operation of the address trap function 2.
Bit 2
TRC2
Description
0
Address trap function 2 disabled
1
Address trap function 2 enabled
(Initial value)
Bit 1⎯Trap Control 1 (TRC1): Sets ON/OFF operation of the address trap function 1.
Bit 1
TRC1
Description
0
Address trap function 1 disabled
1
Address trap function 1 enabled
Rev.2.00 Jan. 15, 2007 page 532 of 1174
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(Initial value)
Section 25 Address Trap Controller (ATC)
Bit 0⎯Trap Control 0 (TRC0): Sets ON/OFF operation of the address trap function 0.
Bit 0
TRC0
Description
0
Address trap function 0 disabled
1
Address trap function 0 enabled
25.2.2
(Initial value)
Trap Address Register 2 to 0 (TAR2 to TAR0)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
A23
A22
A21
A20
A19
A18
A17
A16
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
A15
A14
A13
A12
A11
A10
A9
A8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
—
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
—
The TAR is composed of three 8-bit readable/writable registers (TARnA, B, and C) (n = 2 to 0)
The TAR sets the address to trap. The function of the TAR2 to TAR0 is the same.
The TAR is initialized to H'00 by a reset.
TARA bits 7 to 0: Addresses 23 to 16 (A23 to A16)
TARB bits 7 to 0: Addresses 15 to 8 (A15 to A8)
TARC bits 7 to 0: Addresses 7 to 1 (A7 to A1)
If the value installed in this register and internal address buses A23 to A1 match as a result of
comparison, an interruption occurs.
For the address to trap, set to the address where the first byte of an instruction exists. In the case of
other addresses, it may not be considered that the condition has been satisfied.
Bit 0 of this register is fixed at 0. The address to trap becomes an even address.
The range where comparison is made is H'000000 to H'FFFFFE.
Rev.2.00 Jan. 15, 2007 page 533 of 1174
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Section 25 Address Trap Controller (ATC)
25.3
Precautions in Usage
Address trap interrupt arises 2 states after prefetching the trap address. Trap interrupt may occur
after the trap instruction has been executed, depending on a combination of instructions
immediately preceding the setting up of the address trap.
If the instruction to trap immediately follows the branch instruction or the conditional branch
instruction, operation may differ, depending on whether the condition was satisfied or not, or the
address to be stacked may be located at the branch. Figures 25.2 to 25.22 show specific operations.
For information as to where the next instruction prefetch occurs during the execution cycle of the
instruction, see appendix A.5, Bus Status during Instruction Execution of this manual or section
2.7 Bus State during Execution of Instruction of the H8S/2600 and H8S/2000 Series Software
Manual. (R: W NEXT is the next instruction prefetch.)
25.3.1
Basic Operations
After terminating the execution of the instruction being executed in the second state from the trap
address prefetch, the address trap interrupt exception handling is started.
1. Figure 25.2 shows the operation when the instruction immediately preceding the trap address is
that of 3 states or more of the execution cycle and the next instruction prefetch occurs in the
state before the last 2 states. The address to be stacked is 0260.
Data
read
MOV
NOP Internal
instruc- instruc- operation
tion
tion
pre-fetch pre-fetch
Start of exception
handling
(ER3 = H'0000)
φ
Address bus
025E
0260
0000
0262
Immediately Address
preceding → 025E MOV.B @ER3+,R2L
Instruction * 0260 NOP
0262 NOP
0264 NOP
MOV
execution
Interrupt
request
signal
* Trap setting address
The underlines address is the
one to be actually stacked.
Note: In the figure above, the NOP instruction is used as the typical example of instruction with
execution cycle of 1 state. Other instructions with the execution cycle of 1 state also apply
(Ex. MOV.B, Rs, Rd).
Figure 25.2 Basic Operations (1)
Rev.2.00 Jan. 15, 2007 page 534 of 1174
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Section 25 Address Trap Controller (ATC)
2. Figure 25.3 shows the operation when the instruction immediately preceding the trap address is
that of 2 states or more of the execution cycle and the next instruction prefetch occurs in the
second state from the last. The address to be stacked is 0268.
MOV
NOP
Data
instruc- instruc- read
tion
tion
pre-fetch pre-fetch
NOP
instruction
pre-fetch
Start of exception
handling
φ
Address bus
0266 0268 0000 026A
MOV
execution
Immediately Address
preceding → 0266 MOV.B
instruction
R2L, @0000
* 0268 NOP
026A NOP
026C NOP
026C
NOP
execution
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.3 Basic Operations (2)
3. Figure 25.4 shows the operation when the instruction immediately preceding the trap address is
that of 1 state or 2 states or more and the prefetch occurs in the last state. The address to be
stacked is 025C.
NOP
NOP
NOP
NOP
instruc- instruc- instruc- instruction
tion
tion
tion
pre-fetch pre-fetch pre-fetch pre-fetch
Start of
exception
handling
φ
Address bus
0256 0258 025A 025C
Address
Immediately → 0256 NOP
* 0258 NOP
preceding
025A NOP
instruction
025C NOP
025E NOP
025E
NOP NOP
NOP
execu- execu- execution
tion
tion
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.4 Basic Operations (3)
Rev.2.00 Jan. 15, 2007 page 535 of 1174
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Section 25 Address Trap Controller (ATC)
25.3.2
Enabling
The address trap function becomes valid after executing one instruction following the setting of
the enable bit of the address trap control register (ATCR) to 1.
029C
*029E
02A0
02A2
02A4
02A6
BSET #0, @TRCR
MOV.W R0, R1
MOV.B R1L, R3H
NOP
CMP.W R0, R1
NOP
After executing the MOV instruction,
the address trap interrupt does not
arise, and the next instruction is
executed.
Note: * Trap setting address
Figure 25.5 Enabling
25.3.3
Bcc Instruction
1. When the condition is satisfied by Bcc instruction (8-bit displacement)
If the trap address is the next instruction to the Bcc instruction and the condition is satisfied by
the Bcc instruction and then branched, transition is made to the address trap interrupt after
executing the instruction at the branch. The address to be stacked is 02A8.
BEQ
NOP
CMP
NOP
instruc- instruc- instruc- instruction
tion
tion
tion
pre-fetch pre-fetch pre-fetch pre-fetch
Start of
exception
handling
φ
Address bus
029C 029E 02A6 02A8
BEQ
execution
02AA
CMP
execution
(NEXT = H'02A6)
029C
* 029E
02A0
02A2
02A4
02A6
02A8
BEQ NEXT:8
NOP
NOP
NOP
NOP
CMP.W R0, R1
NOP
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.6 When the Condition Satisfied by Bcc Instruction (8-Bit Displacement)
Rev.2.00 Jan. 15, 2007 page 536 of 1174
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Section 25 Address Trap Controller (ATC)
2. When the condition is not satisfied by Bcc instruction (8-bit displacement)
If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied
by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt
after executing the trap address instruction and prefetching the next instruction. The address to
be stacked is 02A2.
BEQ
NOP
CMP
NOP
instruc- instruc- instruc- instruction
tion
tion
tion
pre-fetch pre-fetch pre-fetch pre-fetch
Start of
exception
handling
(NEXT = H'02A8)
029E
* 02A0
02A2
02A4
02A6
NEXT: 02A8
02AA
φ
Address bus
029E 02A0 02A8 02A2
BEQ
execution
02A4
NOP
execution
BEQ NEXT:8
NOP
NOP
NOP
NOP
CMP.W R0, R1
NOP
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.7 When the Condition Not Satisfied by Bcc Instruction (8-Bit Displacement)
Rev.2.00 Jan. 15, 2007 page 537 of 1174
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Section 25 Address Trap Controller (ATC)
3. When condition is not satisfied by Bcc instruction (16-bit displacement)
If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied
by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt
after executing the trap address instruction (if the trap address instruction is that of 2 states or
more. If the instruction is that of 1 state, after executing two instructions). The address to be
stacked is 02C0.
BEQ
instruction
pre-fetch
Data
fetch
Internal
operation
NOP
NOP
NOP
instruc- instruc- instruction
tion
tion
pre-fetch pre-fetch pre-fetch
Start of
exception handling
(NEXT = H'02C4)
φ
Address bus
02B8
02BA
02BC 02BE 02C0
BEQ
execution
02C2
NOP NOP
execu- execution
tion
02B8 BEQ NEXT:16
* 02BC NOP
02BE NOP
02C0 NOP
02C2 NOP
NEXT: 02C4 NOP
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.8 When the Condition Not Satisfied by Bcc Instruction (16-Bit Displacement)
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REJ09B0329-0200
Section 25 Address Trap Controller (ATC)
4. When the condition is not satisfied by Bcc instruction (Trap address at branch)
When the trap address is at the branch of the Bcc instruction and the condition is not satisfied
by the Bcc instruction and thus it fails to branch, transition is made into the address trap
interrupt after executing the next instruction (if the next instruction is that of 2 states or more.
If the next instruction is that of 1 state, after executing two instructions). The address to be
stacked is 0262.
BEQ
NOP
CMP
NOP
NOP
instruc- instruc- instruc- instruc- instruction
tion
tion
tion
tion
pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch
Start of
exception
handling
φ
Address bus
025C 025E 0266 0260 0262
BEQ
execution
0264
NOP NOP
execu- execution
tion
(NEXT = H'0266)
025C
025E
0260
0262
0264
NEXT: * 0266
0268
BEQ NEXT:8
NOP
NOP
NOP
NOP
CMP.W R0, R1
NOP
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.9 When the Condition Not Satisfied by Bcc Instruction
(Trap Address at Branch)
Rev.2.00 Jan. 15, 2007 page 539 of 1174
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Section 25 Address Trap Controller (ATC)
25.3.4
BSR Instruction
1. BSR Instruction (8-bit displacement)
When the trap address is the next instruction to the BSR instruction and the addressing mode is
an 8-bit displacement, transition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02C2.
BSR
NOP
MOV
instruc- instruc- instruction
tion
tion
pre-fetch pre-fetch pre-fetch
Stack
saving
Start of
exception handling
0294
* 0296
0298
:
φ
Address bus
(@ER0 = H'02C2)
0294 0296 02C2 SP−2 SP−4
02C4
BSR execution
02C2
02C4
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.10 BSR Instruction (8-Bit Displacement)
Rev.2.00 Jan. 15, 2007 page 540 of 1174
REJ09B0329-0200
BSR @ER0
NOP
NOP
:
MOV.W R4, @OUT
NOP
Section 25 Address Trap Controller (ATC)
25.3.5
JSR Instruction
1. JSR Instruction (Register indirect)
When the trap address is the next instruction to the JSR instruction and the addressing mode is
a register indirect, transition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02C8.
JSR
NOP
MOV
instruc- instruc- instruction
tion
tion
pre-fetch pre-fetch pre-fetch
Stack
saving
Start of
exception
handling
029A
* 029C
029E
:
φ
Address bus
(@ER0 = H'02C8)
029A 029C 02C8 SP−2 SP−4
02CA
JSRexecution
02C8
02CE
JSR @ER0
NOP
NOP
:
MOV.W R4, @OUT
NOP
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.11 JSR Instruction (Register Indirect)
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REJ09B0329-0200
Section 25 Address Trap Controller (ATC)
2. JSR Instruction (Memory indirect)
When the trap address is the next instruction to the JSR instruction and the addressing mode is
memory indirect, transition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02EA.
JSR
NOP
instruc- instruction
tion
pre-fetch pre-fetch
Data
fetch
Stack
saving
NOP
instruction
pre-fetch
Start of
exception
handling
φ
Address bus
0294 0296 006C 006E SP−2 SP−4 02EA
02EC
JSR execution
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.12 JSR Instruction (Memory Indirect)
Rev.2.00 Jan. 15, 2007 page 542 of 1174
REJ09B0329-0200
006C
:
0294
* 0296
0298
:
02EA
02EC
H'02EA
:
JSR @@H'6C:8
NOP
NOP
:
NOP
NOP
Section 25 Address Trap Controller (ATC)
25.3.6
JMP Instruction
1. JMP Instruction (Register indirect)
When the trap address is the next instruction to the JMP instruction and the addressing mode is
a register indirect, transition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02AA.
JMP
NOP
MOV
instruc- instruc- instruction
tion
tion
pre-fetch pre-fetch pre-fetch
Data
fetch
NOP
instruction
pre-fetch
Start of
exception
handling
φ
Address bus
029A 029C 02A4 02A6 02A8 02AA
JMP
execution
02AC
MOV.L
execution
(@ER0 = H'02A4)
029A
* 029C
029E
02A0
02A2
02A4
02AA
JMP @ER0
NOP
NOP
NOP
NOP
MOV.L #DATA, ER1
NOP
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.13 JMP Instruction (Register Indirect)
2. JMP Instruction (Memory indirect)
When the trap address is the next instruction to the JMP instruction and the addressing mode is
memory indirect, transition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02E4.
Rev.2.00 Jan. 15, 2007 page 543 of 1174
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Section 25 Address Trap Controller (ATC)
JMP
NOP
instruc- instruction
tion
pre-fetch pre-fetch
Data
fetch
Internal NOP
opera- instruction
tion
Start of
exception
handling
pre-fetch
006C
:
0294
* 0296
0298
:
φ
Address bus
0294 0296 006C 006E 006C 02E4
02E6
02E4
02E6
JMP execution
H'02E4
:
JMP @@H'6C:8
NOP
NOP
:
NOP
NOP
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.14 JMP Instruction (Memory Indirect)
25.3.7
RTS Instruction
When the trap address is the next instruction to the RTS instruction, transition is made to the
address trap interrupt after reading the CCR and PC from the stack and prefetching the instruction
at the return location. The address to be stacked is 0298.
RTS
NOP
instruc- instruction
tion
pre-fetch pre-fetch
Stack
saving
Internal NOP
opera- instruction
tion
pre-fetch
Start of
exception
handling
0296
0298
029A
φ
Address bus
02AC 02AE
SP
SP+2
SP
0298
029A
RTS execution
Break interrupt
request signal
Notes:
(@ER0 = H'02C8)
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.15 RTS Instruction
Rev.2.00 Jan. 15, 2007 page 544 of 1174
REJ09B0329-0200
BSR SUB
NOP
NOP
:
02AC
* 02AE
:
RTS
NOP
Section 25 Address Trap Controller (ATC)
25.3.8
SLEEP Instruction
1. SLEEP Instruction 1
When the trap address is the SLEEP instruction and the instruction execution cycle
immediately preceding the SLEEP instruction is that of 2 states or more and prefetch does not
occur in the last state, the SLEEP instruction is not executed and transition is made to the
address trap interrupt without going into SLEEP mode. The address to be stacked is 0274.
MOV SLEEP Data
NOP
instruc- instrucinstrucwrite
tion
tion
tion
pre-fetch pre-fetch
pre-fetch
Start of
exception
handling
φ
Address bus
0272 0274 FFF9
MOV
execution
0276
SP−2 SP−4
0272
* 0274
0276
0278
:
MOV.B R2L, @FFF8
SLEEP
NOP
NOP
:
SLEEP
cancel
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.16 SLEEP Instruction (1)
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Section 25 Address Trap Controller (ATC)
2. SLEEP Instruction 2
When the trap address is the SLEEP instruction and the instruction execution cycle
immediately preceding the SLEEP instruction is that of 1 state 2 states or more and prefetch
occurs in the last state, this puts in the SLEEP mode after execution of the SLEEP instruction,
and the SLEEP mode is cancelled by the address trap interrupt and transition is made to the
exception handling. The address to be stacked is 0264.
NOP SLEEP NOP
instruc- instruc- instruction
tion
tion
pre-fetch pre-fetch pre-fetch
Start of
exception
handling
φ
Address bus
0260 0262
NOP
SLEEP
execution execution
0264
SP−2 SP−4
SLEEP
mode
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.17 SLEEP Instruction (2)
Rev.2.00 Jan. 15, 2007 page 546 of 1174
REJ09B0329-0200
0260
* 0262
0264
0266
:
NOP
SLEEP
NOP
NOP
:
Section 25 Address Trap Controller (ATC)
3. SLEEP Instruction 3
When the trap address is the next instruction to the SLEEP instruction, this puts in the SLEEP
mode after execution of the SLEEP instruction, and the SLEEP mode is cancelled by the
address trap interrupt and transition is made to the exception handling. The address to be
stacked is 0282.
SLEEP NOP
instruc- instruction
tion
pre-fetch pre-fetch
Start of
exception
handling
φ
Address bus
0280
0282
SLEEP
execution
SP−2 SP−4
027E
0280
* 0282
0284
:
NOP
SLEEP
NOP
NOP
:
SLEEP mode
Interrupt
request
signal
Notes:
The underlined address is the one to be actually stacked.
* Trap setting address
Figure 25.18 SLEEP Instruction (3)
Rev.2.00 Jan. 15, 2007 page 547 of 1174
REJ09B0329-0200
Section 25 Address Trap Controller (ATC)
4. SLEEP Instruction 4 (Standby or Watch Mode Setting)
When the trap address is the SLEEP instruction and the instruction immediately preceding the
SLEEP instruction is that of 1 state or 2 states or more and prefetch occurs in the last state, this
puts in the standby (watch) mode after execution of the SLEEP instruction. After that, if the
standby (watch) mode is cancelled by the NMI interrupt, transition is made to NMI interrupt
following the CCR and PC (at the address of 0266) stack saving and vector reading. However,
if the address trap interrupt arises before starting execution of the NMI interrupt processing,
transition is made to the address trap exception handling. The address to be stacked is the
starting address of the NMI interrupt processing.
NOP SLEEP NOP
instruc- instruc- instruction
tion
tion
pre-fetch pre-fetch pre-fetch
NMI
interrupt
Address trap
interruption
0262
* 0264
0266
φ
Address bus
0262 0264
0266
SP−2 SPCA SP−2
SLEEP Standby
execution mode
Interrupt
request
signal
Note: * Trap setting address
Figure 25.19 SLEEP Instruction (4) (Standby or Watch Mode Setting)
Rev.2.00 Jan. 15, 2007 page 548 of 1174
REJ09B0329-0200
NOP
SLEEP
NOP
Section 25 Address Trap Controller (ATC)
5. SLEEP Instruction 5 (Standby or Watch Mode Setting)
When the trap address is the next instruction to the SLEEP instruction, this puts in the standby
(watch) mode after execution of the SLEEP instruction. After that, if the standby (watch) mode
is cancelled by the NMI interruption, transition is made to the NMI interrupt following the
CCR and PC (at the address of 0266) stack saving and vector reading. However, if the address
trap interrupt arises before starting execution of the NMI interrupt processing, transition is
made to the address trap exception handling. The address to be stacked is the starting address
of the NMI interrupt processing.
NOP SLEEP
instruc- instruction
tion
pre-fetch pre-fetch
NMI
interruption
Address trap
interrupt
0280
0282
* 0284
φ
Address bus
0280 0282
0284
NOP
SLEEP
NOP
SP−2 SPCA SP−2
SLEEP Standby
execution mode
Interrupt
request
signal
Note: * Trap setting address
Figure 25.20 SLEEP Instruction (5) (Standby or Watch Mode Setting)
25.3.9
Competing Interrupt
1. General Interrupt (Interrupt other than NMI)
When the ATC interrupt request is made at the timing in (1) (A) against the general interrupt
request, the interruption appears to take place in the ATC at the timing earlier than usual,
because higher priority is assigned to the ATC interrupt processing (Simultaneous interrupt
with the general interrupt has no effect on processing). The address to be stacked is 029E.
For comparison, the case where the trap address is set at 02A0 if no general interrupt request
was made is shown in (2). The address to be stacked is 02A4.
Rev.2.00 Jan. 15, 2007 page 549 of 1174
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Section 25 Address Trap Controller (ATC)
0296 MOV.B R2L, @Port
029A NOP
029C NOP Set one of these to the
029E NOP
02A0 NOP trap address
02A2 NOP
02A4 NOP
Start of general
NOP
MOV
instruc- Data instruction
tion
read pre-fetch
pre-fetch
(1)
Data
write
interrupt processing
NOP
NOP
instruc- instruction
tion
pre-fetch pre-fetch Range of start of ATC
interrupt processing
φ
Address bus
0296 0298 029A
Port
MOV execution
029C
029E
02A0
SP−2 SP−4 Vector Vector
NOP NOP
execu- execution
tion
General Interrupt
request signal
(A)
Interrupt
request signal
Address
to be
stacked
(2)
0296 MOV.B R2L, @Port
029A NOP
029C NOP
029E NOP
02A0 NOP Trap address
02A2 NOP
02A4 NOP
MOV
NOP
instruc- Data instruction
read tion
pre-fetch
pre-fetch
Data
write
NOP
NOP
NOP
NOP
NOP
instruc- instruc- instruc- instruc- instruction
tion
tion
tion
tion
pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch
Start of ATC interrupt
processing
φ
Address bus
0296 0298 029A
Port
MOV execution
029C
029E 02A0 02A2 02A4
NOP NOP
NOP NOP NOP
execu- execu- execu- execu- execution
tion
tion
tion
tion
Interrupt
request
signal
Figure 25.21 Competing Interrupt (General Interrupt)
Rev.2.00 Jan. 15, 2007 page 550 of 1174
REJ09B0329-0200
02A6
SP−2
Section 25 Address Trap Controller (ATC)
2. In case of NMI
When the NMI interruption request is made at the timing in (1) (A) against the ATC interrupt
request, the interrupt appears to take place in NMI at the timing earlier than usual, because
higher priority is assigned to the NMI interrupt processing. The ATC interrupt processing
starts after fetching the instruction at the starting address of the NMI interrupt processing. The
address to be stacked is 02E0 for the NMI and 340 for the ATC.
When the ATC interrupt request is made at the timing in (2) (B) against the NMI interrupt
request, the ATC interrupt processing starts after fetching the instruction at the starting address
of the NMI interrupt processing. The address to be stacked is 02E6 for the NMI and 0340 for
the ATC.
Rev.2.00 Jan. 15, 2007 page 551 of 1174
REJ09B0329-0200
φ
Rev.2.00 Jan. 15, 2007 page 552 of 1174
REJ09B0329-0200
φ
Figure 25.22 Competing Interrupt (In Case of NMI)
ATC interrupt
request signal
NMI interrupt
request signal
Address bus
(2)
ATC interrupt
request signal
NMI interrupt
request signal
Address bus
(1)
02E2
NMI interrupt
processing
NOP
instruction
pre-fetch
02DC 02DE 02E0 02E2 02E4 02E6
(B)
02E8
0342
NOP
instruction
pre-fetch
02DC
02DE
02E0
02E2
02E4
02E6
02E8
:
:
0340
0342
Start of ATC
Interrupt processing
SP−6 SP−8 Vector
Start of ATC interrupt processing
SP−2 SP−4 Vector Vector Vector 0340
NMI interrupt
processing
NMI vector
read
SP−2 SP−4 Vector Vector Vector 0340
Start of ATC interrupt processing
NOP
NOP
NOP
NOP
NOP
NOP
instruc- instruc- instruc- instruc- instruc- instruction
tion
tion
tion
tion
tion
pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch
(A)
NOP NOP
execu- execution tion
02DC 02DE 02E0
NOP
NOP
NOP
instruc- instruc- instruction
tion
tion
pre-fetch pre-fetch pre-fetch
NOP (1) Set to the trap address
NOP
NOP
NOP
NOP
(2) Set one of these to
NOP
the trap address
NOP
:
:
The starting address of NMI
interrupt
Section 25 Address Trap Controller (ATC)
Section 26 Servo Circuits
Section 26 Servo Circuits
26.1
Overview
26.1.1
Functions
Servo circuits for a video cassette recorder are included on-chip.
The functions of the servo circuits can be divided into four groups, as listed in table 26.1.
Rev.2.00 Jan. 15, 2007 page 553 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
Table 26.1 Servo Circuit Functions
Group
Function
(1) Input and CTL I/O amplifier
output circuits
(2) Error
detectors
Description
Gain variable input amplifier
Output amplifier with rewrite mode
CFGDuty compensation input
Duty accuracy: 50 ±2%
(Zero cross type comparator)
DFG, DPG separation/overlap
input
Overlap input available: Three-level input
method, DFG noise mask function
Reference signal generators
V compensation, field detection, external signal
sync, V sync in REC mode, REF30 signal output
to outside
HSW timing generator
Head-switching signals, FIFO 20 stages
Compatible with DFG counter soft-reset
Four-head high-speed switching
circuit for special playback
Chroma-rotary/head-amplifier switching output
12-bit PWM
Improved speed of carrier frequency
Frequency division circuit
With CFG mask, no CFG for phase or CTL mask
Sync detection circuit
Noise count, field discrimination, Hsync
compensation, Hsync detection noise mask
Drum speed error detector
Lock detector function, pause at the counter
overflow, R/W error latch register, limiter function
Drum phase error detector
Latch signal selectable, R/W error latch register
Capstan speed error detector
Lock detector function, pause at the counter
overflow, R/W error latch register, limiter function
Capstan phase error detector
R/W error latch register
X-value adjustment and tracking
adjustment circuit
(Separate setting available)
(3) Phase and Digital filter computation circuit
gain
compensation
Computations performed automatically by
hardware
Output gain variable: ×2 to ×64 (exponents of 2)
-1
(Partial write in Z (high-order 8 bits) available)
(4) Other
circuits
Additional V signal circuit
Valid in special playback
CTL circuit
Duty discrimination circuit, CTL head R/W
control, compatible with wide aspect
26.1.2
Block Diagram
Figure 26.1 shows a block diagram of the servo circuits.
Rev.2.00 Jan. 15, 2007 page 554 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
PPG0 to 7/
(P70 to 77)
RP0 to B/
(P60 to 67,
P74 to 77)
PPG0 to 7/
(P70 to 77)
RP0 to B/
(P60 to 67,
P74 to 77)
EXTTRG(P86)
Csync
4-head
special
playback
controller
Sync
separator
OSCH
COMP(P85)
C.Rotary(P83)
H.Amp SW(P84)
Additional
V pulse
generator
Vpulse
System
clock
VD
REC:ON
Res Drum system
reference
signal
Capstan
system
reference
signal
XE:ON
Head-switch
timing
generator
AudioFF
VideoFF
ADTRIG
DPG(P87)
Phase
error
detector
Noise
Det.
Ep
Digital
filter
DFG
Speed
error
detector
Es
+
Digital
filter
PWM
+
Gain up.
CAP
PWM
PWM
Gain up.
Frequency
divider
CFG
Speed
error
detector
DVCFG2
DVCFG
+
Digital
filter
A/D
converter
AN pins
CREF
DRM
PWM
REF30P(PB:30Hz,REC:1/2VD)
(HSW)
+
Es
SV2(P31)
(
)
EXCTL(P82)
)
DVCTL
Internal signal
monitor
controller
SV1(P30)
(
)
REF30,REF30X,CREF,
CTLMONI,DVCFG,
DFG,DPG,DFG,etc
Timer X1
Timer L
Timer R
REC
PB.ASM
Frequency
divider
CTLFB
PB.CTL
CTL Amp
+-+
Gain control
by register
setting
-+
CTL Head +
Phase
error
detector
Ep
Digital
filter
(NTSC)
PB.
ASM REC
(PAL)
REF30X
VISS
circuit
(Duty deter- DutyI/O
minator)
X-value
adjustment
REC-CTL
generator
(Assemble
recording)
REC-CTL
CTL Head -
EXCAP(P81)
Figure 26.1 Block Diagram of Servo Circuits
Rev.2.00 Jan. 15, 2007 page 555 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
26.2
Servo Port
26.2.1
Overview
This LSI is equipped with seventeen pins dedicated to the servo circuit and twenty-nine pins
multiplexed with general-purpose ports. It also has an input amplifier to amplify CTL signals, a
CTL output amplifier, a CTL Schmitt comparator, and a CFG zero cross type comparator. The
CTL input amplifier allows gain adjustment by software. DFG and DPG signals, which control the
drum, can be input as separate signals or an overlapped signal.
SV1 and SV2 pins allow internal signals of the servo circuit to be output for monitoring. The
signals to be output can be selected out of eight kinds of signals. See the description of Servo
Monitor Control Register (SVMCR) in section 26.2.5, Register Description.
26.2.2
Block Diagram
1. DFG and DPG Input Circuit
The DFG and DPG input pins have on-chip Schmit circuits. Figure 26.2 shows the input circuit
of DFG and DPG.
DPG SW
DFG
DFG
DPG
DPG
RES+LPM
DPG SW
Figure 26.2 Input Circuit of DFG and DPG
Rev.2.00 Jan. 15, 2007 page 556 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
2. CFG Input Circuit
The CFG input pin has an amplifier and a zero cross type comparator. Figure 26.3 shows the
input circuit of CFG.
+
BIAS
P250
VREF
REF
CFGCOMP
-
M250
F/F
S
CFGCOMP
O
R stp
CFG
+
VREF
+
CFG
-
RES+ModuleSTOP
Figure 26.3 CFG Input Circuit
Rev.2.00 Jan. 15, 2007 page 557 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
3. CTL Input Circuit
The CTL input pin has an amplifier. Figure 26.4 shows the input circuit of CTL.
AMPON
(PB-CTL)
AMPSHORT
(REC-CTL)
CTLGR3 to 1
CTLFB
CTLGR0
- +
+
-
-
+
PB-CTL(+)
PB-CTL(-)
CTL(-)
CTL(+)
CTLREF
CTLBias
CTLFB
CTLAmp(o)
CTLSMT(i)
Note
Note: Be sure to connect a capacitor between CTLAmp (o) and CTLSMT (i)
Figure 26.4 CTL Input Circuit
26.2.3
Pin Configuration
Table 26.2 shows the pin configuration of the servo circuit. P30, P31, P6n, P7n, and P81 to P87
are general-purpose ports. As for P3, P6, P7, and P8, see section 10, I/O Port.
Rev.2.00 Jan. 15, 2007 page 558 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
Table 26.2 Pin Configuration
Name
Abbrev.
I/O
Function
Servo Vcc pin
SVCC
Input
Power source pin for servo circuit
Servo Vss pin
SVSS
Input
Power source pin for servo circuit
Audio head switching pin
Audio FF
Output
Audio head switching signal output
Video head switching pin
Video FF
Output
Video head switching signal output
Capstan mix pin
CAPPWM
Output
12-bit PWM square wave output
Drum mix pin
DRMPWM
Output
12-bit PWM square wave output
Additional V pulse pin
Vpulse
Output
Additional V signal output
Color rotary signal output pin
P83/C.Rotary
I/O, Output
General-purpose port/control signal output
port for processing color signals
Head amplifier switching pin
P84/H.Amp SW I/O, Output
General-purpose port/pre-amplifier output
selection signal input
Compare signal input pin
P85/COMP
I/O, Input
General-purpose port/pre-amplifier output
result signal input
CTL (+) I/O pin
CTL (+)
I/O
CTL signal input/output
CTL (-) I/O pin
CTL (-)
I/O
CTL signal input/output
CTL Bias input pin
CTLBias
Input
CTL primary amplifier bias supply
CTL Amp (O) output pin
CTLAMP (O)
Output
CTL amplifier output
CTL SMT (I) input pin
CTLSMT (I)
Input
CTL Schmitt amplifier input
CTL FB input pin
CTLFB
Input
CTL amplifier high-range characteristics
control
CTL REF output pin
CTLREF
Output
CTL amplifier reference voltage output
Capstan FG amplifier input pin
CFG
Input
CFG signal amplifier input
Drum FG input pin
DFG
Input
DFG signal input
Drum PG input pin
P87/DPG
I/O, Input
General-purpose port/DPG signal input
External CTL signal input pin
P82/EXCTL
I/O, Input
General-purpose port/external CTL signal
input/
Composite sync signal input pin
Csync
Input
Composite sync signal input
External reference signal input pin P86/EXTTRG
I/O, input
General-purpose port/external reference
signal input
External capstan signal input pin
P81/EXCAP
I/O, input
General-purpose port/external capstan
signal input
Servo monitor signal output pin 1
P30/SV1
I/O, output
General-purpose port/servo monitor signal
output
Servo monitor signal output pin 2
P31/SV2
I/O, output
General-purpose port/servo monitor signal
output
PPG output pin
P7n/PPGn
I/O, output
General-purpose port/PPG output
RTP output pin
P6n/RPn,
P7n/RPn
I/O, output
General-purpose port/RTP output
Rev.2.00 Jan. 15, 2007 page 559 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
26.2.4
Register Configuration
Table 26.3 shows the register configuration of the servo port section.
Table 26.3 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address
Servo port mode register
SPMR
R/W
Byte
H'5F
H'D0A0
Servo monitor control register
SVMCR
R/W
Byte
H'C0
H'D0A3
CTL gain control register
CTLGR
R/W
Byte
H'C0
H'D0A4
26.2.5
Register Description
Servo Port Mode Register (SPMR)
Bit :
Initial value :
R/W :
7
CTLSTOP
6
⎯
5
CFGCOMP
4
⎯
3
⎯
2
⎯
1
⎯
0
⎯
0
R/W
1
⎯
0
R/W
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
SPMR is an 8-bit read/write register that switches the CFG input system.
It is initialized to H'5F by a reset or in stand-by mode.
Bit 7⎯CTLSTOP Bit (CTLSTOP): Controls whether the CTL circuit is operated or stopped.
Bit 7
CTLSTOP
Description
0
CTL circuit operates
1
CTL circuit stops operation
Bit 6⎯Reserved: Cannot be modified and is always read as 1.
Rev.2.00 Jan. 15, 2007 page 560 of 1174
REJ09B0329-0200
(Initial value)
Section 26 Servo Circuits
Bit 5⎯CFG Input System Switching Bit (CFGCOMP) : Selects whether the CFG input signal
system is set to the zero cross type comparator system or digital signal input system.
Bit 5
CFGCOMP Description
0
CFG signal input system is set to the zero cross type comparator system.
(Initial value)
1
CFG signal input system is set to the digital signal input system.
Bits 4 to 0⎯Reserved: Cannot be modified and are always read as 1.
Servo Monitor Control Register (SVMCR)
Bit :
7
—
6
—
Initial value :
R/W :
1
—
1
—
5
4
3
2
1
0
SVMCR5 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
SVMCR is an 8-bit read/write register that selects the monitor signal output from the SV1 and
SV2 pins when the P30/SV1 pin is used as the SV1 monitor output pin or when the P31/SV2 pin is
used as the SV2 monitor output pin. It is initialized to H'C0 by a reset or in stand-by mode.
Bits 7 and 6⎯Reserved: Cannot be modified and are always read as 1.
Bits 5 to 3⎯SV2 Pin Servo Monitor Output Control(SVMCR5 to SVMCR3): select the servo
monitor signal output from the SV2 pin.
Bit 5
Bit 4
Bit 3
SVMCR5
SVMCR4
SVMCR3
Description
0
0
0
Outputs REF30 signal to SV2 output pin.
1
Outputs CAPREF30 signal to SV2 output pin.
0
Outputs CREF signal to SV2 output pin.
1
Outputs CTLMONI signal to SV2 output pin.
0
Outputs DVCFG signal to SV2 output pin.
1
Outputs CFG signal to SV2 output pin.
0
Outputs DFG signal to SV2 output pin.
1
Outputs DPG signal to SV2 output pin.
1
1
0
1
(Initial value)
Rev.2.00 Jan. 15, 2007 page 561 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
Bits 2 to 0⎯SV1 Pin Servo Monitor Output Control (SVMCR2 to SVMCR0): Select the
servo monitor signal output from the SV1 pin.
Bit 2
Bit 1
Bit 0
SVMCR2
SVMCR1
SVMCR0
Description
0
0
0
Outputs REF30 signal to SV1 output pin.
1
Outputs CAPREF30 signal to SV1 output pin.
0
Outputs CREF signal to SV1 output pin.
1
Outputs CTLMONI signal to SV1 output pin.
1
1
0
1
0
Outputs DVCFG signal to SV1 output pin.
1
Outputs CFG signal to SV1 output pin.
0
Outputs DFG signal to SV1 output pin.
1
Outputs DPG signal to SV1 output pin.
(Initial value)
CTL Gain Control Register (CTLGR)
Bit :
7
—
6
—
5
CTLE/A
4
CTLFB
3
CTLGR3
2
CTLGR2
1
CTLGR1
0
CTLGR0
Initial value :
R/W :
1
—
1
—
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
CTLGR is an 8-bit read/write register that turns on or off the CTLFB switch in the CTL amplifier
circuit and specifying the CTL amplifier gain. It is initialized to H'C0 by a reset or in stand-by
mode.
Bits 7 and 6⎯Reserved: Cannot be modified and are always read as 1.
Bit 5⎯CTL Selection Bit (CTLE/A): Controls whether the amplifier output or EXCTL is used
as the CTLP signal supplied to the CTL circuit.
Bit 5
CTLE/A
Description
0
AMP output
1
EXCTL
Rev.2.00 Jan. 15, 2007 page 562 of 1174
REJ09B0329-0200
(Initial value)
Section 26 Servo Circuits
Bit 4⎯SW Bit of the Feedback Section of CTL Amplifier (CTLFB): Turns on or off the switch
of the feedback section to adjust the gain. See figure 26.4.
Bit 4
CTLFB
Description
0
Turns off CTLFB SW
1
Turns on CTLFB SW
(Initial value)
Bits 3 to 0⎯CTL Amplifier Gain Setting Bits (CTLGR3 to CTLGR0): Set the output gain of
the CTL amplifier.
Bit 3
Bit 2
Bit 1
Bit 0
CTLGR3
CTLGR2
CTLGR1
CTLGR0
0
0
0
0
34.0 dB
1
36.5 dB
0
39.0 dB
1
41.5 dB
0
44.0 dB
1
46.5 dB
0
49.0 dB
1
51.5 dB
0
54.0 dB
1
56.5 dB
0
59.0 dB
1
61.5 dB
0
64.0 dB
66.5 dB*
1
1
0
1
1
0
0
1
1
0
1
1
0
1
Note:
*
CTL Output Gain
(Initial value)
69.0 dB*
71.5 dB*
With a setting of 65.0 dB or more, the CTLAMP is in a very sensitive status. When
configuring the set board, take a countermeasure against noise around the control head
signal input port. Also, consider well the setting of the filter between the CTLAMP and
the CTLSMT.
Rev.2.00 Jan. 15, 2007 page 563 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
26.2.6
DFG/DPG Input Signals
DFG and DPG signals can be input either as separate signals or as an overlapped signal. When the
latter is selected (PMR87 = 1), take care to control the input levels of DFG and DPG. Figure 26.5
shows DFG/DPG input signals.
DPG
DPG Schmitt level
3.45/3.55
VIL/VIH
DFG
DFG Schmitt level
1.85/1.95
VIL/VIH
(1) DPG/DFG separate input (PMR87 = 0)
DPG Schmitt level
DFG Schmitt level
DFG/DPG
(2) DPG/DFG overlapped input (PMR87 = 1)
Figure 26.5 DFG/DPG Input Signals
Rev.2.00 Jan. 15, 2007 page 564 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
26.3
Reference Signal Generators
26.3.1
Overview
The reference signal generators consist of a REF30 signal generator and a CREF signal generator
and create the reference signals (REF30 and CREF signals) used in phase comparison, etc. The
REF30 signal is used to control the phase of the drum and capstan. The CREF signal is used if
REF30 signal cannot be used as the reference signal to control the phase of the capstan in REC
mode. Each signal generator consists of a 16-bit counter which uses the servo clock φ s/2 (or φ s/4)
as its clock source, a reference period register, and a comparator.
The value set in the reference period register should be 1/2 of the desired reference signal period.
26.3.2
Block Diagram
Figure 26.6 shows the block diagram of REF30 signal generator. Figure 26.7 shows that of CREF
signal generator.
Rev.2.00 Jan. 15, 2007 page 565 of 1174
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Figure 26.6 REF30 Signal Generator
Rev.2.00 Jan. 15, 2007 page 566 of 1174
REJ09B0329-0200
φs = fosc/2
φs/4
φs/2
RCS
W
W
Reference period buffer 1 (16 bits)
W
Internal bus
External
frequency
signal
(EXTTRG)
Field
VD
detection
signal
OD/EV
Dummy read
Match
Mask
Reference period register 1 (16 bits)
Comparator (16 bits)
Counter (16 bits)
REF30 counter register (16 bits)
R/W
Internal bus
W
REX
R/W
TBC
REC/PB
ASM
PB→REC
FDS
R/W
Toggle
Clear
PB
VST
W
W
V noise detection signal
REF30
REF30P
Video FF
W
CVS
↑ Edge
detection
VNA
Edge
detection
↑,↓
VEG
W
Section 26 Servo Circuits
Section 26 Servo Circuits
PB(ASM)
↓
REC
Q S
Counter clear
R
φs/2
DVCFG2
Counter (16 bits)
φs/4
Clear
Comparator (16 bits)
Match
↑ Edge
detection
Toggle
CREF
Reference period register 2 (16 bits)
RCS
Reference period buffer 2 (16 bits)
W
CRD
Dummy read
W
W
Internal bus
φs = fosc/2
Figure 26.7 Block Diagram of CREF Signal Generator
26.3.3
Register Configuration
Table 26.4 shows the register configuration of the reference signal generators.
Table 26.4 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address
Reference period mode
register
RFM
W
Byte
H'00
H'D096
Reference period register 1
RFD
W
Word
H'FFFF
H'D090
Reference period register 2
CRF
W
Word
H'FFFF
H'D092
REF30 counter register
RFC
R/W
Word
H'0000
H'D094
Reference period mode
register 2
RFM2
R/W
Byte
H'FE
H'D097
Rev.2.00 Jan. 15, 2007 page 567 of 1174
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Section 26 Servo Circuits
26.3.4
Register Description
Reference Period Mode Register (RFM)
Bit :
Initial value :
R/W :
7
RCS
6
VNA
5
CVS
4
REX
3
CRD
2
OD/EV
1
VST
0
VEG
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
RFM is an 8-bit write-only register which determines the operational state of the reference signal
generators. If a read is attempted, an undetermined value is read out.
It is initialized to H'00 by a reset and in stand-by and module stop modes.
RFM is accessible in byte units only. If accessed by a word, correct operation is not guaranteed.
Bit 7⎯Clock Source Selection Bit (RCS): Selects the clock source supplied to the counter.
(φs = fosc/2)
Bit 7
RCS
Description
0
φs/2
1
φs/4
(Initial value)
Bit 6⎯Mode Selection Bit (VNA): Selects the mode for controlling transition to free-run
operation when the REF30 signal is generated synchronously with the VD signal in REC mode:
automatic mode which controls the transition by the V noise detection signal detected by the sync
signal detection circuit, or manual mode which controls the transition by software.
Bit 6
VNA
Description
0
Manual mode
1
Automatic mode
Rev.2.00 Jan. 15, 2007 page 568 of 1174
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(Initial value)
Section 26 Servo Circuits
Bit 5⎯Manual Selection Bit (CVS): Selects whether the REF30 signal is generated
synchronously with VD or it is operated in free-run state in the manual mode (VNA = 0). (This
selection is ignored in PB mode except in TBC mode.)
Bit 5
CVS
Description
0
Synchronous with VD
1
Free-run operation
(Initial value)
Bit 4⎯External Signals Sync Selection Bit (REX): Selects whether the REF30 signal is
generated synchronously with VD, in free-run state or synchronously with the external signal.
(Valid in both PB and REC modes.)
Bit 4
REX
Description
0
VD signal or free-run
1
Synchronous with external signal
(Initial value)
Bit 3⎯DVCFG2 Sync Selection Bit (CRD): Selects whether the reset timing in the CREF signal
generation is immediately after switching the mode or it is synchronous with the DVCFG2 signal
immediately after the mode switching.
Bit 3
CRD
Description
0
On switching the mode
1
Synchronous with DVCFG2 signal
(Initial value)
Bit 2⎯ODD/EVEN Edge Switching Selection Bit (OD/EV): Selects whether the REF30P signal
is generated by the rising edge (even) or falling edge (odd) of the field signal in REC mode.
Bit 2
OD/EV
Description
0
Generated at the rising edge of the field signal
1
Generated at the falling edge of the field signal
(Initial value)
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Section 26 Servo Circuits
Bit 1⎯Video FF Counter Set (VST): Selects whether the REF30 counter register value is set on
or off by the Video FF signal when the drum phase is in FIX on in the PB mode.
Bit 1
VST
Description
0
Counter set off by Video FF signal
1
Counter set on by Video FF signal
(Initial value)
Bit 0⎯Video FF Edge Selection Bit (VEG): Selects the edge at which REF30 counter is set
(VST = 1) by the Video FF signal.
Bit 0
VEG
Description
0
Set at the rising edge of Video FF signal
1
Set at the falling edge of Video FF signal
(Initial value)
Reference Period Register 1 (RFD)
Bit :
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
REF15 REF14 REF13 REF12 REF11 REF10 REF9 REF8 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W :
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
The reference period register 1 (RFD) is a buffer register which generates the reference signal
(REF30) for playback, VD compensation for recording, and the reference signals for free-running.
It is an 16-bit write-only register accessible in word units only. If a read is attempted, an
undetermined value is read out.
The value set in RFD should be 1/2 of the desired reference signal period. Care is required when
VD is unstable, such as when the field is weak (synchronization with VD cannot be acquired if a
value less than 1/2 is set in REC). When data is written in RFD, it is stored in the buffer once, and
then fetched into RFD by a match signal of the comparator. (The data which generates the
reference signal is updated by the match signal.) A forcible write, such as initial setting, etc.,
should be done by a dummy read of RFD.
If a byte-write in RFD is attempted, correct operation is not guaranteed. RFD is initialized to
H'FFFF by a reset, and in stand-by and module stop modes.
Use bit 7 (ASM) and bit 6 (REC/PB) in the CTL mode register (CTLM) in the CTL circuit to
switch between record and playback modes. Use bit 4 (CR/RF bit) in the capstan phase error
detection control register (CPGCR) to switch between REF30 and CREF for capstan phase
control.
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Section 26 Servo Circuits
Reference Period Register 2 (CRF)
Bit :
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CRF15 CRF14 CRF13 CRF12 CRF11 CRF10 CRF9 CRF8 CRF7 CRF6 CRF5 CRF4 CRF3 CRF2 CRF1 CRF0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W :
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
The reference period register 2 (CRF) is an 16-bit write-only buffer register which generates the
reference signals to control the capstan phase (CREF). CRF is accessible in word units only. If a
read is attempted, an undetermined value is read out. The value set in CRF should be 1/2 of the
desired reference signal period.
When data is written in CRF, it is stored in the buffer once, and then fetched into CRF by a match
signal of the comparator. (The data which generates the reference signal is updated by the match
signal.) A forcible write, such as initial setting, etc., should be done by a dummy read of CRF.
If a byte-write in CRF is attempted, correct operation is not guaranteed. CRF is initialized to
H'FFFF by a reset and in stand-by and module stop modes.
Use bit 4 (CR/RF bit) in the capstan phase error detection control register (CPGCR) to switch
between REF30 and CREF for capstan phase control. See section 26.9, Capstan Phase Error
Detector.
REF30 Counter Register (RFC)
Bit :
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8 RFC7 RFC6 RFC5 RFC4 RFC3 RFC2 RFC1 RFC0
Initial value :
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The REF30 counter register (RFC) is a register which determines the initial value of the free-run
counter when it generates REF30 signals in playback. When data is written in RFC, its value is
written in the counter by a match signal of the comparator. If the bit 1 (VST) of RFM is set to 1,
the counter is set by the Video FF signal when the drum phase is in FIX ON. The counter setting
by the Video FF signal should be done by setting bit 1 (VST) and bit 0 (VEG) of the RFM. Do not
set the RFC to a value greater than 1/2 of the reference period register 1 (RFD) value.
RFC is a read/write register. If a read is attempted, the value of the counter is read out. If a byteaccess is attempted, correct operation is not guaranteed. RFC is initialized to H'0000 by a reset and
in stand-by and module stop modes.
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Section 26 Servo Circuits
Reference Period Mode Register 2 (RFM2)
Bit :
7
TBC
6
⎯
5
⎯
4
⎯
3
⎯
2
⎯
1
⎯
0
FDS
Initial value :
R/W :
1
R/W
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
REM2 is an 8-bit read/write register which determines the operational state of the reference signal
generators.
It is initialized to H'FE by a reset and in stand-by and module stop modes. RFM2 is a byte accessonly register; if accessed by a word, correct operation is not guaranteed.
Bit 7⎯TBC Selection Bit (TBC): Selects whether the reference signal in PB mode is generated
by the VD signal or by the free-run counter.
Bit 7
TBC
Description
0
Generated by the VD signal
1
Generated by the free-run counter
(Initial value)
Bits 6 to 1⎯Reserved: Cannot be modified and are always read as 1.
Bit 0⎯Field Selection Bit (FDS): Determines whether selection between ODD or EVEN is made
for the field signal when PB mode was switched over to REC mode, or these signals are
synchronized with VD signals within a phase error of 90° immediately after the switching over.
Bit 0
FDS
Description
0
Generated by the VD signal of ODD or EVEN selected
1
Generated by the VD signal within mode transition phase error of 90°
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(Initial value)
Section 26 Servo Circuits
26.3.5
Operation
• Operation of REF30 Signal Generator
The REF30 signal generator generates the reference signals required to control the phase of the
drum and capstan.
To generate the REF30 signal, set the 1/2 the reference period to the reference period register 1
(RFD) corresponding to the 50 percent duty cycle. In playback mode, the REF30 signal is
generated by free-running the REF30 signal generator. The generator has the external signal
synchronization function, and if the bit 4 (REX) of the reference period mode register (RFM)
is set to 1, it generates the REF30 signal from the external signal (EXTTGR).
In record mode, the reference signal is generated from the VD signal generated in the sync
detector. Any VD drop-out caused by weak field intensity, etc., is compensated by a value set
in RFD. To cope with the VD noises, the generator automatically masks the VD for a period
about 75% of the RFD setting after REF30 signal was changed due to VD. In record mode, the
generation of the reference signal either by VD or free-run operation can be controlled
automatically using the V noise detection signal detected in the sync signal detection circuit or
manually by software. Select which is used by setting bit 6 (VNA) or 5 (CVS) of RFM.
The phase of the toggle output of the REF30 signal is cleared to L level when the mode shifts
from PB to REC (ASM). Also the frame servo function can be set, allowing for control of the
phase of REF30 signals with the field signal detected in the sync signal detection circuit. Use
bit 2 (OD/EV) of RFM for such control.
See the description of CTL mode register (CTLM) in section 26.13.5, Register Description, as
for switching over between PB, ASM and REC.
• Operation of the Mask Circuit
The REF30 signal generator has a toggle mask circuit and a counter mask (counter set signal
mask) circuit built-in. Each mask circuit masks irregular VD signals which may occur when
the VD signal is unstable because of weak field intensity, etc., in record mode.
The toggle mask and counter mask circuits mask the VD automatically for about 75% of
double the period set in the reference period register 1 (RFD) after VD signal was detected (see
figure 26.9). If a VD signal dropped out and V was compensated, the toggle mask circuit
begins masking, but the counter mask circuit does not begin masking for about 25% of the
period. If VD signal was detected during such a period, the circuit does masking for about 75%
of the period after the VD detection. If not detected, it does masking for about 75% of the
period after V was compensated (see figures 26.10 and 26.11).
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Section 26 Servo Circuits
• Timing of the REF30 Signal Generation
Figures 26.8 to 26.12 show the timing of the generation of REF30 and REF30P signals.
Counter set
Counter set
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
REF30
REF30P
Figure 26.8 REF30 Signals in Playback Mode
Rev.2.00 Jan. 15, 2007 page 574 of 1174
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Counter set
Section 26 Servo Circuits
Field signal
VD
Selected VD
(OD/EV = 0)
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
Toggle mask
Masking
period
Counter mask
(clear signal mask)
Masking
period
About 75%
REF30
REF30P
HSW
Drum phase counter
Sampling
T
Sampling
Sampling
Figure 26.9 Generation of Reference Signal in Record Mode (Normal Operation)
Rev.2.00 Jan. 15, 2007 page 575 of 1174
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Section 26 Servo Circuits
Field signal
Drop-out of V
VD
Selected VD
(OD/EV = 0)
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
Toggle mask
Cleared
Cleared
Masking
period
About 75%
Counter mask
(clear signal mask)
Cleared
About 75%
About 75%
Masking
period
About 75%
About
25%
REF30
REF30P
HSW
Drum phase counter
Sampling
T
Sampling
Sampling
Figure 26.10 Generation of the Reference Signal when in REC (V Dropped Out)
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Section 26 Servo Circuits
Field signal
Dislocation of V
VD
Selected VD
(OD/EV = 0)
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
Toggle mask
Cleared
Cleared
Masking
period
About 75%
Counter mask
(clear signal mask)
Cleared
About 75%
Masking
period
About 75%
About 75%
REF30
REF30P
HSW
Drum phase counter
Sampling
T
Sampling
Sampling
Figure 26.11 Generation of the Reference Signal when in REC (V Dislocated)
Rev.2.00 Jan. 15, 2007 page 577 of 1174
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Section 26 Servo Circuits
External sync
signal
Cleared
Cleared
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
Reset
REF30
REF30P
Figure 26.12 Generation of REF30 Signal by the External Sync Signal
• CREF Signal Generator
The CREF signal generator generates the CREF signal which is the reference signal to control
the phase of capstan.
To generate the CREF signal, set the 1/2 the reference period to the reference period register 2
(CRF). If the set value matches the counter value, a toggle waveform is generated
corresponding to the 50 percent duty cycle, and a one-shot pulse is output at each rising edge
of the waveform. The counter of CREF signal generator is initialized to H'0000 and the phase
of the toggle is cleared to L level when the mode shifts from PB (ASM) to REC. The timing of
clearing is selectable between immediately after the transition from PB (ASM) to REC and the
timing of DVCFG2 after the transition. Use bit 3 (CRD) of the reference period mode register
(RFM) for this selection.
In the capstan phase error detection circuit, either REF30 signal or CREF signal can be
selected for the reference signal. Use either of them according to the use of the system.
Use the CREF signal to control the phase of the capstan at a period which is different from the
period used to control the phase of the drum. For the switching between REF30 and CREF in
the capstan phase control, see the description of capstan phase error detection control register
(CPGCR) in section 26.9.4, Register Description.
Rev.2.00 Jan. 15, 2007 page 578 of 1174
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Section 26 Servo Circuits
• Timing Chart of the CREF Signal Generation
Figures 26.13 to 26.15 show the generation of CREF signal.
Cleared
Cleared
Cleared
Value set in reference
period register 2 (CRF)
Counter
Toggle signal
CREF
Figure 26.13 Generation of CREF Signal
Rev.2.00 Jan. 15, 2007 page 579 of 1174
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Section 26 Servo Circuits
Cleared
Cleared
Cleared
Value set in reference
period register 2 (CRF)
Counter
REC/PB
Toggle signal
Period set in CRF
CREF
PB(ASM)
REC
Figure 26.14 CREF Signal when PB Is Switched to REC (when CRD Bit = 0)
Rev.2.00 Jan. 15, 2007 page 580 of 1174
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Section 26 Servo Circuits
Cleared
Cleared
Cleared
Value set in reference
period register 2 (CRF)
Counter
REC/PB
DVCFG2
Toggle signal
Period set in CRF
CREF
PB(ASM)
REC
Figure 26.15 CREF Signal when PB Is Switched to REC (when CRD Bit = 1)
Rev.2.00 Jan. 15, 2007 page 581 of 1174
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Section 26 Servo Circuits
Figures 26.16 and 26.17 show REF30 (REF30P) when PB is switched to REC.
PB
REC(ASM)
Field signal
VD (except in PB)
Selected VD*
(OD/EV = 0)
REC/PB
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
Cleared Cleared
Toggle mask
Masking
period
Counter mask
(Clear signal mask)
Masking
period
Cleared
Cleared
About 75%
Cleared
REF30
REF30P
Note: * In the field discrimination mode
Figure 26.16 Generation of the Reference Signal when PB Is Switched to REC (1)
Rev.2.00 Jan. 15, 2007 page 582 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
PB
REC(ASM)
Field signal
VD (except in PB)
Selected VD
(OD/EV = 0)
REC/PB
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
Cleared
Cleared
Cleared
Toggle mask
Masking
period
Counter mask
(Clear signal mask)
Masking
period
About
50%
Cleared
REF30
REF30P
Figure 26.17 Generation of the Reference Signal when PB Is Switched to REC (2)
Rev.2.00 Jan. 15, 2007 page 583 of 1174
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Section 26 Servo Circuits
Figures 26.18 to 26.21 show REF30 (REF30P) when PB is switched to REC (where FDS bit = 1).
PB
REC(ASM)
REC/PB
VD (except in PB)
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
Cleared
Toggle mask
Masking
period
Counter mask
(Clear signal mask)
Masking
period
Cleared
Cleared
REF30
REF30P
FDS bit = 1
Figure 26.18 Generation of the Reference Signal when PB Is Switched to REC
where RFD Bit Is 1 (1)
Rev.2.00 Jan. 15, 2007 page 584 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
PB
REC(ASM)
REC/PB
VD (except in PB)
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
Toggle mask
Masking
period
Counter mask
(Clear signal mask)
Masking
period
25%
25%
25%
REF30
REF30P
FDS bit = 1
Figure 26.19 Generation of the Reference Signal when PB Is Switched to REC
where RFD Bit Is 1 (when VD Signal Is Not Detected) (2)
Rev.2.00 Jan. 15, 2007 page 585 of 1174
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Section 26 Servo Circuits
PB
REC(ASM)
REC/PB
VD (except in PB)
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
Cleared
Toggle mask
Masking
period
Counter mask
(Clear signal mask)
Masking
period
Cleared
25% max.
REF30
REF30P
FDS bit = 1
Figure 26.20 Generation of the Reference Signal when PB Is Switched to REC
where RFD Bit Is 1 (3)
Rev.2.00 Jan. 15, 2007 page 586 of 1174
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Section 26 Servo Circuits
PB
REC(ASM)
REC/PB
VD (except in PB)
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
Cleared
Toggle mask
Masking
period
Counter mask
(Clear signal mask)
Masking
period
Cleared
25% max.
REF30
REF30P
FDS bit = 1
Figure 26.21 Generation of the Reference Signal when PB Is Switched to REC
where RFD Bit Is 1 (4)
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Section 26 Servo Circuits
26.4
HSW (Head-switch) Timing Generator
26.4.1
Overview
The HSW timing generator consists of a 5-bit DFG counter, a 16-bit timer counter, a matching
circuit, and two 31-bit 10-stage FIFOs.
The 5-bit counter counts the DFG pulses following a DPG pulse. Each of them determines the
timing to reset the 16-bit timer counter for each field. The 16-bit timer counter is a timer clocked
by a φ s/4 clock source, and can be used as a programmable pattern generator (PPG) as well as a
free-running counter (FRC). If used as a free-running counter, it is cleared by overflow of the
prescaler unit. Accordingly, two FRCs operate synchronously. The matching circuit compares the
timing data in the most significant 16 bits of FIFO with the 16-bit timer counter, and controls the
output of the pattern data set in the least significant 15 bits of FIFO.
26.4.2
Block Diagram
Figure 26.22 shows a block diagram of the HSW timing generator.
Rev.2.00 Jan. 15, 2007 page 588 of 1174
REJ09B0329-0200
DPG ↑
FRCOVF
NCDFG
EDG
R/W
↑, ↓
Edge
detector
Comparator
(5 bits)
W
CCLR
DFCRA
Cleared
5-bit counter
R
R
R/W
HSM1
R/W
R/W
FGR20FF
HSM2
Comparator
(5 bits)
R/W
FRT
DFCRB
DFG reference
register 2
FLA,B EMPA,B OVWA,B CLRA,B
R
DFCRA
DFG reference
register 1
W W
DFCTR
HSW loop stage
number setting
register
HSLP
R/W
W
CKSL
DFCRA
W
15 bits
15 bits
R
FTCTR (16 bits)
16-bit timer counter
Cleared
Compare circuit (16 bits)
W
R/W
ISEL1
DFCRA
W
ISEL2
W
15 bits
FIFO output pattern
register 2
FPDRB
AudioFF
IRRHSW2
VideoFF
IRRHSW1
ADTRG
Vpulse
Mlevel
NHSW
HSW
P77 to 70
(PPG output)
FIFO2
(31 bits × 10 stages)
16 bits
FIFO timing pattern
register 2
FTPRB
HSM2
STRIG
R/W
VFF/NFF
HSM2
VD PB
Capture
FIFO output selector & output buffer
16 bits
W
FIFO output pattern
register 1
FPDRA
FIFO 1
(31 bits × 10 stages)
16 bits
FIFO timing pattern
register 1
FTPRA
Internal bus
φ s/8 φ s/4
CLK
HSM2
R
Internal bus
LOP SOFG OFG
R/W
Control
circuit
R/W
Section 26 Servo Circuits
Figure 26.22 Block Diagram of the HSW Timing Generator
Rev.2.00 Jan. 15, 2007 page 589 of 1174
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Section 26 Servo Circuits
26.4.3
HSW Timing Generator Configuration
The HSW timing generator is composed of the elements shown in table 26.5.
Table 26.5 Configuration of the HSW Timing Generator
Element
Function
HSW mode register 1 (HSM1)
Confirmation/determination of this circuits' operating
status
HSW mode register 2 (HSM2)
Confirmation/determination of this circuits' operating
status
HSW loop stage number setting register
(HSLP)
Setting of number of loop stages in loop mode
FIFO output pattern register 1 (FPDRA)
Output pattern register of FIFO1
FIFO output pattern register 2 (FPDRB)
Output pattern register of FIFO2
FIFO timing pattern register 1 (FTPRA)
Output timing register of FIFO1
FIFO timing pattern register 2 (FTPRB)
Output timing register of FIFO2
DFG reference register 1 (DFCRA)
Setting of reference DFG edge for FIFO1
DFG reference register 2 (DFCRB)
Setting of reference DFG edge for FIFO2
FIFO timer capture register (FTCTR)
Capture register of timer counter
DFG reference count register (DFCTR)
DFG edge count
FIFO control circuit
FIFO status control
DFG count compare circuit (×2)
Detection of match between DFCR and DFG counters
16-bit timer counter
16-bit free-run timer counter
31-bit x 20 stage FIFO
First In First Out data buffer
31-bit FIFO data buffer
Data storing buffer for the first stage of FIFO
16-bit compare circuit
Detection of match between timer counter and FIFO
data buffer
FPDRA and FPDRB are intermediate buffers; an FTPRA and FTPRB write results in
simultaneous writing of all 31 bits to the FIFO. The FIFO has two 31-bit x 10-stage data buffers;
its operating status is controlled by HSM1 and HSM2. Data is stored in the 31-bit data buffer. The
values of FTPRA/FTPRB and the timer counter are compared, and if they match, the 15-bit
pattern data is output to each function. AudioFF, VideoFF, and PPG (P70 to P77) are outputs from
the corresponding pins, ADTRG is the A/D converter hardware start signal, Vpulse and Mlevel
signals are the signals for generating the additional V pulses, and HSW and NHSW signals are the
same as VideoFF signals used for the phase control of the drum. The 16-bit timer counter is
initialized by the overflow of the prescaler unit in the free-run mode (FRT bit of HSM2 = 1), or by
Rev.2.00 Jan. 15, 2007 page 590 of 1174
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Section 26 Servo Circuits
a signal indicating a match between DFCRA/DFCRB and the 5-bit DFG counter in DFG reference
mode.
26.4.4
Register Configuration
Table 26.6 shows the register configuration of the HSW timing generator.
Table 26.6 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address
HSW mode register 1
HSM1
R/W
Byte
H'30
H'D060
HSW mode register 2
HSM2
R/W
Byte
H'00
H'D061
HSW loop stage number setting
register
HSLP
R/W
Byte
Undetermined
H'D062
FIFO output pattern register 1
FIFO timing pattern register 1*
FPDRA
W
Word
Undetermined
H'D064
FTPRA
W
Word
Undetermined
H'D066
FIFO output pattern register 2
FPDRB
W
Word
Undetermined
H'D068
FIFO timing pattern register 2
DFG reference register 1*
FTPRB
W
Word
H'FFFF
H'D06A
DFCRA
W
Byte
Undetermined
H'D06C
DFG reference register 2
DFCRB
W
Byte
Undetermined
H'D06D
FIFO timer capture register*
FTCTR
R
Word
H'0000
H'D066
DFG reference count register*
DFCTR
R
Byte
H'E0
H'D06C
Note:
26.4.5
FTPRA and FTCTR, as well as DFCRA and DFCTR, are allocated to the same
addresses.
*
Register Description
HSW Mode Register 1 (HSM1)
Bit :
Initial value :
R/W :
7
FLB
6
FLA
5
EMPB
4
EMPA
3
OVWB
2
OVWA
1
CLRB
0
CLRA
0
R
0
R
1
R
1
R
0
R/(W)*
0
R/(W)*
0
R/W
0
R/W
Note: * Only 0 can be written
HSM1 is an 8-bit register which confirms and determines the operational state of the HSW timing
generator.
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Section 26 Servo Circuits
Bits 7 to 4 are read-only bits, and write is disabled. All the other bits accept both read and write. It
is initialized to H'30 by a reset or in stand-by mode.
Bit 7⎯FIFO2 Full Flag (FLB): When the FLB bit is 1, it indicates that the FIFO2 is full of the
timing pattern data and the output pattern data. If a write is attempted in this state, the write
operation becomes invalid, an interrupt is generated, the OVWB flag (bit 3) is set to 1, and the
write data is lost. Wait until space becomes available in the FIFO2, then write again.
Bit 7
FLB
Description
0
FIFO2 is not full, and can accept data input.
1
FIFO2 is full of data.
(Initial value)
Bit 6⎯FIFO1 Full Flag (FLA): When the FLA bit is 1, it indicates that the FIFO1 is full of the
timing pattern data and the output pattern data. If a write is attempted in this state, the write
operation becomes invalid, an interrupt is generated, the OVWA flag (bit 2) is set to 1, and the
write data is lost. Wait until space becomes available in the FIFO1, then write again.
Bit 6
FLA
Description
0
FIFO1 is not full, and can accept data input.
1
FIFO1 is full of data.
(Initial value)
Bit 5⎯FIFO2 Empty Flag (EMPB): Indicates that FIFO2 has no data, or that all the data has
been output in single mode.
Bit 5
EMPB
Description
0
FIFO2 contains data.
1
FIFO2 contains no data.
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(Initial value)
Section 26 Servo Circuits
Bit 4⎯FIFO1 Empty Flag (EMPA): Indicates that FIFO1 has no data, or that all the data has
been output in single mode.
Bit 4
EMPA
Description
0
FIFO1 contains data.
1
FIFO1 contains no data.
(Initial value)
Bit 3⎯FIFO2 Overwrite Flag (OVWB): If a write is attempted when the FIFO2 is full of the
timing pattern data and the output pattern data (FLB bit = 1), the write operation becomes invalid,
an interrupt is generated, the OVWB flag is set to 1, and the write data is lost. Wait until space
becomes available in the FIFO2, then write again.
Write 0 to clear the OVWB flag, because it is not cleared automatically.
Bit 3
OVWB
Description
0
Normal operation.
1
Indicates that a write in FIFO2 was attempted when FIFO2 was full of data. Clear this
flag by writing 0 to this bit.
(Initial value)
Bit 2⎯FIFO1 Overwrite Flag (OVWA): If a write is attempted when the FIFO1 is full of the
timing pattern data and the output pattern data (FLA bit = 1), the write operation becomes invalid,
an interrupt is generated, the OVWA flag is set to 1, and the write data is lost. Wait until space
becomes available in the FIFO1, then write again.
Write 0 to clear the OVWA flag, because it is not cleared automatically.
Bit 2
OVWA
Description
0
Normal operation.
1
Indicates that a write in FIFO1 was attempted when FIFO1 was full. Clear this flag by
writing 0 to this bit.
(Initial value)
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Section 26 Servo Circuits
Bit 1⎯FIFO2 Pointer Clear (CLRB): Clears the FIFO2 write position pointer. After 1 is
written, the bit immediately reverts to 0. Writing 0 in this bit has no effect.
Bit 1
CLRB
Description
0
Normal operation.
1
Clears the FIFO2 pointer.
(Initial value)
Bit 0⎯FIFO1 Pointer Clear (CLRA): Clears the FIFO1 write position pointer. After 1 is
written, the bit immediately reverts to 0. Writing 0 in this bit has no effect.
Bit 0
CLRA
Description
0
Normal operation
1
Clears the FIFO1 pointer
(Initial value)
HSW Mode Register 2 (HSM2)
Bit :
7
FRT
6
FGR2OFF
5
LOP
4
EDG
3
ISEL1
2
SOFG
1
OFG
0
VFF/NFF
Initial value :
R/W :
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
W
HSM2 is an 8-bit register which confirms and determines the operational state of the HSW timing
generator.
Bit 1 is a read-only bit, and write is disabled. Bit 0 is a write-only bit, and if a read is attempted, an
undetermined value is read out. All the other bits accept both read and write. It is initialized to
H'00 by a reset or in stand-by mode.
Bit 7⎯Free-run Bit (FRT): Selects whether the matching timing is determined by the DPG
counter and timer, or by the FRC.
Bit 7
FRT
Description
0
5-bit DFG counter + 16-bit timer counter
1
16-bit FRC
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(Initial value)
Section 26 Servo Circuits
Bit 6⎯FRG2 Clear Stop Bit (FGR2OFF): Disables clearing of the counter by the DFG register
2. The FIFO group, including both FIFO1 and FIFO2, is available.
Bit 6
FGR2OFF
Description
0
Enables clearing of the16-bit timer counter by DFG register 2
1
Disables clearing of the16-bit timer counter by DFG register 2
(Initial value)
Bit 5⎯Mode Selection Bit (LOP): Selects the output mode of FIFO. If the loop mode is selected,
LOB3 to LOB0 bits and LOA3 to LOA0 bits become valid. If the LOP bit is modified, the pointer
which counts the writing position of FIFO is cleared. In this case, the last output data is kept.
Bit 5
LOP
Description
0
Single mode
1
Loop mode
(Initial value)
Bit 4⎯DFG Edge Selection Bit (EDG): Selects the edge by which to count DFG pulses.
Bit 4
EDG
Description
0
Counts by the rising edge of DFG
1
Counts by the falling edge of DFG
(Initial value)
Bit 3⎯Interrupt Selection Bit (ISEL1): Selects the interrupt source. (IRRHSW1)
Bit 3
ISEL1
Description
0
Generates an interrupt request by the rising edge of the STRIG signal of FIFO
(Initial value)
1
Generates an interrupt request by the matching signal of FIFO
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Section 26 Servo Circuits
Bit 2⎯FIFO Output Group Selection Bit (SOFG): Selects whether 20 stages of FIFO1 +
FIFO2 or only 10 stages of FIFO1 are used.
If 20-stage output mode is used in single mode, data must be written to FIFO1 and FIFO2.
Monitor the output FIFO group flag (OFG) and control data writing by software. All the data of
FIFO1 is output, then all the data of FIFO2 is output. These steps are repeated. If 10-stage output
mode is used, the data of FIFO2 is not reflected.
Modifying the SOFG bit from 0 to 1, then again to 0 initializes the control signal of the FIFO
output stage to the FIFO1 side.
Bit 2
SOFG
Description
0
20-stage output of FIFO1 + FIFO2
1
10-stage output of FIFO1 only
(Initial value)
Bit 1⎯Output FIFO Group Flag (OFG): Indicates the FIFO group which is outputting.
Bit 1
OFG
Description
0
Pattern is being output by FIFO1
1
Pattern is being output by FIFO2
(Initial value)
Bit 0⎯Output Switching Bit between VideoFF and NarrowFF (VFF/NFF): Switches the
signal output from the VideoFF pin.
Bit 0
VFF/NFF
Description
0
VideoFF output
1
NarrowFF output
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(Initial value)
Section 26 Servo Circuits
HSW Loop Stage Number Setting Register (HSLP)
Bit :
Initial value :
R/W :
7
6
5
4
3
2
1
0
LOB3
LOB2
LOB1
LOB0
LOA3
LOA2
LOA1
LOA0
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
HSLP is an 8-bit read/write register that sets the number of the loop stages when the HSW timing
generator is in loop mode. It is valid when bit 5 (LOP) of HSM2 is 1. Bits 7 to 4 set the number of
FIFO2 stages. Bits 3 to 0 set the number of FIFO1 stages.
It is not initialized by a reset or in stand-by or module stop mode; accordingly be sure to set the
number of the stages when the loop mode is used.
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Section 26 Servo Circuits
Bits 7 to 4⎯FIFO2 Stage Number Setting Bits (LOB3 to LOB0): Set the number of FIFO2
stages in loop mode. They are valid only when the loop mode is set (LOP bit of HSM2 is 1).
HSM2
HSLP
Bit 5
Bit 7
Bit 6
Bit 5
Bit 4
LOP
LOB3
LOB2
LOB1
LOB0
Description
0
*
*
*
*
Single mode
1
0
0
0
0
Only 0th stage of FIFO2 is output
1
0th and 1st stages of FIFO2 are output
0
0th to 2nd stages of FIFO2 are output
1
0th to 3rd stages of FIFO2 are output
0
0th to 4th stages of FIFO2 are output
1
0th to 5th stages of FIFO2 are output
0
0th to 6th stages of FIFO2 are output
1
0th to 7th stages of FIFO2 are output
0
0th to 8th stages of FIFO2 are output
1
0th to 9th stages of FIFO2 are output
0
Setting prohibited
1
1
0
1
1
0
0
1
1
1
0
0
1
1
0
1
Legend: * Don't care.
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(Initial value)
Section 26 Servo Circuits
Bits 3 to 0⎯FIFO1 Stage Number Setting Bits (LOA3 to LOA0): Set the number of FIFO1
stages in loop mode. They are valid only when the loop mode is set (LOP bit of HSM2 is 1).
HSM2
HSLP
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
LOP
LOA3
LOA2
LOA1
LOA0
Description
0
*
*
*
*
Single mode
1
0
0
0
0
Only 0th stage of FIFO1 is output
1
0th and 1st stages of FIFO1 are output
0
0th to 2nd stages of FIFO1 are output
1
0th to 3rd stages of FIFO1 are output
0
0th to 4th stages of FIFO1 are output
1
0th to 5th stages of FIFO1 are output
0
0th to 6th stages of FIFO1 are output
1
0th to 7th stages of FIFO1 are output
0
0th to 8th stages of FIFO1 are output
1
0th to 9th stages of FIFO1 are output
0
Setting prohibited
1
1
0
1
1
0
0
1
(Initial value)
1
1
0
0
1
1
0
1
Legend: * Don’t care.
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Section 26 Servo Circuits
FIFO Output Pattern Register 1 (FPDRA)
Bit :
15
—
14
ADTRGA
Initial value :
R/W :
1
—
*
W
*
W
7
PPGA7
6
PPGA6
*
W
*
W
Bit :
Initial value :
R/W :
13
12
STRIGA NarrowFFA
11
VFFA
10
AFFA
9
VpulseA
8
MlevelA
*
W
*
W
*
W
*
W
*
W
5
PPGA5
4
PPGA4
3
PPGA3
2
PPGA2
1
PPGA1
0
PPGA0
*
W
*
W
*
W
*
W
*
W
*
W
Note : * Undefined
FPDRA is a buffer register for the FIFO1 output pattern register. The output pattern data written in
FPDRA is written at the same time to the position of the FIFO1 pointed by the buffer pointer. Be
sure to write the output pattern data in FPDRA before writing it in FTPRA.
FPDRA is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted,
correct operation is not guaranteed. No read is valid. If a read is attempted, an undetermined value
is read out. It is not initialized by a reset, or in stand-by or module stop mode; accordingly be sure
to write data before use.
Bit 15⎯Reserved: Cannot be read or modified.
Bit 14⎯A/D Trigger A Bit (ADTRGA): Indicates a hardware trigger signal for the A/D
converter.
Bit 13⎯S-TRIGA Bit (STRIGA): Indicates a signal that generates an interrupt. When the
STRIGB is selected by the ISEL, modifying this bit from 0 to 1 generates an interrupt.
Bit 12⎯NarrowFFA Bit (NarrowFFA): Controls the narrow video head.
Bit 11⎯VideoFFA Bit (VFFA): Controls the video head.
Bit 10⎯AudioFFA Bit (AFFA): Controls the audio head.
Bit 9⎯VpulseA Bit (VpulseA): Used for generating an additional V signal. For details, refer to
section 26.12, Additional V Signal Generator.
Bit 8⎯MlevelA Bit (MlevelA): Used for generating an additional V signal. For details, refer to
section 26.12, Additional V Signal Generator.
Bits 7 to 0⎯PPG Output Signal A Bits (PPGA7 to PPGA0): Used for outputting a timing
control signal from port 7 (PPG).
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Section 26 Servo Circuits
FIFO Output Pattern Register 2 (FPDRB)
Bit :
15
—
14
ADTRGB
Initial value :
R/W :
1
—
*
W
*
W
7
PPGB7
6
PPGB6
*
W
*
W
Bit :
Initial value :
R/W :
13
12
STRIGB NarrowFFB
11
VFFB
10
AFFB
9
VpulseB
8
MlevelB
*
W
*
W
*
W
*
W
*
W
5
PPGB5
4
PPGB4
3
PPGB3
2
PPGB2
1
PPGB1
0
PPGB0
*
W
*
W
*
W
*
W
*
W
*
W
Note : * Undefined
FPDRB is a buffer register for the FIFO2 output pattern register. The output pattern data written in
FPDRB is written at the same time to the position of the FIFO2 pointed by the buffer pointer. Be
sure to write the output pattern data in FPDRB before writing it in FTPRB.
FPDRB is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted,
correct operation is not guaranteed. No read is valid. If a read is attempted, an undetermined value
is read out. It is not initialized by a reset, or in stand-by or module stop mode; accordingly be sure
to write data before use.
Bit 15⎯Reserved: Cannot be read or modified.
Bit 14⎯A/D Trigger B Bit (ADTRGB): Indicates a hardware trigger signal for the A/D
converter.
Bit 13⎯S-TRIGB Bit (STRIGB): Indicates a signal that generates an interrupt. When the
STRIGB is selected by the ISEL, modifying this bit from 0 to 1 generates an interrupt.
Bit 12⎯NarrowFFB Bit (NarrowFFB): Controls the narrow video head.
Bit 11⎯VideoFFB Bit (VFFB): Controls the video head.
Bit 10⎯AudioFFB Bit (AFFB): Controls the audio head.
Bit 9⎯VpulseB Bit (VpulseB): Used for generating an additional V signal. For details, refer to
section 26.12, Additional V Signal Generator.
Bit 8⎯MlevelB Bit (MlevelB): Used for generating an additional V signal. For details, refer to
section 26.12, Additional V Signal Generator.
Bits 7 to 0⎯PPG Output Signal B Bits (PPGB7 to PPGB0): Used for outputting a timing
control signal from port 7 (PPG).
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Section 26 Servo Circuits
FIFO Timing Pattern Register 1 (FTPRA)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
15
14
13
12
11
10
9
FTPRA15 FTPRA14 FTPRA13 FTPRA12 FTPRA11 FTPRA10 FTPRA9
8
FTPRA8
*
W
*
W
*
W
*
W
*
W
*
W
*
W
*
W
7
FTPRA7
6
FTPRA6
5
FTPRA5
4
FTPRA4
3
FTPRA3
2
FTPRA2
1
FTPRA1
0
FTPRA0
*
W
*
W
*
W
*
W
*
W
*
W
*
W
*
W
Note : * Undefined
FTPRA is a register to write the timing pattern data of FIFO1. The timing data written in FPDRA
is written at the same time to the position of the FIFO1 pointed by the buffer pointer together with
the buffer data of FPDRA.
FTPRA is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted,
correct operation is not guaranteed. It is not initialized by a reset or in stand-by or module stop
mode; accordingly be sure to write data before use.
Note: The same address is assigned to the FTPRA and the FIFO timer capture register (FTCTR).
Accordingly, the value of FTCTR is read out if a read is attempted.
FIFO Timing Pattern Register 2 (FTPRB)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
9
10
12
11
15
14
13
FTPRB15 FTPRB14 FTPRB13 FTPRB12 FTPRB11 FTPRB10 FTPRB9
8
FTPRB8
*
W
*
W
*
W
*
W
*
W
*
W
*
W
*
W
7
FTPRB7
6
FTPRB6
5
FTPRB5
4
FTPRB4
3
FTPRB3
2
FTPRB2
1
FTPRB1
0
FTPRB0
*
W
*
W
*
W
*
W
*
W
*
W
*
W
*
W
Note : * Undefined
FTPRB is a register to write the timing pattern data of FIFO2. The timing data written in FPDRB
is written at the same time to the position of the FIFO2 pointed by the buffer pointer together with
the buffer data of FPDRB.
FTPRB is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted,
correct operation is not guaranteed. If a read is attempted, an undetermined value is read out. It is
not initialized by a reset or in stand-by or module stop mode; accordingly be sure to write data
before use.
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Section 26 Servo Circuits
DFG Reference Register 1 (DFCRA)
Bit :
Initial value :
R/W :
7
ISEL2
6
CCLR
5
CKSL
4
DFCRA4
3
DFCRA3
0
W
0
W
0
W
*
W
*
W
2
1
DFCRA2 DFCRA1
*
W
0
DFCRA0
*
W
*
W
Note : * Undefined
DFCRA is a register which determines the operation of the HSW timing generator as well as the
starting point of the timing of FIFO1.
DFCRA is an 8-bit write-only register. It is not initialized by a reset or in stand-by or module stop
mode; accordingly be sure to write data before use.
Note: The same address is assigned to the DFCRA and the DFG reference counter register
(DFCTR). Accordingly, the value of DFCTR is read out in the low-order five bits if a read
is attempted.
Bit 7⎯Interrupt Selection Bit (ISEL2): Selects the interrupt source. (IRRHSW2)
Bit 7
ISEL2
Description
0
Generates an interrupt request by the clear signal of the 16-bit timer counter
(Initial value)
1
Generates an interrupt request by the VD signal in PB mode
Bit 6⎯DFG Counter Clear Bit (CCLR): Forcibly clears the 5-bit DFG counter by software.
After 1 is written, the bit immediately reverts to 0. Writing 0 in this bit has no effect.
Bit 6
CCLR
Description
0
Normal operation
1
Clears the 5-bit DFG counter
(Initial value)
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Section 26 Servo Circuits
Bit 5⎯16-bit Timer Counter Clock Source Selection Bit (CKSL): Selects the clock source of
the 16-bit timer counter.
Bit 5
CKSL
Description
0
φs/4
1
φs/8
(Initial value)
Bits 4 to 0⎯FIFO1 Output Timing Setting Bits (DFCRA4 to DFCRA0): Determines the
starting point of the timing of FIFO1. The initial value is undetermined. Be sure to set a value after
a reset or stand-by. It is valid only if bit 7 (FRT bit) of HSM2 is 0.
DFG Reference Register 2 (DFCRB)
Bit :
7
⎯
6
⎯
5
⎯
4
DFCRB4
3
DFCRB3
2
DFCRB2
1
DFCRB1
0
DFCRB0
Initial value :
R/W :
1
⎯
1
⎯
1
⎯
*
W
*
W
*
W
*
W
*
W
Note : * Undefined
DFCRB is a register which determines the starting point of the timing of FIFO2.
DFCRB is an 8-bit write-only register. If a read is attempted, an undetermined value is read out.
Bits 7 to 5 are reserved; they cannot be modified and are always read as 1. It is not initialized by a
reset or in stand-by or module stop mode; accordingly be sure to write data before use.
Bits 4 to 0⎯FIFO2 Output Timing Setting Bits (DFCRB4 to DFCRB0): Sets the starting point
of the timing of FIFO2. The value after reset or after stand-by mode is entered is undetermined; be
sure to write data before use.
It is valid only if bit 7 (FRT bit) of HSM2 is 0.
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Section 26 Servo Circuits
FIFO Timer Capture Register (FTCTR)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
9
10
12
11
15
14
13
FTCTR15 FTCTR14 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9
8
FTCTR8
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
7
FTCTR7
6
FTCTR6
5
FTCTR5
4
FTCTR4
3
FTCTR3
2
FTCTR2
1
FTCTR1
0
FTCTR0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
FTCRT is a register to display the count of the 16-bit timer counter.
FTCRT is an 16-bit read-only register. It captures the counter value when the VD signal is
detected in PB mode. Only a word access is accepted. If a byte access is attempted, correct
operation is not guaranteed. It is initialized to H'0000 by a reset or in stand-by mode.
Note: The same address is assigned to the FTCTR and the FIFO timing pattern register 1
(FTPRA). Accordingly, if a write is attempted, the value is written in FTPRA.
DFG Reference Count Register (DFCTR)
Bit :
7
⎯
6
⎯
5
⎯
4
DFCTR4
3
DFCTR3
2
DFCTR2
1
DFCTR1
0
DFCTR0
Initial value :
R/W :
1
⎯
1
⎯
1
⎯
0
R
0
R
0
R
0
R
0
R
DFCTR is a register to count DFG pulses.
DFCTR is an 8-bit read-only register. Bits 7 to 5 are reserved; they cannot be modified and are
always read as 1. It is initialized to H'E0 by a reset or in stand-by mode.
Note: The same address is assigned to the DFCTR and the DFG reference register 1 (DFCRA).
Accordingly, if a write is attempted, the value is written in DFCRA.
Bits 4 to 0—DFG Pulse Count Bits (DFCTR4 to DFCTR0): These bits count DFG pulses.
Rev.2.00 Jan. 15, 2007 page 605 of 1174
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Section 26 Servo Circuits
26.4.6
Operation
5-Bit DFG Counter: The 5-bit DFG counter increments the count at the DFG edges selected by
the EDG bit of HSW Mode Register 2. The DFG counter is cleared by a DPG rising edge, or by
writing to the CCLR bit of the DFG reference register 1.
16-Bit Timer Counter: The 16-bit timer counter can operate in DFG reference mode or in freerunning mode.
• DFG Reference Mode
The timer counter operates by referencing the DFG signal. When the 5-bit DFG counter value
matches the value specified in the DFG reference register 1 or 2, the 16-bit timer counter is
initialized; this is the start point of the FIFO output timing.
In DFG reference mode, the start point specifying method can be selected by the FGR2OFF bit
of the HSW mode register 2: one way is to specify both FIFO1 and FIFO2 by only one register
(DFG reference register 1), and the other is to specify FIFO1 and FIFO2 by DFG reference
registers 1 and 2, respectively. When only the DFG reference register 1 is used, the continuous
values must be set to FIFO1 and FIFO2 as the timing patters.
• Free-Running Mode
The timer counter operates in association with the prescaler unit. When the 18-bit free-running
counter in the prescaler unit overflows, the 16-bit timer counter in the HSW timing generator is
initialized; this is the start point of the FIFO output timing.
Compare Circuit: The compare circuit compares the 16-bit timer counter value with the FIFO
timing pattern, and when they match, the compare circuit generates a trigger signal for outputting
the next-stage FIFO data.
FIFO: The FIFO generates a head switch signal for VCR and patterns for servo control. Data is
set to FIFO by using the FIFO timing pattern registers 1 and 2, and FIFO output pattern registers 1
and 2.
The FIFO operates in single mode and loop mode. In these two modes, the number of output
stages can be selected by the FIFO output group selection bit: 20-stage output using both FIFO1
and FIFO2 or 10-stage output using only FIFO1.
• Single Mode
The output pattern data is output when the timing pattern matches the counter value. The data,
once output, is lost, and the internal pointer is decrementd by 1. After the last data is output,
the FIFO stops operation until data is written again. When 20-stage output is used, writing in
FIFO1 and FIFO2 must be controlled by software.
Rev.2.00 Jan. 15, 2007 page 606 of 1174
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Section 26 Servo Circuits
• Loop Mode
The data output cycle is repeated from stage 0 to the final stage selected in the HSW loop
number setting register. As in single mode, the output pattern data is output when the timing
pattern matches the counter value. In loop mode, the FIFO data is retained.
Data in each FIFO group can be modified in loop mode. The FIFO group currently outputting
data can be checked by the OFG bit of the HSW mode register 2; after checking the outputting
FIFO group, clear the FIFO group which is not outputting data, then write new data to it.
Writing new data must be completed before the FIFO group starts operation. The FIFO cannot
be modified partially because the write pointer is outside the loop stages.
Figures 26.23 and 26.24 show examples of the timing waveform and operation of the HSW timing
generator.
Rev.2.00 Jan. 15, 2007 page 607 of 1174
REJ09B0329-0200
Example of setting: DFCRA = H'02, DFCRB = H'08, HSLP = H'21, DFG falling edge
Clear B
Clear A
A.FF
V.FF
DFG
DPG
0
1
2
3
tA1
tA2
4
5
6
7
8
9
tA3
tB1
10
11
0
1
2
tA1
Section 26 Servo Circuits
Figure 26.23 Example of Timing Waveform of HSW (for 12 DFG Pulses)
Rev.2.00 Jan. 15, 2007 page 608 of 1174
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Section 26 Servo Circuits
Internal bus
W
W
W
FPDRA
FTPRA
FIFO1
W
FPDRB
FTPRB
tA0
PA9
tB0
PB9
tA5
tA4
tA3
tA2
tA1
PA4
PA3
PA2
PA1
PA0
tB5
tB4
tB3
tB2
tB1
PB4
PB3
PB2
PB1
PB0
FIFO2
Output select buffer Output data buffer
Comparator
φs/4
Timer counter
Output pattern data
Figure 26.24 Example of Operation of the HSW Timing Generator
Rev.2.00 Jan. 15, 2007 page 609 of 1174
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Section 26 Servo Circuits
• Example of operation in single mode (20 stages of FIFO used)
1. Set to single mode (LOP = 0)
2. Write the output pattern data (PA0) to FPDRA.
3. Write the output timing (tA1) to FTPRA. tA1 is written in FIFO1 together with PA0. This
initializes the output pattern data to PA0.
4. Repeat the steps in the same way, until PA1, PA2, etc., are set.
5. Write the output pattern data (PB0) to FPDRB.
6. Write the output timing (tB1) to FTPRB. tB1 is written in FIFO2 together with PB0. This
initializes the output pattern data to PB0.
7.
Repeat these steps in the same way, until PB1, PB2, etc., are set.
By step 3, the pattern data of PA0 is output.
If tA1 matches with the timer counter, the pattern data of PA1 is output.
If tA2 matches with the timer counter, the pattern data of PA2 is output.
.
.
.
After this sequence is repeated and all the pattern data set in FIFO1 is output, the pattern data of
FIFO2 is output. After the pattern data is output, the pointer is decremented by 1. Care is required,
however, because matching of tA0 is not detected until data is written in FIFO2. Matching of tB0
also is not detected until data is written in FIFO1 again.
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Section 26 Servo Circuits
• Example of the operation in loop mode mode
1. Set the number of loop stages in HSLP register (e.g. HSLP = H'44)
2. Write the output pattern data (PA0) to FPDRA.
3. Write the output timing (tA1) to FTPRA. tA1 is written in FIFO1 together with PA0. This
initializes the output pattern data to PA0.
4. Repeat the steps in the same way, until PA1, PA2, etc., are set.
5. Write the output pattern data (PB0) to FPDRB.
6. Write the output timing (tB1) to FTPRB. tB1 is written in FIFO2 together with PB0. This
initializes the output pattern data to PB0.
7. Repeat the steps in the same way, until PB1, PB2, etc., are set.
By step 3, the pattern data PA0 is output.
If tA1 matches the timer counter, the pattern data PA1 is output.
If tA2 matches the timer counter, the pattern data PA2 is output.
.
.
.
If tA4 matches the timer counter, the pattern data PA4 is output.
If tA5 matches the timer counter, the pattern data PB0 is output.
If tB1 matches the timer counter, the pattern data PB1 is output.
.
.
.
If tB4 matches the timer counter, the pattern data PB4 is output.
If tB5 matches the timer counter, the pattern data PA0 is output.
.
.
.
Rev.2.00 Jan. 15, 2007 page 611 of 1174
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Section 26 Servo Circuits
26.4.7
Interrupts
The HSW timing generator generates interrupts under the following conditions.
1. IRRHSW1 occurs when pattern data is written (OVWA, OVWB = 1) while FIFO is full
(FULL).
2. IRRHSW1 occurs when matching is detected while the STRIG bit of FIFO is 1.
3. IRRHSW1 occurs when the values of the 16-bit timer counter and 16-bit timing pattern
register match.
4. IRRHSW2 occurs when the 16-bit timer counter is cleared.
5. IRRHSW2 occurs when a VD signal (capture signal of the timer capture register) is received in
PB mode.
Condition 2 or 3, as well as 4 or 5, are selected by ISEL1 and ISEL2.
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Section 26 Servo Circuits
26.4.8
Cautions
• When both the 5-bit DFG counter and 16-bit timer counter are operating, the latter is not
cleared if input of DPG and DFG signals is stopped. This leads to free-running of the 16-bit
timer counter, and periodical detection of matching by the 16-bit timer counter. In such a case,
the period of the output from the HSW timing generator is independent from DPG or DFG.
• Specify the mode setting bit (LOP) of the HSW mode register 2 (HSM2) immediately before
writing the FIFO data.
• Input the rising edge of DPG and DFG count edge at different timings. If they are input at the
same timing, counting up DFG and clearing the 5-bit DFG counter occur simultaneously. In
this case, the latter will take precedence. This leads to the DFG counter lag by 1. Figure 26.25
shows the input timing of DPG and DFG.
• If stop of the drum system is required when FIFO output is being used in the 20-stage output
mode, modify the SOFG bit of HSM2 register from 0 to 1, then again to 0 by software, and be
sure to initialize the FIFO output stage to the FIFO1 side. Also clear and rewrite the data of
FIFO1 and FIFO2.
I ±Tp · FG
| > φ (1 state)
DPG
DFG
Tp · FG
Note: When the 5-bit DFG counter increments count at the rising edge of DFG
Figure 26.25 Input Timing of DPG and DFG
Rev.2.00 Jan. 15, 2007 page 613 of 1174
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Section 26 Servo Circuits
26.5
High-Speed Switching Circuit for Four-Head Special Playback
26.5.1
Overview
This high-speed switching circuit generates a color rotary signal (C.Rotary) and head-amplifier
switching signal (H.Amp SW) for use in four-head special playback.
A pre-amplifier output comparison result signal is input from the COMP pin. The signal output to
the C.Rotary pin is a chroma signal processing control signal. The signal output at the H.Amp SW
pin is a pre-amplifier output select signal. To reduce the width of noise bars, the C.Rotary and
H.Amp SW signals are synchronized to the horizontal sync signal (OSCH). OSCH is made by
adding supplemented H, which has been separated from Csync signal in the sync signal detector
circuit. For more details of OSCH, see section 26.15, Sync Signal Detector.
If the VCR system does not require this circuit, C.Rotary, H.Amp SW, and COMP pins can be
used as the I/O port.
Rev.2.00 Jan. 15, 2007 page 614 of 1174
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Section 26 Servo Circuits
26.5.2
Block Diagram
Figure 26.26 shows the block diagram of this circuit.
Internal bus
W
W
CRH
HAH
W
CHCR
SIG3 to 0
CHCR
OSCH
(Synchronization)
Synchronization
control
C.Rotary
Decoding circuit
H.Amp SW
COMP
NarrowFF
RTP0
VideoFF
V/N
HSWPOL
CHCR
CHCR
W
W
Internal bus
Figure 26.26 High-Speed Switching Circuit for Four-Head Special Playback
26.5.3
Pin Configuration
Table 26.7 summarizes the pin configuration of the high-speed switching circuit for four-head
special playback. If this circuit is not used, the pins can be used as I/O port. See section 26.2,
Servo Port.
Table 26.7 Pin Configuration
Namea
Abbrev.
I/O
Function
Compare input pin
COMP
Input
Input of pre-amplifier output result signal
Color rotary signal output pin
C.Rotary
Output
Output of chroma processing control signal
Head amplifier switch pin
H.Amp SW
Output
Output of pre-amplifier output select signal
Rev.2.00 Jan. 15, 2007 page 615 of 1174
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Section 26 Servo Circuits
26.5.4
Register Description
Register Configuration
Table 26.8 shows the register configuration of the high-speed switching circuit for four-head
special playback.
Table 26.8 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address
Special playback control register
CHCR
W
Byte
H'00
H'D06E
Special Playback Control Register (CHCR)
Bit :
Initial value :
R/W :
7
V/N
6
HSWPOL
5
CRH
4
HAH
3
SIG3
2
SIG2
1
SIG1
0
SIG0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
CHCR is an 8-bit write-only register. It cannot be read. It is initialized to H'00 by a reset, or in
standby or module stop mode.
Bits 7⎯HSW Signal Select Bit (V/N): Selects the HSW signal to be used at special playback.
Bit 7
V/N
Description
0
Video FF signal output
1
Narrow FF signal output
(Initial value)
Bit 6⎯COMP Polarity Select Bit (HSWPOL): Selects the polarity of the COMP signal.
Bit 6
HSWPOL
Description
0
Positive
1
Negative
Rev.2.00 Jan. 15, 2007 page 616 of 1174
REJ09B0329-0200
(Initial value)
Section 26 Servo Circuits
Bit 5⎯C.Rotary Synchronization Control Bit (CRH): Synchronizes C.Rotary signal with the
OSCH signal.
Bit 5
CRH
Description
0
Synchronous
1
Asynchronous
(Initial value)
Bit 4⎯H.AmpSW Synchronization Control Bit (HAH): Synchronizes H.AmpSW signal with
the OSCH signal.
Bit 4
HAH
Description
0
Synchronous
1
Asynchronous
(Initial value)
Bits 3 to 0⎯Signal Control (SIG3 to SIG0): These bits, combined with the state of the COMP
input pin, control the outputs at the C.Rotary and H.AmpSW pins.
Bit 3
Bit 2
Bit 1
Bit 0
Output pins
SIG3
SIG2
SIG1
SIG0
C.Rotary
H.Amp SW
0
0
*
*
L
L
1
0
0
HSW
L
1
HSW
H
0
L
HSW
1
H
HSW
*
HSW EX-OR COMP COMP
1
1
0
1
0
1
HSW EX-NOR
COMP
COMP
0
HSW E-OR RTP0
RTP0
1
HSW EX-NOR RTP0 RTP0
(Initial value)
Legend: * Don’t care.
Rev.2.00 Jan. 15, 2007 page 617 of 1174
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Section 26 Servo Circuits
26.6
Drum Speed Error Detector
26.6.1
Overview
Drum speed error control holds the drum at a constant revolution speed, by measuring the period
of the DFG signal. A digital counter detects the speed error against a preset value. The speed error
data is processed and added to phase error data in a digital filter. This filter controls a pulse-width
modulated (PWM) output, which controls the revolution speed and phase of the drum.
The DFG input signal is reshaped into a square wave by a reshaping circuit, and sent to the speed
error detector as the DFG signal.
The speed error detector uses the system clock to measure the period of the DFG signal, and
detects the error against a preset data value. The preset data is the value that results from
measuring the DFG signal period with the clock signal when the drum motor is running at the
correct speed.
The error detector operates by latching a counter value when it detects an edge of the DFG signal.
The latched count provides 16 bits of speed error data for the digital filter to operate on. The
digital filter processes and adds the speed error data to phase error data from the drum phase
control system, then sends the result to the PWM as drum error data.
26.6.2
Block Diagram
Figure 26.27 shows a block diagram of the drum speed error detector.
Rev.2.00 Jan. 15, 2007 page 618 of 1174
REJ09B0329-0200
Error data
(16 bits)
To DFU
ADDFGN
NCDFG
φs
φs/2
φs/4
φs/8
DFCS1,0
W
DRF
FGCR
↑, ↓
Edge
detector
DFVCR
R/W
R
F/F
Q S
DFER
R/W
DFVCR
R/W
OVF
R/W
DFESS
DFRLOR
Lock range
detector
DFRUDR
Lock range data 2
(16 bits)
W
Internal bus
DFVCR
R/W
Internal bus
W
Lock range data 1 (16 bits)
DFEFON
Error data
limiter
control circuit
DFOVF
DFUCR
Error data (16 bits)
Latch
Counter (16 bits)
Preset
DFPR
Preset data
(16 bits)
W
Lock 2 up
Lock 1 up
S
R
Clear
Q
F/F
R/W
UDF
DF-R/UNR
IRRDRM2
IRRDRM1
DFVCR
R
To DROCKON
DFU
Lock counter
(2 bits)
DFVCR
DPCNT
S
F/F
Q R
DFRCS1,0
DFRVCR
(R)/W
Section 26 Servo Circuits
Figure 26.27 Block Diagram of the Drum Speed Error Detector
Rev.2.00 Jan. 15, 2007 page 619 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
26.6.3
Register Configuration
Table 26.9 shows the register configuration of the drum speed error detector.
Table 26.9 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address
Specified DFG speed
preset data register
DFPR
W
Word
H'0000
H'D030
DFG speed error data
register
DFER
R/W
Word
H'0000
H'D032
DFG lock upper data
register
DFRUDR
W
Word
H'7FFF
H'D034
DFG lock lower data
register
DFRLDR
W
Word
H'8000
H'D036
Drum speed error
detection control register
DFVCR
R/W
Byte
H'00
H'D038
Rev.2.00 Jan. 15, 2007 page 620 of 1174
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Section 26 Servo Circuits
26.6.4
Register Description
Specified DFG Speed Preset Data Register (DFPR)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
15
DFPR15
14
DFPR14
13
DFPR13
12
DFPR12
11
DFPR11
10
DFPR10
9
DFPR9
8
DFPR8
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
7
DFPR7
6
DFPR6
5
DFPR5
4
DFPR4
3
DFPR3
2
DFPR2
1
DFPR1
0
DFPR0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
The DFG speed preset data is set in DFPR. When data is written, the 16-bit preset data is sent to
the preset circuit. The preset data can be calculated from the following equation by using H'8000*
as the reference value.
Specified DFG speed preset data = H'8000 − (
φ s:
φs/n
− 2)
DFG frequency
Servo clock frequency (fosc/2) in Hz
DFG frequency: In Hz
Constant 2 is the presetting interval (see figure 26.28).
φ s/n
Clock source of the selected counter
DFPR is a 16-bit write-only register. Only a word access is valid. If a byte access is attempted,
correct operation is not guaranteed. DFPR cannot be read. If a read is attempted, an undetermined
value is read. DFPR is initialized to H'0000 by a reset, and in standby mode and module stop
mode.
Note: * The preset data value is calculated so that the counter will reach H'8000 when the error
is zero. When the counter value is latched as error data in the DFG speed error data
register (DFER), however, it is converted to a value referenced to H'0000.
Rev.2.00 Jan. 15, 2007 page 621 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
DFG Speed Error Data Register (DFER)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
15
DFER15
14
DFER14
13
DFER13
12
DFER12
11
DFER11
10
DFER10
9
DFER9
8
DFER8
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
7
DFER7
6
DFER6
5
DFER5
4
DFER4
3
DFER3
2
DFER2
1
DFER1
0
DFER0
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
Note: * Note that only detected error data can be read.
DFER is a 16-bit read/write register that stores 16-bit DFG speed error data. When the drum motor
speed is correct, the data latched in DFER is H'0000. Negative data will be latched if the speed is
faster than the specified speed, and positive data if the speed is slower than the specified speed.
The DFER value is sent to the digital filter either automatically or by software.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed.
DFER is initialized to H'0000 by a reset, and in standby mode and module stop mode.
Refer to the note Specified DFG Speed Preset Data Register (DFPR) in section 26.6.4, Register
Description.
DFG Lock Upper Data Register (DFRUDR)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
15
14
13
12
11
10
9
8
DFRUDR15 DFRUDR14 DFRUDR13 DFRUDR12 DFRUDR11 DFRUDR10 DFRUDR9 DFRUDR8
0
W
1
W
1
W
1
W
1
W
1
W
1
W
1
W
7
6
5
4
3
2
1
0
DFRUDR7 DFRUDR6 DFRUDR5 DFRUDR4 DFRUDR3 DFRUDR2 DFRUDR1 DFRUDR0
1
W
1
W
1
W
1
W
1
W
1
W
1
W
1
W
DFRUDR is a 16-bit write-only register used to set the lock range on the UPPER side when drum
speed lock is detected, and to set the limit value on the UPPER side when limiter function is in
use. Set a signed data to DFRUDR (bit 15 is a sign-setting bit).
When lock is being detected, if the drum speed is detected within the lock range, the lock counter
which has been set by DFRCS 1 and 0 bits of DFVCR register decrements the count. If the set
value of DFRCS 1 and 0 matches the number of times of occurrence of locking, the computation
of the digital filter in the drum phase system can be controlled automatically. Also, if the DFG
speed error data exceeds the DFRUDR value within the limiter function is in use, the DFRUDR
value can be used as the data for computation by the digital filter.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
Rev.2.00 Jan. 15, 2007 page 622 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'7FFF
by a reset, or in stand-by or module-stop mode.
DFG Lock LOWER Data Register (DFRLDR)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
15
14
13
12
11
10
9
8
DFRLDR15 DFRLDR14 DFRLDR13 DFRLDR12 DFRLDR11 DFRLDR10 DFRLDR9 DFRLDR8
1
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
7
6
5
4
3
2
1
0
DFRLDR7 DFRLDR6 DFRLDR5 DFRLDR4 DFRLDR3 DFRLDR2 DFRLDR1 DFRLDR0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
DFRLDR is a 16-bit write-only register used to set the lock range on the LOWER side when drum
speed lock is detected, and to set the limit value on LOWER side when limiter function is in use.
Set a signed data to DFRLDR (bit 15 is a sign-setting bit).
When lock is being detected, if the drum speed is detected within the lock range, the lock counter
which has been set by DFRCS 1 and 0 bits of DFVCR register decrements the count. If the set
value of DFRCS 1 and 0 matches the number of times of occurrence of locking, the computation
of the digital filter in the drum phase system can be controlled automatically. Also, if the DFG
speed error data is under the DFRLDR value when the limiter function is in use, the DFRLDR
value can be used as the data for computation by the digital filter.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'8000 by
a reset, or in stand-by or module-stop mode.
Drum Speed Error Detection Control Register (DFVCR)
Bit :
Initial value :
R/W :
7
DFCS1
6
DFCS0
5
DFOVF
0
R/W
0
R/W
0
R/(W)*1
4
3
DFRFON DF-R/UNR
0
R/W
0
R
2
DPCNT
1
DFRCS1
0
DFRCS0
0
R/W
0
(R)*2/W
0
(R)*2/W
Notes: 1. Only 0 can be written.
2. If read-accessed, the counter value is read out.
DFVCR is an 8-bit read/write register that controls the operation of drum speed error detection.
Bit 3 accepts only read, and bit 5 accepts only read and 0 write. It is initialized to H'00 by a reset,
or in stand-by or module-stop mode.
Rev.2.00 Jan. 15, 2007 page 623 of 1174
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Section 26 Servo Circuits
Bits 7 and 6⎯Clock Source Selection Bits (DFCS1, DFCS0): DFCS1 and DFCS0 select the
clock to be supplied to the counter. (φs = fosc/2)
Bit 7
Bit 6
DFCS1
DFCS0
Description
0
0
φs
1
φs/2
0
φs/4
1
φs/8
1
(Initial value)
Bit 5⎯Counter Overflow Flag (DFOVF): DFOVF flag indicates the overflow of the 16-bit
timer counter. It is cleared by writing 0. Write 0 after reading 1. Setting has the highest priority in
this flag. If a flag set and 0 write occurs simultaneously, the latter is invalid.
Bit 5
DFOVF
Description
0
Normal state.
1
Indicates that overflow has occurred in the counter.
(Initial value)
Bit 4⎯Error Data Limit Function Selection Bit (DFRFON): Enables the error data limit
function. (Limit values are the values set in the lock range data registers (DFRUDR and
DFRLDR)).
Bit 4
DFRFON
Description
0
Disables limit function.
1
Enables limit function.
(Initial value)
Bit 3⎯Drum Lock Flag (DF-R/UNR): Sets a flag if an underflow occurred in the drum lock
counter.
Bit 3
DF-R/UNR
Description
0
Indicates that the drum speed system is not locked.
1
Indicates that the drum speed system is locked.
Rev.2.00 Jan. 15, 2007 page 624 of 1174
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(Initial value)
Section 26 Servo Circuits
Bit 2⎯Drum Phase System Filter Computation Automatic Start Bit (DPCNT): Enables the
filter computation of the phase system if an underflow occurred in the drum lock counter.
Bit 2
DPCNT
Description
0
Disables the filter computation by detection of the drum lock.
1
Enables the filter computation of the phase system when drum lock is detected.
(Initial value)
Bits 1 and 0⎯Drum Lock Counter Setting Bits (DFRCS1, DFRCS0): Set the number of times
to detect drum locks (which means the number of times DFG is detected in the range set by the
lock range data register). The drum lock flag is set when the specified number of drum locks is
detected. If the NCDFG signal is detected outside the lock range after data is written in DFRCS1
and DFRCS0, the data will be stored in the lock counter.
Note: If DFRCS1 or DFRCS0 is read-accessed, the counter value is read out. If bit 3 (drum lock
flag) is 1 and the drum lock counter's value is 3, it indicates that the drum speed system is
locked. The drum lock counter stops until lock is released after underflow.
Bit 1
Bit 0
DFRCS1
DFRCS0
0
0
Underflow occurs after lock was detected once.
1
Underflow occurs after lock was detected twice.
0
Underflow occurs after lock was detected three times.
1
Underflow occurs after lock was detected four times.
1
Description
(Initial value)
Rev.2.00 Jan. 15, 2007 page 625 of 1174
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Section 26 Servo Circuits
26.6.5
Operation
The drum speed error detector detects the speed error based on the reference value set in the DFG
specified speed preset register (DFPR). The reference value set in DFPR is preset in the counter by
NCDFG signal, and the counter decrements the count by the selected clock. The timing of the
counter presetting and the error data latching can be selected between the rising or falling edge of
NCDFG signal. See section 26.14.4, DFG Noise Removal Circuit. The error data detected is sent
to the digital filter circuit. The error data is signed binaries. The data takes a positive number (+) if
the speed is slower than the specified speed, a negative number (-) if the speed is faster, or 0 if it
had no error (revolving at the specified speed). Figure 26.28 shows an example of operation to
detect the drum speed.
• Setting the error data limit
A limit can be set to the error data sent to the digital filter circuit using the DFG lock data
register (DFRUDR, DFRLDR). Set the upper limit of the error data in DFRUDR and the lower
limit in DFRLDR, and write 1 in DFRFON bit. If the error data is outside the limit range, the
DFRLDR value is sent to the digital filter circuit if a negative number is latched, or the
DFRUDR value if a positive number is latched, as a limit value. Be sure to turn off the limit
setting (DFRFON = 0) when you set the limit value. If the limit was set with the limit setting
on (DFRFON = 1), result of computation is not assured.
• Lock detection
If an error data is detected within the lock range set in the lock data register, the drum lock flag
(DF-R/UNR) is set by the number of the times of locking set by DFRCS1 and DFRCS0 bits,
and an interrupt is requested (IRRDRM2) at the same time. The number of the occurrence of
locking (once to 4 times) before the flag is set can be specified. Use DFRCS1 and DFRCS0
bits for this purpose. The on/off status of the phase system digital filter computation can be
controlled automatically by the status of lock detection when bit 5 (DPHA bit) of the drum
system digital filter control register (DFIC) is 0 (phased system digital filter computation off)
and DPCNT bit is 1.
• Drum system speed error detection counter
The drum system speed error detection counter stops the counter and sets the overflow flag
(DFOVF) when an overflow occurs. At the same time, it generates an interrupt request
(IRRDRM1). To clear DFOVF, write 0 after reading 1. If setting the flag and writing 0 take
place simultaneously, the latter is invalid.
Rev.2.00 Jan. 15, 2007 page 626 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
• Interrupt request
IRRDRM1 is generated by the NCDFG signal latch and the overflow of the error detection
counter. IRRDRM2 is generated by detection of lock (after the detection of the specified
number of times of locking).
NCDFG signal
Error data latch
signal (DFG ↑)
Preset data
load signal
Preset period
(2 counts)
Specified speed value
–value+value
Counter
Preset value
Latch data 0
(no error)
Figure 26.28 Example of the Drum Speed Error Detection
(When the Rising Edge of DFG Is Selected)
Rev.2.00 Jan. 15, 2007 page 627 of 1174
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Section 26 Servo Circuits
26.6.6
fH Correction in Trick Play Mode
In trick play mode, the tape speed relative to the video head changes. This change alters the
horizontal sync signal (fH), causing skew. To correct the skew, the drum motor speed must be
shifted to a different speed in each trick play mode, so as to obtain the normal horizontal sync
frequency. To shift the drum motor speed, software should modify the value written in the
specified DFG speed preset data register in the speed error detector.
This fH correction can be expressed in terms of the basic frequency fF of the drum as follows.
fF =
N0
×f
N0 + αH (1 − n) F0
Legend:
n:
Speed multiplier (FWD = positive, REV = negative)
αH:
H alignment (1.5H in standard mode, 0.75H in 2x mode, and 0.5H in 3x mode for VHS
and β systems; 1H for an 8-mm VCR)
N0:
Standard H numbers within field
fF0:
Field frequency
NTSC: N0 = 262.5, fF0 = 59.94
PAL:
N0 = 312.5, fF0 = 50.00
Rev.2.00 Jan. 15, 2007 page 628 of 1174
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Section 26 Servo Circuits
26.7
Drum Phase Error Detector
26.7.1
Overview
The drum phase control system must start after the drum motor has reached the specified
revolution speed by the speed control system. Drum phase control works as follows in record and
playback mode.
• Record Mode: Phase is controlled so that the vertical blanking intervals of the video signal to
be recorded will line up along the bottom edge of the tape.
• Playback Mode: Phase is controlled so as to trace the recorded tracks accurately.
A counter detects the phase error against a preset value. The phase error data is processed and
added to speed error data in a digital filter. This filter controls a pulse-width modulated (PWM)
output, which controls the revolution phase and speed of the drum.
The DPG signal from the drum motor is reshaped into a square wave by a reshaping circuit,
and sent to the phase error detector.
The phase error detector compares the phase of the DPG pulse (tach pulse), which contains
video head phase information, with a reference signal. In the actual circuit, the comparison is
carried out by comparing the head-switching (HSW) signal, which is delayed by a counter that
is reset by DPG, with a reference signal value. The reference signal is the REF30 signal, which
differs between record and playback as follows:
• Record: Vsync signal extracted from the video signal to be recorded (frame rate signal,
actually 1/2 Vsync).
• Playback: 30 Hz or 25 Hz signal divided from the system clock.
Rev.2.00 Jan. 15, 2007 page 629 of 1174
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Rev.2.00 Jan. 15, 2007 page 630 of 1174
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DPGCR
NHSW
(Narrow FF)
HSW
(Video FF)
φs
φs/2
φs/4
φs/8
REF30P
Figure 26.29 Block Diagram of Drum Phase Error Detector
R/W
N/V
DPCS1,0
R/W
DPGCR
HSWES
↑, ↓
Edge
detector
S
F/F
Q R
R/W
Internal bus
MSB
DPER1
Error data
(4 bits)
Sequence
controller
R/W
LSB
DPGCR
R/(W)
R/W
DFEPS
DFUCR
DPOVF
OVF
LSB
DPER2
Error data
(16 bits)
Latch
Counter (20 bits)
Preset
(16 bits)
MSB
(4 bits)
DPPR2
W
Preset data
W
Preset data
DPPR1
Internal bus
φs = fosc/2
Error data (20 bits)
To DFU
IRRDRM3
26.7.2
DPGCR
R/W
Section 26 Servo Circuits
Block Diagram
Figure 26.29 shows a block diagram of the drum phase error detector.
Section 26 Servo Circuits
26.7.3
Register Configuration
Table 26.10 shows the register configuration of the drum phase error detector.
Table 26.10 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address
Specified drum phase preset data
register 1
DPPR1
W
Byte
H'F0
H'D03C
Specified drum phase preset data
register 2
DPPR2
W
Word
H'0000
H'D03A
Drum phase error data register 1
DPER1
R/W
Byte
H'F0
H'D03D
Drum phase error data register 2
DPER2
R/W
Word
H'0000
H'D03E
Drum phase error detection control
register
DPGCR
R/W
Byte
H'07
H'D039
Rev.2.00 Jan. 15, 2007 page 631 of 1174
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Section 26 Servo Circuits
26.7.4
Register Description
Drum Phase Preset Data Registers (DPPR1, DPPR2)
DPPR1
Bit :
7
—
6
—
5
—
4
—
3
DPPR19
2
DPPR18
1
DPPR17
0
DPPR16
Initial value :
R/W :
1
—
1
—
1
—
1
—
0
W
0
W
0
W
0
W
15
DPPR15
14
DPPR14
13
DPPR13
12
DPPR12
11
DPPR11
10
DPPR10
9
DPPR9
8
DPPR8
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
7
DPPR7
6
DPPR6
5
DPPR5
4
DPPR4
3
DPPR3
2
DPPR2
1
DPPR1
0
DPPR0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
DPPR2
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
The 20-bit preset data that defines the specified drum phase is set in DPPR1 and DPPR2. The 20
bits are weighted as follows: bit 3 of DPPR1 is the MSB, and bit 0 of DPPR2 is the LSB. When
data is written to DPPR2, the 20-bit preset data, including DPPR1, is loaded into the preset circuit.
Write to DPPR1 first, and DPPR2 next. The preset data can be calculated from the following
equation by using H'80000* as the reference value.
Target phase difference = (reference signal frequency/2) − 6.5H
Drum phase preset data = H'80000 - (φs/n × target phase difference)
φs:
φs/n:
Servo clock frequency in Hz (fosc/2)
Clock source of selected counter
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is valid. If a read is attempted, an undetermined value is read out. DPPR1 and DPPR2 are
initialized to H'F0 and H'0000 by a reset, and in standby mode.
Note: * The preset data value is calculated so that the counter will reach H'80000 when the
error value is zero. When the counter value is latched as error data in the drum phase
error data registers (DPER1 and DPER2), however, it is converted to a value
referenced to H'00000.
Rev.2.00 Jan. 15, 2007 page 632 of 1174
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Section 26 Servo Circuits
Drum Phase Error Data Registers (DPER1, DPER2)
DPER1
Bit :
7
—
6
—
5
—
4
—
3
DPER19
2
DPER18
1
DPER17
0
DPER16
Initial value :
R/W :
1
—
1
—
1
—
1
—
0
R*/W
0
R*/W
0
R*/W
0
R*/W
15
DPER15
14
DPER14
13
DPER13
12
DPER12
11
DPER11
10
DPER10
9
DPER9
8
DPER8
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
7
DPER7
6
DPER6
5
DPER5
4
DPER4
3
DPER3
2
DPER2
1
DPER1
0
DPER0
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
DPER2
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Note: * Note that only detected error data can be read.
DPER1 and DPER2 constitute a 20-bit drum phase error data register. The 20 bits are weighted as
follows: bit 3 of DPER1 is the MSB, and bit 0 of DPER2 is the LSB. When the rotational phase is
correct, the data H'00000 is latched. Negative data will be latched if the drum leads the correct
phase, and positive data if it lags. Values in DPER1 and DPER 2 are transferred to the digital filter
circuit.
DPER1 and DPER are 20-bit read/write registers. When writing data to DPER 1 and DPER2,
write to DPER1 first, and then write to DPER2. Only a word access is valid. If a byte access is
attempted, correct operation is not guaranteed. DPER1 and DPER2 are initialized to H'F0 and
H'0000 by a reset, and in standby mode.
See the note on the drum phase preset data registers (DPPR1 and DPPR2).
Rev.2.00 Jan. 15, 2007 page 633 of 1174
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Section 26 Servo Circuits
Drum Phase Error Detection Control Register (DPGCR)
Bit :
7
DPCS1
6
DPCS0
5
DPOVF
4
N/V
3
HSWES
2
—
1
—
0
—
0
R/W
0
R/W
0
R/(W)*
0
R/W
0
R/W
1
—
1
—
1
—
Initial value :
R/W :
Note: * Only 0 can be written.
DPGCR is an 8-bit read/write register that controls the operation of drum phase error detection.
Bits 2-0 are reserved, bit 5 accepts only read and 0 write.
It is initialized to H'07 by a reset or in stand-by mode.
Bits 7 and 6⎯Clock Source Selection Bit (DPCS1, DPCS0): These bits select the clock
supplied to the counter. (φs = fosc/2)
Bit 7
Bit 6
DPCS1
DPCS0
Description
0
0
φs
1
φs/2
0
φs/4
1
φs/8
1
(Initial value)
Bit 5⎯Counter Overflow Flag (DPOVF): DPOVF flag indicates the overflow of the 20-bit
counter. It is cleared by writing 0. Write 0 after reading 1. Setting has the highest priority in this
flag. If a flag set and 0 write occurs simultaneously, the latter is invalid.
Bit 5
DPOVF
Description
0
Normal state
1
Indicates that a overflow has occurred in the counter
(Initial value)
Bit 4⎯Error Data Latch Signal Selection Bit (N/V): Selects the latch signal of error data.
Bit 4
N/V
Description
0
HSW (VideoFF) signal
1
NHSW (NarrowFF) signal
Rev.2.00 Jan. 15, 2007 page 634 of 1174
REJ09B0329-0200
(Initial value)
Section 26 Servo Circuits
Bit 3⎯Edge Selection Bit (HSWES): Selects the edge of the error data latch signal (HSW or
NHSW).
Bit 3
HSWES
Description
0
Latches at the rising edge
1
Latches at the falling edge
(Initial value)
Bits 2 to 0⎯Reserved: Cannot be modified and are always read as 1.
26.7.5
Operation
The drum phase error detector detects the phase error based on the reference value set in the drum
specified phase preset data registers 1 and 2 (DPPR1 and DPPR2). The reference values set in
DPPR1 and DPPR2 are preset in the counter by REF30P signal, and counted up by the clock
selected. The latch of the error data can be selected between the rising or falling edge of HSW
(NHSW). The error data detected in the error data automatic transmission mode (DFEPS bit of
DFUCR = 0) is sent to the digital filter circuits automatically. In soft transmission mode (DFEPS
bit of DFUCR = 1), the data written in DPER1 and DPER2 is sent to the digital filter circuit. The
error data is signed binary. It takes a positive number (+) if the phase is behind the specified
phase, a negative number (-) if in advance of the specified phase, or 0 if it had no phase error
(revolving at the specified phase). Figures 26.30 and 26.31 show examples of operation to detect a
drum phase error.
Drum Phase Error Detection Counter: The drum phase error detection counter stops counting
when an overflow or latch occurs. At the same time, it generates an interrupt request (IRRDRM3),
and sets the overflow flag (DPOVF) if an overflow occurred. To clear DPOVF, write 0 after
reading 1. If setting the flag and writing 0 take place simultaneously, the latter is invalid.
Interrupt Request: IRRDRM3 is generated by the HSW (NHSW) signal latch and the overflow
of the error detection counter.
Rev.2.00 Jan. 15, 2007 page 635 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
REF30P
HSW (NHSW)*
Preset
Counter
Preset
Latch
Preset value
Latch
Preset value
Note: * Edge selectable
Figure 26.30 Drum Phase Control in Playback Mode (HSW Rising Edge Selected)
VD
Reset
Reset
Preset
Preset
REF30P
HSW (NHSW)*
Counter
Latch
Preset value
Note:
*
Latch
Preset value
Edge selectable
Figure 26.31 Drum Phase Control in Record Mode (HSW Rising Edge Selected)
Rev.2.00 Jan. 15, 2007 page 636 of 1174
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Section 26 Servo Circuits
26.7.6
Phase Comparison
The phase comparison circuit measures the difference of time between the reference signal and the
comparing signal with a digital counter. REF30 signal is used for the reference signal, and HSW
signal (VideoFF) or NHSW signal (NarrowFF) from the HSW timing generator is used for the
comparing signal. In record mode, however, the phase of REF30 signal is the same as that of the
vertical sync signal (Vsync) because the reference signal generator (REF30 generator) is reset by
the vertical sync signal (Vsync) in the video signals.
The error detection counter latches data at the rising or falling edge of HSW signal. The digital
filter circuit performs computation using this data as 20-bit phase error data. After processing and
adding the phase error data and the speed error data from the drum speed control system, the
digital filter circuit sends the data as the error data of the drum system to the PWM modulation
circuit.
26.8
Capstan Speed Error Detector
26.8.1
Overview
Capstan speed control holds the capstan motor at a constant revolution speed, by measuring the
period of the CFG signal. A digital counter detects the speed error against a preset value. The
speed error data is added to phase error data in a digital filter. This filter controls a pulse-width
modulated (PWM) output, which controls the revolution speed and phase of the capstan motor.
The CFG input signal is downloaded by the comparator circuit, then reshaped into a square wave
by a reshaping circuit, divided by the CFG divider, and sent to the speed error detector as the
DVCFG signal.
The speed error detector uses the system clock to measure the period of the DVCFG signal, and
detects the error against a preset data value. The preset data is the value that results from
measuring the DVCFG signal period with the clock signal when the capstan motor is running at
the correct speed.
The error detector operates by latching a counter value when it detects an edge of the DVCFG
signal. The latched count provides 16 bits of speed error data for the digital filter to operate on.
The digital filter adds the speed error data to phase error data from the capstan phase control
system, then sends the result to the PWM as capstan error data.
Rev.2.00 Jan. 15, 2007 page 637 of 1174
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Rev.2.00 Jan. 15, 2007 page 638 of 1174
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Error data
(16 bits)
To DFU
DVCFG
φs
φs/2
φs/4
φs/8
CFCS1,0
R
F/F
Q S
CFVCR
R/W
OVF
R/W
CFESS
Internal bus
R/W
W
Lock range data (16 bits)
CFRLDR
Lock range
detector
Lock range data (16 bits)
CFRUDR
W
Internal bus
CFVCR
CFRFON
Error data
limiter
control
circuit
CFOVF
CFUCR
CFER
Error data
(16 bits)
R/W
Latch
Counter (16 bits)
Preset
Preset data (16 bits)
CFPR
W
Lock 2 up
Lock 1 up
S
R
Clear
Q
F/F
Lock counter
(2 bits)
CFVCR
R/W
CPCNT
S
F/F
Q R
CFRCS1,0
CFRVCR
CROCKON
To DFU
IRRCAP2
IRRCAP1
CFVCR
R
CF-R/UNR
UDF
(R)/W
26.8.2
CFVCR
R/W
Section 26 Servo Circuits
Block Diagram
Figure 26.32 shows a block diagram of the capstan speed error detector.
Figure 26.32 Block Diagram of Capstan Speed Error Detector
Section 26 Servo Circuits
26.8.3
Register Configuration
Table 26.11 shows the register configuration of the capstan speed error detector.
Table 26.11 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value Address
Specified CFG speed preset data
register
CFPR
W
Word
H'0000
H'D050
CFG speed error data register
CFER
R/W
Word
H'0000
H'D052
CFG lock upper data register
CFRUDR
W
Word
H'7FFF
H'D054
CFG lock lower data register
CFRLDR
W
Word
H'8000
H'D056
R/W
Byte
H'00
H'D058
Capstan speed error detection control CFVCR
register
Rev.2.00 Jan. 15, 2007 page 639 of 1174
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Section 26 Servo Circuits
26.8.4
Register Description
Specified CFG Speed Preset Data Register (CFPR)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
15
CFPR15
14
CFPR14
13
CFPR13
12
CFPR12
11
CFPR11
10
CFPR10
9
CFPR9
8
CFPR8
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
7
CFPR7
6
CFPR6
5
CFPR5
4
CFPR4
3
CFPR3
2
CFPR2
1
CFPR1
0
CFPR0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
The 16-bit preset data that defines the specified CFG speed is set in CFPR. When data is written,
the 16-bit preset data is sent to the preset circuit. The preset data can be calculated from the
following equation by using H'8000* as the reference value.
CFG speed preset data = H'8000 − (
φs:
φs/n
DVCFG frequency
− 2)
Servo clock frequency in Hz (fOSC/2)
DVCFG frequency: In Hz
The constant 2 is the preset interval (see figure 26.33).
φs/n:
Clock source of the selected counter
CFPR is a 16-bit write-only register. Only a word acces is valid. If a byte access is attempted,
correct operation is not guaranteed. CFPR is initialized to H'0000 by a reset.
Note: * The preset data value is calculated so that the counter will reach H'8000 when the error
is zero. When the counter value is latched as error data in the CFG speed error data
register (CFER), however, it is converted to a value referenced to H'0000.
Rev.2.00 Jan. 15, 2007 page 640 of 1174
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Section 26 Servo Circuits
CFG Speed Error Data Register (CFER)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
15
CFER15
14
CFER14
13
CFER13
12
CFER12
11
CFER11
10
CFER10
9
CFER9
8
CFER8
0
0
0
0
0
0
0
0
R*/W
R*/W
R*/W
R*/W
R*/W
R*/W
R*/W
R*/W
7
CFER7
6
CFER6
5
CFER5
4
CFER4
3
CFER3
2
CFER2
1
CFER1
0
CFER0
0
0
0
0
0
0
0
0
R*/W
R*/W
R*/W
R*/W
R*/W
R*/W
R*/W
R*/W
Note: * Note that only detected error data can be read.
CFER is a 16-bit read/write register that stores 16-bit CFG speed error data. When the speed of the
capstan motor is correct, the data latched in CFER is H'0000. Negative data will be latched if the
speed is faster than the specified speed, and positive data if the speed is slower than the specified
speed. The CFER value is sent to the digital filter either automatically or by software.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed.
CFER is initialized to H'0000 by a reset, and in module stop mode and standby mode.
See the note on the specified CFG speed preset data register (CFPR) in section 26.8.4, Register
Description.
CFG Lock UPPER Data Register (CFRUDR)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
15
14
13
12
11
10
9
8
CFRUDR15 CFRUDR14 CFRUDR13 CFRUDR12 CFRUDR11 CFRUDR10 CFRUDR9 CFRUDR8
0
W
1
W
1
W
1
W
1
W
1
W
1
W
1
W
1
0
2
4
3
7
6
5
CFRUDR7 CFRUDR6 CFRUDR5 CFRUDR4 CFRUDR3 CFRUDR2 CFRUDR1 CFRUDR0
1
W
1
W
1
W
1
W
1
W
1
W
1
W
1
W
CFRUDR is a 16-bit write-only register used to set the lock range on the UPPER side when
capstan speed lock is detected, and to set the limit value on the UPPER side when limiter function
is in use.
When lock is being detected, if the capstan speed is detected within the lock range, the lock
counter which has been set by CFRCS1 and CFRCS0 bits of CFVCR register decrements the
count. If the set value of CFRCS1 and CFRCS0 matches the number of times of occurrence of
locking, the computation of the digital filter in the capstan phase system can be controlled
automatically. Also, if the CFG speed error data exceeds the CFRUDR value when the limiter
function is in use, the DFRUDR value can be used as the data for computation by the digital filter.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. A
Rev.2.00 Jan. 15, 2007 page 641 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
read is invalid. If a read is attempted, an undetermined value is read out. It is initialized to H'7FFF
by a reset, or in stand-by or module-stop mode.
CFG Lock LOWER Data Register (CFRLDR)
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
9
8
10
12
11
15
14
13
CFRLDR15 CFRLDR14 CFRLDR13 CFRLDR12 CFRLDR11 CFRLDR10 CFRLDR9 CFRLDR8
1
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
1
0
2
4
3
7
6
5
CFRLDR7 CFRLDR6 CFRLDR5 CFRLDR4 CFRLDR3 CFRLDR2 CFRLDR1 CFRLDR0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
CFRLDR is a 16-bit write-only register used to set the lock range on the LOWER side when
capstan speed lock is detected, and to set the limit value on LOWER side when limiter function is
in use.
When lock is being detected, if the drum speed is detected within the lock range, the lock counter
that has been set by CFRCS 1 and 0 bits of CFVCR register decrements the count. If the set value
of CFRCS 1 and 0 matches the number of times of occurrence of locking, the computation of the
digital filter in the drum phase system can be controlled automatically. Also, if the CFG speed
error data is under the CFRLDR value when the limiter function is in use, the CFRLDR value can
be used as the data for computation by the digital filter.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'8000 by
a reset, or in stand-by or module-stop mode.
Capstan Speed Error Detection Control Register (CFVCR)
Bit :
Initial value :
R/W :
7
CFCS1
6
CFCS0
5
CFOVF
0
R/W
0
R/W
0
R/(W)*1
4
3
2
CFRFON CF-R/UNR CPCNT
0
R/W
0
R
0
R/W
1
CFRCS1
0
CFRCS0
0
(R)*2/W
0
(R)*2/W
Notes: 1. Only 0 can be written.
2. If read-accessed, the counter value is read out.
CFVCR is an 8-bit read/write register that controls the operation of capstan speed error detection.
Bit 3 accepts only read, and bit 5 accepts only read and 0 write. It is initialized to H'00 by a reset,
or in stand-by or module-stop mode.
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Section 26 Servo Circuits
Bits 7 and 6⎯Clock Source Selection Bits (CFCS1, CFCS0): CFCS1 and CFCS0 select the
clock to be supplied to the counter. (φs = fosc/2)
Bit 7
Bit 6
CFCS1
CFCS0
Description
0
0
φs
1
φs/2
0
φs/4
1
φs/8
1
(Initial value)
Bit 5⎯Counter Overflow Flag (CFOVF): CFOVF flag indicates overflow of the 16-bit counter.
It is cleared by writing 0. Write 0 after reading 1. Setting has the highest priority in this flag. If a
flag set and 0 write occurs simultaneously, the latter is invalid.
Bit 5
CFOVF
Description
0
Normal state.
1
Indicates that a overflow has occurred in the counter.
(Initial value)
Bit 4⎯Error Data Limit Function Selection Bit (CFRFON): Enables the error data limit
function. (Limit values are the values set in the lock range data register (CFRUDR, CFRLDR)).
Bit 4
CFRFON
Description
0
Disables limit function.
1
Enables limit function.
(Initial value)
Bit 3⎯Capstan Lock Flag (CF-R/UNR): Sets a flag if an underflow occurred in the capstan lock
counter.
Bit 3
CF-R/UNR
Description
0
Indicates that the capstan speed system is not locked.
1
Indicates that the capstan speed system is locked.
(Initial value)
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Section 26 Servo Circuits
Bit 2⎯Capstan Phase System Filter Computation Automatic Start Bit (CPCNT): Enables the
filter computation of the phase system if an underflow occurred in the capstan lock counter.
Bit 2
CPCNT
Description
0
Disables the filter computation by detection of the capstan lock.
(Initial value)
1
Enables the filter computation of the phase system when capstan lock is detected.
Bits 1 and 0⎯Capstan Lock Counter Setting Bits (CFRCS1, CFRCS0): Sets the number of
times to detect capstan locks (DVCFG has been detected in the rage set by the lock range data
register). The capstan lock flag is set when the specified number of capstan lock is detected. If the
DVCFG signal is detected outside the lock range after data is written in CFRCS1 and CFRCS0,
the data will be stored in the lock counter.
Note: If CFRCS1 or CFRCS0 is read-accessed, the counter value is read out. If bit 3 (capstan
lock flag) is 1 and the capstan lock counter's value is 3, it indicates that the capstan speed
system is locked. The capstan lock counter stops until lock is released after underflow.
Bit 1
Bit 0
CFRCS1
CFRCS0
Description
0
0
Underflow occurs after lock was detected once
(Initial value)
1
1
Underflow occurs after lock was detected twice
0
Underflow occurs after lock was detected three times
1
Underflow occurs after lock was detected four times
Rev.2.00 Jan. 15, 2007 page 644 of 1174
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Section 26 Servo Circuits
26.8.5
Operation
The capstan speed error detector detects the speed error based on the reference value set in the
CFG specified speed preset register (CFPR). The reference value set in CFPR is preset in the
counter by the DVCFG signal, and the counter decrements the count by the selected clock. The
timing of the counter presetting and the error data latching can be selected between the rising or
falling edge of DVCFG signal. See DVCFG Control Register (CDVC) in section 26.14.3, CFG
Frequency Divider. The error data detected is sent to digital filter circuit. The error data is signed
binaries. The data takes a positive number (+) if the speed is slower than the specified speed, a
negative number (-) if the speed is faster, or 0 if it had no error (revolving at the specified speed).
Figure 26.33 shows an example of operation to detect the capstan speed.
Setting the Error Data Limit: A limit can be set to the error data sent to the digital filter circuit
using the CFG lock data register (CFRUDR, CFRLDR). Set the upper limit of the error data in
CFRUDR and the lower limit in CFRLDR, and write 1 in CFRFON bit. If the error data is outside
the limit range, the CFRLDR value is sent to the digital filter circuit if a negative number is
latched, or the CFRUDR value if a positive number is latched, as a limit value. Be sure to turn off
the limit setting (CFRFON = 0) when you set the limit value. If the limit was set with the limit
setting on (CFRFON = 1), result of computation is not assured.
Lock Detection: If an error data is detected within the lock range set in the lock data register, the
capstan lock flag (CF-R/UNR) is set by the number of the times of locking set by CFRCS1 and
CFRCS0 bits, and an interrupt is requested (IRRCAP2) at the same time. The number of the
occurrence of locking (once to 4 times) before the flag is set can be specified. Use CFRCS1 and
CFRCS0 bits for this purpose. The on/off state of the phase system digital filter computation can
be controlled automatically by the status of lock detection when bit 5 (CPHA bit) of the capstan
system digital filter control register (CFIC) is 0 (phased system digital filter computation off) and
DPCNT bit is 1.
Capstan System Speed Error Detection Counter: The capstan system speed error detection
counter stops the counter and sets the overflow flag (CFOVF) when an overflow occurs. At the
same time, it generates an interrupt request (IRRCAP1). To clear CFOVF, write 0 after reading 1.
If setting the flag and writing 0 take place simultaneously, the latter is invalid.
Interrupt Request: IRRCAP1 is generated by the DVCFG signal latch and the overflow of the
error detection counter. IRRCAP2 is generated by detection of lock (after the detection of the
specified number of times of locking).
Rev.2.00 Jan. 15, 2007 page 645 of 1174
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Section 26 Servo Circuits
Error data
latch signal
(DVCFG)
Preset data
load signal
Preset period
(2 counts)
Specified speed value
Counter
–value +value
Preset value
Latch data 0
(no error)
Figure 26.33 Example of the Capstan Speed Error Detection
Rev.2.00 Jan. 15, 2007 page 646 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
26.9
Capstan Phase Error Detector
26.9.1
Overview
The capstan phase control system must start operation after the capstan motor has reached the
specified speed by the speed control system. The capstan phase control system operates as follows
in record/playback mode:
• Record mode: Controls the tape running so that it may run at a specified speed together with
the speed control system.
• Playback mode: Controls the tape running so that the recorded track may be traced correctly.
Any error deviated from the reference phase is detected by the digital counter. This phase error
data and the speed error data is processed and added by the digital filter circuit to control the
PWM output. The phase and speed of the capstan, in turn, is control this PWM output.
The control signal of the capstan phase control in the record mode differ from that in playback
mode. In record mode, the control is performed by the DVCFG2 signal which is generated by
dividing the frequencies of the reference signal (REF30P or CREF) and the CFG signal. In
playback mode, it is performed by divided rising signal (DVCTL) of the reference signal
(CAPREF30) and the playback control pulse (PB-CTL).
The reference signal in record and playback modes are as follows:
• Record mode: 1/2 Vsync signal extracted from the video signal to be recorded.
• Playback mode: Signal generated by dividing the PB-CTL signal (DVCTL) at its rising edge.
26.9.2
Block Diagram
Figure 26.34 shows the block diagram of the capstan phase error detector.
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Rev.2.00 Jan. 15, 2007 page 648 of 1174
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R/W
CTLM
R/W
R/P ASM
φs
φs/2
φs/4
φs/8
R/W
SELCFG2
CPGCR
DVCTL
DVCFG2
RECREF
CAPREF30
CREF
REF30P
CPGCR
R/W
CR/RF CPCS1,0
R/W
Internal bus
S
F/F
Q R
W
R/W
CPER1
Error data
(4 bits)
MSB
Preset
R/W
LSB
CPER2
Error data
(16 bits)
Latch
DFUCR
R/W
CFEPS
φs = fosc/2
Error data (20 bits)
To DFU
IRRCAP3
Latch
PB : DVCTL
REC : DVCFG2
Preset
PB: X value + TRK value = CAPREF30
REC: REF30P or CREF
CPGCR
R/(W)
CPOVF
OVF
LSB
CPPR2
Preset data
(16 bits)
W
Counter (20 bits)
Sequence
controller
MSB
(4 bits)
Preset data
CPPR1
Internal bus
Section 26 Servo Circuits
Figure 26.34 Block Diagram of Capstan Phase Error Detector
Section 26 Servo Circuits
26.9.3
Register Configuration
Table 26.12 shows the register configuration of the capstan phase error detector.
Table 26.12 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address
Specified Capstan phase preset data
register 1
CPPR1
W
Byte
H'F0
H'D05C
Specified Capstan phase preset data
register 2
CPPR2
W
Word
H'0000
H'D05A
Capstan phase error data register 1
CPER1
R/W
Byte
H'F0
H'D05D
Capstan phase error data register 2
CPER2
R/W
Word
H'0000
H'D05E
Capstan phase error detection control CPGCR
register
R/W
Byte
H'07
H'D059
Rev.2.00 Jan. 15, 2007 page 649 of 1174
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Section 26 Servo Circuits
26.9.4
Register Description
Specified Capstan Phase Preset Data Registers (CPPR1, CPPR2)
CPPR1
Bit :
7
—
6
—
5
—
4
—
3
CPPR19
2
CPPR18
1
CPPR17
0
CPPR16
Initial value :
R/W :
1
—
1
—
1
—
1
—
0
W
0
W
0
W
0
W
15
CPPR15
14
CPPR14
13
CPPR13
12
CPPR12
11
CPPR11
10
CPPR10
9
CPPR9
8
CPPR8
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
7
CPPR7
6
CPPR6
5
CPPR5
4
CPPR4
3
CPPR3
2
CPPR2
1
CPPR1
0
CPPR0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
CPPR2
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
The 20-bit preset data that defines the specified capstan phase is set in CPPR1 and CPPR2. The 20
bits are weighted as follows: bit 3 of CPPR1 is the MSB. Bit 0 of CPPR2 is the LSB. When
CPPR2 is written to, the 20-bit preset data, including CPPR1, is loaded into the preset circuit.
Write to CPPR1 first, and CPPR2 next. The preset data can be calculated from the following
equation by using H'80000* as the reference value.
Target phase difference = Reference signal frequency/2
Capstan phase preset data = H'80000 − (φs/n × target phase difference)
φs:
Servo clock frequency in Hz (fosc/2)
φs/n:
Clock source of selected counter
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is valid. If a read is attempted, an undetermined value is read out. CPPR1 and CPPR2 are
initialized to H'F0 and H'0000 by a reset, and in standby mode.
Note: * The preset data value is calculated so that the counter will reach H'80000 when the
error is zero. When the counter value is latched as error data in the capstan phase error
data registers (CPER1 and CPER2), however, it is converted to a value referenced to
H'00000.
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Section 26 Servo Circuits
Capstan Phase Error Data Registers (CPER1, CPER2)
Bit :
7
—
6
—
5
—
4
—
3
CPER19
2
CPER18
1
CPER17
0
CPER16
Initial value :
R/W :
1
—
1
—
1
—
1
—
0
R*/W
0
R*/W
0
R*/W
0
R*/W
15
CPER15
14
CPER14
13
CPER13
12
CPER12
11
CPER11
10
CPER10
9
CPER9
8
CPER8
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
7
CPER7
6
CPER6
5
CPER5
4
CPER4
3
CPER3
2
CPER2
1
CPER1
0
CPER0
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
0
R*/W
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Note: * Note that only detected error data can be read.
CPER1 and CPER2 constitute a 20-bit capstan phase error data register. The 20 bits are weighted
as follows: bit 3 of CPER1 is the MSB. Bit 0 of CPER2 is the LSB. When the rotational phase is
correct, the data H'00000 is latched. Negative data will be latched if the phase leads the correct
phase, and positive data if it lags. Values in CPER1 and CPER 2 are transferred to the digital filter
circuit.
CPER1 and CPER are 20-bit read/write registers. When writing data to CPER 1 and CPER2, write
to CPER1 first, and then write to CPER2. Only a word access is valid. If a byte access is
attempted, correct operation is not guaranteed. CPER1 and CPER2 are initialized to H'F0 and
H'0000 by a reset, and in standby mode.
See the note on the capstan phase preset data registers (CPPR1 and CPPR2) in section 26.9.4,
Register Description.
Rev.2.00 Jan. 15, 2007 page 651 of 1174
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Section 26 Servo Circuits
Capstan Phase Error Detection Control Register (CPGCR)
Bit :
7
CPCS1
6
CPCS0
5
CPOVF
4
CR/RF
3
SELCFG2
2
—
1
—
0
—
0
R/W
0
R/W
0
R/(W)*
0
R/W
0
R/W
1
—
1
—
1
—
Initial value :
R/W :
Note: * Only 0 can be written
CPGCR is an 8-bit read/write register that controls the operation of capstan phase error detection.
Bits 2-0 are reserved, and bit 5 accepts only read and 0 write.
It is initialized to H'07 by a reset or in stand-by mode.
Bits 7 and 6⎯Clock Source Selection Bit (CPCS1, CPCS0): These bits select the clock
supplied to the counter. (φs = fosc/2)
Bit 7
Bit 6
CPCS1
CPCS0
Description
0
0
φs
1
φs/2
0
φs/4
1
φs/8
1
(Initial value)
Bit 5⎯Counter Overflow Flag (CPOVF): CPOVF flag indicates the overflow of the 20-bit
counter. It is cleared by writing 0. Write 0 after reading 1. Setting has the highest priority in this
flag. If a flag set and 0 write occurs simultaneously, the latter is invalid.
Bit 5
CPOVF
Description
0
Normal state
1
Indicates that a overflow has occurred in the counter
(Initial value)
Bit 4⎯Preset Signal Selection Bit (CR/RF): Selects the preset signal.
Bit 4
CR/RF
Description
0
Presets REF30P
1
Presets CREF signal
Rev.2.00 Jan. 15, 2007 page 652 of 1174
REJ09B0329-0200
(Initial value)
Section 26 Servo Circuits
Bit 3⎯Latch Signal Selection Bit (SELCFG2): Selects the counter preset signal and the error
data latch signal data in PB (ASM) mode.
Bit 3
SELCFG2
Description
0
Presets CAPREF30 signal; latches DVCTL signal
1
Presets REF30P (CREF) signal; latches DVCFG2 signal
(Initial value)
Bits 2 to 0⎯Reserved: Cannot be modified and are always read as 1.
26.9.5
Operation
The capstan phase error detector detects the phase error based on the reference value set in the
capstan specified phase preset data registers 1 and 2 (CPPR1 and CPPR2). The reference values
set in CPPR1 and CPPR2 are preset in the counter by REF30P (CREF) signal or CAPREF signal,
and counted up by the clock selected. The latching of the error data is performed by DVCTL or
DVCFG2.
The error data detected in the error data automatic transmission mode (CFEPS bit of DFUCR = 0)
is sent to the digital filter circuit automatically. In soft transmission mode (CFEPS bit of DFUCR
= 1), the data written in CPER1 and CPPR2 is sent to the digital filter circuit. The error data is
signed binary. It takes a positive number (+) if the phase is behind the specified phase, a negative
number (-) if in advance of the specified phase, or 0 if it had no phase error (revolving at the
specified phase). Figures 26.35 and 26.36 show examples of operation to detect a capstan phase
error.
Capstan Phase Error Detection Counter: The capstan phase error detection counter stops
counting when an overflow or latch occurs. At the same time, it generates an interrupt request
(IRRCAP3), and sets the overflow flag (CPOVF) if overflow occurred. To clear CPOVF, write 0
after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is invalid.
Interrupt Request: IRRCAP3 is generated by the DVCTL or DVCFG2 signal latch and the
overflow of the error detection counter.
Rev.2.00 Jan. 15, 2007 page 653 of 1174
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Section 26 Servo Circuits
CAPREF30
PB-CTL
DVCTL
or
DVCFG2
Preset
Preset
Counter
Latch
Latch
Preset value
Figure 26.35 Capstan Phase Control in Playback Mode
REF30P
or
CREF
DVCFG2
Preset
Counter
Preset
Latch
Preset value
Figure 26.36 Capstan Phase Control in Record Mode
Rev.2.00 Jan. 15, 2007 page 654 of 1174
REJ09B0329-0200
Latch
Section 26 Servo Circuits
26.10
X-Value and Tracking Adjustment Circuit
26.10.1 Overview
To maintain compatibility with other VCRs, an on-chip adjustment circuit adjusts the phase of the
reference signal (internal reference signal (REF30) or external reference signal (EXCAP)) during
playback. Because of manufacturing tolerances, the physical distance between the video head and
control head (the X-value: 79.244 mm) may vary from set to set, so when a tape that was recorded
on a different set is played back, the phase of the reference signal may need to be adjusted. The
adjustment can be made by a register setting. The same setting can adjust the rotational phase of
the capstan motor to maintain positional alignment (tracking alignment) of the video head with the
recorded tracks in autotracking, or when tracks that were recorded with an EP head are traced by a
wider head. These tracking adjustments can be made by the acquisition of the envelope signal by
the A/D converter.
26.10.2 Block Diagram
The adjustment circuit consists of a 10-bit counter clocked by the system clock (φs or φs/2), and
two down-counters with load registers. Individual setting of X-value adjustment can be made by
X-value data register (XDR) and tracking adjustment by TRK data register (TRDR). The reference
signal clears the 10-bit counter and sets the load register value in the down-counter with two load
registers. After the adjusted reference signal is generated, clock supply stops and the circuit halts
until the next reference signal is input. REF30 signal can be divided as necessary.
Figure 26.37 shows a block diagram.
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Figure 26.37 Block Diagram of X-Value Adjustment Circuit
W
CAPRF
R*/W
DVREF1, 0
XTCR
(2 bits)
Down counter
Edge
selection
W
EXC/REF
XTCR
R
Q S
Internal bus
Counter
(10 bits)
AT/MU
W
(12 bits)
X-value data
register
XDR
(12 bits)
Down counter
XTCR
W
ASM
R
S Q
REC/PB
XTCR
W
TRK/X
Internal bus
Note: * When DVREF1 and DVREF0 are read, values in the down counter (2 bits) are readout.
φs = fosc/2
REF30P
EXCAP
,
φs
φs /2
XCS
XTCR
W
(12 bits)
Down counter
(12 bits)
TRK value data
register
TRDR
W
REF30X
CAPREF30
Section 26 Servo Circuits
Section 26 Servo Circuits
26.10.3
Register Description
Register Configuration
Table 26.13 shows the register configuration of X-value correction and tracking correction
circuits.
Table 26.13 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address
X-value and TRK-value
control register
XTCR
R/W
Byte
H'80
H'D074
X-value data register
XDR
W
Word
H'F000
H'D070
TRK-value data register
TRDR
W
Word
H'F000
H'D072
X-Value and TRK-Value Control Register (XTCR)
Bit :
7
—
6
CAPRF
5
AT/MU
4
TRK/X
3
EXC/REF
2
XCS
1
DVREF1
0
DVREF0
Initial value :
R/W :
1
—
0
W
0
W
0
W
0
W
0
W
0
R/W
0
R/W
XTCR is an 8-bit register to determine the X-value and TRK-value correction circuits. Bits 6 to 2
are write-only bits. No read is valid. If a read is attempted, an undetermined value is read out. Bits
1 and 0 are read/write bits. Only a byte access is valid for XTCR. If a word access is attempted,
correct operation is not guaranteed.
It is initialized to H'80 by a reset, or in stand-by or module stop mode.
Bit 7⎯Reserved: Cannot be modified and is always read as 1.
Bit 6⎯External Sync Signal Edge Selection Bit (CAPRF): Selects the EXCAP edge when a
selection is made to generate external sync signals.
Bit 6
CAPRF
Description
0
Signal generated at the rising edge of EXCAP.
1
Signal generated at both edges of EXCAP.
(Initial value)
Rev.2.00 Jan. 15, 2007 page 657 of 1174
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Section 26 Servo Circuits
Bit 5⎯Capstan Phase Correction Auto/Manual Selection Bit (AT/MU): Selects whether the
generation of the correction reference signal (CAPREF30) for capstan phase control is controlled
automatically or manually depending on the status of the ASM and REC/PB bits of CTL mode
register.
Bit 5
AT/MU
Description
0
Manual mode
1
Auto mode
(Initial value)
Bit 4⎯Capstan Phase Correction Register Selection Bit (TRK/X): Determines the method to
generate the CAPREF30 signal when AT/MU bit is 0.
Bit 4
TRK/X
Description
0
Generates CAPREF30 only by the set value of XDR.
1
Generates CAPREF30 by the set value of XDR and TRDR.
(Initial value)
Bit 3⎯Reference Signal Selection Bit (EXC/REF): Selects the reference signal to generate the
correction reference signal (CAPREF30).
Bit 3
EXC/REF
Description
0
Generates the signal based on REF30P.
1
Generates the signal based on the external reference signal.
(Initial value)
Bit 2⎯Clock Source Selection Bit (XCS): Selects the clock source to be supplied to the 10-bit
counter.
Bit 2
XCS
Description
0
φs
1
φs/2
Rev.2.00 Jan. 15, 2007 page 658 of 1174
REJ09B0329-0200
(Initial value)
Section 26 Servo Circuits
Bits 1 and 0⎯REF30P Division Ratio Selection Bit (DVREF1, DVREF0): Select the division
value of REF30P. If they are read-accessed, the counter value is read out. (The selected division
value is set by the UDF of the counter.)
Bit 1
Bit 0
DVREF1
DVREF0
Description
0
0
Division in 1
1
Division in 2
0
Division in 3
1
Division in 4
1
(Initial value)
X-Value Data Register (XDR)
Bit :
Initial value :
R/W :
15
14
13
12
—
—
—
—
1
—
1
—
1
—
1
—
11
10
9
8
7
6
5
4
3
2
1
0
XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
The X-value data register (XDR) is an 16-bit write-only register. No read is valid. If a read is
attempted, an undetermined value is read out. Only a word access is valid. If a byte access is
attempted, correct operation is not guaranteed.
Set an X-value correction data to XDR, except a value which is beyond the cycle of the CTL
pulse. If AT/MU = 0, TRK/X = 0 is set, CAPREF30 can be generated only by setting the XDR.
Set an X-value and TRK correction value in PB mode, and X- value in REC mode.
It is initialized to H'F000 by a reset, or in stand-by or module stop mode.
TRK-Value Data Register (TRDR)
Bit : 15
14
13
12
—
—
—
— TRD11 TRD10 TRD9 TRD8 TRD7 TRD6 TRD5 TRD4 TRD3 TRD2 TRD1 TRD0
1
R/W : —
1
—
1
—
1
—
Initial value :
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
The TRK-value data register (TRDR) is an 16-bit write-only register. No read is valid. If a read is
attempted, an undetermined value is read out. Only a word access is valid. If a byte access is
attempted, correct operation is not guaranteed.
Set an TRK-value correction data to TRDR, except a value which is beyond the cycle of the CTL
pulse. It is initialized to H'F000 by a reset, or in stand-by or module stop mode.
Rev.2.00 Jan. 15, 2007 page 659 of 1174
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Section 26 Servo Circuits
26.11
Digital Filters
26.11.1 Overview
The digital filters required in servo control make extensive use of multiply-accumulate operations
on signed integers (error data) and coefficients. A filter computation circuit (digital filter
computation circuit) is provided in on-chip hardware to reduce the load on software, and to
improve processing efficiency. Figure 26.38 shows a block diagram of the filter circuit
configuration.
The filter circuit includes a high-speed 24-bit × 16-bit multiplier-accumulator, an arithmetic
buffer, and an I/O processor. The digital filter computations are carried out by the high-speed
multiplier-accumulator. The arithmetic buffer stores coefficients and gain constants needed in the
filter computations, which are referenced by the high-speed multiplier-accumulator.
The I/O processor is activated by a frequency generator signal, and determines what operation is
carried out. When activated, it reads the speed error and phase error from the speed and phase
error detectors and sends them to the accumulator.
When the filter computation is completed, the I/O processor reads the result from the accumulator
and sends it to a 12-bit PWM. At this time, the accumulation result gain can be controlled.
Rev.2.00 Jan. 15, 2007 page 660 of 1174
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Section 26 Servo Circuits
Block Diagram
Error latch signal
Accumulation
controller
End
Start
Data
shifter
UA (32 bits),
upper accumulator
Sign
controller
Buffer/
register
select &
R/W
A, B, G, etc.
Write-only
Calculation
buffer
Coefficient
register
Constant
register
LA (16 bits),
lower accumulator
Accumulation
sequence circuit
Data bus
Error check
Address bus
Accumulator
Accumulator
26.11.2
MD (32 bits),
multiplied data
Read-only
Buffer circuit
Error data
(from the error detector)
Motor control data
(to PWM circuit)
Figure 26.38 Block Diagram of Digital Filter Circuit
Rev.2.00 Jan. 15, 2007 page 661 of 1174
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Rev.2.00 Jan. 15, 2007 page 662 of 1174
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Phase
system
Speed
system
16
DAs15 to 0
CAs15 to 0
+
As
24
XAs
8 +
Figure 26.39 Digital Filter Representation
DAp15 to 0
CAp15 to 0
16
AP
24
XAp
8
-
+
8
VBp
24
8
BP
8
CZp11 to 0
24
8
VSn
24
+
24
DZs11 to 0
CZs11 to 0
8
KP
DGKp15 to 0
CGKp15 to 0
DBp15 to 0
CBp15 to 0
16
8
Bs
8
8
GKp
16
GP
VBs
24
Usn
*
1
+
Usn-1
24
Z -1
8
-
*1 DZp11 to 0
Upn-1
24
Upn
Z -1
+
• Add the same 8-bit value as MSB
• Add 0s to 8 bits after the decimal point
αEp
VPn
24
24
8
+
Error detector
DPER19 to 0
CPER19 to 0
20
Ep
Error detector
DFER15 to 0
CFER15 to 0
16
Es
• Add the same 8-bit value as MSB
• Add 0s to 8 bits after the decimal point
αEs
XSn
24
8
+
24
Tp
24
DBs15 to 0
CBs15 to 0
16
KS
8
+
DGKs15 to 0
CGKs15 to 0
GKs
16
GS
16
OfP
-
Ofs
Y
-
8
12
*2
• DFUCR
PION CP/DP
Phase direct test output
4
DOfs15 to 0
COfs15 to 0
PWM
Note: Go = ×64, ×32 are optional.
Go = ×64, ×32, ×16, ×8,×4, ×2
Right-bit shift of the decimal point
along with Go
8
12
PWM
Go
DFIC
CFIC
• OPTION
PWM
PWM
Notes: 1. See figure 26.42, Z-1 initialization circuit.
2. Gain control is disabled during phase output.
Overflows during accumulation are ignored, and
values below the decimal point are always omitted.
24
14
8
DOfp15 to 0
COfp15 to 0
Ws
24
+
DFUout
24
Digital filter
control
register
Section 26 Servo Circuits
Section 26 Servo Circuits
26.11.3
Arithmetic Buffer
This buffer stores computational data used in the digital filters. See table 26.14. Write access is
-1
limited to the gain and coefficient data (Z ). The other data is used by hardware. None of the data
can be read.
Table 26.14 Arithmetic Buffer Register Configuration
Buffer Data Length
Arithmetic
Data
Phase
system
Gain or
Processing 16 bits
Coefficient Data
16 bits
16 bits
Ep
Upn
Upn-1 (Zp-1)
Vpn
Tp
Y
Ap
Bp
GKp
Ofp
Ap × Epn
Bp × Vpn
Speed
system
Es
Xsn
Usn
Usn-1 (Zs-1)
Vsn
Ws
As
Bs
GKs
Ofs
As × Xsn
Bs × Vsn
Error
output
Legend:
PWM
Valid bits
Non-existent bits
↑
Decimal point
Rev.2.00 Jan. 15, 2007 page 663 of 1174
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Section 26 Servo Circuits
26.11.4
Register Configuration
Table 26.15 shows the register configuration of the digital circuit.
Table 26.15 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address
Capstan phase gain constant
CGKp
W
Word
Undetermined
H'D010
Capstan speed gain constant
CGKs
W
Word
Undetermined
H'D012
Capstan phase coefficient A
CAp
W
Word
Undetermined
H'D014
Capstan phase coefficient B
CBp
W
Word
Undetermined
H'D016
Capstan speed coefficient A
CAs
W
Word
Undetermined
H'D018
Capstan speed coefficient B
CBs
W
Word
Undetermined
H'D01A
Capstan phase offset
COfp
W
Word
Undetermined
H'D01C
Capstan speed offset
COfs
W
Word
Undetermined
H'D01E
Drum phase gain constant
DGKp
W
Word
Undetermined
H'D000
Drum speed gain constant
DGKs
W
Word
Undetermined
H'D002
Drum phase coefficient A
DAp
W
Word
Undetermined
H'D004
Drum phase coefficient B
DBp
W
Word
Undetermined
H'D006
Drum speed coefficient A
DAs
W
Word
Undetermined
H'D008
Drum speed coefficient B
DBs
W
Word
Undetermined
H'D00A
Drum phase offset
DOfp
W
Word
Undetermined
H'D00C
Drum speed offset
DOfs
W
Word
Undetermined
H'D00E
Drum system speed delay
initialization register
DZs
W
Word
H'F000
H'D020
Drum system phase delay
initialization register
DZp
W
Word
H'F000
H'D022
Capstan system speed delay
initialization register
CZs
W
Word
H'F000
H'D024
Capstan system phase delay
initialization register
CZp
W
Word
H'F000
H'D026
Drum system digital filter
control register
DFIC
R/W
Byte
H'80
H'D028
Capstan system digital filter
control register
CFIC
R/W
Byte
H'80
H'D029
Digital filter control register
DFUCR
R/W
Byte
H'C0
H'D02A
Rev.2.00 Jan. 15, 2007 page 664 of 1174
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Section 26 Servo Circuits
26.11.5
Register Description
Gain Constants (CGKp, CGKs, DGKp, DGKs)
Bit :
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value :
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W :
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Note: * Initial value is uncertain.
These registers are 16-bit write-only buffers that set accumulation gain of the digital filter. Only a
word access is valid. Accumulation gain can be set to gain 1 value as maximum value. If a byte
access is attempted, correct operation is not guaranteed. If a read is attempted, an undetermined
value is read out.
These registers are not initialized by a reset or in standby mode. Be sure to write data in them
before processing starts.
In the digital filter, output gain and accumulation gain can be adjusted separately. Take output
gain into account when setting accumulation gain.
Coefficients (CAp, CBp, CAs, CBs, DAp, DBp, DAs, DBs)
Bit :
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value :
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W :
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Note: * Initial value is uncertain.
These registers are 16-bit write-only buffers that determine the cutoff frequency f1 and f2. Only a
word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a read is
attempted, an undetermined value is read out.
These registers are not initialized by a reset or in standby mode. Be sure to write data in them
before processing starts.
In the digital filter, output gain and accumulation gain can be adjusted separately. Take output
gain into account when setting accumulation gain.
Rev.2.00 Jan. 15, 2007 page 665 of 1174
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Section 26 Servo Circuits
Offset (COfp, Cofs, DOfp, DOfs)
Bit :
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value :
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W :
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Note: * Initial value is uncertain.
These registers are 16-bit write-only buffers that set offset level of digital filter output. Only a
word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a read is
attempted, an undetermined value is read out.
These registers are not initialized by a reset or in standby mode. Be sure to write data in them
before processing starts.
In this digital filter, output gain adjustment (×1, 2, 4, 8, 16, 32, 64) after offset adding is enabled.
Take output gain into account when setting accumulation gain.
Delay Initialization Register (CZp, CZs, DZp, DZs)
Bit :
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value :
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
R/W :
—
—
—
—
W
W
W
W
W
W
W
W
W
W
W
W
The delay initialization register is a 16-bit write-only register. Only a word access is valid. If a
byte access is attempted, correct operation is not guaranteed. If a read is attempted, an
undetermined value is read out.
It is initialized to H'F000 by a reset, or in stand-by or module stop mode. The MSB of 12-bit data
(bit 11) is a sign bit.
-1
Loading to Z is performed automatically by bits 4 and 3 of CFIC and DFIC (CZPON, CZSON,
-1
DZPON, DZSON). Writing in register is always available, but loading in Z is not possible when
the digital filter is performing computation in relation to such register. In such a case, loading to
-1
Z will be done the next time computation begins.
Rev.2.00 Jan. 15, 2007 page 666 of 1174
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Section 26 Servo Circuits
Drum System Digital Filter Control Register (DFIC)
Bit :
Initial value :
R/W :
—
7
6
DROV
5
DPHA
4
DZPON
3
DZSON
2
DSG2
1
DSG1
0
DSG0
1
—
0
R/(W)*
0
R/(W)
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Note: * Only 0 can be written
DFIC is an 8-bit read/write register that controls the status of the drum digital filter and operating
mode. Only a byte access is valid. If a word access is attempted, correct operation is not
guaranteed. DFIC is initialized to H'80 by a reset, and in standby mode and module stop mode.
Bit 7⎯Reserved: Cannot be modified and is always read as 1.
Bit 6⎯Drum System Range Over Flag (DROV): This flag is set to 1 when the result of a filter
computation exceeds 12 bits in width. To clear this flag, write 0 after reading 1.
Bit 6
DROV
Description
0
Indicates that the filter computation result did not exceed 12 bits
1
Indicates that the filter computation result exceeded 12 bits
(Initial value)
Bit 5⎯Drum Phase System Filter Computation Start Bit (DPHA): Starts or stops filter
processing for drum phase system.
Bit 5
DPHA
Description
0
Phase system filter computations are disabled
Phase computation result (Y) is not added to Es (see figure 26.39)
1
(Initial value)
Phase system filter computations are enabled
Rev.2.00 Jan. 15, 2007 page 667 of 1174
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Section 26 Servo Circuits
-1
-1
Bit 4⎯Drum Phase System Z Initialization Bit (DZPON): Reflects the DZp value on Z of the
phase system when computation processing of the drum phase system begins. If 1 is written, it is
reflected on the computation, and then cleared to 0. Set this bit after writing data to DZp.
Bit 4
DZPON
Description
0
DZp value is not reflected on Z of the phase system
-1
(Initial value)
-1
1
DZp value is reflected on Z of the phase system
-1
-1
Bit 3⎯Drum Speed System Z Initialization Bit (DZSON): Reflects the DZs value on Z of the
speed system when computation processing of the drum speed system begins. If 1 is written, it is
reflected on the computation, and then cleared to 0. Set this bit after writing data to DZs.
Bit 3
DZSON
Description
0
DZs value is not reflected on Z of the speed system
-1
(Initial value)
-1
1
DZs value is reflected on Z of the speed system
Bits 2 to 0⎯Drum System Output Gain Control Bits (DSG2 to DSG0): Control the gain output
to DRMPWM.
Bit 2
Bit 1
Bit 0
DSG2
DSG1
DSG0
Description
0
0
1
1
0
1
Note:
*
0
×1
1
×2
0
×4
1
×8
0
×16
1
0
(×32)*
(×64)*
1
Invalid (Do not use this setting)
Setting optional.
Rev.2.00 Jan. 15, 2007 page 668 of 1174
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(Initial value)
Section 26 Servo Circuits
Capstan System Digital Filter Control Register (CFIC)
Bit :
7
—
6
DROV
5
DPHA
4
DZPON
3
DZSON
2
DSG2
1
DSG1
0
DSG0
Initial value :
R/W :
1
—
0
R/(W)*
0
R/(W)
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Note: * Only 0 can be written
CFIC is an 8-bit read/write register that controls the status of the capstan digital filter and
operating mode. Only a byte access is valid. If a word access is attempted, correct operation is not
guaranteed. CFIC is initialized to H'80 by a reset, and in standby mode and module stop mode.
Bit 7⎯Reserved: Cannot be modified and is always read as 1.
Bit 6⎯Capstan System Range Over Flag (CROV): This flag is set to 1 when the result of a
filter computation exceeds 12 bits in width. To clear this flag, write 0 after reading 1.
Bit 6
DROV
Description
0
Indicates that the filter computation result did not exceed 12 bits.
1
Indicates that the filter computation result exceeded 12 bits.
(Initial value)
Bit 5⎯Capstan Phase System Filter Start (CPHA): Starts or stops filter processing for capstan
phase system.
Bit 5
CPHA
Description
0
Phase filter computations are disabled.
Phase computation result (Y) is not added to Es (see figure 26.39).
1
(Initial value)
Phase filter computations are enabled.
-1
-1
Bit 4⎯Capstan Phase System Z Initialization Bit (CZPON): Reflects the CZp value on Z of
the capstan phase system when computation processing of the phase system begins. If 1 is written,
it is reflected on the computation, and then cleared to 0. Set this bit after writing data to CZp.
Bit 4
CZPON
Description
0
CZp value is not reflected on Z of the phase system
1
CZp value is reflected on Z of the phase system
-1
(Initial value)
-1
Rev.2.00 Jan. 15, 2007 page 669 of 1174
REJ09B0329-0200
Section 26 Servo Circuits
-1
-1
Bit 3⎯Capstan Speed System Z Initialization Bit (CZSON): Reflects the CZs value on Z of
the capstan speed system when computation processing of the speed system begins. If 1 is written,
it is reflected on the computation, and then cleared to 0. Set this bit after writing data to CZs.
Bit 3
CZSON
Description
0
CZs value is not reflected on Z of the speed system
-1
(Initial value)
-1
1
CZs value is reflected on Z of the speed system
Bits 2 to 0⎯Capstan System Gain Control Bits (CSG2 to CSG0): Control the gain output to
CAPPWM.
Bit 1
Bit 2
Bit 0
CSG2
CSG1
CSG0
Description
0
0
0
×1
1
×2
1
1
0
1
Note:
*
0
×4
1
×8
0
×16
1
(×32)*
0
(×64)*
1
Invalid (Do not use this setting)
Setting optional
Rev.2.00 Jan. 15, 2007 page 670 of 1174
REJ09B0329-0200
(Initial value)
Section 26 Servo Circuits
Digital Filter Control Register (DFUCR)
Bit :
7
—
6
—
5
PTON
4
CP/DP
3
CFEPS
2
DFEPS
1
CFESS
0
DFESS
Initial value :
R/W :
1
—
1
—
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
DFUCR is an 8-bit read/write register which controls the operation of the digital filter. Only a byte
access is valid. If a word access is attempted, correct operation is not guaranteed. It is initialized to
H'00 by a reset, or in stand-by or module stop mode.
Bits 7 and 6⎯Reserved: Cannot be modified and are always read as 1.
Bit 5⎯Phase System Computation Result PWM Output Bit (PTON): Outputs the computation
results of only the phase system to PWM. (The computation results of the drum phase system is
output to CAPPWM pin, and that of the capstan phase system is output to DRMPWM pin.)
Bit 5
PTON
Description
0
Outputs the results of ordinary computation of the filter to PWM pin
1
Outputs the computation results of only the phase system to PWM pin
(Initial value)
Bit 4⎯PWM Output Selection Bit (CP/DP): Selects whether the phase system computation
results when PTON was set to 1 is output to the drum or capstan. The PWM of the selected side
outputs ordinary filter computation results (speed system of MIX).
Bit 4
CP/DP
Description
0
Outputs the drum phase system computation results (DRMPWM)
1
Outputs the capstan phase system computation results (CAPPWM)
(Initial value)
Rev.2.00 Jan. 15, 2007 page 671 of 1174
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Section 26 Servo Circuits
Bit 3⎯Capstan Phase System Error Data Transfer Bit (CFEPS): Transfers the capstan phase
system error data to the digital filter when the data write is enforced.
Bit 3
CFEPS
Description
0
Error data is transferred by DVCFG2 signal latching.
1
Error data is transferred when the data is written.
(Initial value)
Bit 2⎯Drum Phase System Error Data Transfer Bit (DFEPS): Transfers the drum phase
system error data to the digital filter when the data write is enforced.
Bit 2
DFEPS
Description
0
Error data is transferred by HSW (NHSW) signal latching.
1
Error data is transferred when the data is written.
(Initial value)
Bit 1⎯Capstan Speed System Error Data Transfer Bit (CFESS): Transfers the capstan phase
system error data to the digital filter when the data write is enforced.
Bit 1
CFESS
Description
0
Error data is transferred by DVCFG signal latching.
1
Error data is transferred when the data is written.
(Initial value)
Bit 0⎯Drum Speed System Error Data Transfer Bit (DFESS): Transfers the drum speed
system error data to the digital filter when the data write is enforced.
Bit 0
DFESS
Description
0
Error data is transferred by NCDFG signal latching.
1
Error data is transferred when the data is written.
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(Initial value)
Section 26 Servo Circuits
26.11.6
Filter Characteristics
• Lag-Lead Filter
A filter required for a servo loop is built in the hardware. This filter uses IIR (infinite impulse
response) type digital filter (another type of the digital filter is FIR, i.e. finite impulse response
type). This digital filter circuit implements a lag-lead filter, as shown in figure 26.40.
R1
INPUT
OUTPUT
R2
+
C
Figure 26.40 Lag-Lead Filter
The transfer function is expressed by the following equation:
S
2πf2
Transfer function G (S) =
S
1+
2πf1
1+
f1 = 1/2πC (R1 + R2)
f2 = 1/2πCR2
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Section 26 Servo Circuits
• Frequency Characteristics
The computation circuit repeats computation of the function, which is obtained by s-z
conversion according to bi-linear approximation of the transfer function on the s-plane. Figure
26.41 shows the frequency characteristics of the lag-lead filter.
gain(dB)
20log(f1/f2)
f1
f2
phase(deg)
Frequency (Hz)
0
Figure 26.41 Frequency Characteristics of the Lag-Lead Filter
The pulse transfer function G (Z) is obtained by the bi-linear approximation of the transfer G
(S).
In the transfer G (S),
S=
1 – Z–1
2
·
Ts 1 + Z–1
Where, assumed that Z = e ω ,
-1
G (Z) = G ·
2
1 + AZ–1
·
Ts 1 + BZ–1
1
πf2
1
Ts +
πf1
Ts +
G (Z) =
-j Ts
1
πf2
A=
1
Ts +
πf2
Ts –
Ts: Sampling cycle (sec)
Rev.2.00 Jan. 15, 2007 page 674 of 1174
REJ09B0329-0200
1
πf1
B=
1
Ts +
πf1
Ts –
Section 26 Servo Circuits
26.11.7
Operations in Case of Transient Response
In case of transient response when the motor is activated, the digital filter computation circuit
must prevent computation due to a large error. The convergence of the computations becomes
slow and servo retraction deteriorates if a large error is input to the filter circuit when it is
performing repeated computations. To prevent them from occurring, operate the filter (set
constants A and B) after pulling in the speed and phase within a certain range of error, initialize
-1
-1
the Z (set initial values in CZp, CZs, DZp, DZs)(see section 26.11.8, Initialization of Z ), or use
the error data limit function (see section 26.6, Drum Speed Error Detector, and section 26.8,
Capstan Speed Error Detector).
-1
26.11.8 Initialization of Z
-1
-1
Z can be initialized by its delay initialization register (CZp, CZs, DZp, DZs). Loading to Z is
performed automatically by bits 4 and 3 of CFIC and DFIC (CZPON, CZSON, DZPON,
-1
DZSON). Writing in register is always available, but loading in Z is not possible when the digital
-1
filter is performing computation in relation to such register. In such a case, loading to Z will be
-1
done when the next time computation begins. Figure 26.42 shows the initialization circuit of Z .
-1
The delay initialization register sets 12-bit data. The MSB (bit 11) is a sign bit. Z has 24 bits for
integrals and 8 bits for decimals. Accordingly, the same value as the sign bit should be set in the
-1
13 bits on the MSB side of Z , and 0 in the entire decimal section.
-1
Example: Value set for the delay initialization register
MSB
1 0 0 0 0 0 0 0 0 0 0 0
Value set for Z
MSB
1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
Set here the value in the
sign bit
00000000
Fixed
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Section 26 Servo Circuits
Xn
Vn
+
+
Usn-1
24
Z
Res
8
Delay initialization
register
-1
12
USn
-
+
A
DAs15 to 0
DAp15 to 0
CAs15 to 0
CAp15 to 0
DZs11 to 0
DZp11 to 0
CZs11 to 0
CZp11 to 0
B
16
DBs15 to 0
DBp15 to 0
CBs15 to 0
CBp15 to 0
16
Z -1initialization bit
DZSON
DZPON
CZSON
CZSON
W
W
W
W
Internal bus
Note: MSB of 12-bit data to be written in the delay initialization register is a sign bit.
-1
Figure 26.42 Z Initialization Circuit
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Section 26 Servo Circuits
26.12
Additional V Signal Generator
26.12.1 Overview
The additional V signal generator outputs an additional vertical sync signal to take the place of
Vsync in special playback. It is activated at both edges of the HSW signal output by the headswitch timing generator. The head-switch timing generator also outputs a V pulse signal
containing the additional vertical sync pulse itself, and an M level signal that defines the width of
the additional vertical sync signal including the equalizing pulses.
The additional V signal is output at a three-level output pin (V pulse).
Figure 26.43 shows the additional V signal control circuit.
Vpulse signal
Mlevel signal
HSW timing
generator
Csync
Sync signal detector
OSCH
Additional V
pulse generator
Additional V pulse
Figure 26.43 Additional V Pulse Control Circuit
HSW Timing Generator: This circuit generates signals that are synchronized with head
switching. It should be programmed to generate the Mlevel and Vpulse signals at edges of the
HSW signal (VideoFF). For details, see section 26.4, HSW (Head-switch) Timing Generator.
Sync Signal Detector: This circuit detects pulses of the width specified by VTR or HTR from the
signal input at the Csync pin and generates an internal horizontal sync signal (OSCH). The sync
signal detector has an interpolation function, so OSCH has a regular period even if there are
horizontal sync dropouts in the signal received at the pin. For details, see section 26.15, Sync
Signal Detector.
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Section 26 Servo Circuits
26.12.2 Pin Configuration
Table 26.16 summarizes the pin configuration of the additional V signal.
Table 26.16 Pin Configuration
Name
Abbrev.
I/O
Function
Additional V pulse pin
Vpulse
Output
Output of additional V signal synchronized to
video FF
26.12.3 Register Configuration
Table 26.17 summarizes the register that controls the additional V signal.
Table 26.17 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value
Address
Additional V control register ADDVR
R/W
Byte
H'E0
H'D06F
26.12.4 Register Description
Additional V Control Register (ADDVR)
Bit :
Initial value :
R/W :
7
6
5
—
—
—
4
HMSK
3
Hi-Z
2
CUT
1
VPON
0
POL
1
—
1
—
1
—
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
ADDVR is an 8-bit read/write register. It is initialized to H'E0 by a reset, and in standby mode.
Bits 7 to 5⎯Reserved: Cannot be modified and are always read as 1.
Bit 4⎯OSCH Mask (HMSK): Masks the OSCH signal in the additional V signal.
Bit 4
HMSK
Description
0
OSCH is added in
1
OSCH is not added in
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(Initial value)
Section 26 Servo Circuits
Bit 3⎯High Impedance (Hi-Z): Set to 1 when the intermediate level is generated by an external
circuit.
Bit 3
Hi-Z
Description
0
Vpulse is a three-level output pin
1
Vpulse is a three-state output pin (high, low, or high-impedance)
(Initial value)
Bits 2 to 0⎯Additional V Output Control (CUT, VPON, POL): These bits control the output
at the additional V pin.
Bit 2
Bit 1
Bit 0
CUT
VPON
POL
0
0
*
Low level
1
0
Negative polarity (see figure 26.46)
1
Positive polarity (see figure 26.45)
0
Intermediate level (high impedance if Hi-Z bit = 1)
1
High level
1
*
Description
(Initial value)
Legend: * Don’t care.
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Section 26 Servo Circuits
26.12.5
Additional V Pulse Signal
Figure 26.44 shows the additional V pulse signal. The M level and V pulse signals are generated
by the head-switch timing generator. The OSCH signal is combined with these to produce
equalizing pulses. The polarity can be selected by the POL bit in the additional V control register
(ADDVR). V pulse pin outputs a low level by a reset, and in standby mode and module stop
mode.
Internal bus
R/W
R/W
R/W
•ADDVR
VPON CUT HMSK
R/W
POL
R/W
•ADDVR
Hi-Z
STBY
VCC
VCC
OSCH
Rs
V pulse
V pulse pin
Rs
M level
Note:
STBY : Power-down mode signal
V pulse, M level : Signal from the HSW timing generator
Rs : Voltage division resistance (20 kΩ: reference value)
VSS
Figure 26.44 Additional V Pulse Pin
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VSS
Section 26 Servo Circuits
Additional V Pulses When Sync Signal is Not Detected: With additional V pulses, the pulse
signal (OSCH) detected by the sync signal detector is superimposed on the V pulse and Mlevel
signals generated by the head-switch timing generator. If there is a lot of noise in the input sync
signal (Csync), or a pulse is missing, OSCH will be a complementary pulse, and therefore an H
pulse of the period set in HRTR and HPWR will be superimposed. In this case, there may be slight
timing drift compared with the normal sync signal, depending on the HRTR and HPWR setting,
with resultant discontinuity.
If no sync signal is input, the additional V pulse is generated as a complementary pulse. Set the
sync signal detector registers and activate the sync signal detector by manipulating the SYCT bit
in the sync signal control register (SYNCR). See section 26.15.7, Activation of the Sync Signal
Detector.
Figures 26.45 and 26.46 show the additional V pulse timing charts.
HSW signal edge
Mlevel
signal
Vpulse
signal
OSCH
Additional
V pulse
Notes: VPON = 1
CUT = 0
POL = 1
Figure 26.45 Additional V Pulse when Positive Polarity Is Specified
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Section 26 Servo Circuits
HSW signal edge
M level
signal
V pulse
signal
OSCH
Additional
V pulse
Notes: VPON = 1
CUT = 0
POL = 0
Figure 26.46 Additional V Pulse when Negative Polarity Is Specified
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Section 26 Servo Circuits
26.13
CTL Circuit
26.13.1 Overview
The CTL circuit includes a Schmitt amplifier that amplifies and reshapes the CTL input, then
outputs it as the PB-CTL signal to the servo, linear time counter, and other circuits.
The PB-CTL signal is also sent to a duty discriminator in the CTL circuit that detects and records
VISS, ASM, and VASS marks. A REC-CTL amplifier is included in the record circuits. Detection
and recording whether the CTL pulse pattern is long or short can also be enabled to correspond to
the wide-aspect.
The following operating modes can be selected by settings in the CTL mode register:
• Duty discrimination
VISS detect, ASM detect, VASS detect, L/S bit pattern detect
• CTL record
VISS record, ASM record, VASS record, L/S bit pattern record
• Rewrite
Trapezoid waveform generator
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Section 26 Servo Circuits
26.13.2
Block Diagram
Figure 26.47 shows a block diagram of the CTL circuit.
PB-CTL
CTL mode
IRRCTL
FW/RV
Duty discriminator
CTL
detector
VISS detect
VISS
control circuit
Bit pattern
register
Write control
circuit
Schmitt
amplifier
+ -
CTL(+)
VISS write
Duty I/O flag
RECCTL amplifier
CTL(-)
Figure 26.47 Block Diagram of CTL Circuit
Rev.2.00 Jan. 15, 2007 page 684 of 1174
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REF30X
Internal bus
Section 26 Servo Circuits
26.13.3
Pin Configuration
Table 26.18 summarizes the pin configuration of the CTL circuit.
Table 26.18 Pin Configuration
Name
Abbrev.
I/O
Function
CTL (+) I/O pin
CTL (+)
I/O
CTL signal input/output
CTL (–) I/O pin
CTL (–)
I/O
CTL signal input/output
CTL bias input pin
CTL Bias
Input
CTL primary amplifier bias supply
CTL Amp (O) output pin
CTLAmp (O)
Output
CTL amplifier output
CTL SMT (i) input pin
CTLSMT (i)
Input
CTL Schmitt amplifier input
CTL FB input pin
CTL FB
Input
CTL amplifier high-range characteristics
control
CTL REF output pin
CTL REF
Output
CTL amplifier reference voltage output
26.13.4 Register Configuration
Table 26.19 shows the register configuration of the CTL circuit.
Table 26.19 Register Configuration
Name
Abbrev.
R/W
Size
Initial Value Address
CTL control register
CTCR
R/W
Byte
H'30
H'D080
CTL mode register
CTLM
R/W
Byte
H'00
H'D081
REC-CTL duty data register 1
RCDR1
W
Word
H'F000
H'D082
REC-CTL duty data register 2
RCDR2
W
Word
H'F000
H'D084
REC-CTL duty data register 3
RCDR3
W
Word
H'F000
H'D086
REC-CTL duty data register 4
RCDR4
W
Word
H'F000
H'D088
REC-CTL duty data register 5
RCDR5
W
Word
H'F000
H'D08A
Duty I/O register
DI/O
R/W
Byte
H'F1
H'D08C
Bit pattern register
BTPR
R/W
Byte
H'FF
H'D08D
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Section 26 Servo Circuits
26.13.5
Register Description
CTL Control Register (CTCR)
Bit :
7
6
5
4
3
2
1
0
NT/PL
FSLC
FSLB
FSLA
CCS
LCTL
UNCTL
SLWM
Initial value :
0
0
1
1
0
0
0
0
R/W :
W
W
W
W
W
W
R
W
CTCR is an 8-bit read/write register that controls PB-CTL rewrite and sets the slow mode. When
CTL pulse cannot be detected with the input amplifier gain set at the CTL gain control register
(CTLGR) in PB-CTL circuit, bit 1 (UNCTL) of CTCR is set to 1. It is automatically cleared to 0
when CTL pulse is detected.
Bit 1 is read-only, and the rest are write-only. If a read is attempted to a write-only bit, an
undetermined value is read out.
CTCR is initialized to H'30 by a reset, and in standby and module stop mode.
Bit 7⎯NTSC/PAL Select (NT/PL): Selects the period of the rewrite circuit.
Bit 7
NT/PL
Description
0
NTSC mode (frame rate: 30 Hz)
1
PAL mode (frame rate: 25 Hz)
(Initial value)
Bits 6 to 4⎯Frequency Select (FSLA, FSLB, FSLC); These bits select the operating frequency
of the CTL write circuit. They should be set according to fOSC.
Bit 6
Bit 5
Bit 3
FSLC
FSLB
FSLA
Description
0
0
0
Reserved (do not use this setting)
1
Reserved (do not use this setting)
0
fosc = 8 MHz
1
fosc = 10 MHz
*
Reserved (do not use this setting)
1
1
*
Legend: * Don’t care.
Rev.2.00 Jan. 15, 2007 page 686 of 1174
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(Initial value)
Section 26 Servo Circuits
Bits 3⎯Clock Source Select Bit (CCS): Selects clock source of CTL.
Bit 3
CCS
Description
0
φs
1
φs/2
(Initial value)
Bit 2⎯Long CTL Bit (LCTL): Sets the long CTL detection mode.
Bit 2
LCTL
Description
0
Clock source (CCS) operates at the setting value
1
Clock source (CCS) operates for further 8-division after operating at the setting value
(Initial value)
Bit 1⎯CTL Undetected Bit (UNCTL): Indicates the CTL pulse detection status at the CTL
input amplifier sensitivity set at the CTL gain control register.
Bit 1
UNCTL
Description
0
Detected
1
Undetected
(Initial value)
Bit 0⎯Mode Select Bit (SLWM): Selects CTL mode.
Bit 0
SLWM
Description
0
Normal mode
1
Slow mode
(Initial value)
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Section 26 Servo Circuits
CTL Mode Register (CTLM)
Bit :
7
6
5
4
3
2
1
0
ASM
REC/PB
FW/RV
MD4
MD3
MD2
MD1
MD0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value :
R/W :
CTLM is an 8-bit read/write register that controls the operating state of the CTL circuit. If 1 is
written in bits MD3 and MD2, they will be cleared to 0 one cycle (φ) later.
CTLM is initialized to H'00 by a reset, and in standby mode and module stop mode. When CTL is
being stopped, only bits 7, 6 and 5 operate.
Note: Do not set any value other than the setting value for each mode (see table 26.20, CTL
Mode Functions).
Bits 7 and 6⎯Record/Playback Mode Bits (ASM, REC/PB): These bits switch between record
and playback. Combined with bits 4 to 0 (MD4 to MD0), they support the VISS, VASS, and ASM
mark functions.
Bit 7
Bit 6
ASM
REC/PB
Description
0
0
Playback mode
1
Record mode
0
Assemble mode
1
Invalid (do not set)
1
(Initial value)
Bit 5⎯Direction (FW/RV): Selects the direction in playback. Clear this bit to 0 during record.
Figure 26.48 shows the PB-CTL signal.
Bit 5
FW/RV
Description
0
Forward
1
Reverse
Rev.2.00 Jan. 15, 2007 page 688 of 1174
REJ09B0329-0200
(Initial value)
Section 26 Servo Circuits
CTL input
FWD
PB-CTL
REV
Figure 26.48 Internal PB-CTL Signal in Forward and Reverse
Bits 4 to 0⎯CTL Mode Select (MD4 to MD0): These bits select the detect, record, and rewrite
modes for VISS, VASS, and ASM marks. If 1 is written in bits MD3 and MD2, they will be
cleared to 0 one cycle (φ) later.
The 5 bits from MD4 to MD0 are used in combination with bits 7 and 6 (ASM and REC/PB).
Table 26.20 describes the modes.
Table 26.20 CTL Mode Functions
Bit
ASM
R/P
F/R
MD4
MD3
MD2
MD1
MD0
Mode
Description
0
0
0/1
0
0
0
0
0
VASS PB-CTL duty discrimination
(Initial value)
detect
(duty
• Duty I/O flag is set to 1 if duty ≥
detect)
44% is detected
• Duty I/O flag is cleared to 0 if duty
< 44% is detected
• Interrupt request is generated
when one CTL pulse has been
detected
0
1
0
0
0
0
0
0
VASS
record
• If 0 is written in the duty I/O flag,
REC-CTL is generated and
recorded with the duty cycle set by
register RCDR2 or RCDR3
• If 1 is written in the duty I/O flag,
REC-CTL is generated and
recorded with the duty cycle set by
register RCDR4 or RCDR5
0
0
0
1
0
0
1
0
VASS
rewrite
Same as above (VASS record);
trapezoid waveform circuit operation
Rev.2.00 Jan. 15, 2007 page 689 of 1174
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Section 26 Servo Circuits
Bit
ASM
R/P
F/R
MD4
MD3
MD2
MD1
MD0
Mode
0
0
0/1
0
1
0
0
1
• The duty I/O flag is set to 1 at the
VISS
detect
point of write access to register
(index
CTLM
detect)
• The 1 pulses recognized by the
duty discrimination circuit are
counted in the VISS control circuit
Description
• The duty I/O flag is cleared to 0,
indicating VISS detection, when
the value set at VCTR register is
repeatedly detected
• An interrupt request is generated
when VISS is detected
0
1
0
0
0
1
0
1
• 64 pulse data with 0 pulse data at
VISS
record
both edge are written (index
(index
record)
record)
• The index bit string is written
through the duty I/O flag
• An interrupt request is generated
at the end of VISS recording
0
0
0
0
0
1
0
1
VISS
rewrite
Same as above (VISS record;
trapezoid waveform circuit operation)
0
0
0
1
0
0
0
0
VISS
VISS write is forcibly aborted
initialize
1
0
0/1
0
0
0
0
0
ASM
mark
detect
ASM mark detection
• The duty I/O flag is cleared to 0
when PB-CTL duty ≥ 66% is
detected
• An interrupt request is generated
when an ASM mark is detected
0
1
0
1
0
0
0
0
ASM
mark
record
• An ASM mark is recorded by
writing 0 in the duty I/O flag
• An interrupts is requested for
every one CTL pulse
• REC-CTL is generated and
recorded with the duty cycle set by
register RCDR3
Rev.2.00 Jan. 15, 2007 page 690 of 1174
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Section 26 Servo Circuits
REC-CTL Duty Data Register 1 (RCDR1)
Bit :
Initial value :
R/W :
15
14
13
12
—
—
—
—
1
—
1
—
1
—
1
—
11
10
9
8
7
6
5
4
3
2
1
0
CMT1B CMT1A CMT19 CMT18 CMT17 CMT16 CMT15 CMT14 CMT13 CMT12 CMT11 CMT10
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
RCDR1 is a 12-bit write-only register that sets the REC-CTL rising timing. This setting is valid
only for recording and rewriting, and is not used in detection.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a
read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved and are not
affected by write access.
RCDR1 is initialized to H'F000 by a reset, and in standby mode, module stop mode and CTL stop
mode.
The value to set in RCDR1 can be calculated from the transition timing T1 and the servo clock
frequency φs by the equation given below. See figure 26.60. Any transition timing can be set. The
timing should be selected with attention to playback tracking compensation and the latch timing
for phase control.
RCDR1 = T1 × φs/64
φs is the servo clock frequency (= fOSC/2) in Hz, and T1 is the set timing (s).
Note: 0 cannot be set to RCDR1. Set a value 1 or above.
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Section 26 Servo Circuits
REC-CTL Duty Data Register 2 (RCDR2)
Bit :
Initial value :
R/W :
15
14
13
12
—
—
—
—
1
—
1
—
1
—
1
—
11
10
9
8
7
6
5
4
3
2
1
0
CMT2B CMT2A CMT29 CMT28 CMT27 CMT26 CMT25 CMT24 CMT23 CMT22 CMT21 CMT20
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
RCDR2 is a 12-bit write-only register that sets 1 pulse (short) falling timing of REC-CTL at
recording and rewriting, and detects long/short pulses at detecting.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a
read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved and are not
affected by write access.
RCDR2 is initialized to H'F000 by a reset, and in standby mode, module stop mode, and CTL stop
mode.
At recording, the value to set in RCDR2 can be calculated from the transition timing T2 and the
servo clock frequency φs by the equation given below, and the set value should be 25% of the duty
obtained by the equation. See figure 26.60.
RCDR2 = T2 × φ s/64
φs is the servo clock frequency (= fOSC/2) in Hz, and T2 is the set timing (s).
At bit pattern detection, set the 1 pulse long/short threshold value at FWD. See figure 26.56.
RCDR2 = T2' × φ s/64
φs is the servo clock frequency (= fOSC/2) in Hz, and T2' is the 1 pulse long/short threshold value at
FWD (s).
Rev.2.00 Jan. 15, 2007 page 692 of 1174
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Section 26 Servo Circuits
REC-CTL Duty Data Register 3 (RCDR3)
Bit : 15
14
13
12
—
—
—
—
1
R/W : —
1
—
1
—
1
—
Initial value :
11
10
9
8
7
6
5
4
3
2
1
0
CMT3B CMT3A CMT39 CMT38 CMT37 CMT36 CMT35 CMT34 CMT33 CMT32 CMT31 CMT30
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
RCDR3 is a 12-bit write-only register that sets 1 pulse (long) and assemble mark falling timing of
REC-CTL at recording and rewriting, and detects long/short pulses at detecting.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a
read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved and are not
affected by write access.
RCDR3 is initialized to H'F000 by a reset, and in standby mode, module stop mode, and CTL stop
mode.
At recording, the value to set in RCDR3 can be calculated from the transition timing T3 and the
servo clock frequency φs by the equation given below. The set value should be 30 percent of the
duty when the RCDR3 is used for REC-CTL 1 pulse, and 67 to 70 percent when used for assemble
mark. The set value must not exceed the frequency of REF30X. See figure 26.60.
RCDR3 = T3 × φs/64
φs is the servo clock frequency (= fOSC/2) in Hz, and T3 is the set timing (s).
At bit pattern detection, set the 0 pulse long/short threshold value at FWD. See figure 26.56.
RCDR3 = T3' × φs/64
φs is the servo clock frequency (= fOSC/2) in Hz, and T3' is the 0 pulse long/short threshold value at
FWD (s).
Rev.2.00 Jan. 15, 2007 page 693 of 1174
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Section 26 Servo Circuits
REC-CTL Duty Data Register 4 (RCDR4)
Bit : 15
14
13
12
—
—
—
—
1
R/W : —
1
—
1
—
1
—
Initial value :
11
10
9
8
7
6
5
4
3
2
1
0
CMT4B CMT4A CMT49 CMT48 CMT47 CMT46 CMT45 CMT44 CMT43 CMT42 CMT41 CMT40
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
RCDR4 is a 12-bit write-only register that sets the timing of falling edge of the 0 pulse (short) of
REC-CTL in record or rewrite mode. In detection mode, it is used to detect the long/short pulse.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a
read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved, and no write in
them is valid.
It is initialized to H'F000 by a reset, stand-by or module stop.
In record mode, set a value with the 57.5 percent duty cycle obtained from the set time T4
corresponding to the frequency φs according to the following equation. See figure 26.60.
RCDR4 = T4 × φ s/64
φ is the servo clock frequency (= fOSC/2) in Hz, and T4 is the set timing (s).
At bit pattern detection, set the 0 pulse long/short threshold value at REV. See figure 26.56.
RCDR4 = H'FFF − (T4' × φ s/80)
φs is the servo clock frequency (= fOSC/2) in Hz, and T4' is the 0 pulse long/short threshold value at
REV (s).
Rev.2.00 Jan. 15, 2007 page 694 of 1174
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Section 26 Servo Circuits
REC-CTL Duty Data Register 5 (RCDR5)
15
14
13
12
—
—
—
—
1
R/W : —
1
—
1
—
1
—
Bit :
Initial value :
11
10
9
8
7
6
5
4
3
2
1
0
CMT5B CMT5A CMT59 CMT58 CMT57 CMT56 CMT55 CMT54 CMT53 CMT52 CMT51 CMT50
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
RCDR5 is a 12-bit write-only register that sets the timing of falling edge of the 0 pulse (short) of
REC-CTL in record or rewrite mode. In detection mode, it is used to detect the long/short pulse.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a
read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved, and no write in
them is valid.
It is initialized to H'F000 by a reset, stand-by or module stop.
In record mode, set a value with the 62.5 percent duty cycle obtained from the set time T5
corresponding to the frequency φs according to the following equation. See figure 26.60.
RCDR5 = T5 × φ s/64
φ is the servo clock frequency (= fOSC/2) in Hz, and T5 is the set timing (s).
At bit pattern detection, set the 1 pulse long/short threshold value at REV. See figure 26.56.
RCDR5 = H'FFF − (T5' × φ s/80)
φs is the servo clock frequency (= fOSC/2) in Hz, and T5' is the 1 pulse long/short threshold value at
REV (s).
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Section 26 Servo Circuits
Duty I/O Register (DI/O)
Bit :
7
VCTR2
6
VCTR1
5
VCTR0
4
—
3
BPON
2
BPS
1
BPF
0
DI/O
1
W
1
W
1
W
1
—
0
W
0
W
0
R/(W)*
1
R/W
Initial value :
R/W :
Note: * Only 0 can be written
DI/O is an 8-bit register that confirms and determines the operating status of the CTL circuit.
It is initialized to H'F1 by a reset, and in standby mode, module stop mode, and CTL stop mode.
Bits 7 to 5⎯VISS Interrupt Setting Bit (VCTR2 to VCTR0): Combination of VCTR2, VCTR1
and VCTR0 sets number of 1 pulse detection in VISS detection mode. Detecting the set number of
pulse detection is considered as VISS detection, and an interrupt request is generated.
Note: When changing the detection pulse number during VISS detection, initialize VISS first,
then resume the VISS detection setting.
Bit 7
Bit 6
Bit 5
VCTR2
VCTR1
VCTR0
Number of 1-Pulse for Detection
0
0
0
2
1
4 (SYNC mark)
0
6
1
8 (mark A, short)
0
12 (mark A, long)
1
16
0
24 (mark B)
1
32
1
1
0
1
Bit 4⎯Reserved: Cannot be modified and is always read as 1.
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Section 26 Servo Circuits
Bit 3⎯Bit Pattern Detection ON/OFF Bit (BPON): Determines ON or OFF of bit pattern
detection.
Note: When writing 1 to BPON bit, be sure to set appropriate data to RCDR 2 to 5 beforehand.
Bit 3
BPON
Description
0
Bit pattern detection off
1
Bit pattern detection on
(Initial value)
Bit 2⎯Bit Pattern Detection Start Bit (BPS): Starts 8-bit bit pattern detection. When 1 is
written to this bit, it returns to 0 after one cycle. Writing 0 to this bit does not affect operation.
Bit 2
BPS
Description
0
Normal status
1
Starts 8-bit bit pattern detection
(Initial value)
Bit 1⎯Bit Pattern Detection Flag (BPF): Sets flag every time 8-bit PB-CTL is detected in PB or
ASM mode. To clear flag, write 0 after reading 1.
Bit 1
BPF
Description
0
Bit pattern (8-bit) is not detected
1
Bit pattern (8-bit) is detected
(Initial value)
Bit 0⎯Duty I/O Register (DI/O): This flag has different functions for record and playback.
In VISS detect mode, VASS detect mode, and ASM mark detect mode, this flag indicates the
detection result.
In VISS record or rewrite mode, this flag controls the write control circuit so as to write an index
code, operating according to a control signal from the VISS control circuit.
In VASS record or rewrite mode and ASM mark record mode, this flag is used for write control,
one CTL pulse at a time.
This bit can always be written to, but this does not affect the write control circuit in modes other
than VISS record, rewrite, and ASM record.
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Section 26 Servo Circuits
• VISS Detect Mode and VASS Detect Mode: The duty I/O flag indicates the result of duty
discrimination. The duty I/O flag is 1 when the duty cycle of the PB-CTL signal is above 44%
(a 0 pulse in the CTL signal). The duty I/O flag is 0 when the duty cycle of the PB-CTL signal
is below 43% (a 1 pulse in the CTL signal).
• ASM Mark Detect Mode: The duty I/O flag indicates the result of duty discrimination. The
duty I/O flag is 0 when the duty cycle of the PB-CTL signal is above 66% (when an ASM
mark is detected).
The duty I/O flag is 1 when the duty cycle of the PB-CTL signal is below 65% (when an ASM
mark is not detected).
• VISS Record Mode and VISS Rewrite Mode: The duty I/O flag operates according to a control
signal from the VISS control circuit, and controls the write control circuit so as to write an
index code. The write timing is set in the REC-CTL duty data registers (RCDR1 to RCDR5).
For VISS recording, registers RCDR1 to RCDR5 are set with reference to REF30X. For VISS
rewrite, RCDR2 to RCDR5 are set with reference to the low-to-high transition of the
previously recorded CTL signal, and the write is carried out through the trapezoid waveform
generator.
Set the duty timing for a 1 pulse (short) in RCDR2, for a 1 pulse (long) in RCDR3, for a 0
pulse (short) in RCDR4, and for a 0 pulse (long) in RCDR5.
While an index code is being written, the value of the bit being written can be read by reading
the duty I/O flag. If the CTL signal currently being written is a 0 pulse, the duty I/O flag will
read 1. If the CTL signal currently being written is a 1 pulse, the duty I/O flag will read 0.
• VASS Record Mode and VASS Rewrite Mode: The duty I/O flag is used for write control, one
CTL pulse at a time. The write timing is set in the REC-CTL duty data registers (RCDR1 to
RCDR5). For VASS recording, registers RCDR1 to RCDR5 are set with reference to REF30X.
For VASS rewrite, RCDR2 to RCDR5 are set with reference to the low-to-high transition of
the previously recorded CTL signal, and the write is carried out through the trapezoid
waveform generator.
Set the duty timing for a 1 pulse (short) in RCDR2, for a 1 pulse (long) in RCDR3, for a 0
pulse (short) in RCDR4, and for 0 pulse (long) in RCDR5.
If 0 is written in the duty I/O flag, a CTL pulse will be written with a duty cycle set in RCDR2
and RCDR3, referenced to the immediately following REF30X. If 1 is written in the duty I/O
flag, a CTL pulse will be written with a duty cycle set in RCDR4 and RCDR5, referenced to
the immediately following REF30X.
• ASM Record Mode: The duty I/O flag is used for write control, one CTL pulse at a time. The
write timing is set in the REC-CTL duty data registers (RCDR1 and RCDR3). If 0 is written in
the duty I/O flag, a CTL pulse will be written with a duty cycle of 67% to 70% as set in
RCDR3, referenced to the immediately following REF30X.
Rev.2.00 Jan. 15, 2007 page 698 of 1174
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Section 26 Servo Circuits
Bit Pattern Register (BTPR)
Bit :
7
LSP7
6
LSP6
5
LSP5
4
LSP4
3
LSP3
2
LSP2
1
LSP1
0
LSP0
Initial value :
R/W :
1
R/W*
1
R/W*
1
R/W*
1
R/W*
1
R/W*
1
R/W*
1
R/W*
1
R/W*
Note: * Write is prohibited when bit pattern detection is selected.
BTPR is an 8-bit shift register which detects and records the bit pattern of the CTL pulses. If a
CTL pulse is detected in PB or ASM mode, the register is shifted leftward at the rising edge of
PB-CTL, and reflects the determined result of long/short on the bit 0 (long pulse = 1, short pulse =
0).
If BPON bit is set to 1 in PB mode, the register starts detection of bit pattern immediately after the
CTL pulse. To exit the bit pattern detection, set the BPON bit at 0.
If 1 was written in the BPS bit when the bit pattern is being detected, the BPF bit is set at 1 when
an 8-bit bit pattern was detected. If continuous detection of 8-bits is required, write 0 in the BPF
bit, and then write 1 in BPS bit.
At the time of VISS detection, the bit pattern detection is disabled. Set the BPON bit to 0 at the
time of VISS detection.
In REC mode, the register record the long/shorts in the bit pattern set in BTPR. The pulse in
record mode is determined always by bit 7 (LSP7) of BTPR. BTPR records one pulse, shifts
leftward, and stores the data of bit 7 to bit 0.
BTPR is initialized to H'FF by a reset, in stand-by, module stop, or CTL stop mode.
Rev.2.00 Jan. 15, 2007 page 699 of 1174
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Section 26 Servo Circuits
26.13.6
Operation
CTL Circuit Operation: As shown in figure 26.49, the CTL discrimination/record circuit is
composed of a 16-bit up/down counter and 12-bit registers (×5).
In playback (PB) mode, the 16-bit up/down counter counts on a φs/4 clock when the PB-CTL
pulse is high, and on a φs/5 clock when low. In record or slow mode, this counter increments the
count on a φs/4 clock. In ASM mode, this counter increments the count on a φs/8 clock when the
pulse is high, and on a φs/4 clock when low.
This counter always counts up in record and slow modes.
In playback or slow mode, it is cleared on the rise of PB-CTL signal. In record mode, it is cleared
on the rise of REF30X signal.
Up/Down control signal
REC: UP
PB, ASM:
UP when PB-CTL is high
Down when PB-CTL is low
Counter clear signal
REF30X ↑ (REC)
PB-CTL ↑ (PB, ASM)
UP
φs/4
(φs/8)
φs/5
(φs/4)
UP/DOWN counter (16 bits)
UDF
Duty
detection
Upper 12 bits
DOWN
Legend:
UDF: Underflows when PB-CTL
duty is 43% or less
RCDR1
Match
detection
REC-CTL↑
RCDR2
Match
detection
REC-CTL↓(S1)
RCDR3
Match
detection
REC-CTL↓(L1and ASM)
RCDR4
Match
detection
REC-CTL↓(S0)
RCDR5
Match
detection
REC-CTL↓(L0)
12-bit register
Figure 26.49 CTL Discrimination/Record Circuit
CTL Mode Register (CTLM) Switchover Timing: CTLM is enabled immediately after data is
written to the register. Care must be taken with changes in the operating state.
Capstan phase control is performed by the VD sync REF30X (X-value + tracking value) and PBCTL in ASM mode, and by the REF30P or CREF and CFG division signal (DVCFG2) in REC
mode. If CAPREF30 signal to be used for capstan phase control is always generated by XDR, the
Rev.2.00 Jan. 15, 2007 page 700 of 1174
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Section 26 Servo Circuits
value of XDR must be overwritten when switching between PB and REC modes. Figures 26.50
and 26.51 show examples of switch timing of CTLM and XDR.
The X-value is updated by REF30P. Modification of XDR must be performed before REF30P
in the cycle in which the X-value is changed.
X-value (XDR) is
rewritten in this
cycle
VD
REF30P
HSW
X-value
after
change
X-value
Latch
Preset
Capstan phase control
ASM mode, PB mode : REF30X-PB-CTL
REC mode
: REF30P-DVCFG2
Tx
REF30X
PB-CTL
REC-CTL
CTL
Ta
16bit
UP/DOWN
counter
Tb
φ/5
φ/4
φ/4
RCDR1
RCDR3 RCDR1 RCDR2
UDF
0 pulse
1 pulse
0 pulse
1 pulse
DVCFG2
CDIVR2
Register write
Notes: 1. Ta is the interval calculated from RCDR3.
2. Tb is the interval in which switchover is performed from ASM mode to REC mode.
3. Tx is the cycle in which the REF30X period is shortened due to the change of XDR.
Figure 26.50 Example of CTLM Switchover Timing
(When Phase Control Is Performed by REF30P and DVCFG2 in REC Mode)
Rev.2.00 Jan. 15, 2007 page 701 of 1174
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Section 26 Servo Circuits
The X-value is updated by REF30P. Modification of XDR must be performed before REF30P
in the cycle in which the X-value is changed.
X-value (XDR) is
rewritten in this
cycle
VD
REF30P
HSW
X-value after
change
X value
Tx
Capstan phase control
ASM mode, PB mode: REF30X-PB-CTL
REF30X
PB-CTL
REC-CTL
CTL
Tb
Ta
16bit
UP/DOWN
counter
φ/5
φ/4
φ/4
RCDR1
RCDR3 RCDR1 RCDR2
UDF
0 pulse
1 pulse
0 pulse
1 pulse
DVCFG2
CDIVR2
Register write
CREF
ASM-REC
switchover
Latch
Preset
Capstan phase control
REC mode : CREF30P-DVCFG2
Notes: 1.
2.
3.
4.
Ta is the interval calculated from RCDR3.
Tb is the interval in which switchover is performed from ASM mode to REC mode.
Tx is the cycle in which the REF30X period is shortened due to the change of XDR.
With CREF and DVCFG2 phase alignment, the frequency need not be 25 Hz or 30 Hz.
Figure 26.51 Example of CTLM Switchover Timing
(When Phase Control Is Performed by CREF and DVCFG2 in REC Mode)
Rev.2.00 Jan. 15, 2007 page 702 of 1174
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Section 26 Servo Circuits
26.13.7
CTL Input Section
The CTL input section consists of an input amplifier of which gain can be controlled by the
register setting and a Schmitt amplifier. Figure 26.52 shows a block diagram of the CTL input
section.
Trivial CTL pulse signal is received from the CTL head, amplified by the input amplifier,
reshaped into a square wave by the Schmitt amplifier, and sent to the servo circuits, and the Timer
L as the PB-CTL signal. Control the CTL input amplifier gain by bits 3 to 0 in CTL gain control
register (CTLGR) of the servo port.
AMPON
(PB-CTL)
AMPSHORT
(REC-CTL)
CTLGR3 to 1
CTLFB
CTLGR0
– +
+
–
–
+
PB-CTL(+)
PB-CTL(-)
CTL(-)
CTL(+)
CTLREF
CTLBias
CTLFB
CTLAmp(o)
CTLSMT(i)
Note
Note : Be sure to set a capacitor between CTLAmp (o) and CTLSMT (i).
Figure 26.52 Block Diagram of CTL Input Amplifier
Rev.2.00 Jan. 15, 2007 page 703 of 1174
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Section 26 Servo Circuits
CTL Detector: If the CTL detector fails to detect a CTL pulse, it sets the CTL control register
(CTCR) bit 1 to 1 indicating that the pulse has not been detected. If a CTL pulse is detected after
that, the bit is automatically cleared to 0. Duration used for determining detection or non-detection
of the pulse depends on magnitude of phase shift of the last detected pulse from the reference
phase (phase difference between REF30 and CTL signal). Typically, detection or non-detection is
determined within 3 to 4 cycles of the reference period.
If settings of the CTL gain control register are maintained in a table format, you can refer to it
when the CTL detector failed to detect CTL pulses. From the table, you can control amplifier gain
of the CTL according to state of UNCTL bit, thereby selecting an optimum CTL amplifier gain
depending on state of the pulse recorded.
Figure 26.53 illustrates concept of gain control for detecting the CTL input pulse.
*
V+TH (fixed)
V-TH (fixed)
*
Note: * CTL input sensitivity is variable depending on CTL
gain control register (CTLGR) setting.
Figure 26.53 CTL Input Pulse Gain Control
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Section 26 Servo Circuits
PB-CTL Waveform Shaper in Slow Mode Operation: If bit 0 in CTL control register (CTCR)
is set to slow mode, slow reset function is activated. In slow mode, if falling edge is not detected
within the specified time from rising edge detection, PB-CTL is forcibly shut down (slow reset).
The time TFS (s) until the signal falls is the following interval after the rising edge of the internal
CTL signal is detected:
TFS = 16384 × 4/φ s
(φs = fOSC/2)
When fOSC = 10 MHz, TFS = 13.1 ms.
Figure 26.54 shows the PB-CTL waveform in slow mode.
1 frame
1 frame
1 frame
CTL waveform
Slow reset
Internal CTL signal
CTLP↑
Acceleration
CTLP↑
Deceleration
Slow tracking delay
Stop
Acceleration
CTLP↑
Deceleration
Slow tracking delay
Acceleration
Stop
Slow tracking delay
Figure 26.54 PB-CTL Waveform in Slow Mode Operation
Rev.2.00 Jan. 15, 2007 page 705 of 1174
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Section 26 Servo Circuits
26.13.8
Duty Discriminator
The duty discriminator circuit measures the period of the control signal recorded on the tape (PBCTL signal) and discriminates its duty cycle. In VISS or VASS detection, the duty I/O flag is set
or cleared according to the result of duty discrimination. The duty I/O flag is set to 1 when the
duty cycle of the PB-CTL signal is above 44%, and is cleared to 0 when the duty cycle is below
43%.
In ASM detection, an ASM mark is recognized (and the duty I/O flag is cleared to 0) when the
duty cycle is above 66%. When the duty cycle is below 65%, no ASM mark is recognized and the
duty I/O flag is set to 1.
The detection direction can be switched between forward and reverse by bit 5 (FW/RV) in the
CTL mode register.
Long or short pulse can be detected by comparing REC-CTL duty data register (RCDR2 to
RCDR5) and UP/DOWN counter. Long or short pulse is discriminated at PB-CTL signal falling.
Discrimination result is stored in bit 0 of bit pattern register (BTPR). At the same time, BTPR is
shifted to the left. LSP0 indicates 0 when short pulse is detected, and 1 when long pulse is
detected.
Set the threshold value of long/short pulse in RCDR2 to RCDR5. See the description on the
detection of the long/short pulse.
Figure 26.55 shows the duty cycle of the PB-CTL signal.
Rev.2.00 Jan. 15, 2007 page 706 of 1174
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Section 26 Servo Circuits
Input signal
Short 1 pulse
PB-CTL
25 ±0.5%
Input signal
Long 1 pulse
PB-CTL
30 ±0.5%
Input signal
Short 0 pulse
PB-CTL
57.5 ±0.5%
Input signal
Long 0 pulse
PB-CTL
62.5 ±0.5%
Input signal
ASM mark
PB-CTL
67 to 70%
Figure 26.55 PB-CTL Signal Duty Cycle
Figure 26.56 shows the duty discrimination circuit. A 44% duty cycle is discriminated by counting
with the 16-bit up/down counter, using a φs/4 clock for the up-count and a φs/5 clock for the
down-count. An up-count is performed when the PB-CTL signal is high, and a down-count when
low. Long or short pulse is discriminated by comparing with RCDR2 to RCDR5.
Rev.2.00 Jan. 15, 2007 page 707 of 1174
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Section 26 Servo Circuits
PB-CTL
UP/DOWN
φ s/4
UDF
UP/DOWN counter (16 bits)
0/1
discrimination
φ s/5
Comparison of upper
12-bit
S
* RCDR2or4 (12-bit)
Q
L/S
discrimination
R
* RCDR3or5 (12-bit)
Clear
PB-CTL↑
* FWD : Discriminated by RCDR2 and RCDR3
REV : Discriminated by RCDR4 and RCDR5
φ s/4
φ s/5
Counter
PB-CTL
1 pulse
φ s/5
Counter
φ s/4
PB-CTL
0 pulse
0 pulse L/S threshold value
RCDR3
Counter
FWD
φ s/5
RCDR2
1 pulse L/S threshold value
φ s/4
PB-CTL
Short pulse
(0 pulse)
φ s/5
REV
0 pulse L/S threshold value
RCDR4
φ s/4
Counter
RCDR5
1 pulse L/S threshold value
PB-CTL
Long pulse
(1 pulse)
Figure 26.56 Duty Discriminator
Rev.2.00 Jan. 15, 2007 page 708 of 1174
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Section 26 Servo Circuits
VISS (Index) Detect Mode: VISS detection is carried out by the VISS control circuit, which
counts 1 pulses in the PB-CTL signal. If the pulse count detects any value set in the VISS interrupt
setting bits (bits 5, 6, or 7 in the duty I/O register), an interrupt request is generated and the duty
I/O flag is cleared to 0.
At VISS record or rewrite, INDEX code is automatically written. INDEX code is composed of 0
continuous 62-bit data with 0 pulse data at both edge.
Examples of bit strings and the duty I/O flag at VISS detection/record is illustrated in figure 26.57.
IRRCTL
Thirty-two 1 pulses
detected
0 1 1 1 1
Tape direction
1
1
1
1
0
61 ±3 bits
63 ±3 bits
Start
Duty I/O flag
(a) VISS detection (INDEX: Thirty-two 1 pulse setting)
IRRCTL
1 2 3
Tape direction
62 63 64
0 1 1 1 1
1
1
1
1
0
62 bits
64 bits
Start
Duty I/O flag
(b) VISS record
Figure 26.57 Examples of VISS Bit Strings and Duty I/O Flag
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Section 26 Servo Circuits
Duty Detection Mode (VASS): VASS detection is carried out by the duty discriminator. Software
can detect index sequences by reading the duty I/O flag at each CTL pulse.
At each CTL pulse, the duty discriminator sends the result of duty discrimination to the duty I/O
flag, and simultaneously generates an interrupt request. The duty I/O flag is cleared to 0 if the
CTL pulse is a 1 (duty cycle below 43%), and is set to 1 if the CTL pulse is a 0 (duty cycle above
44%).
The duty I/O flag is modified at each CTL pulse. It should be read by the interrupt-handling
routine within the period of the PB-CTL signal. VASS detection format is illustrated in figure
26.58.
Tape direction
Written three times
M
B
1 1 1 1 1 1 1 1 1 1 1 S
Header (11 bits)
L M
S S
B B
Thousands
L M
S S
B B
Hundreds
L M
S S
B B
Tens
L
S
B
Ones
Data (16 bits: 4 digits of 4-bit BCD)
Figure 26.58 VASS (Index) Format
Assemble (ASM) Mark Detect Mode: ASM mark detection is carried out by the duty
discriminator. If the duty discriminator detects that the duty cycle of the PB-CTL signal is 66% or
higher, it generates an interrupt request, and simultaneously clears the duty I/O flag to 0.
The duty I/O flag is updated at every CTL pulse. It should be read by the interrupt-handling
routine within the period of the PB-CTL signal.
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Section 26 Servo Circuits
Detection of the Long/Short Pulse: The long/short pulse is detected in PB mode by the L/S
determination based on the comparison of the REC-CTL duty register (RCDR2 to RCDR5) with
the up/down counter and the results of the duty I/O flag. The results of the determination is stored
in bit 0 (LSP0) of the bit pattern register (BTPR) at the rising edge of PB-CTL, shifting at the
same time BTPR leftward.
RCDR2-5 set the L/S thresholds for each of FWD/REV. Set to RCDR2 a threshold of 1 pulse L/S
for FWD, to RCDR3 a threshold of 0 pulse L/S for FWD, to RCDR4 a threshold of 0 pulse L/S for
REV, and to RCDR5 a threshold of 1 pulse L/S for REV. Figure 26.59 shows the detection of
long/short pulse.
Also, the bit pattern of 8-bit can be detected by BTPR. Check that an 8-bit detection has been done
by bit 1 (BPF bit) of the duty I/O register, and then read BTPR.
Internal bus
R
BTPR
Shift left-ward
Bit patter register (8 bits)
LSB
RCDR2 (12 bits)
S
RCDR3 (12 bits)
Q
R
RCDR4 (12 bits)
S
RCDR5 (12 bits)
Q
R
FW/RV
DI/O
High-order 12-bit data
φs/4
Note:
Up/Down counter (16 bits)
L/S is determined at the rising edge of PB-CTL. After the determination, bit pattern
register is shifted leftward, and the results of the determination is stored in the LSB.
Figure 26.59 Detection of Long/Short Pulse
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Section 26 Servo Circuits
26.13.9
CTL Output Section
An on-chip control head amplifier is provided for writing the REC-CTL signal generated by the
write control circuit onto the tape.
The write control circuit controls the duty cycle of the REC-CTL signal in the writing of VISS and
VASS sequences and ASM marks and the rewriting of VISS and VASS sequences. The duty cycle
of the REC-CTL signal is set in REC-CTL duty data registers 1 to 5 (RCDR1 to RCDR5). Times
calculated in terms of φs (= fOSC/2) should be converted to appropriate data to be set in these
registers. In VISS or VASS mode, set RCDR2 for a duty cycle of 25% ±0.5%, RCDR3 for a duty
cycle of 30% ±0.5%, RCDR4 for a duty cycle of 57.5 ±0.5%, and RCDR5 for a duty cycle of 62.5
±0.5%. When 1 is written in the duty I/O flag, the REC-CTL signal will be written on the tape
with a 25% ±0.5% duty cycle when 0 is written in bit 7 (LSP7) in the bit pattern register (BTPR)
and with a 30 ±0.5% duty cycle when 1 is written. Table 26.21 shows the relationship between the
REC-CTL duty register and CTL outputs.
In ASM mark write mode, set RCDR3 for a duty cycle of 67% to 70%. An ASM mark will be
written when 0 is written in the duty I/O flag.
An interrupt request is generated at the rise of the reference signal after one CTL pulse has been
written. The reference signal is derived from the output signal (REF30X) of the X-value
adjustment circuit, and has a period of one frame.
Figure 26.60 shows the timings that generate the REC-CTL signal.
Table 26.21 REC-CTL Duty Register and CTL Outputs
MODE
D/IO
LSP7
Pulse
RCDR
Duty
VISS, VASS modes
0
0
S1
RCDR2
25 ±0.5%
1
L1
RCDR3
30 ±0.5%
0
S0
RCDR4
57.5 ±0.5%
1
L0
RCDR5
62.5 ±0.5%
*
⎯
RCDR3
67 to 70%
1
ASM mode
0
Legend: * Don’t care.
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Section 26 Servo Circuits
Internal bus
RESET
REF30X↑
W
W
W
Clear
φs/4
RCDR1
(12 bits)
UP/DOWN counter (12 bits)
RCDR2or4
(12 bits)
RCDR3or5
(12 bits)
Compare
Compare
Upper 12 bits
Compare
REC-CTL rise timing
REC-CTL1 pulse,
ASM fall timing
REC-CTL 0 pulse fall
timing
End of writing of one CTL
pulse (except VISS) IRRCTL
REF30X
Counter
reset
Match detection
Counter
Match detection
REC-CTL
RCDR1
RCDR2 (VISS/VASS S1 pulse)
RCDR3 (VISS/VASS L1 pulse, or ASM)
RCDR4 (VISS/VASS S0 pulse)
RCDR5 (VISS/VASS L0 pulse)
Figure 26.60 REC-CTL Signal Generation Timing
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Section 26 Servo Circuits
The 16-bit counter in the REC-CTL circuit continues counting on a clock derived by dividing the
system clock φs (= fOSC/2) by 4. The counter is cleared on the rise of REF30X in record mode, and
on the rise of PB-CTL in rewrite mode. REC-CTL match detection is carried out by comparing the
counter value with each RCDR value.
RCDR1 to RCDR5 can be written to by software at all times. If RCDR is changed before the
respective match detection is performed, match detection is performed using the new value. The
value changed after match detection becomes valid on the rise of REF30X following the change.
Figure 26.61 shows examples of RCDR change timing.
REF30X
RCDR4
Counter
RCDR2
RCDR1
REC-CTL
RCDR1 RCDR2
1 pulse (Short)
RCDR1
RCDR4 RCDR1
RCDR4
RCDR4
Interval in which
RCDR4 can be
written to
0 pulse (Short)
RCDR1
Rewritten 0 pulse
(Short)
Figure 26.61 Example of RCDR Change Timing (Example Showing RCDR4)
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Section 26 Servo Circuits
26.13.10 Trapezoid Waveform Circuit
In rewriting, the trapezoid waveform circuit leaves the rising edge of the already-recorded PBCTL signal intact, but changes the duty cycle.
In rewriting, the CTL pulse is written with reference to the rise of PB-CTL. The CTL duty cycle
for a rewrite is set in the REC-CTL duty data registers (RCDR2 to RCDR5). Time values T2 to T5
are referenced to the rise of PB-CTL.
Figure 26.62 shows the rewrite waveform.
RESET
PB-CTL↑
Internal bus
W
W
W
Clear
φs/4
Up/Down counter (16 bits)
RCDR2or4
(12 bits)
RCDR3or5
(12 bits)
RCDR1
(12 bits)
Not used when
rewriting
Upper 12 bits
Compare
Compare
REC-CTL 1 pulse
fall timing
REC-CTL 0 pulse
fall timing
End of writing of one
CTL pulse (except
VISS) IRRCTL
PB-CTL
Eliminated
pulse
New pulse
High-impedance
interval
REC-CTL when
rewriting
T2 to T5
RCDR2 (BISS/VASS S1 pulse)
RCDR3 (VISS/VASS L1 pulse)
RCDR4 (VISS/VASS S0 pulse)
RCDR5 (VISS/VASS L0 pulse)
Figure 26.62 Relationship between REC-CTL and RCDR2 to RCDR5 when Rewriting
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Section 26 Servo Circuits
26.13.11 Note on CTL Interrupt
After a reset, the CTL circuit is in the VISS discrimination input mode.
Depending on the CTL pin states, a false PB-CTL input pulse may be recognized and an interrupt
request generated. If the interrupt request will be enabled, first clear the CTL interrupt request
flag.
26.14
Frequency Dividers
26.14.1 Overview
On-chip frequency dividers are provided for the pulse signal picked up from the control track
during playback (the PB-CTL signal), and the pulse signal received from the capstan motor (CFG
signal). The CTL frequency divider generates a CTL divided control signal (DVCTL) from the
PB-CTL signal, for use in capstan phase control during high-speed search, for example. The CFG
frequency divider generates two divided CFG signals (DVCFG for speed control and DVCFG2 for
phase control) from the CFG signal. The DFG noise canceller is a circuit which considers signal
less than 2φ as noise and mask it.
26.14.2 CTL Frequency Divider
Block Diagram: Figure 26.63 shows a block diagram of the CTL frequency divider.
Internal bus
R/W
CTVC
R/W
CTVC
CEG
CEX
W
CTLR
CTL division register
(8 bits)
EXCTL
Edge
detector
↑, ↓
Down counter (8 bits)
PB-CTL↑
Figure 26.63 CTL Frequency Divider
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UDF
DVCTL
Section 26 Servo Circuits
Register Description
Register configuration
Table 26.22 shows the register configuration of the CTL frequency dividers.
Table 26.22
Register Configuration
Name
Abbrev.
DVCTL control register
CTVC
CTL frequency division register
CTLR
R/W
Size
Initial Value Address
R/W
Byte
Undefined
H'D098
W
Byte
H'00
H'D099
DVCTL Control Register (CTVC)
Bit :
Initial value :
R/W :
7
CEX
6
CEG
5
⎯
4
⎯
3
⎯
2
CFG
1
HSW
0
CTL
0
W
0
W
1
⎯
1
⎯
1
⎯
*
R
*
R
*
R
Note: * Undefined
CTVC consists of the external input signal selection bits and the flags which show the CFG,
HSW, and CTL levels.
Note: It has an undetermined value by a reset or in stand-by mode.
Bit 7⎯DVCTL Signal Generation Selection Bit (CEX): Selects which of the PB-CTL signal or
the external input signal is used to generate the DVCTL signal.
Bit 7
CEX
Description
0
Generates DVCTL signal with PB-CTL signal
1
Generates DVCTL signal with external input signal
(Initial value)
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Section 26 Servo Circuits
Bit 6⎯External Sync Signal Edge Selection Bit (CEG): Selects the edge of the external signal
at which the frequency division is made when the external signal was selected to generate DVCTL
signal.
Bit 6
CEG
Description
0
Rising edge
1
Falling edge
(Initial value)
Bits 5 to 3⎯Reserved: Cannot be modified and are always read as 1.
Bit 2⎯CFG Flag (CFG): Shows the CFG level.
Bit 2
CFG
Description
0
CFG is at low level
1
CFG is at high level
(Initial value)
Bit 1⎯HSW Flag (HSW): Shows the level of the HSW signal selected by the VFF/NFF bit of the
HSW mode register 2 (HSM2).
Bit 1
HSW
Description
0
HSW is at low level
1
HSW is at high level
(Initial value)
Bit 0⎯CTL Flag (CTL): Shows the CTL level.
Bit 0
CTL
Description
0
REC or PB-CTL is at low level
1
REC or PB-CTL is at high level
Rev.2.00 Jan. 15, 2007 page 718 of 1174
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(Initial value)
Section 26 Servo Circuits
CTL Frequency Division Register (CTLR)
Bit :
Initial value :
R/W :
7
CTL7
6
CTL6
5
CTL5
4
CTL4
3
CTL3
2
CTL2
1
CTL1
0
CTL0
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
CTLR is an 8-bit write-only register to set the frequency dividing value (N-1 if divided by N) for
PB-CTL. If a read is attempted, an undetermined value is read out.
PB-CTL is divided by N at its rising edge. If the register value is 0, no division operation is
performed, and the DVCTL signal with the same cycle with PB-CTL is output. It is initialized by
a reset or in stand-by mode.
Operation: During playback, control pulses recorded on the tape are picked up by the control
head and input to the CTL pin. The control pulse signal is amplified by a Schmitt amplifier,
reshaped, then input to the CTL frequency divider as the PB-CTL signal.
This circuit is employed when the control pulse (PB-CTL signal) is used for phase control of the
capstan motor. The divided signal is sent as the DVCTL signal to the capstan pha