SPANSION MB84SF6H6H6L2-70 3 stacked mcp (multi-chip package) flash & flash & fcram 128m (x16) burst flash memory & 128m (x16) page/burst mobile fcram Datasheet

TM
SPANSION MCP
Data Sheet
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50405-1E
3 Stacked MCP (Multi-Chip Package) FLASH & FLASH & FCRAM
CMOS
128M (×16) Burst FLASH MEMORY &
128M (×16) Burst FLASH MEMORY &
128M (×16) Page/Burst Mobile FCRAMTM
MB84SF6H6H6L2-70
■ FEATURES
• Power supply voltage
Flash _1 & 2: VCCf = 1.65 V to 1.95 V
FCARM: VCCr = 2.5 V to 3.1 V, VCCQr = 1.65 V to 1.95 V
• High performance
11 ns maximum Burst read access time, 56 ns maximum random access time (Flash_1 & Flash_2)
11 ns maximum Burst read access time, 70 ns maximum random access time (FCRAMTM)
(Continued)
■ PRODUCT LINEUP
Flash_1 & Flash_2
Supply Voltage (V)
VCCf_1 & 2* = 1.8 V
I/O Supply Voltage (V)
Max Latency Time (ns)
Synchronous/
Max Burst Access Time (ns)
Burst
Max OE Access Time (ns)
Max Address Access Time (ns)
Max CE Access Time (ns)
Asynchronous
Max OE Access Time (ns)
Max Page Access Time (ns)
+0.15V
–0.15V
VCCQr = 1.65 V to 1.95 V
71
11
11
56
56
11
—
FCRAM
VCCr* = 3.0 V
VCCQr = 1.65 V to 1.95 V
—
11
—
70
70
40
20
*: All of VCCf_1, VCCf_2 and VCCr must be the same level when either part is being accessed.
■ PACKAGE
115-ball plastic FBGA
BGA-115P-M03
+0.10V
–0.50V
MB84SF6H6H6L2-70
• Operating Temperature
–30 °C to +85 °C
• Package 115-ball BGA
— FLASH MEMORY_1 & FLASH MEMORY_2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
0.13 µm process technology
Single 1.8 volt read, program and erase (1.65 V to 1.95 V)
Simultaneous Read/Write operation (Dual Bank)
FlexBankTM *1
Bank A: 16Mbit (4 Kwords × 8 and 32 Kwords × 31)
Bank B: 48Mbit (32 Kwords × 96)
Bank C: 48Mbit (32 Kwords × 96)
Bank D: 16Mbit (4 Kwords × 8 and 32 Kwords × 31)
High Performance Burst frequency reach at 66MHz
Burst access times of 11 ns @ 30 pF at industrial temperature range
Asynchronous random access times of 56 ns (at 30 pF)
Programmable Burst Interface
Linear Burst: 8, 16, and 32 words with wrap-around
Minimum 100,000 program/erase cycles
Sector Erase Architecture
Eight 4 Kwords, two hundred fifty-four 32 Kwords sectors, eight 4 Kwords sectors.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
WP Input Pin (WP_1, WP_2)
At VIL, allows protection of "outermost" 4×4 K words on low, high end or both ends of boot sectors, regardless
of sector protection/unprotection status.
Accelerate Pin (ACC)
At VACC, increases program performance. ; all sectors locked when ACC = VIL
Embedded EraseTM *2 Algorithms
Automatically preprograms and erases the chip or any sector
Embedded ProgramTM *2 Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready Output (RY/BY)
In Synchronous Mode, indicates the status of the Burst read.
In Asynchronous Mode, indicates the status of the internal program and erase function.
Automatic sleep mode
When address remain stable, the device automatically switches itself to low power mode
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
Hardware reset pin (RESET)
Hardware method to reset the device for reading array data
Please refer to “MBM29BS12DH” Datasheet in deteiled function
(Continued)
MB84SF6H6H6L2-70
(Continued)
— FCRAMTM *3
• Power dissipation
Operating : 35 mA Max
Standby
: 300 µA Max (no CLK)
• Various Partial Power Down mode
Sleep
: 10 µA Max
16M Partial : 120 µA Max
32M Partial : 150 µA Max
• Power down control by CE2r
• 8 words Page Read Access Capability
• Burst Read/Write Access Capability
• Byte write control: LB(DQ7 to DQ0), UB(DQ15 to DQ8)
*1: FlexBankTM is a trademark of Fujitsu Limited, Japan.
*2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
*3: FCRAMTM is a trademark of Fujitsu Limited, Japan.
3
MB84SF6H6H6L2-70
■ PIN ASSIGNMENT
(Top View)
Marking side
A10
B10
C10
D10
E10
F10
G10
H10
J10
K10
L10
M10
N10
P10
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C..
N.C.
N.C.
A9
B9
C9
D9
E9
F9
G9
H9
J9
K9
L9
M9
N9
P9
N.C.
N.C.
N.C.
A15
A21
A22
A16
N.C.
VSS
N.C.
N.C.
N.C.
N.C.
C8
D8
E8
F8
G8
H8
J8
K8
L8
M8
N.C.
A11
A12
A13
A14
N.C.
DQ15
DQ7
DQ14
N.C.
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
N.C.
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
N.C.
C6
D6
E6
F6
G6
H6
J6
K6
L6
M6
N.C.
WE
CE2r
A20
WP_2
N.C.
DQ4
VCCQr
N.C.
N.C.
C5
D5
E5
F5
G5
H5
J5
K5
L5
M5
CEf_2
ACC
RESET
RY/BY
N.C.
VCCr
DQ3
VCCf_1
DQ11
VCCf_2
C4
D4
E4
F4
G4
H4
J4
K4
L4
M4
CLK
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
VSS
N.C.
C3
D3
E3
F3
G3
H3
J3
K3
L3
M3
N.C.
A7
A6
A5
A4
VSS
OE
DQ0
DQ8
N.C.
A2
B2
C2
D2
E2
F2
G2
H2
J2
K2
L2
M2
N2
P2
N.C.
N.C.
ADV
WP_1
A3
A2
A1
A0
CEf_1
CE1r
N.C.
N.C.
N.C.
N.C.
A1
B1
D1
E1
F1
G1
H1
J1
K1
L1
M1
N1
P1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
(BGA-115P-M03)
4
MB84SF6H6H6L2-70
■ PIN DESCRIPTION
Pin name
Input/
Output
A22 to A0
I
DQ15 to DQ0
I/O
CEf_1
I
Chip Enable (Flash_1)
CEf_2
I
Chip Enable (Flash_2)
CE1r
I
Chip Enable (FCRAM)
CE2r
I
Chip Enable (FCRAM)
OE
I
Output Enable (Common)
WE
I
Write Enable (Common)
RY/BY
O
Ready Output. (In asynchronous mode, RY/BY Output) / (Low Active)
(Flash_1 & Flash_2) & Wait Signal Output (FCRAM)
UB
I
Upper Byte Control (FCRAM)
LB
I
Lower Byte Control (FCRAM)
ADV
I
Address Data Valid (Common)
CLK
I
CLK Input (Common)
RESET
I
Hardware Reset Pin/Sector Protection Unlock (Flash_1& Flash_2)
WP_1
I
Write Protect (Flash_1)
WP_2
I
Write Protect (Flash_2)
ACC
I
Program Acceleration (Flash_1&2)
N.C.
—
VSS
Power
Device Ground (Common)
VCCf_1
Power
Device Power Supply (Flash_1)
VCCf_2
Power
Device Power Supply (Flash_2)
VCCr
Power
Device Power Supply (FCRAM)
VCCQr
Power
I/O Power Supply (FCRAM)
Description
Address Inputs (Common)
Data Inputs/Outputs (Common)
No Internal Connection
5
MB84SF6H6H6L2-70
■ BLOCK DIAGRAM
VCCf_1
CEf_1
VSS
CEf_1
WP_1
WP
OE
OE
WE
WE
CLK
CLK
ADV
ADV
RY/BY
RY/BY
RESET
RESET
128 Mbit Burst
Flash Memory
ACC
DQ15 to DQ0
A22 to A0
VCCf_2
CEf_2
CEf_2
WP_2
WP
VSS
RY/BY
RESET
OE
WE
CLK
ADV
128 Mbit Burst
Flash Memory
DQ15 to DQ0
A22 to A0
A22 to A0
VCCr
CE1r
CE1r
CE2r
CE2r
UB
UB
VCCQr
VSS
WAIT
WAIT
LB
LB
OE
WE
CLK
ADV
A22 to A0
6
128 Mbit Burst
FCRAM
DQ15 to DQ0
DQ15 to DQ0
MB84SF6H6H6L2-70
■ DEVICE BUS OPERATIONS
CE2r
OE
WE
LB
UB
A22 to A0
ADV
RESET
WP_1
WP_2
ACC
RY/BY(WAIT)
H
H
H
X
X
X
X
X
High-Z High-Z
X
H
X
X
X
High
-Z
Output
Disable*1
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X*3
X
X
High-Z High-Z
X
X
X
H
X
X
X
High
-Z
L
H
H
H
L
H
X
X
Addr
In
DOUT
DOUT
L
H
X
X
X
High
-Z
H
H
H
L
X
X
Addr
In
DIN
DIN
L
H
X*5 X*5 H*5
High
-Z
H
H
H
X
X
Addr
In
DIN
DIN
H
X*5 X*5 H*5
High
-Z
Flash_1 or 2
Asynchronous
Read Addresses
Latched*2
Flash_1or 2
Write - WE
address
latched*4
Flash_1or 2
Write - ADV
address
latched*4
FCRAM NO
Read
FCRAM Read
(Upper Byte)
FCRAM Read
(Lower Byte)
FCRAM Read
(Word)
FCRAM Page
Read
FCRAM No
Write
FCRAM Write
(Upper Byte)
FCRAM Write
(Lower Byte)
FCRAM Write
(Word)
Flash_1 Boot
Sector Write
Protection*5
Flash_2 Boot
Sector Write
Protection*5
Flash_1 &2 All
Sector Write
Protection*5
Flash_1 &
Flash_2
RESET
FCRAM
Power Down*8
DQ15 to DQ8
CE1r
H
DQ7 to DQ0
CEf_2
Full Standby
Operation
CEf_1
• Asynchronous Operation
H
L
L
H
H
L
L
H
H
L
H
H
L
H
L
H
H
H
Valid High-Z High-Z
*6
X
X
X
X
High
-Z
H
H
L
H
L
H
H
L
Valid High-Z Output
Valid
*6
X
X
X
X
High
-Z
H
H
L
H
L
H
L
H
High-Z
Valid Output
Valid
*6
X
X
X
X
High
-Z
H
H
L
H
L
H
L
L
Output
Valid Output
Valid
Valid
*6
X
X
X
X
High
-Z
H
H
L
H
L
H
*6
X
X
X
X
High
-Z
H
H
L
H*9
H*9
L
H
H
Valid Invalid Invalid
*6
X
X
X
X
High
-Z
H
H
L
H*9
H*9
L
H
L
Valid Invalid
Input
Valid
*6
X
X
X
X
High
-Z
H
H
L
H*9
H*9
L
L
H
Valid
Input
Valid
Invalid
*6
X
X
X
X
High
-Z
H
H
L
H*9
H*9
L
L
L
Valid
Input
Valid
Input
Valid
*6
X
X
X
X
High
-Z
X
X
X
X
X
X
X
X
X
X
X
X
H
L*5
X
X
High
-Z
X
X
X
X
X
X
X
X
X
X
X
X
H
X
L*5
X
High
-Z
X
X
H
H
X
X
X
X
X
X
X
X
H
X
X
L*5
High
-Z
X
X
H
H
X
X
X
X
X
High-Z High-Z
X
L
X
X
X
High
-Z
X
X
X
L
X
X
X
X
X
High-Z High-Z
X
X
X
X
X
High
-Z
L/H L/H Valid
*7
*7
(Continued)
7
MB84SF6H6H6L2-70
(Continued)
Legend : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance.
See “• DC Characteristics” in “■ ELECTRICAL CHARACTERISTICS” for voltage levels.
*1 : FCRAM Output Disable Mode(CE1r = “L“)Should not be kept this logic condition longer than 4 ms.
Please contact local FUJITSU representative for the relaxation of 4 ms limitation.
*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3 : Can be either VIL or VIH but must be valid before Read or Write.
*4 : Write Operation: at asynchronous mode, addresses are latched on the last falling edge of
WE pulse while ADV is held low or rising edge of ADV pulse whichever comes first.
Data is latched on the 1st rising edge of WE.
*5 : At WP=VIL, SA0 to SA3 and SA266 to SA269 are protected. At ACC=VIL, all sectors are protected.
*6 : "L" for address pass through and "H" for address latch on the rising edge of ADV.
*7 : Output is either Valid or High-Z depending on the level of UB and LB input.
*8 : Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
Data retention depends on the selection of Partial Size.
Refer to “2. Functional Description • Power Down” in “■ 128M FCRAM CHARACTERISTICS for MCP” for the
details.
*9 : OE can be VIL during Write operation if the following conditions are satisfied;
(1) Write pulse is initiated by CE1r (refer to CE1r Controlled Write timing), or
cycle time of the previous operation cycle is satisfied.
(2) OE stays VIL during Write cycle.
8
MB84SF6H6H6L2-70
FCRAM
Advance
Burst Read to
Next
Address*2
FCRAM Burst
Read
Suspend*2
H
H
L
L
H
Addr
In
X
X
H
H
L
H
X
X
X
DOUT
DOUT
H
H
X
H
X
X
X
X
HIGHZ
H
H
X
H
X
X
Addr
In
DOUT
DOUT
H
H
H
H
X
X
X
H
H
H
L
X
X
Addr
In
DIN
DIN
H
H
H
X
X
Addr
In
DIN
DIN
H
H
H
X
X
Addr
In
DIN
DIN
H/L
X
X
X
X
HIGHZ
HIGHZ
X
Valid
*7
HighZ*8
HighZ*8
H
L
L
H
H
L
L
H
L
L
X
X
H
H
H
H
L
H
H
X*5 X*5 X*6 X*6
High-Z High-Z
RY/BY(WAIT)
L
X
ACC
L
X
WP_2
H
H
WP_1
H
X
RESET
L
H
H
X
X
X
High
-Z
H
H
X
X
X
High
-Z
X
H
X
X
X
H
X
X
X
X
X
X
ADV
H
H
CLK*1
H
DQ15 to DQ8
L
DQ7 to DQ0
H
A22 to A0
H
UB
L
LB
L
WE
H
OE
FCRAM Start
Address*2
Latch
H
CE2r
Flash_1 or 2
Synchronous
Write - WE
address
latched*12
Flash_1 or 2
Synchronous
Write - CLK
address
latched*12
Flash_1 or 2
Synchronous
Write -ADV
address
latched *12
Flash_1& 2
Terminate
current Burst
read via
RESET
L
CE1r
Flash_1 or 2
Burst
Suspend
CEf_2
Flash_1 or 2
Load Starting
Burst Address
(CLK latch)*3
Flash_1 or 2
Advance Burst
to next
address with
appropriate
Data
presented on
the Data Bus*3
Flash_1 or 2
Terminate
current Burst
read cycle
Flash_1 or 2
Terminate
current Burst
read cycle and
start new
Burst read
cycle
CEf_1
Operation
• Synchronous Operation
*9
*9
*9
*9
High
-Z
High
-Z
High
-Z
X
H
H
H/L
L
H
X*4 X*4 H*4
L
H
X*4 X*4 H*4
High
-Z
H
X*4 X*4 H*4
High
-Z
*9
High
-Z
L
X
X
X
High
-Z
X
X
X
X
High
-Z*14
H
X
X
X
X
Output
Valid
H
X
X
X
X
High
-Z*15
X
*9
H
H
H
H
L
L
H
H
L
H
H
H
X*6 X*6
X
X*6 X*6
X
Output Output
Valid
Valid
*10
*10
*9
High-Z High-Z
*9
(Continued)
9
MB84SF6H6H6L2-70
A22 to A0
DQ7 to DQ0
DQ15 to DQ8
X*6
X*6
X
Input
Valid
*11
Input
Valid
*11
H
H
L
H
H
H*13
X*6
X*6
X
*9
Input
Invalid
Input
Invali
d
*9
RY/BY(WAIT)
UB
L*13
ACC
LB
H
WP_2
WE
H
WP_1
OE
L
RESET
CE2r
H
ADV
CE1r
H
CLK*1
CEf_2
FCRAM
Advance
Burst Write
to Next
Address*2
FCRAM
Burst Write
Suspend*2
FCRAM
Terminate
Burst Read
FCRAM
Terminate
Burst Write
CEf_1
Operation
(Continued)
H
X
X
X
X
High
-Z*16
H
X
X
X
X
High
-Z*15
H
H
H
L
H
X*6
X*6
X
HighZ
HighZ
X
H
X
X
X
X
High
-Z
H
H
H
H
L
X*6
X*6
X
HighZ
HighZ
X
H
X
X
X
X
High
-Z
Legend : L = VIL, H = VIH, X can be either VIL or VIH,
= positive edge,
= positive edge of Low pulse,
High-Z = High Impedance. See “• DC Characteristics” in “■ ELECTRICAL CHARACTERISTICS” for
voltage levels.
*1 : Default state is “X“ after power-up.
*2 : FCRAM Output Disable Mode(CE1r = “L“)Should not be kept this logic condition longer than 4 ms.
Please contact local FUJITSU representative for the relaxation of 4 ms limitation.
*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4 : At WP=VIL, SA0 to SA3 and SA266 to SA269 are protected. At ACC=VIL, all sectors are protected.
*5 : Can be either VIL or VIH except for the case the both of OE and WE are VIL.
It is prohibited to bring the both of OE and WE to VIL.
*6 : Can be either VIL or VIH but must be valid before Read or Write is determined.
And once UB and LB inputs are determined, it must not be changed until the end of burst.
*7 : Once valid address is determined, input address must not be changed during ADV=L.
In case A22, “H” must not be changed until end of burst.
*8 : If OE=L, output is either Invalid or High-Z depending on the level of UB and LB input. If WE=L,
Input is Invalid. If OE=WE=H, output is High-Z.
*9 : Valid clock edge shall be set on either positive or negative edge through CR (Configration Register) Set.
*10 : Output is either Valid or High-Z depending on the level of UB and LB input.
*11 : Input is either Valid or Invalid depending on the level of UB and LB input.
*12 : Write Operation: at synchronous mode, addresses are latched on the falling edge of WE while ADV is held low,
active edge of CLK while ADV is held low or rising edge of ADV whichever happens first.
Data is latched on the 1st rising edge of WE.
*13 : When device is operationg in "WE Single Clock Pulse Control" mode, WE is don't care once write operation
is determined by WE Low Pulse at the begginig of write access together with address latcing. Write suspend
feature is not supported in "WE Single Clock Pulse Control" mode.
*14 : Output is either High-Z or Invalid depending on the level of OE and WE input.
*15 : Keep the level from previous cycle except for suspending on last data. Refere to “2. Functional Description
• WAIT Output Function” in “■ 128M FCRAM CHARACTERISTICS for MCP” for the details.
*16 : WAIT output is driven in High level during write operation.
10
MB84SF6H6H6L2-70
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Storage Temperature
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins
except RESET, ACC *1 *2
VCCf_1/ VCCf_2 / VCCQr Supply *1
Unit
Min
Max
Tstg
–55
+125
°C
TA
–30
+85
°C
VCCf_1 +0.3
V
VCCf_2 +0.3
V
VCCQr +0.3
V
VIN, VOUT
VCCr Supply *1
Rating
–0.3
VCCr
–0.3
+3.6
V
VCCf_1, VCCf_2,
VCCQr
–0.3
+2.5
V
VACC
–0.5
+10.5
V
ACC *1,*3
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to –1.0 V for periods of up to 10 ns. Maximum DC voltage on input or I/O pins is VCCf_1 + 0.3 V or
VCCf_2 +0.3V or VCCQr + 0.2 V . During voltage transitions, input or I/O pins may overshoot to VCCf + 1.0 V or
VCCf_2 + 1.0 V or VCCQr + 1.0 V for periods of up to 5 ns.
*3 : Minimum DC input voltage on ACC pin is –0.5 V. During voltage transitions, ACC pin may undershoot VSS to
–2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - VCC) does not
exceed +9.0 V. Maximum DC input voltage on ACC pin is +10.5 V which may overshoot to +12.0 V for periods
of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Min
Max
Unit
Ambient Temperature
TA
–30
+85
°C
VCCr Supply Voltages
VCCr
+2.5
+3.1
V
VCCf_1, VCCf_2, VCCQr
+1.65
+1.95
V
VCCf/VCCQr Supply Voltages
Note : Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating conditionranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
11
MB84SF6H6H6L2-70
■ ELECTRICAL CHARACTERISTICS
• DC Characteristics
Parameter
Input Leakage Current
Output Leakage Current
Flash VCCf Current
(Standby)
(Flash_1 & Flash_2)
Flash_1 & 2 VCCf Current
(Standby, Reset)
(Flash_1 & Flash_2)
Flash_1 & 2 VCCf Current
(Automatic Sleep Mode)*3
(Flash_1 & Flash_2)
Flash VCCf Active Burst
Read Current
(Flash_1 or Flash_2)
Flash VCCf Active
Asynchronous Read
Current*1
(Flash_1 or Flash_2)
Flash VCCf Active Current *2
(Flash_1 or Flash_2)
Flash VCCf Active Current
(Read-While-Program ) *4
(Flash_1 or Flash_2)
Flash VCCf Active Current
(Read-While-Erase) *4
(Flash_1 or Flash_2)
FCRAM VCCr Power Down
Current*5
FCRAM VCCr Standby
Current*5, *8
Symbol
ILI
ILO
Conditions
Min
–1.0
–1.0
VIN = VSS to VCCf, VCCQr
VOUT = VSS to VCCf, VCCQr
Value
Typ
Max
—
+1.0
—
+1.0
Unit
µA
µA
ISB1f
CEf = RESET = VCCf ± 0.2 V *9
—
1*7
50*7
µA
ISB2f
RESET = VSS ± 0.2 V, CLK = VIL *9
—
1*7
50*7
µA
ISB3f
VCCf = VCCf Max, CEf = VSS ± 0.2 V,
RESET = VCCf ± 0.2 V,
VIN = VCCf ±0.2 V or VSS ± 0.2 V *9
—
1*7
50*7
µA
ICC1f
CEf = VIL, OE = VIH, WE = VIH, 66 MHz *9
—
15
30
mA
20
30
ICC2f
CEf = VIL, OE = VIH, WE = VIH *9
10
15
10 MHz
—
5 MHz
mA
ICC3f
CEf = VIL, OE = VIH, VPP = VIH *9
—
15
40
mA
ICC4f
CEf = VIL, OE = VIH *9
—
25
60
mA
ICC5f
CEf = VIL, OE = VIH *9
—
25
60
mA
—
—
—
—
10
120
µA
µA
—
—
150
µA
—
—
1.5
mA
—
—
300
µA
—
—
350
µA
IDDPSr
IDDP8r
VCCr = VCCr Max,
Sleep
VCCQr = VCCQr Max,
16M Partial
VIN = VIH or VIL,
IDDP16r
32M Partial
CE2r ≤ 0.2 V
VCCr = VCCr Max,
VCCQr = VCCQr Max,
ISBSr
VIN (including CLK) = VIH or VIL ,
CE1r = CE2r = VIH
VCCr = VCCr Max,
VCCQr = VCCQr Max,
ISB1r VIN (including CLK) ≤ 0.2 V or
VIN (including CLK) ≥ VCCQr – 0.2 V,
CE1r = CE2r ≥ VCCQr – 0.2 V
VCCQr = VCCQr Max, tCK = Min,
ISB2r VIN ≤ 0.2 V or VIN ≥ VCCQr – 0.2 V,
CE1r = CE2r ≥ VCCQr – 0.2 V
(Continued)
12
MB84SF6H6H6L2-70
(Continued)
Parameter
Symbol
ICC1r
FCRAM VCCr Active
Current *5, *8
ICC2r
FCRAM VCCr Page Read
Current *5, *8
ICC3r
FCRAM VCCr Burst Access
Current *5, *8
ICC4r
Conditions
Min
VCCr = VCCr Max,
tRC / tWC = Min
VCCQr = VCCQr Max,
VIN = VIH or VIL,
CE1r = VIL and CE2r = VIH, tRC / tWC = 1 µs
IOUT = 0 mA
VCCr = VCCr Max,
VCCQr = VCCQr Max, VIN = VIH or VIL,
CE1r = VIL and CE2r = VIH,
IOUT= 0 mA, tPRC = Min
VCCr = VCCr Max,
VCCQr = VCCQr Max, VIN = VIH or VIL,
CE1r = VIL and CE2r = VIH,
tCK = tCK Min, BL = Continuous, IOUT = 0 mA
Value
Typ Max
—
—
35
mA
—
—
5
mA
—
—
15
mA
—
—
30
mA
Input Low Level
VIL
—
–0.3
—
Input High Level
VIH
—
VCC –
0.4 *6
—
Output Low Voltage Level
VOLf
IOL = 0.1 mA
VOLr
IOL = 1.0 mA
VOHf
IOH = – 0.1 mA
VOHr
VCCQr = VCCQr Min,
IOH = – 0.5 mA
Output High Voltage Level
Voltage for ACC Program
Acceleration*10
VACC
Unit
VCC ×
0.2 *6
VCC +
0.2 *6
V
V
Flash_1 or
Flash_2
FCRAM
Flash_1 or
Flash_2
—
—
0.1
V
—
VCCf –
0.1
—
0.4
V
—
—
V
FCRAM
1.4
—
—
V
8.5
—
9.5
V
—
*1 : The ICC current listed includes both the DC operating current and the frequency dependent component.
*2 : ICC active while Embedded Algorithm (program or erase) is in progress.
*3 : Automatic sleep mode enables the low power mode when address remains stable for tACC + 60 ns.
*4 : Embedded Alogorithm (program or erase) is in progress. (@5 MHz)
*5 : FCRAM DC Current is measured after following POWER-UP timing.
*6 : VCC means VCCf_1 or VCCf_2 or VCCQr.
*7 : Actual Standby Current is twice of what is indicated in the table, due to two Flash chips embedment withn one
device.
*8 : IOUT depemds on the output load comditions.
*9 : CEf means CEf_1 or CEf_2.
*10 : Applicable for only VCCf_1 or VCCf_2.
13
MB84SF6H6H6L2-70
• AC Characteristics
• CE Timing
Parameter
Symbol
JEDEC
Standard
CE Recover Time
—
tCCR
CEf Hold Time
—
CE1r High to WE Invalid time for
Standby Entry
—
Condition
Value
Max
—
0
—
ns
tCHOLD
—
3
—
ns
tCHWX
—
10
—
ns
• Timing Diagram for alternating RAM to Flash
CEf_1 or
CEf_2
tCCR
tCCR
CE1r
WE
tCHWX
tCCR
tCHOLD
tCCR
CE2r
• NOR Flash_1&2 Characteristics
Please refer to “■ 128M BURST FLASH MEMORY CARACTERISTICS for MCP”.
• FCRAM Characteristics
Please refer to “■ 128M FCRAM CHARACTERISTICS for MCP”.
14
Unit
Min
MB84SF6H6H6L2-70
■ 128M BURST FLASH MEMORY CHARACTERISTICS for MCP
SA71 : 64KB
SA72 : 64KB
SA73 : 64KB
SA74 : 64KB
SA75 : 64KB
SA76 : 64KB
SA77 : 64KB
SA78 : 64KB
SA79 : 64KB
SA80 : 64KB
SA81 : 64KB
SA82 : 64KB
SA83 : 64KB
SA84 : 64KB
SA85 : 64KB
SA86 : 64KB
SA87 : 64KB
SA88 : 64KB
SA89 : 64KB
SA90 : 64KB
SA91 : 64KB
SA92 : 64KB
SA93 : 64KB
SA94 : 64KB
SA95 : 64KB
SA96 : 64KB
SA97 : 64KB
SA98 : 64KB
SA99 : 64KB
SA100: 64KB
SA101: 64KB
SA102: 64KB
SA103: 64KB
SA104: 64KB
SA105: 64KB
SA106: 64KB
SA107: 64KB
SA108: 64KB
SA109: 64KB
SA110: 64KB
SA111: 64KB
SA112: 64KB
SA113: 64KB
SA114: 64KB
SA115: 64KB
SA116: 64KB
SA117: 64KB
SA118: 64KB
SA119: 64KB
SA120: 64KB
SA121: 64KB
SA122: 64KB
SA123: 64KB
SA124: 64KB
SA125: 64KB
SA126: 64KB
SA127: 64KB
SA128: 64KB
SA129: 64KB
SA130: 64KB
SA131: 64KB
SA132: 64KB
SA133: 64KB
SA134: 64KB
200000h
208000h
210000h
218000h
220000h
228000h
230000h
238000h
240000h
248000h
250000h
258000h
260000h
268000h
270000h
278000h
280000h
288000h
290000h
298000h
2A0000h
2A8000h
2B0000h
2B8000h
2C0000h
2C8000h
2D0000h
2D8000h
2E0000h
2E8000h
2F0000h
2F8000h
300000h
308000h
310000h
318000h
320000h
328000h
330000h
338000h
340000h
348000h
350000h
358000h
360000h
368000h
370000h
378000h
380000h
388000h
390000h
398000h
3A0000h
3A8000h
3B0000h
3B8000h
3C0000h
3C8000h
3D0000h
3D8000h
3E0000h
3E8000h
3F0000h
3F8000h
3FFFFFh
SA135: 64KB
SA136: 64KB
SA137: 64KB
SA138: 64KB
SA139: 64KB
SA140: 64KB
SA141: 64KB
SA142: 64KB
SA143: 64KB
SA144: 64KB
SA145: 64KB
SA146: 64KB
SA147: 64KB
SA148: 64KB
SA149: 64KB
SA150: 64KB
SA151: 64KB
SA152: 64KB
SA153: 64KB
SA154: 64KB
SA155: 64KB
SA156: 64KB
SA157: 64KB
SA158: 64KB
SA159: 64KB
SA160: 64KB
SA161: 64KB
SA162: 64KB
SA163: 64KB
SA164: 64KB
SA165: 64KB
SA166: 64KB
SA167: 64KB
SA168: 64KB
SA169: 64KB
SA170: 64KB
SA171: 64KB
SA172: 64KB
SA173: 64KB
SA174: 64KB
SA175: 64KB
SA176: 64KB
SA177: 64KB
SA178: 64KB
SA179: 64KB
SA170: 64KB
SA181: 64KB
SA182: 64KB
SA183: 64KB
SA184: 64KB
SA185: 64KB
SA186: 64KB
SA187: 64KB
SA188: 64KB
SA189: 64KB
SA190: 64KB
SA191: 64KB
SA192: 64KB
SA193: 64KB
SA194: 64KB
SA195: 64KB
SA196: 64KB
SA197: 64KB
SA198: 64KB
400000h
408000h
410000h
418000h
420000h
428000h
430000h
438000h
440000h
448000h
450000h
458000h
460000h
468000h
470000h
478000h
480000h
488000h
490000h
498000h
4A0000h
4A8000h
4B0000h
4B8000h
4C0000h
4C8000h
4D0000h
4D8000h
4E0000h
4E8000h
4F0000h
4F8000h
500000h
508000h
510000h
518000h
520000h
528000h
530000h
538000h
540000h
548000h
550000h
558000h
560000h
568000h
570000h
578000h
580000h
588000h
590000h
598000h
5A0000h
5A8000h
5B0000h
5B8000h
5C0000h
5C8000h
5D0000h
5D8000h
5E0000h
5E8000h
5F0000h
5F8000h
5FFFFFh
BANK C
000000h
001000h
002000h
003000h
004000h
005000h
006000h
007000h
008000h
010000h
018000h
020000h
028000h
030000h
038000h
040000h
048000h
050000h
058000h
060000h
068000h
070000h
078000h
080000h
088000h
090000h
098000h
0A0000h
0A8000h
0B0000h
0B8000h
0C0000h
0C8000h
0D0000h
0D8000h
0E0000h
0E8000h
0F0000h
0F8000h
100000h
108000h
110000h
118000h
120000h
128000h
130000h
138000h
140000h
148000h
150000h
158000h
160000h
168000h
170000h
178000h
180000h
188000h
190000h
198000h
1A0000h
1A8000h
1B0000h
1B8000h
1C0000h
1C8000h
1D0000h
1D8000h
1E0000h
1E8000h
1F0000h
1F8000h
1FFFFFh
BANK C
: 8KB
: 8KB
: 8KB
: 8KB
: 8KB
: 8KB
: 8KB
: 8KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
: 64KB
BANK B
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
BANK D
BANK B
BANK A
1. Flexible Sector-erase Architecture on Flash Memory
• Sixteen 4K words, and one hundred twenty-six 32K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
SA199: 64KB
SA200: 64KB
SA201: 64KB
SA202: 64KB
SA203: 64KB
SA204: 64KB
SA205: 64KB
SA206: 64KB
SA207: 64KB
SA208: 64KB
SA209: 64KB
SA210: 64KB
SA211: 64KB
SA212: 64KB
SA213: 64KB
SA214: 64KB
SA215: 64KB
SA216: 64KB
SA217: 64KB
SA218: 64KB
SA219: 64KB
SA220: 64KB
SA221: 64KB
SA222: 64KB
SA223: 64KB
SA224: 64KB
SA225: 64KB
SA226: 64KB
SA227: 64KB
SA228: 64KB
SA229: 64KB
SA230: 64KB
SA231: 64KB
SA232: 64KB
SA233: 64KB
SA234: 64KB
SA235: 64KB
SA236: 64KB
SA237: 64KB
SA238: 64KB
SA239: 64KB
SA240: 64KB
SA241: 64KB
SA242: 64KB
SA243: 64KB
SA244: 64KB
SA245: 64KB
SA246: 64KB
SA247: 64KB
SA248: 64KB
SA249: 64KB
SA250: 64KB
SA251: 64KB
SA252: 64KB
SA253: 64KB
SA254: 64KB
SA255: 64KB
SA256: 64KB
SA257: 64KB
SA258: 64KB
SA259: 64KB
SA260: 64KB
SA261: 64KB
SA262: 8KB
SA263: 8KB
SA264: 8KB
SA265: 8KB
SA266: 8KB
SA267: 8KB
SA268: 8KB
SA269: 8KB
600000h
608000h
610000h
618000h
620000h
628000h
630000h
638000h
640000h
648000h
650000h
658000h
660000h
668000h
670000h
678000h
680000h
688000h
690000h
698000h
6A0000h
6A8000h
6B0000h
6B8000h
6C0000h
6C8000h
6D0000h
6D8000h
6E0000h
6E8000h
6F0000h
6F8000h
700000h
708000h
710000h
718000h
720000h
728000h
730000h
738000h
740000h
748000h
750000h
758000h
760000h
768000h
770000h
778000h
780000h
788000h
790000h
798000h
7A0000h
7A8000h
7B0000h
7B8000h
7C0000h
7C8000h
7D0000h
7D8000h
7E0000h
7E8000h
7F0000h
7F8000h
7F9000h
7FA000h
7FB000h
7FC000h
7FD000h
7FE000h
7FF000h
7FFFFFh
Sector Architecture
15
MB84SF6H6H6L2-70
• FlexBankTM Architecture
Bank 1
Bank
Splits
Volume
Combination
Bank 2
Volume
Combination
1
16 Mbit
Bank A
112Mbit
Remember (Bank B, C, D)
2
48 Mbit
Bank B
96 Mbit
Remember (Bank A, C, D)
3
48 Mbit
Bank C
96 Mbit
Remember (Bank A, B, D)
4
16 Mbit
Bank D
112Mbit
Remember (Bank A, B, C)
• Simultaneous Operation
Case
Bank 1 Status
Bank 2 Status
1
Read mode
Read mode
2
Read mode
Autoselect mode
3
Read mode
Program mode
4
Read mode
Erase mode
5
Autoselect mode
Read mode
6
Program mode
Read mode
7
Erase mode
Read mode
Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank
consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) meant to specify each of the
Banks.
16
MB84SF6H6H6L2-70
• Sector Address Tables (Bank A)
Sector Address
Bank
Sector
Bank A
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank Address
A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
0
0
0
0 0 0 0 0 0 0 0
0
0
0
0 0 0 0 0 0 0 1
0
0
0
0 0 0 0 0 0 1 0
0
0
0
0 0 0 0 0 0 1 1
0
0
0
0 0 0 0 0 1 0 0
0
0
0
0 0 0 0 0 1 0 1
0
0
0
0 0 0 0 0 1 1 0
0
0
0
0 0 0 0 0 1 1 1
0
0
0
0 0 0 0 1 X X X
0
0
0
0 0 0 1 0 X X X
0
0
0
0 0 0 1 1 X X X
0
0
0
0 0 1 0 0 X X X
0
0
0
0 0 1 0 1 X X X
0
0
0
0 0 1 1 0 X X X
0
0
0
0 0 1 1 1 X X X
0
0
0
0 1 0 0 0 X X X
0
0
0
0 1 0 0 1 X X X
0
0
0
0 1 0 1 0 X X X
0
0
0
0 1 0 1 1 X X X
0
0
0
0 1 1 0 0 X X X
0
0
0
0 1 1 0 1 X X X
0
0
0
0 1 1 1 0 X X X
0
0
0
0 1 1 1 1 X X X
0
0
0
1 0 0 0 0 X X X
0
0
0
1 0 0 0 1 X X X
0
0
0
1 0 0 1 0 X X X
0
0
0
1 0 0 1 1 X X X
0
0
0
1 0 1 0 0 X X X
0
0
0
1 0 1 0 1 X X X
0
0
0
1 0 1 1 0 X X X
0
0
0
1 0 1 1 1 X X X
0
0
0
1 1 0 0 0 X X X
0
0
0
1 1 0 0 1 X X X
0
0
0
1 1 0 1 0 X X X
0
0
0
1 1 0 1 1 X X X
0
0
0
1 1 1 0 0 X X X
0
0
0
1 1 1 0 1 X X X
0
0
0
1 1 1 1 0 X X X
0
0
0
1 1 1 1 1 X X X
Sector Size
(Kwords)
(× 16)
Address Range
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 06FFFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
17
MB84SF6H6H6L2-70
• Sector Address Tables (Bank B)
Sector Address
Bank
Sector
Bank B
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
Bank Address
A22 A21 A20
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
A18
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
A17
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
A16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Sector
Size
(Kwords)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
200000h to 207FFFh
208000h to 20FFFFh
210000h to 217FFFh
218000h to 21FFFFh
220000h to 227FFFh
228000h to 22FFFFh
230000h to 237FFFh
(Continued)
18
MB84SF6H6H6L2-70
Sector Address
Bank
Sector
Bank B
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
Bank Address
A22 A21 A20
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
A19
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A18
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
A17
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
A16
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A15
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Sector
Size
(Kwords)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
238000h to 23FFFFh
240000h to 247FFFh
248000h to 24FFFFh
250000h to 257FFFh
258000h to 25FFFFh
260000h to 267FFFh
268000h to 26FFFFh
270000h to 277FFFh
278000h to 27FFFFh
280000h to 287FFFh
288000h to 28FFFFh
290000h to 297FFFh
298000h to 29FFFFh
2A0000h to 2A7FFFh
2A8000h to 2AFFFFh
2B0000h to 2B7FFFh
2B8000h to 2BFFFFh
2C0000h to 2C7FFFh
2C8000h to 2CFFFFh
2D0000h to 2D7FFFh
2D8000h to 2DFFFFh
2E0000h to 2E7FFFh
2E8000h to 2EFFFFh
2F0000h to 2F7FFFh
2F8000h to 2FFFFFh
300000h to 307FFFh
308000h to 30FFFFh
310000h to 317FFFh
318000h to 31FFFFh
320000h to 327FFFh
328000h to 32FFFFh
330000h to 337FFFh
338000h to 33FFFFh
340000h to 347FFFh
348000h to 34FFFFh
350000h to 357FFFh
358000h to 35FFFFh
360000h to 367FFFh
368000h to 36FFFFh
(Continued)
19
MB84SF6H6H6L2-70
(Continued)
Sector Address
20
Bank
Sector
Bank B
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
Bank Address
A22 A21 A20
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
A19
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A17
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Sector
Size
(Kwords)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
370000h to 377FFFh
378000h to 37FFFFh
380000h to 387FFFh
388000h to 38FFFFh
390000h to 397FFFh
398000h to 39FFFFh
3A0000h to 3A7FFFh
3A8000h to 3AFFFFh
3B0000h to 3B7FFFh
3B8000h to 3BFFFFh
3C0000h to 3C7FFFh
3C8000h to 3CFFFFh
3D0000h to 3D7FFFh
3D8000h to 3DFFFFh
3E0000h to 3E7FFFh
3E8000h to 3EFFFFh
3F0000h to 3F7FFFh
3F8000h to 3FFFFFh
MB84SF6H6H6L2-70
• Sector Address Tables (Bank C)
Sector Address
Bank
Sector
Bank C
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
SA159
SA160
SA161
SA162
SA163
SA164
SA165
SA166
SA167
SA168
SA169
SA170
SA171
SA172
SA173
Bank Address
A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
1
0
0
0 0 0 0 0 X X X
1
0
0
0 0 0 0 1 X X X
1
0
0
0 0 0 1 0 X X X
1
0
0
0 0 0 1 1 X X X
1
0
0
0 0 1 0 0 X X X
1
0
0
0 0 1 0 1 X X X
1
0
0
0 0 1 1 0 X X X
1
0
0
0 0 1 1 1 X X X
1
0
0
0 1 0 0 0 X X X
1
0
0
0 1 0 0 1 X X X
1
0
0
0 1 0 1 0 X X X
1
0
0
0 1 0 1 1 X X X
1
0
0
0 1 1 0 0 X X X
1
0
0
0 1 1 0 1 X X X
1
0
0
0 1 1 1 0 X X X
1
0
0
0 1 1 1 1 X X X
1
0
0
1 0 0 0 0 X X X
1
0
0
1 0 0 0 1 X X X
1
0
0
1 0 0 1 0 X X X
1
0
0
1 0 0 1 1 X X X
1
0
0
1 0 1 0 0 X X X
1
0
0
1 0 1 0 1 X X X
1
0
0
1 0 1 1 0 X X X
1
0
0
1 0 1 1 1 X X X
1
0
0
1 1 0 0 0 X X X
1
0
0
1 1 0 0 1 X X X
1
0
0
1 1 0 1 0 X X X
1
0
0
1 1 0 1 1 X X X
1
0
0
1 1 1 0 0 X X X
1
0
0
1 1 1 0 1 X X X
1
0
0
1 1 1 1 0 X X X
1
0
0
1 1 1 1 1 X X X
1
0
1
0 0 0 0 0 X X X
1
0
1
0 0 0 0 1 X X X
1
0
1
0 0 0 1 0 X X X
1
0
1
0 0 0 1 1 X X X
1
0
1
0 0 1 0 0 X X X
1
0
1
0 0 1 0 1 X X X
1
0
1
0 0 1 1 0 X X X
Sector Size
(Kwords)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
400000h to 407FFFh
408000h to 40FFFFh
410000h to 417FFFh
418000h to 41FFFFh
420000h to 427FFFh
428000h to 42FFFFh
430000h to 437FFFh
438000h to 43FFFFh
440000h to 447FFFh
448000h to 44FFFFh
450000h to 457FFFh
458000h to 45FFFFh
460000h to 467FFFh
468000h to 46FFFFh
470000h to 477FFFh
478000h to 47FFFFh
480000h to 487FFFh
488000h to 48FFFFh
490000h to 497FFFh
498000h to 49FFFFh
4A0000h to 4A7FFFh
4A8000h to 4AFFFFh
4B0000h to 4B7FFFh
4B8000h to 4BFFFFh
4C0000h to 4C7FFFh
4C8000h to 4CFFFFh
4D0000h to 4D7FFFh
4D8000h to 4DFFFFh
4E0000h to 4E7FFFh
4E8000h to 4EFFFFh
4F0000h to 4F7FFFh
4F8000h to 4FFFFFh
500000h to 507FFFh
508000h to 50FFFFh
510000h to 517FFFh
518000h to 51FFFFh
520000h to 527FFFh
528000h to 52FFFFh
530000h to 537FFFh
(Continued)
21
MB84SF6H6H6L2-70
Sector Address
22
Bank
Sector
Bank C
SA174
SA175
SA176
SA177
SA178
SA179
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
SA191
SA192
SA193
SA194
SA195
SA196
SA197
SA198
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
SA211
SA212
Bank Address
A22 A21 A20
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
A19 A18 A17 A16 A15 A14 A13 A12
0 0 1 1 1 X X X
0 1 0 0 0 X X X
0 1 0 0 1 X X X
0 1 0 1 0 X X X
0 1 0 1 1 X X X
0 1 1 0 0 X X X
0 1 1 0 1 X X X
0 1 1 1 0 X X X
0 1 1 1 1 X X X
1 0 0 0 0 X X X
1 0 0 0 1 X X X
1 0 0 1 0 X X X
1 0 0 1 1 X X X
1 0 1 0 0 X X X
1 0 1 0 1 X X X
1 0 1 1 0 X X X
1 0 1 1 1 X X X
1 1 0 0 0 X X X
1 1 0 0 1 X X X
1 1 0 1 0 X X X
1 1 0 1 1 X X X
1 1 1 0 0 X X X
1 1 1 0 1 X X X
1 1 1 1 0 X X X
1 1 1 1 1 X X X
0 0 0 0 0 X X X
0 0 0 0 1 X X X
0 0 0 1 0 X X X
0 0 0 1 1 X X X
0 0 1 0 0 X X X
0 0 1 0 1 X X X
0 0 1 1 0 X X X
0 0 1 1 1 X X X
0 1 0 0 0 X X X
0 1 0 0 1 X X X
0 1 0 1 0 X X X
0 1 0 1 1 X X X
0 1 1 0 0 X X X
0 1 1 0 1 X X X
Sector Size
(Kwords)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
538000h to 53FFFFh
540000h to 547FFFh
548000h to 54FFFFh
550000h to 557FFFh
558000h to 55FFFFh
560000h to 567FFFh
568000h to 56FFFFh
570000h to 577FFFh
578000h to 57FFFFh
580000h to 587FFFh
588000h to 58FFFFh
590000h to 597FFFh
598000h to 59FFFFh
5A0000h to 5A7FFFh
5A8000h to 5AFFFFh
5B0000h to 5B7FFFh
5B8000h to 5BFFFFh
5C0000h to 5C7FFFh
5C8000h to 5CFFFFh
6D0000h to 5D7FFFh
6D8000h to 5DFFFFh
5E0000h to 5E7FFFh
5E8000h to 5EFFFFh
5F0000h to 5F7FFFh
5F8000h to 5FFFFFh
600000h to 607FFFh
608000h to 60FFFFh
610000h to 617FFFh
618000h to 61FFFFh
620000h to 627FFFh
628000h to 62FFFFh
630000h to 637FFFh
638000h to 63FFFFh
640000h to 647FFFh
648000h to 64FFFFh
650000h to 657FFFh
658000h to 65FFFFh
660000h to 667FFFh
668000h to 66FFFFh
(Continued)
MB84SF6H6H6L2-70
(Continued)
Sector Address
Bank
Sector
Bank C
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
SA224
SA225
SA226
SA227
SA228
SA229
SA230
Bank Address
A22
A21
A20
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
A19 A18 A17 A16 A15 A14 A13 A12
0 1 1 1 0 X X X
0 1 1 1 1 X X X
1 0 0 0 0 X X X
1 0 0 0 1 X X X
1 0 0 1 0 X X X
1 0 0 1 1 X X X
1 0 1 0 0 X X X
1 0 1 0 1 X X X
1 0 1 1 0 X X X
1 0 1 1 1 X X X
1 1 0 0 0 X X X
1 1 0 0 1 X X X
1 1 0 1 0 X X X
1 1 0 1 1 X X X
1 1 1 0 0 X X X
1 1 1 0 1 X X X
1 1 1 1 0 X X X
1 1 1 1 1 X X X
Sector
Size
(Kwords)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
670000h to 677FFFh
678000h to 67FFFFh
680000h to 687FFFh
688000h to 68FFFFh
690000h to 697FFFh
698000h to 69FFFFh
6A0000h to 6A7FFFh
6A8000h to 6AFFFFh
6B0000h to 6B7FFFh
8B8000h to 6BFFFFh
6C0000h to 6C7FFFh
6C8000h to 6CFFFFh
6D0000h to 6D7FFFh
6D8000h to 6DFFFFh
6E0000h to 6E7FFFh
6E8000h to 6EFFFFh
6F0000h to 6F7FFFh
6F8000h to 6FFFFFh
23
MB84SF6H6H6L2-70
• Sector Address Tables (Bank D)
Sector Address
24
Bank
Sector
Bank D
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
SA256
SA257
SA258
SA259
SA260
SA261
SA262
SA263
SA264
SA265
SA266
SA267
SA268
SA269
Bank Address
A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
1
1
1
0 0 0 0 0 X X X
1
1
1
0 0 0 0 1 X X X
1
1
1
0 0 0 1 0 X X X
1
1
1
0 0 0 1 1 X X X
1
1
1
0 0 1 0 0 X X X
1
1
1
0 0 1 0 1 X X X
1
1
1
0 0 1 1 0 X X X
1
1
1
0 0 1 1 1 X X X
1
1
1
0 1 0 0 0 X X X
1
1
1
0 1 0 0 1 X X X
1
1
1
0 1 0 1 0 X X X
1
1
1
0 1 0 1 1 X X X
1
1
1
0 1 1 0 0 X X X
1
1
1
0 1 1 0 1 X X X
1
1
1
0 1 1 1 0 X X X
1
1
1
0 1 1 1 1 X X X
1
1
1
1 0 0 0 0 X X X
1
1
1
1 0 0 0 1 X X X
1
1
1
1 0 0 1 0 X X X
1
1
1
1 0 0 1 1 X X X
1
1
1
1 0 1 0 0 X X X
1
1
1
1 0 1 0 1 X X X
1
1
1
1 0 1 1 0 X X X
1
1
1
1 0 1 1 1 X X X
1
1
1
1 1 0 0 0 X X X
1
1
1
1 1 0 0 1 X X X
1
1
1
1 1 0 1 0 X X X
1
1
1
1 1 0 1 1 X X X
1
1
1
1 1 1 0 0 X X X
1
1
1
1 1 1 0 1 X X X
1
1
1
1 1 1 1 0 X X X
1
1
1
1 1 1 1 1 0 0 0
1
1
1
1 1 1 1 1 0 0 1
1
1
1
1 1 1 1 1 0 1 0
1
1
1
1 1 1 1 1 0 1 1
1
1
1
1 1 1 1 1 1 0 0
1
1
1
1 1 1 1 1 1 0 1
1
1
1
1 1 1 1 1 1 1 0
1
1
1
1 1 1 1 1 1 1 1
Sector Size
(Kwords)
(× 16)
Address Range
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
700000h to 707FFFh
708000h to 70FFFFh
710000h to 717FFFh
718000h to 71FFFFh
720000h to 727FFFh
728000h to 72FFFFh
730000h to 737FFFh
738000h to 73FFFFh
740000h to 747FFFh
748000h to 74FFFFh
750000h to 757FFFh
758000h to 75FFFFh
760000h to 767FFFh
768000h to 76FFFFh
770000h to 777FFFh
778000h to 77FFFFh
780000h to 787FFFh
788000h to 78FFFFh
790000h to 797FFFh
798000h to 79FFFFh
7A0000h to 7A7FFFh
7A8000h to 7AFFFFh
7B0000h to 7B7FFFh
7B8000h to 7BFFFFh
7C0000h to 7C7FFFh
7C8000h to 7CFFFFh
7D0000h to 7D7FFFh
7D8000h to 7DFFFFh
7E0000h to 7E7FFFh
7E8000h to 7EFFFFh
7F0000h to 7F7FFFh
7F8000h to 7F8FFFh
7F9000h to 7F9FFFh
7FA000h to 7FAFFFh
7FB000h to 7FBFFFh
7FC000h to 7FCFFFh
7FD000h to 7FDFFFh
7FE000h to 7FEFFFh
7FF000h to 7FFFFFh
MB84SF6H6H6L2-70
• Sector Group Address Table
Sector Group A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
0
0
0
0
0
0
0
0
0
0
SA0
SGA1
0
0
0
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
0
0
0
1
1
1
SA7
SGA8
0
0
0
0
0
0
0
1
X
X
X
SA8
SGA9
0
0
0
0
0
0
1
0
X
X
X
SA9
SGA10
0
0
0
0
0
0
1
1
X
X
X
SA10
SGA11
0
0
0
0
0
1
X
X
X
X
X
SA11 to SA14
SGA12
0
0
0
0
1
0
X
X
X
X
X
SA15 to SA18
SGA13
0
0
0
0
1
1
X
X
X
X
X
SA19 to SA22
SGA14
0
0
0
1
0
0
X
X
X
X
X
SA23 to SA26
SGA15
0
0
0
1
0
1
X
X
X
X
X
SA27 to SA30
SGA16
0
0
0
1
1
0
X
X
X
X
X
SA31 to SA34
SGA17
0
0
0
1
1
1
X
X
X
X
X
SA35 to SA38
SGA18
0
0
1
0
0
0
X
X
X
X
X
SA39 to SA42
SGA19
0
0
1
0
0
1
X
X
X
X
X
SA43 to SA46
SGA20
0
0
1
0
1
0
X
X
X
X
X
SA47 to SA50
SGA21
0
0
1
0
1
1
X
X
X
X
X
SA51 to SA54
SGA22
0
0
1
1
0
0
X
X
X
X
X
SA55 to SA58
SGA23
0
0
1
1
0
1
X
X
X
X
X
SA59 to SA62
SGA24
0
0
1
1
1
0
X
X
X
X
X
SA63 to SA66
SGA25
0
0
1
1
1
1
X
X
X
X
X
SA67 to SA70
SGA26
0
1
0
0
0
0
X
X
X
X
X
SA71 to SA74
SGA27
0
1
0
0
0
1
X
X
X
X
X
SA75 to SA78
(Continued)
25
MB84SF6H6H6L2-70
Sector Group
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA28
0
1
0
0
1
0
X
X
X
X
X
SA79 to SA82
SGA29
0
1
0
0
1
1
X
X
X
X
X
SA83 to SA86
SGA30
0
1
0
1
0
0
X
X
X
X
X
SA87 to SA90
SGA31
0
1
0
1
0
1
X
X
X
X
X
SA91 to SA94
SGA32
0
1
0
1
1
0
X
X
X
X
X
SA95 to SA98
SGA33
0
1
0
1
1
1
X
X
X
X
X
SA99 to SA102
SGA34
0
1
1
0
0
0
X
X
X
X
X
SA103 to SA106
SGA35
0
1
1
0
0
1
X
X
X
X
X
SA107 to SA110
SGA36
0
1
1
0
1
0
X
X
X
X
X
SA111 to SA114
SGA37
0
1
1
0
1
1
X
X
X
X
X
SA115 to SA118
SGA38
0
1
1
1
0
0
X
X
X
X
X
SA119 to SA122
SGA39
0
1
1
1
0
1
X
X
X
X
X
SA123 to SA126
SGA40
0
1
1
1
1
0
X
X
X
X
X
SA127 to SA130
SGA41
0
1
1
1
1
1
X
X
X
X
X
SA131 to SA134
SGA42
1
0
0
0
0
0
X
X
X
X
X
SA135 to SA138
SGA43
1
0
0
0
0
1
X
X
X
X
X
SA139 to SA142
SGA44
1
0
0
0
1
0
X
X
X
X
X
SA143 to SA146
SGA45
1
0
0
0
1
1
X
X
X
X
X
SA147 to SA150
SGA46
1
0
0
1
0
0
X
X
X
X
X
SA151 to SA154
SGA47
1
0
0
1
0
1
X
X
X
X
X
SA155 to SA158
SGA48
1
0
0
1
1
0
X
X
X
X
X
SA159 to SA162
SGA49
1
0
0
1
1
1
X
X
X
X
X
SA163 to SA166
SGA50
1
0
1
0
0
0
X
X
X
X
X
SA167 to SA170
SGA51
1
0
1
0
0
1
X
X
X
X
X
SA171 to SA174
(Continued)
26
MB84SF6H6H6L2-70
(Continued)
Sector Group
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA52
1
0
1
0
1
0
X
X
X
X
X
SA175 to SA178
SGA53
1
0
1
0
1
1
X
X
X
X
X
SA179 to SA182
SGA54
1
0
1
1
0
0
X
X
X
X
X
SA183 to SA186
SGA55
1
0
1
1
0
1
X
X
X
X
X
SA187 to SA190
SGA56
1
0
1
1
1
0
X
X
X
X
X
SA191 to SA194
SGA57
1
0
1
1
1
1
X
X
X
X
X
SA195 to SA198
SGA58
1
1
0
0
0
0
X
X
X
X
X
SA199 to SA202
SGA59
1
1
0
0
0
1
X
X
X
X
X
SA203 to SA206
SGA60
1
1
0
0
1
0
X
X
X
X
X
SA207 to SA210
SGA61
1
1
0
0
1
1
X
X
X
X
X
SA211 to SA214
SGA62
1
1
0
1
0
0
X
X
X
X
X
SA215 to SA218
SGA63
1
1
0
1
0
1
X
X
X
X
X
SA219 to SA222
SGA64
1
1
0
1
1
0
X
X
X
X
X
SA223 to SA226
SGA65
1
1
0
1
1
1
X
X
X
X
X
SA227 to SA230
SGA66
1
1
1
0
0
0
X
X
X
X
X
SA231 to SA234
SGA67
1
1
1
0
0
1
X
X
X
X
X
SA235 to SA238
SGA68
1
1
1
0
1
0
X
X
X
X
X
SA239 to SA242
SGA69
1
1
1
0
1
1
X
X
X
X
X
SA243 to SA246
SGA70
1
1
1
1
0
0
X
X
X
X
X
SA247 to SA250
SGA71
1
1
1
1
0
1
X
X
X
X
X
SA251 to SA254
SGA72
1
1
1
1
1
0
X
X
X
X
X
SA255 to SA258
SGA73
1
1
1
1
1
1
0
0
X
X
X
SA259
SGA74
1
1
1
1
1
1
0
1
X
X
X
SA260
SGA75
1
1
1
1
1
1
1
0
X
X
X
SA261
SGA76
1
1
1
1
1
1
1
1
0
0
0
SA262
SGA77
1
1
1
1
1
1
1
1
0
0
1
SA263
SGA78
1
1
1
1
1
1
1
1
0
1
0
SA264
SGA79
1
1
1
1
1
1
1
1
0
1
1
SA265
SGA80
1
1
1
1
1
1
1
1
1
0
0
SA266
SGA81
1
1
1
1
1
1
1
1
1
0
1
SA267
SGA82
1
1
1
1
1
1
1
1
1
1
0
SA268
SGA83
1
1
1
1
1
1
1
1
1
1
1
SA269
27
MB84SF6H6H6L2-70
• Sector Protection Verify Autoselect Codes Table
A7 A6 A5 A4
Type
A22 to A12
A3
A2
A1
A0
Code (HEX)
Manufacture’s Code
BA
L
L
L
L
L
L
L
L
04h
Device Code
BA
L
L
L
L
L
L
L
H
227Eh
BA
L
L
L
L
H
H
H
L
2218h
BA
L
L
L
L
H
H
H
H
2200h
Sector
Group
Addresses
L
L
L
L
L
L
H
L
01h*1
H
DQ7 - Factory Lock Bit
1 = Locked, 0 = Not Locked
DQ6 - Customer Lock Bit
1 = Locked, 0 = Not Locked
Extended Device Code *2
Sector Group Protection
Indicator Bits
BA
L
L
L
L
L
L
H
Legend : L = VIL, H = VIH. See DC Characteristics for voltage levels.
*1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*2 : A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional
codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these
Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.
28
MB84SF6H6H6L2-70
• Flash Memory Command Definitions
Command
Sequence
Bus
First Bus Second Write Third Write FourthWrite Fifth Write Sixth Write
Seventh
Write Write Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Write Cycle
Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Req’d
Read / Reset
1
XXXh F0h
—
—
—
—
—
—
—
—
Read / Reset
3
555h AAh 2AAh
55h
555h F0h
RA
RD
—
—
—
—
—
—
Autoselect
3
555h AAh 2AAh
55h
(BA)
90h
555h
—
—
—
—
—
—
—
—
Program
4
555h AAh 2AAh
55h
555h A0h
PA
PD
—
—
—
—
—
—
Chip Erase
6
555h AAh 2AAh
55h
555h 80h
555h
AAh 2AAh
55h
555h
10h
—
—
Sector Erase
6
555h AAh 2AAh
55h
555h 80h
555h
AAh 2AAh
55h
SA
30h
—
—
Erase Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
—
—
Erase Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
—
—
Set to Fast Mode
3
555h AAh 2AAh
55h
555h 20h
—
—
—
—
—
—
—
—
Fast Program
2
XXXh
PD
—
—
Reset from Fast
Mode *1
2
BA
Set Burst Mode
Configuration
Register
3
555h AAh 2AAh
Query
1
(BA)
55h
HiddenROM
Entry
3
555h AAh 2AAh 55h 555h 88h
HiddenROM
Program*3
4
555h AAh 2AAh 55h 555h A0h
HiddenROM
Exit*3
HiddenROM
Protect*3
A0
RA
PA
RD
90h XXXh F0h*2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(HRA)
PD
PA
—
—
—
—
—
—
4
555h AAh 2AAh 55h 555h 90h XXXh 00h
—
—
—
—
—
—
6
555h AAh 2AAh 55h 555h 60h OPBP 68h OPBP 48h XXXh RD(0)
—
—
98h
—
55h
—
—
—
—
(CR)
C0h
555h
—
—
Legend :
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the ADV pulse or
active edge of CLK while ADV = VIL whichever comes first or falling edge of wirte pulse while ADV = VIL.
SA = Address of the sector to be erased. The combination of A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12
will uniquely select any sector.
BA = Bank Address. Address setted by A22, A21, A20 will select Bank A, Bank B, Bank C and Bank D.
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data latches on the rising edge of write pulse.
SGA = Sector group address to be protected.
HRA = Address of the HiddenROM area 000000h to 00007Fh
HRBA = Bank Address of the HiddenROM area (A22 = A21 = A20 = A19 = A18 = VIL)
(Continued)
29
MB84SF6H6H6L2-70
(Continued)
RD (0) = Read Data bit. If programmed, DQ0 = 1, if erase, DQ0 = 0
OPBP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 1, 0, 1, 0)
CR = Configuration Register address bits A19 to A12.
*1: This command is valid during Fast Mode.
*2: This command is valid during HiddenROM mode.
*3: The data “00h” is also acceptable.
Notes : • Address bits A22 to A11 = X = “H” or “L” for all address commands except for PA, SA, BA, SGA, OPBP.
• Bus operations are defined in “■ DEVICE BUS OPERATIONS”.
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
30
MB84SF6H6H6L2-70
2. AC Characteristics
• Synchronous/Burst Read
Symbol
Value
Parameter
Unit
JEDEC
Standard
Min
Max
Latency
—
tIACC
—
71
ns
Burst Access Time Valid Clock to Output Delay
—
tBACC
—
11
ns
Address Setup Time to CLK*1
—
tACS
4
—
ns
Address Hold Time from CLK*2
—
tACH
6
—
ns
Data Hold Time from Next Clock Cycle
—
tBDH
3
—
ns
Chip Enable to RY/BY Valid
—
tCR
—
11
ns
Output Enable to Output Valid
—
tOE
—
11
ns
Chip Enable to High-Z
—
tCEZ
—
8
ns
Output Enable to High-Z
—
tOEZ
—
8
ns
CEf Setup Time to CLK
—
tCES
4
—
ns
Ready Access Time from CLK
—
tRACC
—
11
ns
CEf Setup Time to ADV
—
tCAS
0
—
ns
ADV Set Up Time to CLK
—
tAVSC
4
—
ns
ADV Hold Time to CLK
—
tAVHC
6
—
ns
CLK to access resume
—
tCKA
—
11
ns
CLK to High-Z
—
tCKZ
—
8
ns
Output Enable Setup Time
—
tOES
4
—
ns
Read Cycle for Continuous suspend
—
tRCC
—
1
ms
Read Cycle Time
—
tRC
56
—
ns
*1 : Access Time is from the last of either stable addresses .
*2 : Addresses are latched on the active edge of CLK.
Note : Test Conditions
Output Load : VCCQr =1.65 V to 1.95 V : 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V to VCCf
Timing measurement reference level : Input : 0.5 × VCCf, Output : 0.5 × VCCf
31
MB84SF6H6H6L2-70
• Asynchronous Read
Symbol
Value
Parameter
Unit
JEDEC Standard
Min
Max
Read Cycle Time
—
tRC
56
—
ns
Access Time from CEf Low
—
tCE
—
56
ns
Asynchronous Access Time*
—
tACC
—
56
ns
Output Enable to Output Valid
—
tOE
—
11
ns
0
—
ns
—
tOEH
8
—
ns
Read
Output Enable Hold Time
Toggle and Data Polling
Chip Enable to High-Z
—
tCEZ
—
8
ns
CEf High During Toggle Bit Polling
—
tCEPH
20
—
ns
Output Enable to High-Z
—
tOEZ
—
8
ns
* : Asynchronous Access Time is from the last of either stable addresses or the falling edge of ADV.
• Hardware Reset (RESET)
Symbol
Value
Parameter
Unit
JEDEC
Standard
Min
Max
RESET Pin Low (During Embedded Algorithms) to
Read Mode *1
—
tREADY
—
20
µs
RESET Pulse Width
—
tRP
500
—
ns
Reset High Time Before Read *2
—
tRH
200
—
ns
Power On/Off Time
—
tPS
0
—
ns
*1 : Access Time is from the last of either stable addresses.
*2 : Addresses are latched on the active edge of CLK.
Note : Test Conditions :
Output Load : VCCQr =1.65 V to 1.95 V : 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V to VCCf
Timing measurement reference level : Input : 0.5 × VCCf, Output : 0.5 × VCCf
32
MB84SF6H6H6L2-70
• Write (Erase/Program) Operations
Parameter
Symbol
Value
Unit
JEDEC
Standard
Min
Typ
Max
Write Cycle Time
tAVAV
tWC
56
—
—
ns
Address Setup Time
tAVWL
tAS
0
—
—
ns
Address Hold Time
tWLAX
tAH
20
—
—
ns
ADV Low Time
—
tAVDP
10
—
—
ns
CEf Low to ADV High
—
tCLAH
10
—
—
ns
Data Setup Time
tDVWH
tDS
20
—
—
ns
Data Hold Time
tWHDX
tDH
0
—
—
ns
Read Recovery Time Before Write
tGHWL
tGHWL
0
—
—
ns
CEf Hold Time
tWHEH
tCH
0
—
—
ns
Write Pulse Width
tEHWH
tWP
20
—
—
ns
Write Pulse Width High
tWHWL
tWPH
20
—
—
ns
—
tSR/W
0
—
—
ns
tWHWH1
tWHWH1
—
6
—
µs
tWHWH2
tWHWH2
—
0.5
—
s
—
tVCS
50
—
—
µs
tELWL
tCS
0
—
—
ns
ADV Set Up Time to CLK
—
tAVSC
4
—
—
ns
ADV Hold Time to CLK
—
tAVHC
6
—
—
ns
ADV Setup Time to WE
—
tAVSW
4
—
—
ns
ADV Hold Time to WE
—
tAVHW
6
—
—
ns
Address Setup Time to CLK
—
tACS
4
—
—
ns
Address Hold Time to CLK
—
tACH
6
—
—
ns
Address Setup Time to ADV
—
tAAS
4
—
—
ns
tAAH
6
—
—
ns
Latency Between Read and Write Operations
Programming Operation*
1
1, 2
Sector Erase Operation* *
VCCf Setup Time
CEf Setup Time to WE
Address Hold Time to ADV
WE Low to CLK
—
tWLC
0
—
—
ns
ADV High to WE Low
—
tAHWL
5
—
—
ns
CLK to WE Low
—
tCWL
5
—
—
ns
Erase Time-out TIme
—
tTOW
50
—
—
µs
*1 : Not 100% tested.
*2 : See the "Erase and Programming Performance" section in “BS12DH” datasheet for more information.
Notes : • Does not include the preprogramming time.
• Access Time is from the last of either stable addresses.
• Addresses are latched on the active edge of CLK.
33
MB84SF6H6H6L2-70
• Erase and Programming Performance
Value
Parameter
Unit
Remarks
2
s
Excludes programming prior to erasure
6.0
100
µs
Excludes system level overhead
—
50.3
200
s
Excludes system level overhead
100,000
—
—
cycle
Min
Typ
Max
Sector Erase Time
—
0.5
Word Programming Time
—
Chip Programming Time
Erase/Program Cycle
Notes : • Typical Erase Conditions : TA = +25°C, VCCf = 1.8 V
• Typical Program Conditions : TA = +25°C, VCCf = 1.8 V, Data = checker
• Test Conditions :
Output Load : VCCQr =1.65 V to 1.95 V : 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V to VCCf
Timing measurement reference level : Input: 0.5 × VCCf, Output : 0.5 × VCCf
34
—
MB84SF6H6H6L2-70
• Synchronous Burst Mode Read (Latched By Rising Active CLK)
7 cycles for initial access shown.
tCEZ
tCES
CEf
1
2
3
4
5
6
7
CLK
tAVSC
ADV
tAVHC
tACS
tBDH
A22 to A0
Aa
tBACC
tACH
High-Z
DQ15 to
DQ0
tOES
OE
tCR
RY/BY
Da
tIACC
tACC
Da + 1
Da + n
tCKA
tRACC
High-Z
High-Z
Notes : • Figure shows total number of wait states set to seven cycles. The total number of wait
states can be programmed from two cycles to seven cycles.
• The device is in synchronous mode.
35
MB84SF6H6H6L2-70
• Synchronous Burst Mode Read (Latched By Falling Active CLK)
4 cycles for initial access shown.
tCEZ
tCES
CEf
1
2
3
4
5
CLK
tAVSC
ADV
tAVHC
tACS
tBDH
A22 to A0
Aa
tBACC
tACH
High-Z
DQ15 to DQ0
Da
tIACC
Da + 1
Da + n
tACC
tOES
OE
tCR
High-Z
RY/BY
tCKA
tRACC
High-Z
Notes : • Figure shows total number of wait states set to four cycles. The total number of wait
states can be programmed from two cycles to seven cycles. Clock is set for active falling
edge.
• The device is in synchronous mode.
36
MB84SF6H6H6L2-70
• 8-word Linear Burst
7 cycles for initial access shown.
tCES
CEf
1
2
3
4
5
6
7
CLK
tAVSC
ADV
tAVHC
tACS
A22 to A0
tCEZ
tBDH
Aa
tBACC
tACH
DQ15 to DQ0
tOES
OE
RY/BY
tCR
tIACC
tACC
D0
D1
D2
D3
D4
D5
D6
D7
tCKA
tRACC
High-Z
Note : Figure assumes 7 wait states for initial access, synchronous read. D0 to D7 in data waveform
indicate the order of data within a given 8-word address range, from lowest to highest.
See "Requirements for Synchronous (Burst) Read Operation". The Set Configuration Register
command sequence has been written with A18 = 1; device will output RY/BY with valid data.
37
MB84SF6H6H6L2-70
• 8-word Linear Burst with Wrap Around
7 cycles for initial access shown.
tCES
CEf
1
2
3
4
5
6
7
CLK
tAVSC
ADV
tAVHC
tACS
A22 to A0
tCEZ
tBDH
Aa
tBACC
tACH
DQ15 to DQ0
tOES
OE
RY/BY
tCR
tIACC
tACC
D6
D7
D0
D1
D2
D3
D4
D5
tCKA
tRACC
High-Z
Note : Figure assumes 7 wait states for initial access, synchronous read. D0 to D7 in data waveform
indicate the order of data within a given 8-word address range, from lowest to highest. Starting
address in figure is the 7th address in range (A6). See "Requirements for Synchronous (Burst)
Read Operation". The Set Configuration Register command sequence has been written with
A18 = 1; device will output RY/BY with valid data.
38
MB84SF6H6H6L2-70
• Linear Burst with RY/BY Set One Cycle Before Data
6 wait cycles for initial access shown.
tCEZ
tCES
CEf
1
2
3
4
5
6
CLK
tAVSC
ADV
tAVHC
tACS
tBDH
A22 to A0
Aa
tBACC
tACH
High-Z
DQ15 to DQ0
D0
tIACC
tOES
OE
tACC
tCKA
D1
D2
D3
Da + n
tRACC
tCR
RY/BY
High-Z
High-Z
Note : Figure assumes 6 wait states for initial access, 66 MHz clock, and synchronous read.
The Set Configuration Register command sequence has been written with A18 = 0; device
will output RY/BY one cycle before valid data.
39
MB84SF6H6H6L2-70
• Burst Suspend
Suspend
Resume
CLK
VIH
ADV
Address
tOES
tOES
OE
tCKZ
tCKA
Data
D20
D20
tRACC
D21
D22
D23
D24
D25
tRACC
RY/BY
CEf
VIL
Note : The Set Configuration Register command sequence must be written with A18 =1; device
will output RY/BY with valid data. The clock during Burst Suspend is “Don’t care”.
40
D26
MB84SF6H6H6L2-70
• Burst Suspend prior to Initial Access
1
2
3
4
Suspend
5
6
Resume
7
CLK
ADV
Address
A(n)
tOES
OE
tCKA
Data
D(n)
D(n+1)
D(n+2)
D(n+3)
D(n+4)
tRACC
RY/BY
CEf
Note : Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration
Register command sequence must be written with A18 =1; device will output RY/BY with valid
data. The clock during Burst Suspend is “Don’t care”.
41
MB84SF6H6H6L2-70
• Read Cycle for Continuous Suspend
1
2
3
4
Suspend
5
6
Resume
7
CLK
tRCC
ADV
Address
A(n)
tOES
OE
tCKA
tRCC
Data
D(n)
Invalid Data
RY/BY
CEf
Notes : • Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration
Register command sequence must be written with A18 =1; device will output RY/BY with valid
data. The clock during Burst Suspend is “Don’t care”.
• Burst plus Burst Suspend should not last longer than tRCC without relaching an address.
After the period of tRCC the device will output invalid data.
42
MB84SF6H6H6L2-70
• Asynchronous Mode Read
tRC
Address
Address Stable
tACC
CEf
tOE
tCEZ
OE
tOEZ
tOEH
WE
tCE
High-Z
Outputs
tOH
Outputs Valid
High-Z
Notes : • ADV is assumed to be VIL.
• Configuration Register is set to Asynchronous mode.
43
MB84SF6H6H6L2-70
• Reset Timings
CEf, OE
tRH
RESET
tRP
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
CEf, OE
tREADY
RESET
tRP
• Power On/Off Timings (128M Burst Flash)
tPS
tPS
RESET
VCCf
0V
1.65 V
1.65 V
Valid Data In
Address
Data
44
Valid Data Out
tRH
tACC
MB84SF6H6H6L2-70
• Program Operation Timings at Asynchronous Mode (WE latch)
Program Command Sequence (last two cycles)
Read Status Data
CLK
tAVSW
tAVHW
ADV VIL
Data Polling
3rd Bus Cycle
555h
Address
tWC
PA
tAS
VA
PA
tRC
tAH
tOH
tDS tDH
A0h
Data
PD
DQ7
DOUT
DOUT
tCEZ
CEf
tCS
tOEZ
tCH
tCE
OE
tGHWL
tWP
tWPH
tOE
tWHWH1
WE
Notes : • PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
• "In progress" and "complete" refer to status of program operation.
• A22 to A12 are don’t care during command sequence unlock cycles.
• CLK is “Don’t care”.
• Configuration Register is set to Asynchronous mode.
45
MB84SF6H6H6L2-70
• Program Operation Timings at Asynchronous Mode (ADV latch)
Program Command Sequence (last two cycles)
Read Status Data
CLK
tCLAH
ADV
tAVDP
tAAH
tAAS
Address
555h
Data
VA
PA
A0h
VA
In
Progress
PD
Complete
tDS
tDH
CEf
tCH
OE
tAHWL
WE
tWP
tCS
tWHWH1
tWPH
tWC
tVCS
VCCf
Notes : •
•
•
•
•
•
46
PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
"In progress" and "complete" refer to status of program operation.
A22 to A12 are don’t care during command sequence unlock cycles.
CLK is “Don’t care”.
Configuration Register is set to Asynchronous mode.
Addresses are latched on the rising edge of ADV.
MB84SF6H6H6L2-70
• Program Operation Timings at Synchronous Mode (WE latch)
Program Command Sequence (last two cycles)
Read Status Data
CLK
tAVSW
tAVHW
ADV
Address
tAS
VA
PA
555h
tAH
Data
A0h
VA
In
Progress
PD
Complete
tDS
tDH
CEf
OE
tCH
tWLC
tWP
WE
tWPH
tCS
tWHWH1
tWC
tVCS
VCCf
Notes : •
•
•
•
•
PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
“In progress” and “complete” refer to status of program operation.
A22 to A12 are “don’t care” during command sequence unlock cycles.
Configuration Register is set to Synchronous mode.
Addresses are latched on the first of either the falling edge of WE or active edge of CLK.
When "tWLC" is not met then ADV/address set up and hold time to CLK will be required.
47
MB84SF6H6H6L2-70
• Program Operation Timings at Synchronous Mode (CLK latch)
Program Command Sequence (last two cycles)
Read Status Data
CLK
tACS
tACH
CEf
tAVSC
tAVHC
ADV
Address
Data
A0h
tDS
tCAS
VA
PA
555h
VA
In
Progress
PD
Complete
tDH
OE
tCH
tCWL
tWP
WE
tWHWH1
tWPH
tVCS
tWC
Vccf
Notes : •
•
•
•
•
48
PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
"In progress" and "complete" refer to status of program operation.
A22 to A12 are don’t care during command sequence unlock cycles.
Configuration Register is set to Synchronous mode.
Addresses are latched on the first of either the active edge of CLK or the rising edge of ADV.
MB84SF6H6H6L2-70
• Chip/Sector Erase Command Sequence
Program Command Sequence (last two cycles)
Read Status Data
CLK
tAVSW
tAVHW
ADV
Address
SA
555h for
chip erase
2AAh
tAS
tAH
Data
55h
VA
VA
10h for
chip erase
In
Progress
30h
Complete
tDS
tAVHC
tDH
CEf
OE
tCH
tWLC
tWP
WE
tWPH
tCS
tWHWH2
tWC
tVCS
VCCf
Notes : • SA is the sector address for Sector Erase.
• Address bits A22 to A12 are don’t cares during unlock cycles in the command sequence.
• This timing is for Synchronous mode.
49
MB84SF6H6H6L2-70
• Data Polling Timings/Toggle Bit Timings (During Embedded Algorithm)
ADV
tCEZ
tCE
CEf
tCH
tOEZ
tOE
OE
tOEH
WE
tACC
Address
VA
VA
Status Data
Status Data
Notes : • Status reads in figure are shown as asynchronous mode.
• VA = Valid Address. Two read cycles are required to determine status. When the Embedded
Algorithm operation is complete, and Data Polling will output true data and the toggle bits
will stop toggling.
50
MB84SF6H6H6L2-70
• Synchronous Data Polling Timings/Toggle Bit Timings
CEf
CLK
ADV
Address
VA
VA
OE
tIACC
tIACC
Data
Status Data
Status Data
RY/BY
Notes : • The timings are similar to synchronous read timings.
• VA = Valid Address. Two read cycles are required to determine status. When the Embedded
Algorithm operation is complete, the toggle bits will stop toggling.
• RY/BY is active with data (A18 = 0 in the Burst Mode Configuration Register). When A18 = 1
in the Burst Mode Configuration Register, RY/BY is active one clock cycle before data.
51
MB84SF6H6H6L2-70
• Example of Wait States Insertion (Non-Handshaking Device)
Data
D0
Rising edge of next clock cycle
following last wait state triggers
next burst data
ADV
total number of clock cycles
following ADV falling edge
OE
1
2
3
0
1
4
5
6
7
3
4
5
CLK
2
number of clock cycles
programmed
Wait State Decoding Addresses:
A14, A13, A12 = "101" ⇒ 5 programmed, 7 total
A14, A13, A12 = "100" ⇒ 4 programmed, 6 total
A14, A13, A12 = "011" ⇒ 3 programmed, 5 total
A14, A13, A12 = "010" ⇒ 2 programmed, 4 total
A14, A13, A12 = "001" ⇒ 1 programmed, 3 total
A14, A13, A12 = "000" ⇒ 0 programmed, 2 total
Note : Figure assumes address D0 is not at an address boundary, active clock edge is rising, and
wait state is set to "101".
52
D1
MB84SF6H6H6L2-70
• Bank-to-Bank Read/Write Cycle Timings
Last Cycle in
Program or
Sector Erase
Command Sequence
Read status (at least two cycles) in same bank
and/or array data from other bank
tWC
tRC
Begin another
write or program
command sequence
tRC
tWC
tCEPH
CEf
OE
tOE
tOEH
tGHWL
WE
tWP
tWPH
tDS
tDH
Data
tOEZ
tACC
PD/30h
tOEH
AAh
RD
RD
tAS
tAH
Address
PA/SA
tSR/W
RA
RA
555h
ADV
Note : Breakpoints in waveforms indicate that system may alternately read array data from the
"non-busy bank" while checking the status of the program or erase operation in the "busy"
bank. The system should read status twice to ensure valid information.
53
MB84SF6H6H6L2-70
■ 128M FCRAM CHARACTERISTICS for MCP
1. State Diagram
• Initial/Standby State
Asynchronous Operation
(Page Mode)
Power Up
Synchronous Operation
(Burst Mode)
Power
Down
CE2r = H
CE2r = L
Common State
CR Set
Pause Time
@M = 1
CE2r = H
@M = 0
Standby
Standby
Power
Down
CE2r = L
CE2r = CE1r = H
• Asynchronous Operation
Standby
CE1r = L
CE1r = L &
WE = L
CE1r = H
CE1r = H
CE1r = H
Output
Disable
WE = H
OE = L
WE = L
Byte Control
CE1r = L &
OE = L
OE = H
Write
Address Change
or Byte Control
Read
Byte Control @OE = L
CE2r = CE1r = H
• Synchronous Operation
Standby
CE1r = H
CE1r = H
Write
Suspend
WE = H
WE = L
ADV Low Pulse
CE1r = H
CE1r = H
CE1r = L,
ADV Low Pulse,
& WE = L
CE1r = L,
ADV Low Pulse,
& OE = L
Write
Read
Suspend
OE = H
OE = L
Read
ADV Low Pulse
ADV Low Pulse
(@BL = 8 or 16, and after burst
operationis completed)
Note : Assuming all the parameters specified in “3. AC Characteristics” in “■ 128M FCRAM CHARACTERISTICS
for MCP” are satisfied. Refer to “2. Functial Description” and “3. AC Characteristics” for details.
54
MB84SF6H6H6L2-70
2. Functional Description
This device supports asynchronous page read & normal write operation and synchronous burst read & burst
write operation for faster memory access and features three kinds of power down modes for power saving as
user configuable option.
• Power-up
It is required to follow the power-up timing to start executing proper device operation. Refer to POWER-UP
Timing. After Power-up, the device defaults to asynchronous page read & normal write operation mode with
sleep power down feature.
• Configuration Register
The Configuration Register (CR) is used to configure the type of device function among optional features. Each
selection of features is set through CR Set sequence after Power-up. If CR Set sequence is not performed after
power-up, the device is configured for asynchronous operation with sleep power down feature as default configuration.
• CR Set Sequence
The CR Set requires total 6 read/write operation with unique address. Between each read/write operation requires
that device being in standby mode. Following table shows the detail sequence.
Cycle #
Operation
Address
Data
1st
Read
7FFFFFh (MSB)
Read Data (RDa)
2nd
Write
7FFFFFh
RDa
3rd
Write
7FFFFFh
RDa
4th
Write
7FFFFFh
X
5th
Write
7FFFFFh
X
6th
Read
Address Key
Read Data (RDb)
The first cycle is to read from most significant address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle. If the second or third cycle is
written into the different address, the CR Set is cancelled and the data written by the second or third cycle is
valid as a normal write operation.
The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle is don’t-care. If the forth or fifth cycle
is written into different address, the CR Set is also cancelled but write data may not be written as normal write
operation.
The last cycle is to read from specific address key for mode selection. And read data (RDb) is invalid.
Once this CR Set sequence is performed from an initial CR set to the other new CR set, the written data stored
in memory cell array may be lost. So, it should perform the CR Set sequence prior to regular read/write operation
if necessary to change from default configuration.
55
MB84SF6H6H6L2-70
• Address Key
The address key has the following format.
Address
Pin
A22 to A21
Register
Name
—
A20 to A19
PS
Function
Key
Description
Note
—
1
00
01
10
11
000
001
010
011
100
101
110
111
Unused bits must be 1
32M Partial
16M Partial
Reserved for future use
Sleep [Default]
Reserved for future use
Reserved for future use
8 words
16 words
Reserved for future use
Reserved for future use
Reserved for future use
Continuous
Synchronous Mode
(Burst Read / Write)
Asynchronous Mode[Default]
(Page Read / Normal Write)
Reserved for future use
3 clocks
4 clocks
5 clocks
Reserved for future use
Reserved for future use
Sequential
Burst Read & Burst Write
Burst Read & Single Write
Falling Clock Edge
Rising Clock Edge
Unused bits muse be 1
WE Single Clock Pulse Control
without Write Suspend Function
WE Level Control
with Write Suspend Function
Unused bits must be 1
*1
Partial
Size
A18 to A16
BL
Burst
Length
A15
M
Mode
0
1
A14 to A12
RL
Read
Latency
A11
BS
Burst
Sequence
A10
SW
Single
Write
A9
VE
Valid
Clock Edge
A8
—
—
A7
WC
Write Control
000
001
010
011
1xx
0
1
0
1
0
1
1
0
1
A6 to A0
—
—
1
*2
*2
*2
*2
*2
*2
*3
*4
*2
*2
*2
*5
*1
*5
*1
*1 : A22, A21, A8, and A6 to A0 must be all "1" in any cases.
*2 : It is prohibited to apply this key.
*3 : If M=0, all the registers must be set with appropriate Key input at the same time.
*4 : If M=1, PS must be set with appropriate Key input at the same time. Except for PS, all the other key inputs must
be "1".
*5 : Burst Read & Single Write is not supported at WE Single Clock Pulse Control.
56
MB84SF6H6H6L2-70
• Power Down
The Power Down is low power idle state controlled by CE2r. CE2r Low drives the device in power down mode
and mains low power idle state as long as CE2r is kept low. CE2r High resume the device from power down mode.
This device has three power down modes, Sleep, 16M Partial, and 32M Partial.
The selection of power down mode is set through CR Set sequence. Each mode has following data retention
features.
Mode
Data Retention Size
Retention Address
Sleep [default]
No
N/A
16M Partial
16M bit
000000h to 0FFFFFh
32M Partial
32M bit
000000h to 1FFFFFh
The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought
to Low for Power Down. It is not required to perform CR Set sequence to set to Sleep mode after power-up in
case of asynchronous operation.
57
MB84SF6H6H6L2-70
• Burst Read/Write Operation
Synchronous burst read/write operation provides faster memory access that synchronized to microcontroller or
system bus frequency. Configuration Register Set is required to perform burst read & write operation after powerup. Once CR Set sequence is performed to select synchronous burst mode, the device is configured to synchronous burst read/write operation mode with corresponding RL and BL that is set through CR Set sequence
together with operation mode. In order to perform synchronous burst read & write operation, it is required to
control new signals, CLK, ADV and WAIT that Low Power SRAMs don’t have.
• Burst Read Operation
CLK
ADDRESS
Valid
ADV
CE1r
OE
High
WE
DQ
RL
High-Z
Q1
QBL
Q2
BL
WAIT
High-Z
• Burst Write Operation
CLK
ADDRESS
Valid
ADV
CE1r
High
OE
WE
DQ
High-Z
WAIT
High-Z
RL-1
D1
D2
BL
58
DBL
MB84SF6H6H6L2-70
• CLK Input Function
The CLK is input signal to synchronize memory to microcontroller or system bus frequency during synchronous
burst read & write operation. The CLK input increments device internal address counter and the valid edge of
CLK is referred for latency counts from address latch, burst write data latch, and burst read data out. During
synchronous operation mode, CLK input must be supplied except for standby state and power down state. CLK
is don’t care during asynchronous operation.
• ADV Input Function
The ADV is input signal to indicate valid address presence on address inputs. It is applicable to synchronous
operation as well as asynchronous operation. ADV input is active during CE1r = L and CE1r = H disables ADV
input. All the address are determined on the positive edge of ADV.
During synchronous burst read/write operation, ADV = H disables all address inputs. Once ADV is brought to
High after valid address latch, it is inhibited to bring ADV Low until the end of burst or until burst operation is
terminated. ADV Low pulse is mandatory for synchronous burst read/write operation mode to latch the valid
address input.
During asynchronous operation, ADV = H also disables all address inputs. ADV can be tied to Low during
asynchronous operation and it is not necessary to control ADV to High.
• WAIT Output Function
The WAIT is output signal to indicate data bus status when the device is operating in synchronous burst mode.
During burst read operation, WAIT output is enabled after specified time duration from OE = L. WAIT output Low
indicates data out at next clock cycle is invalid, and WAIT output becomes High one clock cycle prior to valid
data out. During OE read suspend, WAIT output doesn’t indicate data bus status but carries the same level from
previous clock cycle (kept High) except for read suspend on the final data output. If final read data out is
suspended, WAIT output become high impedance after specified time duration from OE = H.
During burst write operation, WAIT output is enabled to High level after specified time duration from WE = L and
kept High for entire write cycles including WE write suspend. The actual write data latching starts on the
appropriate clock edge with respect to Valid Click Edge, Read Latency and Burst Length. During WE write
suspend, WAIT output doesn’t indicate data bus status but carries the same level from previous clock cycle (kept
High) except for write suspend on the final data input. If final write data in is suspended, WAIT output become
high impedance after specified time duration from WE = H.
This device doesn’t incur additional delay against accrossing device-row boundary or internal refresh orepation.
Therefore, the burst operation is always started after fixed latency with respect to Read Latency. And there is
no WAITting cycle asserted in the middle of burst operation except for burst suspend by OE brought to High or
WE brought to High. Thus, once WAIT output is enabled and brought to High, WAIT output keep High level until
the end of burst or until the burst operation is terminated.
When the device is operating in asynchronous mode, WAIT output is always in High Impedance.
59
MB84SF6H6H6L2-70
• Latency
Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming
available during synchronous burst read operation. It is set through CR Set sequence after power-up. Once
specific RL is set through CR Set sequence, write latency, that is the number of clock cycles between address
being latched and first write data being latched, is automatically set to RL-1. The burst operation is always started
after fixed latency with respect to Read Latency set in CR.
CLK
ADDRESS
0
Valid
1
2
3
4
5
6
Q1
Q2
Q3
Q4
Q5
D2
D3
D4
D5
D5
Q1
Q2
Q3
Q4
D2
D3
D4
D5
Q1
Q2
Q3
D2
D3
D4
ADV
CE1r
OE or WE
RL = 3
DQ [Out]
WAIT
High-Z
DQ [In]
WAIT
D1
High-Z
RL = 4
DQ [Out]
WAIT
High-Z
DQ [In]
WAIT
D1
High-Z
RL = 5
DQ [Out]
WAIT
High-Z
DQ [In]
WAIT
60
D1
High-Z
MB84SF6H6H6L2-70
• Address Latch by ADV
The ADV indicates valid address presence on address inputs. During synchronous burst read/write operation
mode, all the address are determined on the positive edge of ADV when CE1r = L. The specified minimum value
of ADV = L setup time and hold time against valid edge of clock where RL count begin must be satisfied for
appropriate RL counts. Valid address must be determined with specified setup time against either the negative
edge of ADV or negative edge of CE1r whichever comes late. And the determined valid address must not be
changed during ADV = L period.
• Burst Length
Burst Length is the number of word to be read or write during synchronous burst read/write operation as the
result of a single address latch cycle. It can be set on 8, 16 words boundary or continuous for entire address
through CR Set sequence. The burst type is sequential that is incremental decoding scheme within a boundary
address. Starting from initial address being latched, device internal address counter assign +1 to the previous
address until reaching the end of boundary address and then wrap round to least significant address (= 0). After
completing read data out or write data latch for the set burst length, operation automatically ended except for
continuous burst length. When continuous burst length is set, read/write is endless unless it is terminated by
the positive edge of CE1r.
• Single Write
Single Write is synchronous write operation with Burst Length =1. The device can be configured either to "Burst
Read & Single Write" or to "Burst Read & Burst Write" through CR set sequence. Once the device is configured
to "Burst Read & Single Write" mode, the burst length for syncronous write operation is always fixed 1 regardless
of BL values set in CR, while burst length for read is in accordance with BL values set in CR.
• Write Control
The device has two type of WE singal control method, "WE Level Control" and "WE Single Clock Pulse Control",
for synchronous write operation. It is configured through CR set sequence.
CLK
ADDRESS
0
Valid
1
3
2
4
5
6
D1
D2
D3
D4
D1
D2
D3
D4
ADV
RL = 5
CE1r
WE Level Control
WE
tWLD
DQ [In]
WAIT
tWLTV
High-Z
WE Single Clock Pulse Control
tWSCK
WE
tCKWH
DQ [In]
tWLTV
WAIT
High-Z
61
MB84SF6H6H6L2-70
• Burst Read Suspend
Burst read operation can be suspended by OE High pulse. During burst read operation, OE brought to High
suspends burst read operation. Once OE is brought to High with the specified set up time against clock where
the data being suspended, the device internal counter is suspended, and the data output become high impedance
after specified time duration. It is inhibited to suspend the first data out at the beginning of burst read.
OE brought to Low resumes burst read operation. Once OE is brought to Low, data output become valid after
specified time duration, and internal address counter is reactivated. The last data out being suspended as the
result of OE = H and first data out as the result of OE = L are the from the same address.
CLK
tCKOH tOSCK
tCKOH tOSCK
OE
tAC
tOHZ
Q1
DQ
tAC
tAC
Q2
Q2
tCKQX
tCKTV
tAC
tOLZ
Q3
tCKQX
Q4
tCKQX
WAIT
• Burst Write Suspend
Burst write operation can be suspended by WE High pulse. During burst write operation, WE brought to High
suspends burst write operation. Once WE is brought to High with the specified set up time against clock where
the data being suspended, device internal counter is suspended, data input is ignored. It is inhibited to suspend
the first data input at the beginning of burst write.
WE brought to Low resumes burst write operation. Once WE is brought to Low, data input become valid after
specified time duration, and internal address counter is reactivated. The write address of the cycle where data
being suspended and the first write address as the result of WE = L are the same address.
Burst write suspend function is available when the device is operating in WE level controlled burst write only.
CLK
tCKWH tWSCK
tCKWH tWSCK
WE
tDSCK
tDSCK
tDSCK
DQ
D1
tDHCK
WAIT
62
High
D2
D2
D3
tDHCK
tDHCK
tDSCK
D4
MB84SF6H6H6L2-70
• Burst Read Termination
Burst read operation can be terminated by CE1r brought to High. If BL is set on Continuous, burst read operation
is continued endless unless terminated by CE1r = H. It is inhibited to terminate burst read before first data out
is completed. In order to guarantee last data output, the specified minimum value of CE1r = L hold time from
clock edge must be satisfied. After termination, the specified minimum recovery time is required to start new
access.
CLK
ADDRESS
Valid
ADV
tTRB
tCKCLH
tCHZ
tCKOH
tOHZ
CE1r
OE
WAIT
High-Z
tAC
Q1
DQ
tCKQX
Q2
• Burst Write Termination
Burst write operation can be terminated by CE1r brought to High. If BL is set on Continuous, burst write operation
is continued endless unless terminated by CE1r = H. It is inhibited to terminate burst write before first data in
is completed. In order to guarantee last write data being latched, the specified minimum values of CE1r = L hold
time from clock edge must be satisfied. After termination, the specified minimum recovery time is required to
start new access.
CLK
ADDRESS
Valid
ADV
tTRB
tCKCLH
tCHZ
CE1r
tCKWH
WE
WAIT
DQ
tDSCK
High-Z
tDSCK
D1
tDHCK
D2
tDHCK
63
MB84SF6H6H6L2-70
3. AC Characteristics (Under Recommended Operating Conditions unless otherwise noted)
• Asynchronous Read Operation (Page mode)
Parameter
Symbol
Value
Min
Max
Unit
Notes
Read Cycle Time
tRC
70
1000
ns
*1, *2
CE1r Access Time
tCE
—
70
ns
*3
OE Access Time
tOE
—
40
ns
*3
Address Access Time
tAA
—
70
ns
*3, *5
ADV Access Time
tAV
70
ns
*3
LB, UB Access Time
tBA
—
30
ns
*3
Page Address Access Time
tPAA
—
20
ns
*3, *6
Page Read Cycle Time
tPRC
20
1000
ns
*1, *6, *7
Output Data Hold Time
tOH
5
—
ns
*3
CE1r Low to Output Low-Z
tCLZ
5
—
ns
*4
OE Low to Output Low-Z
tOLZ
0
—
ns
*4
LB, UB Low to Output Low-Z
tBLZ
0
—
ns
*4
CE1r High to Output High-Z
tCHZ
—
20
ns
*3
OE High to Output High-Z
tOHZ
—
20
ns
*3
LB, UB High to Output High-Z
tBHZ
—
20
ns
*3
Address Setup Time to CE1r Low
tASC
–5
—
ns
Address Setup Time to OE Low
tASO
10
—
ns
ADV Low Pulse Width
tVPL
10
—
ns
Address Hold Time from ADV High
tAHV
5
—
ns
Address Invalid Time
tAX
—
10
ns
*5, *9
Address Hold Time from CE1r High
tCHAH
–5
—
ns
*10
Address Hold Time from OE High
tOHAH
–5
—
ns
tCP
15
—
ns
CE1r High Pulse Width
*8
*1 : Maximum value is applicable if CE1r is kept at Low without change of address input of A3 to A22.
If needed by system operation, please contact local FUJITSU representative for the relaxation of 1µs limitation.
*2 : Address should not be changed within minimum tRC.
*3 : The output load 50 pF with 50 Ω termination to VCCQr × 0.5 V.
*4 : The output load 5pF without any other load.
*5 : Applicable to A3 to A22 when CE1r is kept at Low.
*6 : Applicable only to A0, A1 and A2 when CE1r is kept at Low for the page address access.
*7 : In case Page Read Cycle is continued with keeping CE1r stays Low, CE1r must be brought to High within
4 µs. In other words, Page Read Cycle must be closed within 4 µs.
*8 : tVPL is specified from the negative edge of either CE1r or ADV whichever comes late.
*9 : Applicable when at least two of address inputs among applicable are switched from previous state.
*10 : tRC (Min) and tPRC (Min) must be satisfied.
64
MB84SF6H6H6L2-70
• Asynchronous Write Operation
Value
Parameter
Symbol
Min
Max
Unit
Notes
Write Cycle Time
tWC
70
1000
ns
*1, *2
Address Setup Time
tAS
0
—
ns
*3
ADV Low Pulse Width
tVPL
10
—
ns
*4
Address Hold Time from ADV High
tAHV
5
—
ns
CE1r Write Pulse Width
tCW
45
—
ns
*3
WE Write Pulse Width
tWP
45
—
ns
*3
LB, UB Write Pulse Width
tBW
45
—
ns
*3
CE1r Write Recovery Time
tWRC
15
—
ns
*5
WE Write Recovery Time
tWR
15
1000
ns
*5
LB, UB Write Recovery Time
tBR
15
1000
ns
*5
Data Setup Time
tDS
15
—
ns
Data Hold Time
tDH
0
—
ns
OE High to CE1r Low Setup Time for Write
tOHCL
–5
—
ns
*6
OE High to Address Setup Time for Write
tOES
0
—
ns
*7
LB, UB Write Pulse Overlap
tBWO
30
—
ns
CE1r High Pulse Width
tCP
15
—
ns
*1 : Maximum value is applicable if CE1r is kept at Low without any address change. If the relaxation is needed by
system operation, please contact local FUJITSU representative for the relaxation of 1µs limitation.
*2 : Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time
(tWRC, tWR or tBR).
*3 : Write pulse is defined from High to Low transition of CE1r, WE or LB / UB, whichever occurs last.
*4 : tVPL is specified from the negative edge of either CE1r or ADV whichever comes late.
*5 : Write recovery is defined from Low to High transition of CE1r, WE or LB / UB, whichever occurs first.
*6 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns
after CE1r is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC
is met.
*7 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the
same time or before new address valid. Once read cycle is initiated, new write pulse should be input after
minimum tRC is met and data bus is in High-Z.
65
MB84SF6H6H6L2-70
• Synchoronous Operation - Clock Input (Burst mode)
Value
Parameter
Symbol
RL = 5
Clock Period
RL = 4
tCK
RL = 3
Unit
Notes
—
ns
*1
18
—
ns
*1
30
—
ns
*1
Min
Max
13
Clock High Time
tCKH
4
—
ns
Clock Low Time
tCKL
4
—
ns
Clock Rise/Fall Time
tCKT
—
3
ns
*2
Unit
Notes
*1 : Clock period is defined between valid clock edge.
*2 : Clock rise/fall time is defined between VIH Min and VIL Max.
• Synchronous Operation - Address Latch (Burst mode)
Value
Parameter
Symbol
Min
Max
Address Setup Time to ADV Low
tASVL
–5
—
ns
*1
Address Setup Time to CE1r Low
tASCL
–5
—
ns
*1
Address Hold Time from ADV High
tAHV
5
—
ns
ADV Low Pulse Width
tVPL
10
—
ns
*2
ADV Low Setup Time to CLK
tVSCK
5
—
ns
*3
ADV Low Setup Time to CE1r Low
tVLCL
5
—
ns
*1
CE1 Low Setup Time to CLK
tCLCK
5
—
ns
*3
ADV Low Hold Time from CLK
tCKVH
1
—
ns
*3
Burst End ADV High Hold Time from CLK
tVHVL
13
—
ns
*1 : tASCL is applicable if CE1 brought to Low after ADV is brought to Low under the condition where tVLCL is satisfied.
The both of tASCL and tASVL must be satisfied if tVLCL is not satisfied.
*2 : tVPL is specified from the negative edge of either CE1 or ADV whichever comes late.
*3 : Applicable to the 1st valid clock edge.
66
MB84SF6H6H6L2-70
• Synchronous Read Operation (Burst mode)
Value
Parameter
Symbol
Unit
Min
Max
Notes
Burst Read Cycle Time
tRCB
—
8000
ns
CLK Access Time
tAC
—
11
ns
*1
Output Hold Time from CLK
tCKQX
3
—
ns
*1
CE1r Low to WAIT Low
tCLTL
5
20
ns
*1
OE Low to WAIT Low
tOLTL
0
20
ns
*1
ADV Low to WAIT Low
tVLTL
0
20
ns
*1
CLK to WAIT Valid Time
tCKTV
—
11
ns
*1
WAIT Valid Hold Time from CLK
tCKTX
3
—
ns
*1
CE1r Low to Output Low-Z
tCLZ
5
—
ns
*2
OE Low to Output Low-Z
tOLZ
0
—
ns
*2
LB, UB Low to Output Low-Z
tBLZ
0
—
ns
*2
CE1r High to Output High-Z
tCHZ
—
20
ns
*1
OE High to Output High-Z
tOHZ
—
20
ns
*1
LB, UB High to Output High-Z
tBHZ
—
20
ns
*1
CE1r High to WAIT High-Z
tCHTZ
—
20
ns
*1
OE High to WAIT High-Z
tOHTZ
—
20
ns
*1
OE Low Setup Time to 1st Data-out
tOLQ
30
—
ns
UB, LB Setup Time to 1st Data-out
tBSQ
26
—
ns
OE Setup Time to CLK
tOSCK
5
—
ns
OE Hold Time from CLK
tCKOH
5
—
ns
Burst End CE1r Low Hold Time from CLK
tCKCLH
5
—
ns
Burst End UB, LB Hold Time from CLK
tCKBH
5
—
ns
26
—
ns
*4
70
—
ns
*4
BL = 8,16
Burst Terminate Recovery Time
*3
tTRB
BL = Continuous
*1 : The output load 50 pF with 50 Ω termination to VCCQr × 0.5 V.
*2 : The output load 5 pF without any other load.
*3 : Once they are determined, they must not be changed until the end of burst.
*4 : Defined from the Low to High transition of CE1r to the High to Low transition of either ADV or CE1r whichever
occurs late.
67
MB84SF6H6H6L2-70
• Synchronous Write Operation (Burst mode)
Value
Parameter
Symbol
Unit
Min
Max
Notes
Burst Write Cycle Time
tWCB
—
8000
ns
Data Setup Time to Clock
tDSCK
5
—
ns
Data Hold Time from CLK
tDHCK
3
—
ns
WE Low Setup Time to 1st Data In
tWLD
30
—
ns
UB, LB Setup Time for Write
tBS
–5
—
ns
WE Setup Time to CLK
tWSCK
5
—
ns
WE Hold Time from CLK
tCKWH
5
—
ns
CE1r Low to WAIT High
tCLTH
5
20
ns
*2
WE Low to WAIT High
tWLTH
0
20
ns
*2
CE1r High to WAIT High-Z
tCHTZ
—
20
ns
*2
WE High to WAIT High-Z
tWHTZ
—
20
ns
*2
Burst End CE1r Low Hold Time from CLK
tCKCLH
5
—
ns
Burst End CE1r High Setup Time to next CLK
tCHCK
5
—
ns
Burst End UB, LB Hold Time from CLK
tCKBH
5
—
ns
Burst Write Recovery Time
tWRB
26
BL = 8,16
tTRB
26
BL = Continuous
tTRB
70
*1
ns
*3
—
ns
*4
—
ns
*4
Burst Terminate Recovery Time
*1 : Defined from the valid input edge to the High to Low transition of either ADV, CE1r, or WE, whichever occurs
last. And once they are determined, they must not be changed until the end of burst.
*2 : The output load 50 pF with 50 Ω termination to VCCQr × 0.5 V.
*3 : The output load 5 pF without any other load.
*4 : Defined from the valid clock edge where last data-in being latched at the end of burst write to the High to Low
transition of either ADV or CE1r whichever occurs late for the next access.
*5 : Defined from the Low to High transition of CE1r to the High to Low transition of either ADV or CE1r whichever
occurs late for the next access.
68
MB84SF6H6H6L2-70
• Power Down Parameters
Value
Parameter
Symbol
Min
Max
Unit
Note
CE2r Low Setup Time for Power Down Entry
tCSP
20
—
ns
*1
CE2r Low Hold Time after Power Down Entry
tC2LP
70
—
ns
*1
CE1r High Hold Time following CE2r High
after Power Down Exit [SLEEP mode only]
tCHH
300
—
µs
*1
CE1r High Hold Time following CE2r High
after Power Down Exit [not in SLEEP mode]
tCHHP
1
—
µs
*2
CE1r High Setup Time following CE2r High
after Power Down Exit
tCHS
0
—
ns
*1
Unit
Note
*1 : Applicable also to power-up.
*2 : Applicable when Partial mode is set.
• Other Timing Parameters
Value
Parameter
Symbol
Min
Max
CE1r High to OE Invalid Time for Standby Entry
tCHOX
10
—
ns
CE1r High to WE Invalid Time for Standby Entry
tCHWX
10
—
ns
CE2r High Hold Time after Power-up
tC2HL
50
—
µs
CE1r High Hold Time following CE2r High after Power-up
tCHH
300
—
µs
tT
1
25
ns
Input Transition Time (except for CLK)
*1
*2, *3
*1 : Some data might be written into any address location if tCHWX (Min) is not satisfied.
*2 : Except for clock input transition time.
*3 : The Input Transition Time (tT) at AC testing is shown in below. If actual tT is longer than specified values, it may
violate AC specification of some timing parameters.
69
MB84SF6H6H6L2-70
• AC Test Conditions
Description
Symbol
Test Setup
Value
Unit
Input High Level
VIH
—
VCCQr × 0.8
V
Input Low Level
VIL
—
VCCQr × 0.2
V
VREF
—
VCCQr × 0.5
V
5
ns
tT
Between VIL and VIH
3
ns
Input Timing Measurement Level
Async.
Input Transition Time
Sync.
• AC MEASUREMENT OUTPUT LOAD CIRCUIT
VCCr × 0.5 V
50 Ω
VCCr
VSS
VCCQr
0.1 µF
0.1 µF
VSS
70
DEVICE
UNDER
TEST
OUT
50 pF
Note
MB84SF6H6H6L2-70
• Asynchronous Read Timing #1-1 (Basic Timing)
tRC
ADDRESS VALID
ADDRESS
ADV
Low
tASC
tCE
tCHAH
tASC
tCP
CE1r
tOE
tCHZ
OE
tOHZ
tBA
LB / UB
tOLZ
DQ
(Output)
tBHZ
tBLZ
VALID DATA OUTPUT
tOH
Note : This timing diagram assumes CE2r = H and WE = H.
• Asynchronous Read Timing #1-2 (Basic Timing)
tRC
ADDRESS
ADDRESS VALID
tAHV
tAV
tVPL
ADV
tASC
tASC
tCE
tCP
CE1r
tCHZ
tOE
OE
tOHZ
tBA
LB / UB
DQ
(Output)
tOLZ
tBHZ
tBLZ
VALID DATA OUTPUT
tOH
Note : This timing diagram assumes CE2r = H and WE = H.
71
MB84SF6H6H6L2-70
• Asynchronous Read Timing #2 (OE & Address Access)
tAx
tRC
ADDRESS
tRC
ADDRESS VALID
ADDRESS VALID
CE1r
tOHAH
tAA
tAA
Low
tASO
tOE
OE
LB / UB
tOLZ
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
tOHZ
VALID DATA OUTPUT
Note : This timing diagram assumes CE2r = H, ADV = L and WE = H.
• Asynchronous Read Timing #3 (LB / UB Byte Access)
tRC
tAX
ADDRESS
tAx
ADDRESS VALID
tAA
CE1r,
OE
Low
tBA
tBA
LB
tBA
UB
tBHZ
tBLZ
tBHZ
tOH
tBLZ
tOH
DQ7 to DQ0
(Output)
DQ15 to DQ8
(Output)
VALID DATA
OUTPUT
VALID DATA
OUTPUT
tBLZ
VALID DATA OUTPUT
Note : This timing diagram assumes CE2r = H, ADV = L and WE = H.
72
tOH
tBHZ
MB84SF6H6H6L2-70
• Asynchronous Read Timing #4 (Page Address Access after CE1r Control Access)
tRC
ADDRESS
(A22 to A3)
ADDRESS VALID
tRC
ADDRESS
(A2 to A0)
ADDRESS VALID
tPRC
tPRC
ADDRESS
ADDRESS
tPAA
tASC
tPRC
ADDRESS
tPAA
tPAA
tCHAH
ADV
CE1r
tCHZ
tCE
OE
LB / UB
tCLZ
tOH
tOH
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
(Page Access)
VALID DATA OUTPUT
(Normal Access)
Note : This timing diagram assumes CE2r = H and WE = H.
• Asynchronous Read Timing #5 (Random and Page Address Access)
tRC
ADDRESS
(A22 to A3)
ADDRESS VALID
tRC
ADDRESS
(A2 to A0)
ADDRESS
VALID
tAx
ADDRESS VALID
tRC
tPRC
tPRC
ADDRESS
VALID
ADDRESS
VALID
tAA
CE1r
tRC
tAX
tPAA
ADDRESS
VALID
tAA
tPAA
Low
tASO
tOE
OE
tBA
LB / UB
DQ
(Output)
tOLZ
tBLZ
tOH
tOH
VALID DATA OUTPUT
(Normal Access)
tOH
tOH
VALID DATA OUTPUT
(Page Access)
Notes : • This timing diagram assumes CE2r = H, ADV = L and WE = H.
• Either or both LB and UB must be Low when both CE1r and OE are Low.
73
MB84SF6H6H6L2-70
• Asynchronous Write Timing #1-1 (Basic Timing)
tWC
ADDRESS
ADV
ADDRESS VALID
Low
tAS
tCW
tWRC
tAS
CE1r
tAS
tWP
tWR
tAS
WE
tAS
tBW
tBR
tAS
LB, UB
tOHCL
OE
tDS
tDH
DQ
(Input)
VALID DATA INPUT
Note : This timing diagram assumes CE2r = H and ADV = L.
• Asynchronous Write Timing #1-2 (Basic Timing)
tWC
ADDRESS
ADDRESS VALID
tVP04.3.12L
ADV
tAS
tAHV
tCW
tWRC
tAS
CE1r
tAS
tWP
tWR
tAS
WE
tAS
tBW
tBR
LB, UB
tOHCL
OE
tDS
tDH
DQ
(Input)
VALID DATA INPUT
Note : This timing diagram assumes CE2r = H.
74
tAS
MB84SF6H6H6L2-70
• Asynchronous Write Timing #2 (WE Control)
tWC
tWC
ADDRESS VALID
ADDRESS
ADDRESS VALID
tOHAH
CE1r
Low
tAS
tWP
tWR
tAS
tWP
tWR
WE
LB, UB
tOES
OE
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
VALID DATA INPUT
VALID DATA INPUT
Note : This timing diagram assumes CE2r = H and ADV = L.
• Asynchronous Write Timing #3-1 (WE / LB / UB Byte Write Control)
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1r
tWC
Low
tAS
tWP
tAS
tWP
WE
tBR
LB
tBR
UB
tDS
tDH
DQ0 to DQ7
(Input)
DQ8 to DQ15
(Input)
VALID DATA INPUT
tDS
tDH
VALID DATA INPUT
Note : This timing diagram assumes CE2r = H, ADV = L and OE = H.
75
MB84SF6H6H6L2-70
• Asynchronous Write Timing #3-2 (WE / LB / UB Byte Write Control)
tWC
ADDRESS
CE1r
tWC
ADDRESS VALID
ADDRESS VALID
Low
tWR
tWR
WE
tAS
tBW
LB
tAS
tBW
UB
tDS
tDH
DQ0 to DQ7
(Input)
tDS
VALID DATA INPUT
DQ8 to DQ15
(Input)
tDH
VALID DATA INPUT
Note : This timing diagram assumes CE2r = H, ADV = L and OE = H.
• Asynchronous Write Timing #3-3 (WE / LB / UB Byte Write Control)
tWC
ADDRESS
CE1r
tWC
ADDRESS VALID
ADDRESS VALID
Low
WE
tAS
tBW
tBR
LB
tAS
tBW
tBR
UB
tDS
tDH
DQ0 to DQ7
(Input)
VALID DATA INPUT
tDS
tDH
DQ8 to DQ15
(Input)
VALID DATA INPUT
Note : This timing diagram assumes CE2r = H, ADV = L and OE = H.
76
MB84SF6H6H6L2-70
• Asynchronous Write Timing #3-4 (WE / LB / UB Byte Write Control)
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1r
Low
WE
tAS
tBW
tBR
tAS
tBW
tBR
LB
tBWO
DQ0 to DQ7
(Input)
tDS
tDH
tDS
VALID
DATA INPUT
tAS
tBW
tDH
VALID
DATA INPUT
tBR
tAS
tBR
tBWO
tBW
UB
tDS
DQ8 to DQ15
(Input)
tDS
tDH
tDH
VALID
DATA INPUT
VALID
DATA INPUT
Note : This timing diagram assumes CE2r = H, ADV = L and OE = H.
• Asynchronous Read / Write Timing #1-1 (CE1r Control)
tWC
ADDRESS
tRC
WRITE ADDRESS
tAS
tCHAH
tCW
READ ADDRESS
tWRC
tASC
tCE
tCHAH
CE1r
tCP
tCP
WE
UB, LB
tOHCL
OE
tCHZ
tOH
tDS
tDH
tCLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
Notes : • This timing diagram assumes CE2r = H and ADV = L.
• Write address is valid from either CE1r or WE of last falling edge.
77
MB84SF6H6H6L2-70
• Asynchronous Read / Write Timing #1-2 (CE1r / WE / OE Control)
ADDRESS
tWC
tRC
WRITE ADDRESS
READ ADDRESS
tCE
tCHAH
tAS
tCHAH
tWR
tASC
CE1r
tCP
tCP
tWP
WE
UB, LB
tOE
tOHCL
OE
tCHZ
tOH
tDS
tOH
tOLZ
tDH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
READ DATA OUTPUT
Notes : • This timing diagram assumes CE2r = H and ADV = L.
• OE can be fixed Low during write operation if it is CE1r controlled write at
Read-Write-Read sequence.
• Asynchronous Read / Write Timing #2 (OE, WE Control)
ADDRESS
tWC
tRC
WRITE ADDRESS
READ ADDRESS
tOHAH
CE1r
Low
tAS
WE
tOHAH
tAA
tWR
tWP
tOES
UB, LB
tASO
OE
tOHZ
tOH
tDS
tDH
tOE
tOLZ
tOHZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
Notes : • This timing diagram assumes CE2r = H and ADV = L.
• CE1r can be tied to Low for WE and OE controlled operation.
78
READ DATA OUTPUT
MB84SF6H6H6L2-70
• Asynchronous Read / Write Timing #3 (OE, WE, LB, UB Control)
tWC
ADDRESS
tRC
WRITE ADDRESS
READ ADDRESS
tAA
CE1r
Low
tOHAH
tOHAH
WE
tOES
tAS
tBR
tBW
tBA
UB, LB
tASO
tBHZ
OE
tDS
tOH
tBHZ
tOH
tBLZ
tDH
DQ
READ DATA OUTPUT
READ DATA OUTPUT
WRITE DATA INPUT
Notes : • This timing diagram assumes CE2r = H and ADV = L.
• CE1r can be tied to Low for WE and OE controlled operation.
• Clock Input Timing
tCK
CLK
tCK
tCKH
tCKL
tCKT
tCKT
Notes : • Stable clock input must be required during CE1r = L.
• tCK is defined between valid clock edge.
• tCKT is defined between VIH Min and VIL Max.
79
MB84SF6H6H6L2-70
• Address Latch Timing (Synchronous Mode)
Case #1
Case #2
CLK
ADDRESS
Valid
Valid
tASCL
tCKVH
tVSCK
tAHV
tASVL
tVSCK
tCKVH
tAHV
ADV
tVPL
tVLCL
CE1r
tCLCK
tVPL
Low
Notes : • Case #1 is the timing when CE1r is brought to Low after ADV is brought to Low.
Case #2 is the timing when ADV is brought to Low after CE1r is brought to Low.
• tVPL is specified from the negative edge of either CE1r or ADV whichever comes late.
At least one valid clock edge must be input during ADV = L.
• tVSCK and tCLCK are applied to the 1st valid clock edge during ADV = L.
80
MB84SF6H6H6L2-70
• Synchronous Read Timing #1 (OE Control)
RL=5
CLK
tRCB
ADDRESS
tASVL
Valid
tVSCK
Valid
tAHV
tASVL
tVSCK tCKVH
tCKVH
ADV
tVPL
tVHVL
tASCL
tVPL
tASCL
CE1r
tCLCK
tCLCK
tCKOH
tCP
OE
tOLQ
WE
High
tCKBH
tBLQ
LB, UB
tCKTV
WAIT
High-Z
tOLTL
DQ
tOHTZ
tCKTX
tAC
tAC
Q1
High-Z
tOLZ
tCKQX
tOHZ
tAC
QBL
tCKQX
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
81
MB84SF6H6H6L2-70
• Synchronous Read Timing #2 (CE1r Control)
RL=5
CLK
tRCB
ADDRESS
tASVL
Valid
Valid
tVSCK
tAHV
tASVL
tCKVH
tAHV
tVSCK
tCKVH
ADV
tVPL
tVHVL
tASCL
tVPL
tASCL
CE1r
tCP
tCLCK
tCKCLH
tCLCK
OE
WE
High
tCKBH
LB, UB
tCKTV
tCHTZ
tCLTL
WAIT
tCLTL
DQ
tCLZ
tCKTX
tAC
tAC
tAC
tCHZ
Q1
QBL
tCKQX
tCKQX
tCLZ
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
82
MB84SF6H6H6L2-70
• Synchronous Read Timing #3 (ADV Control)
RL = 5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tVSCK
tASVL
tCKVH
tAHV
tVSCK
tCKVH
ADV
tVPL
CE1r
Low
OE
Low
WE
High
tVHVL
tVPL
LB, UB
tVLTL
tCKTV
tVLTL
WAIT
tCKTX
DQ
tAC
tAC
Q1
tCKQX
tAC
QBL
tCKQX
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
83
MB84SF6H6H6L2-70
• Synchronous Write Timing #1 (WE Level Control)
RL = 5
CLK
tWCB
ADDRESS
tASVL
Valid
Valid
tAHV
tVSCK
tASVL
tCKVH
tVHVL
tWRB
ADV
tVPL
tAHV
tCKVH
tVPL
tASCL
tASCL
tVSCK
tCLCK
CE1r
tCLCK
OE
tCP
High
tWLD
tCKWH
WE
tBS
tCKBH
LB, UB
WAIT
High-Z
tWLTH
DQ
tDSCK
tDSCK
D1
tDHCK
tDSCK
D2
tWHTZ
DBL
tDHCK
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
84
tBS
MB84SF6H6H6L2-70
• Synchronous Write Timing #2 (WE Single Clock Pulse Control)
RL = 5
CLK
tWCB
ADDRESS
Valid
tASVL
Valid
tAHV
tVSCK
tASVL
tCKVH
tAHV
tVSCK
tCKVH
tVHVL
tWRB
ADV
tVPL
tVPL
tCLCK
tASCL
tASCL
CE1r
tCLCK
tCP
tCKCLH
High
OE
tWSCK
tCKWH
tWSCK
tCKWH
WE
tBS
tCKBH
tBS
LB, UB
WAIT
High-Z
tWLTH
DQ
tDSCK
tDSCK
D1
tDHCK
tDSCK
D2
tCHTZ
tWLTH
DBL
tDHCK
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
85
MB84SF6H6H6L2-70
• Synchronous Write Timing #3 (ADV Control)
RL = 5
CLK
tWCB
ADDRESS
Valid
tASVL
tVSCK
Valid
tAHV
tASVL
tCKVH
ADV
tVSCK
tVHVL
tVPL
tAHV
tCKVH
tVPL
tWRB
CE1r
High
OE
WE
tBS
tCKBH
tBS
LB, UB
High
WAIT
tDSCK
DQ
tDSCK
D1
tDHCK
tDSCK
D2
DBL
tDHCK
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
86
MB84SF6H6H6L2-70
• Synchronous Write Timing #4 (WE Level Control, Single Write)
RL = 5
CLK
tWCB
ADDRESS
tASVL
Valid
Valid
tAHV
tVSCK
tASVL
tVSCK
tCKVH
tVHVL
tWRB
ADV
tVPL
tCKVH
tVPL
tASCL
tASCL
tAHV
tCLCK
CE1r
tCLCK
OE
tCP
High
tWLD
tCKWH
WE
tBS
tCKBH
tBS
LB, UB
WAIT
High-Z
tWLTH
DQ
tDSCK
tWHTZ
tWLTH
D1
tDHCK
Notes : • This timing diagram assumes CE2r = H, the valid clock edge on rising edge and single write
operation.
• Write data is latched on the valid clock edge.
87
MB84SF6H6H6L2-70
• Synchronous Read to Write Timing #1 (CE1 Control)
RL = 5
CLK
tWCB
ADDRESS
Valid
tASVL
ADV
tAHV
tVSCK
tCKVH
tVHVL
tCKCLH
tVPL
tCLCK
tASCL
tCKCLH
CE1r
tCP
OE
WE
tCKBH
tBS
tCKBH
LB, UB
tCHTZ
WAIT
tCHZ
tAC
DQ
QBL-1
tCKQX
QBL
tCKQX
tCLTH
tDSCK
tDSCK
D1
tDHCK
tDSCK
D2
tDHCK
tDSCK
D3
tDHCK
DBL
tDHCK
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
88
MB84SF6H6H6L2-70
• Synchronous Read to Write Timing #2(ADV Control)
RL = 5
CLK
ADDRESS
Valid
tASVL
tVSCK
tAHV
tCKVH
ADV
tVPL
tVHVL
CE1r
tCKOH
OE
tWLD
tCKWH
WE
tCKBH
tBS
tCKBH
LB, UB
tOHTZ
WAIT
tOHZ
tAC
DQ
QBL-1
tCKQX
QBL
tCKQX
tWLTH
tDSCK
tDSCK
tDSCK
tDSCK
D1
D2
D3
tDHCK
tDHCK
tDHCK
DBL
tDHCK
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
89
MB84SF6H6H6L2-70
• Synchronous Write to Read Timing #1 (CE1r Control)
RL=5
CLK
ADDRESS
Valid
tASVL
tVSCK
tAHV
tCKVH
ADV
tVPL
tASCL
tCKCLH
CE1r
tCP
tCLCK
tWRB
OE
WE
tCKBH
LB, UB
tCKTV
High-Z
WAIT
tDSCK
DQ
tDSCK
DBL-1
tDHCK
tCHTZ
tCLTL
DBL
tDHCK
tCLZ
tCKTX
tAC
tAC
Q1
Q2
tCKQX
tCKQX
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
90
MB84SF6H6H6L2-70
• Synchronous Write to Read Timing #2 (ADV Control)
RL = 5
CLK
ADDRESS
Valid
tASVL
tVSCK
tAHV
tCKVH
ADV
tVPL
tWRB
Low
CE1r
OE
tOLQ
tCKWH
WE
tCKBH
tBLQ
LB, UB
tCKTV
High-Z
WAIT
tDSCK
DQ
tDSCK
DBL-1
tDHCK
tWHTZ
tOLTL
DBL
tDHCK
tOLZ
tCKTX
tAC
tAC
Q1
Q2
tCKQX
tCKQX
Note : This timing diagram assumes CE2r = H, the valid clock edge on rising edge and BL = 8 or 16.
91
MB84SF6H6H6L2-70
• POWER-UP Timing #1
CE1r
*2
tCHH*3
CE2r
*2
VCCQr
VCCQ Min*1
0V
VCCr
VCC Min*1,*2
0V
*1 : VCCQr shall be applied and reach the specified minimum level prior to VCCr applied.
*2 : The both of CE1r and CE2r shall be brought to High together with VCCQr prior to VCCr applied.
Otherwise POWER-UP Timing#2 must be applied for proper operation.
*3 : The tCHH specifies after VCCr reaches specified minimum level and applicable to both CE1r and CE2r.
• POWER-UP Timing #2
CE1r
*3
tCHS
tC2HL*2
tCSP
tC2LP
tCHH
CE2r
tC2HL*2
VCCQr
VCCQr Min*1
0V
VCCr Min*1
VCCr
0V
*1 : VCCQr shall be applied and reach specified minimum level prior to VCC applied.
*2 : The tC2HL specifies from CE2r Low to High transition after VCCr reaches specified minimum level.
If CE2r became High prior to VCCr reached specified minimum level, tC2HL is defined from VCCr minimum.
*3 : CE1r shall be brought to High prior to or together with CE2r Low to High transition.
92
MB84SF6H6H6L2-70
• POWER DOWN Entry and Exit Timing
CE1r
tCHS
CE2r
tCSP
tC2LP
tCHH (tCHHP)
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Note : This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be
satisfied and Power-Down program was not performed prior to this reset.
• Standby Entry Timing after Read or Write
CE1r
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode.
If either of timing is not satisfied, it takes tRC (Min) period for Standby mode from CE1r Low to High
transition.
93
MB84SF6H6H6L2-70
• Configuration Register Set Timing #1 (Asynchronous Operation)
ADDRESS
tRC
tWC
tWC
tWC
tWC
tWC
MSB*1
MSB*1
MSB*1
MSB*1
MSB*1
Key*2
tCP
tCP
tCP
tCP
tCP*3
(tRC)
tCP
CE1r
OE
WE
LB, UB
DQ*3
RDa
Cycle #1
RDa
RDa
Cycle #2
Cycle #3
X
Cycle #4
X
Cycle #5
RDb
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #5.
*2 : The address key must confirm the format specified in FUNCTIONAL DESCRIPTION. If not, the
operation and data are not guaranteed.
*3 : After tCP or tRC following Cycle #6, the Configuration Register Set is completed and returned to
the normal operation. tCP and tRC are applicable to returning to asynchronous mode and to
synchronous mode respectively.
94
MB84SF6H6H6L2-70
• WE Configuration Register Set Timing #2 (Synchronous Operation)
CLK
ADDRESS MSB
MSB
tRCB
MSB
tWCB
MSB
tWCB
MSB
tWCB
Key
tWCB
tRCB
ADV
tTRB
tTRB
tTRB
tTRB
tTRB
tTRB
CE1r
OE
WE
LB, UB
RL
DQ
RL-1
RL-1
RDa
RDa
RDa
Cycle#1
Cycle#2
Cycle#3
RL-1
RL-1
X
Cycle#4
RL
X
Cycle#5
RDb
Cycle#6
Notes : • The all address inputs must be High from Cycle #1 to #5.
• The address key must confirm the format specified in FUNCTIONAL DESCRIPTION. If not,
the operation and data are not guaranteed.
• After tTRB following Cycle #6, the Configuration Register Set is completed and returned to the
normal operation.
95
MB84SF6H6H6L2-70
■ PIN CAPACITANCE
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
Input Capacitance
CIN
VIN = 0


20.0
pF
Output Capacitance
COUT
VOUT = 0


25.0
pF
Control Pin Capacitance
CIN2
VIN = 0


25.0
pF
Note: Test conditions TA = +25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of package create acute angles.
■ CAUTION
• The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when
autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET.
• Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group
Protection” command.
96
MB84SF6H6H6L2-70
■ ORDERING INFORMATION
MB84SF6H6H6L
2
-70
PBS
PACKAGE TYPE
PBS = 115-ball BGA
SPEED OPTION
Device Revision
DEVICE NUMBER/DESCRIPTON
128Mega-bit (8M x 16bit) Burst Flash Memory
1.8V-only Read, Program, and Erase
128Mega-bit (8M x 16bit) Burst Flash Memory
1.8V-only Read, Program, and Erase
128 Mega-bit (8M x 16bit) FCRAM
1.8V I/O Supply Voltage
3.0V Core Supply Voltage
97
MB84SF6H6H6L2-70
■ PACKAGE DIMENSION
115-ball plastic FBGA
(BGA-115P-M03)
12.00±0.10(.472±.004)
0.20(.008) S B
B
1.25±0.10
(Seated height)
(.049±.004)
0.80(.031)
REF
0.40(.016)
REF
10
9
8
7
6
5
4
3
2
1
0.80(.031)
REF
A
9.00±0.10
(.354±.004)
0.40(.016)
REF
0.08(.003) S
INDEX-MARK AREA
0.10±0.05
(Stand off)
(.004±.002)
P N M L K J H G F E D C B A
S
+.010
115-ø0.40 –0.05
0.20(.008) S A
115-ø.016
+.004
–.002
ø0.08(.003)
M
S A B
0.08(.003) S
C
2003 FUJITSU LIMITED B115003S-c-1-1
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
98
MB84SF6H6H6L2-70
FUJITSU LIMITED
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