LTC1290
Single Chip 12-Bit Data
Acquisition System
U
DESCRIPTIO
FEATURES
■
■
■
■
■
Software Programmable Features
– Unipolar/Bipolar Conversion
– Four Differential/Eight Single-Ended Inputs
– MSB- or LSB-First Data Sequence
– Variable Data Word Length
– Power Shutdown
Built-In Sample-and-Hold
Single Supply 5V or ±5V Operation
Direct Four-Wire Interface to Most MPU Serial Ports
and All MPU Parallel Ports
50kHz Maximum Throughput Rate
U
KEY SPECIFICATIO S
■
■
■
Resolution: 12 Bits
Fast Conversion Time: 13µs Max Over Temp
Low Supply Current: 6.0mA
The LTC®1290 is a data acquisition component which
contains a serial I/O successive approximation A/D converter. It uses LTCMOSTM switched capacitor technology
to perform either 12-bit unipolar or 11-bit plus sign bipolar
A/D conversions. The 8-channel input multiplexer can be
configured for either single-ended or differential inputs (or
combinations thereof). An on-chip sample-and-hold is
included for all single-ended input channels. When the
LTC1290 is idle it can be powered down with a serial word
in applications where low power consumption is desired.
The serial I/O is designed to be compatible with industry
standard full duplex serial interfaces. It allows either MSBor LSB-first data and automatically provides 2's complement output coding in the bipolar mode. The output data
word can be programmed for a length of 8, 12 or 16 bits.
This allows easy interface to shift registers and a variety of
processors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOS is a trademark of Linear Technology Corporation.
UO
TYPICAL APPLICATI
12-Bit 8-Channel Sampling Data Acquisition System
SINGLE-ENDED INPUT
0V TO 5V OR ±5V
±15V OVERVOLTAGE RANGE*
1k
•
•
•
VCC
CH0
CH1
ACLK
CH2
SCLK
CH3
DIN
DIFFERENTIAL INPUT (+)
CH4
DOUT
±5V COMMON MODE RANGE (–)
CH5
CS
CH6
REF +
CH7
REF –
COM
V–
•
•
•
LTC1290
DGND
+
5V
22µF
TANTALUM
1N5817
TO AND FROM
MICROPROCESSOR
1N4148
4.7µF
TANTALUM
+
LT ®1027
8V TO 40V
1µF
–5V
AGND
1N5817
0.1µF
1290 • TA01
* FOR OVERVOLTAGE PROTECTION ON ONLY ONE CHANNEL LIMIT THE INPUT CURRENT TO 15mA. FOR OVERVOLTAGE PROTECTION
ON MORE THAN ONE CHANNEL LIMIT THE INPUT CURRENT TO 7mA PER CHANNEL AND 28mA FOR ALL CHANNELS. (SEE SECTION ON
OVERVOLTAGE PROTECTION IN THE APPLICATIONS INFORMATION SECTION.) CONVERSION RESULTS ARE NOT VALID WHEN THE SELECTED
OR ANY OTHER CHANNEL IS OVERVOLTAGED (VIN < V – OR VIN > VCC).
1
LTC1290
W W
W
AXI U
U
ABSOLUTE
RATI GS (Notes 1, 2)
Supply Voltage (VCC) to GND or V – ........................ 12V
Negative Supply Voltage (V –) .................... – 6V to GND
Voltage
Analog/Reference Inputs ......... (V –) – 0.3V to VCC + 0.3V
Digital Inputs ........................................ – 0.3V to 12V
Digital Outputs ........................... – 0.3V to VCC + 0.3V
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1290BC, LTC1290CC, LTC1290DC .... 0°C to 70°C
LTC1290BI, LTC1290CI, LTC1290DI .... – 40°C to 85°C
LTC1290BM, LTC1290CM,
LTC1290DM....................................... – 55°C to 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
W
U
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
CH0
1
20 VCC
CH1
2
19 ACLK
CH2
3
18 SCLK
CH3
4
17 DIN
CH4
5
16 DOUT
CH5
6
15 CS
CH6
7
14 REF +
CH7
8
13 REF –
COM
9
12 V –
DGND 10
J PACKAGE
20-LEAD CERAMIC DIP
11 AGND
N PACKAGE
20-LEAD PDIP
TJMAX = 150°C, θJA = 80°C/W (J)
TJMAX = 110°C, θJA = 100°C/W (N)
ORDER PART
NUMBER
LTC1290BMJ
LTC1290CMJ
LTC1290DMJ
LTC1290BIJ
LTC1290CIJ
LTC1290DIJ
LTC1290BIN
LTC1290CIN
LTC1290DIN
LTC1290BCN
LTC1290CCN
LTC1290DCN
ORDER PART
NUMBER
TOP VIEW
CH0 1
20 VCC
CH1 2
19 ACLK
CH2 3
18 SCLK
CH3 4
17 DIN
CH4 5
16 DOUT
CH5 6
15 CS
CH6 7
14 REF +
CH7 8
13 REF –
COM 9
12 V –
DGND 10
11 AGND
SW PACKAGE
20-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 130°C/W (SW)
U
U W
CO VERTER A D ULTIPLEXER CHARACTERISTICS
LTC1290B
TYP
MAX
MIN
(Note 3)
LTC1290C
TYP
MAX
MIN
LTC1290D
TYP
MAX
PARAMETER
CONDITIONS
Offset Error
(Note 4)
●
±1.5
±1.5
±1.5
LSB
Linearity Error (INL)
(Notes 4,5)
●
±0.5
±0.5
±0.75
LSB
Gain Error
(Note 4)
●
±0.5
±1.0
±4.0
LSB
●
12
12
12
Bits
Minimum Resolution for Which
No Missing Codes are Guaranteed
MIN
LTC1290BCSW
LTC1290CCSW
LTC1290DCSW
LTC1290BISW
LTC1290CISW
LTC1290DISW
(V – ) – 0.05V to VCC + 0.05V (V –) – 0.05V to VCC + 0.05V (V –) – 0.05V to VCC + 0.05V
UNITS
Analog and REF Input Range
(Note 7)
On Channel Leakage Current
(Note 8)
On Channel = 5V
Off Channel = 0V
●
±1
±1
±1
µA
On Channel = 0V
Off Channel = 5V
●
±1
±1
±1
µA
On Channel = 5V
Off Channel = 0V
●
±1
±1
±1
µA
On Channel = 0V
Off Channel = 5V
●
±1
±1
±1
µA
Off Channel Leakage Current
(Note 8)
2
V
LTC1290
AC CHARACTERISTICS
(Note 3)
LTC1290B/LTC1290C/LTC1290D
MIN
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
fSCLK
Shift Clock Frequency
VCC = 5V (Note 6)
0
2.0
MHz
fACLK
A/D Clock Frequency
VCC = 5V (Note 6)
(Note 10)
4.0
MHz
tACC
Delay time from CS↓ to DOUT Data Valid
(Note 9)
2
ACLK
Cycles
tSMPL
Analog Input Sample Time
See Operating Sequence
7
SCLK
Cycles
tCONV
Conversion Time
See Operating Sequence
52
ACLK
Cycles
tCYC
Total Cycle Time
See Operating Sequence (Note 6)
tdDO
Delay Time, SCLK↓ to DOUT Data Valid
See Test Circuits LTC1290BC, LTC1290CC
LTC1290DC, LTC1290BI
LTC1290CI, LTC1290DI
12 SCLK +
56 ACLK
UNITS
Cycles
●
130
220
ns
LTC1290BM, LTC1290CM ●
LTC1290DM
180
270
ns
tdis
Delay Time, CS↑ to DOUT Hi-Z
See Test Circuits
●
70
100
ns
ten
Delay Time, 2nd ACLK↓ to DOUT Enabled
See Test Circuits
●
130
200
ns
thCS
Hold Time, CS After Last SCLK↓
VCC = 5V (Note 6)
0
thDI
Hold Time, DIN After SCLK↑
VCC = 5V (Note 6)
50
thDO
Time Output Data Remains Valid After SCLK↓
tf
DOUT Fall Time
See Test Circuits
●
65
130
ns
tr
DOUT Rise Time
See Test Circuits
●
25
50
ns
tsuDI
Setup Time, DIN Stable Before SCLK↑
VCC = 5V (Note 6)
tsuCS
Setup Time, CS↓ Before Clocking in
First Address Bit
(Notes 6, 9)
tWHCS
CS High Time During Conversion
VCC = 5V (Note 6)
CIN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
ns
ns
50
50
ns
2 ACLK Cycles
+ 100ns
52
Digital Inputs
U
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
ns
ACLK
Cycles
100
5
pF
pF
5
pF
(Note 3)
LTC1290B/LTC1290C/LTC1290D
MIN
TYP MAX
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VCC = 5.25V
●
VIL
Low Level Input Voltage
VCC = 4.75V
●
0.8
V
IIH
High Level Input Current
VIN = VCC
●
2.5
µA
IIL
Low Level Input Current
VIN = 0V
●
– 2.5
µA
VOH
High Level Output Voltage
VCC = 4.75V IO = 10µA
IO = 360µA
●
2.0
2.4
UNITS
V
4.7
4.0
V
V
VOL
Low Level Output Voltage
VCC = 4.75V IO = 1.6mA
●
0.4
V
IOZ
High-Z Output Leakage
VOUT = VCC, CS High
VOUT = 0V, CS High
●
●
3
–3
µA
µA
ISOURCE
Output Source Current
VOUT = 0V
–20
mA
3
LTC1290
U
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
(Note 3)
LTC1290B/LTC1290C/LTC1290D
MIN
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
ISINK
Output Sink Current
VOUT = VCC
ICC
Positive Supply Current
CS High
●
6
12
mA
CS High
LTC1290BC, LTC1290CC
Power Shutdown LTC1290DC, LTC1290BI
ACLK Off
LTC1290CI, LTC1290DI
●
5
10
µA
LTC1290BM, LTC1290CM ●
LTC1290DM
5
15
µA
●
10
50
µA
●
1
50
µA
IREF
Reference Current
VREF = 5V
I–
Negative Supply Current
CS High
The ● denotes specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND
and REF – wired together (unless otherwise noted).
Note 3: VCC = 5V, VREF + = 5V, VREF – = 0V, V – = 0V for unipolar mode and
– 5V for bipolar mode, ACLK = 4.0MHz unless otherwise speicfied.
Note 4: These specs apply for both unipolar and bipolar modes. In bipolar
mode, one LSB is equal to the bipolar input span (2VREF) divided by 4096.
For example, when VREF = 5V, 1LSB (bipolar) = 2(5V)/4096 = 2.44mV.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Recommended operating conditions.
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
UNITS
20
mA
below V –
or one diode drop above VCC. Be careful during testing at low
VCC levels (4.5V), as high level reference or analog inputs (5V) can cause
this input diode to conduct, especially at elevated temperatures and cause
errors for inputs near full scale. This spec allows 50mV forward bias of
either diode. This means that as long as the reference or analog input does
not exceed the supply voltage by more than 50mV, the output code will be
correct. To achieve an absolute 0V to 5V input voltage range will therefore
require a minimum supply voltage of 4.950V over initial tolerance,
temperature variations and loading.
Note 8: Channel leakage current is measured after the channel selection.
Note 9: To minimize errors caused by noise at the chip select input, the
internal circuitry waits for two ACLK falling edge after a chip select falling
edge is detected before responding to control input signals. Therefore, no
attempt should be made to clock an address in or data out until the
minimum chip select setup time has elapsed.
Note 10: Increased leakage currents at elevated temperatures cause the
S/H to droop, therefore it's recommended that fACLK ≥ 500kHz at 125°C,
fACLK ≥ 125kHz at 85°C and fACLK ≥ 15kHz at 25°C.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
0.9
10
22
9
18
14
10
6
VCC = 5V
ACLK = 4MHz
VCC = 5V
OFFSET ERROR (LSB = 1 • VREF)
4096
ACLK = 4MHz
TA = 25°C
SUPPLY CURRENT, ICC (mA)
SUPPLY CURRENT, ICC (mA)
26
8
7
6
5
4
2
4
6
8
SUPPLY VOLTAGE, VCC (V)
10
1290 • TPC01
4
Unadjusted Offset Voltage vs
Reference Voltage
Supply Current vs Temperature
3
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE, TA (°C)
LT1290 • TPC02
0.8
0.7
0.6
0.5
VOS = 0.25mV
0.4
0.3
VOS = 0.125mV
0.2
0.1
1
3
2
4
REFERENCE VOLTAGE, VREF (V)
5
1290 • TPC03
LTC1290
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Change in Gain vs Reference
Voltage
CHANGE IN GAIN ERROR (LSB = 1 • VREF)
4096
VCC = 5V
1.00
0.75
0.50
0.25
1
3
4
2
REFERENCE VOLTAGE, VREF (V)
–0.1
–0.2
–0.3
–0.4
VCC = 5V
5
1
3
2
4
REFERENCE VOLTAGE, VREF (V)
5
0.4
ACLK = 4MHz
VCC = 5V
VREF = 5V
0.3
0.2
0.1
0
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE, TA (°C)
1290 • TPC06
Change in Gain Error vs
Temperature
0.6
ACLK = 4MHz
VCC = 5V
VREF = 5V
0.4
0.3
0.2
0.1
0
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE, TA (°C)
MAGNITUDE OF GAIN CHANGE ∆GAIN (LSB)
Change in Linearity Error vs
Temperature
0.5
0.5
1290 • TPC05
1290 • TPC04
MAGNITUDE OF LINEARITY CHANGE ∆LINEARITY (LSB)
0.5
ACLK = 4MHz
VCC = 5V
VREF = 5V
0.4
0.3
0.2
0.1
0
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE, TA (°C)
1290 • TPC07
1290 • TPC08
Maximum ACLK Frequency vs
Source Resistance
Maximum Filter Resistor vs
Cycle Time
5
10k
VCC = 5V
VREF = 5V
TA = 25°C
4
3
VIN
RSOURCE –
MAXIMUM RFILTER** (Ω)
0
Change in Offset vs Temperature
0
–0.5
0
MAXIMUM ACLK FREQUENCY* (MHz)
LINEARITY ERROR (LSB = 1 • VREF)
4096
1.25
MAGNITUDE OF OFFSET CHANGE ∆OFFSET (LSB)
Change in Linearity vs Reference
Voltage
+ INPUT
– INPUT
2
1
0
100
1k
100
RFILTER
VIN
CFILTER ≥ 1µF
10
+
–
1k
10 k
RSOURCE (Ω)
100k
1290 • TPC09
* MAXIMUM ACLK FREQUENCY REPRESENTS THE ACLK
FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR AT
ANY CODE TRANSITION FROM ITS 4MHz VALUE IS FIRST DETECTED.
1.0
10
100
1000
10000
CYCLE TIME, tCYC (µs)
1290 • TPC10
** MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR VALUE
AT WHICH A 0.1LSB CHANGE IN FULL-SCALE ERROR FROM
ITS VALUE AT RFILTER = 0 IS FIRST DETECTED.
5
LTC1290
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Sample-and-Hold Acquisition
Time vs Source Resistance
Supply Current (Power Shutdown)
vs Temperature
10
VIN
RSOURCE+
9
+
–
200
ACLK OFF DURING
POWER SHUTDOWN
8
7
6
5
4
3
2
1k
RSOURCE+ (Ω)
100
120
100
80
60
0
3.00
1.00
2.00
ACLK FREQUENCY (MHz)
Input Channel Leakage Current
vs Temperature
4.00
1290 • TPC13
1290 • TPC12
LTC1290 • TPC11
Noise Error vs Reference Voltage
1000
2.25
900
GUARANTEED
800
700
600
500
400
300
200
ON CHANNEL
OFF CHANNEL
100
0
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE, TA (°C)
1290 • TPC14
PEAK-TO-PEAK NOISE ERROR (LSBs)
INPUT CHANNEL LEAKAGE CURRENT (nA)
140
20
0
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE, TA (°C)
10k
160
40
1
1
VCC = 5V
CMOS LEVELS
180
SUPPLY CURRENT, ICC (µA)
VREF = 5V
VCC = 5V
TA = 25°C
0V TO 5V INPUT STEP
SUPPLY CURRENT, ICC (µA)
S & H AQUISITION TIME TO 0.02% (µs)
100
10
Supply Current (Power Shutdown)
vs ACLK
LTC1290 NOISE 200µVP-P
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0
4
1
3
2
REFERENCE VOLTAGE, VREF (V)
5
1290 • TPC15
U
U
U
PI FU CTIO S
CH0 to CH7 (Pin 1 to Pin 8): Analog Inputs. The analog
inputs must be free of noise with respect to AGND.
COM (Pin 9): Common. The common pin defines the zero
reference point for all single-ended inputs. It must be free
of noise and is usually tied to the analog ground plane.
DGND (Pin 10): Digital Ground. This is the ground for the
internal logic. Tie to the ground plane.
AGND (Pin 11): Analog Ground. AGND should be tied
directly to the analog ground plane.
6
V – (Pin 12): Negative Supply. Tie V – to most negative
potential in the circuit. (Ground in single supply applications.)
REF –, REF + (Pins 13, 14): Reference Inputs. The reference inputs must be kept free of noise with respect to
AGND.
CS (Pin 15): Chip Select Input. A logic low on this input
enables data transfer.
DOUT (Pin 16): Digital Data Output. The A/D conversion
result is shifted out of this output.
LTC1290
U
U
U
PI FU CTIO S
DIN (Pin 17): Digital Data Input. The A/D configuration
word is shifted into this input after CS is recognized.
ACLK (Pin 19): A/D Conversion Clock. This clock controls
the A/D conversion process.
SCLK (Pin 18): Shift Clock. This clock synchronizes the
serial data transfer.
VCC (Pin 20): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the analog
ground plane.
BLOCK DIAGRAM
VCC
DIN
18
20
INPUT
SHIFT
REGISTER
17
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
OUTPUT
SHIFT
REGISTER
16
SCLK
DOUT
1
SAMPLEANDHOLD
2
3
COMP
4
5
ANALOG
INPUT MUX
12-BIT
SAR
6
12-BIT
CAPACITIVE
DAC
7
8
9
19
10
11
DGND
AGND
12
V–
13
REF –
CONTROL
AND
TIMING
14
REF+
15
ACLK
CS
LTC1290 • BD
TEST CIRCUITS
On and Off Channel Leakage Current
Load Circuit for tdis and ten
5V
ION
TEST POINT
ON CHANNEL
A
IOFF
3k
5V WAVEFORM 2
DOUT
A
•
•
•
•
OFF
CHANNELS
100pF
WAVEFORM 1
LTC1290 • TC02
POLARITY
LTC1290 • TC01
7
LTC1290
TEST CIRCUITS
Voltage Waveforms for DOUT Delay Time, tdDO
SCLK
0.8V
tdDO
2.4V
DOUT
0.4V
LTC1290 • TC03
Voltage Waveform for DOUT Rise and Fall Times, tr, tf
2.4V
DOUT
0.4V
tr
tf
LTC1290 • TC04
Load Circuit for tdDO, tr and tf
1.4V
3k
DOUT
TEST POINT
100pF
1290 • TC05
Voltage Waveforms for ten and tdis
1
2
ACLK
2.0V
CS
DOUT
WAVEFORM 1
(SEE NOTE 1)
2.4V
ten
DOUT
WAVEFORM 2
(SEE NOTE 2)
90%
tdis
0.8V
10%
LTC1290 • TC06
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
8
LTC1290
W
U
U
UO
APPLICATI
S I FOR ATIO
The LTC1290 is a data acquisition component which
contains the following functional blocks:
of the data exchange the requested conversion begins and
CS should be brought high. After tCONV, the conversion is
complete and the results will be available on the next data
transfer cycle. As shown below, the result of a conversion
is delayed by one CS cycle from the input word requesting
it.
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S/H)
4. Synchronous, full duplex serial interface
5. Control and timing logic
DIGITAL CONSIDERATIONS
DIN
DIN WORD 1
DOUT
DOUT WORD 0
DATA
TRANSFER
Serial Interface
DIN WORD 2
DIN WORD 3
DOUT WORD 1
tCONV
A/D
CONVERSION
DOUT WORD 2
tCONV
A/D
CONVERSION
DATA
TRANSFER
LTC1290 • AI01
The LTC1290 communicates with microprocessors and
other external circuitry via a synchronous, full duplex,
four-wire serial interface (see Operating Sequence). The
shift clock (SCLK) synchronizes the data transfer with
each bit being transmitted on the falling SCLK edge and
captured on the rising SCLK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex).
Input Data Word
The LTC1290 8-bit data word is clocked into the DIN input
on the first eight rising SCLK edges after chip select is
recognized. Further inputs on the DIN pin are then ignored
until the next CS cycle. The eight bits of the input word are
defined as follows:
UNIPOLAR/
BIPOLAR
Data transfer is initiated by a falling chip select (CS) signal.
After the falling CS is recognized, an 8-bit input word is
shifted into the DIN input which configures the LTC1290
for the next conversion. Simultaneously, the result of the
previous conversion is output on the DOUT line. At the end
SGL/
DIFF
ODD/
SIGN
SELECT
1
SELECT
0
UNI
WORD
LENGTH
MSBF
WL1
MSB-FIRST/
LSB-FIRST
MUX ADDRESS
WL0
LTC1290 • AI02
Operating Sequence
(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)
tCYC
1
2
3
4
5
6
7
8
9
SCLK
10
11
12
DON’T CARE
tSMPL
tCONV
CS
DIN
DON’T CARE
B11 B10 B9
DOUT
SHIFT CONFIGURATION
WORD IN
(SB)
B8
B7 B6
B5
B4
B3
B2
B1
B0
SHIFT A/D RESULT OUT AND
NEW CONFIGURATION WORD IN
LTC1290 • AI03
9
LTC1290
W
U
U
UO
APPLICATI
S I FOR ATIO
MUX Address
The first four bits of the input word assign the MUX
configuration for the requested conversion. For a given
channel selection, the converter will measure the voltage
between the two channels indicated by the + and – signs
in the selected row of Table 1. Note that in differential
mode (SGL/DIFF = 0) measurements are limited to four
adjacent input pairs with either polarity. In single-ended
mode, all input channels are measured with respect to
COM.
Table 1. Multiplexer Channel Selection
MUX ADDRESS
SGL/ ODD SELECT
DIFF SIGN 1 0
0
0
0 0
0
0
0 1
0
0
1 0
0
0
1 1
0
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
DIFFERENTIAL CHANNEL SELECTION
0
1
+
–
2
3
+
–
5
4
+
0,1
{
2,3
{
4,5
{
6,7
{
7
–
+
–
–
+
–
+
–
+
–
4 Differential
CHANNEL
6
+
8 Single-Ended
CHANNEL
0
1
2
3
4
5
6
7
+ (– )
– (+ )
+ (– )
– (+ )
+ (– )
– (+ )
+ (– )
– (+ )
SINGLE-ENDED CHANNEL SELECTION
MUX ADDRESS
SGL/ ODD SELECT
DIFF SIGN 1 0
1
0
0 0
1
0
0 1
1
0
1 0
1
0
1 1
1
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1
0
1
2
3
4
5
6
7
+
+
+
+
+
+
+
+
Combinations of Differential and Single-Ended
CHANNEL
+
+
+
+
+
+
+
+
0,1
{
+
–
2,3
{
–
+
+
+
+
+
4
5
6
7
COM (–)
COM (–)
Changing the MUX Assignment “On the Fly”
4,5
{
6,7
{
+
–
+
–
COM (UNUSED)
1ST CONVERSION
5,4
{
–
+
6
7
{
+
+
COM (–)
2ND CONVERSION
LTC1290 • F01
Figure 1. Examples of Multiplexer Options on the LTC1290
10
COM
–
–
–
–
–
–
–
–
LTC1290
W
U
U
UO
APPLICATI
S I FOR ATIO
Unipolar/Bipolar (UNI)
The fifth input bit (UNI) determines whether the conversion will be unipolar or bipolar. When UNI is a logical one,
a unipolar conversion will be performed on the selected
input voltage. When UNI is a logical zero, a bipolar conversion will result. The input span and code assignment for
each conversion type are shown in the figures below.
Unipolar Transfer Curve (UNI = 1)
Unipolar Output Code (UNI = 1)
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 5V)
111111111111
111111111110
•
•
•
000000000001
000000000000
VREF – 1LSB
VREF – 2LSB
•
•
•
1LSB
0V
4.9988V
4.9976V
•
•
•
0.0012V
0V
111111111111
111111111110
•
•
•
000000000001
000000000000
LTC1290 • AI04a
VIN
VREF
VREF – 1LSB
VREF – 2LSB
1LSB
0V
LTC1290 AI04b
Bipolar Output Code (UNI = 0)
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 5V)
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 5V)
011111111111
011111111110
•
•
•
000000000001
000000000000
VREF – 1LSB
VREF – 2LSB
•
•
•
1LSB
0V
4.9976V
4.9851V
•
•
•
0.0024V
0V
111111111111
111111111110
•
•
•
100000000001
100000000000
–1LSB
–2LSB
•
•
•
–(VREF) + 1LSB
– (VREF)
–0.0024V
–0.0048V
•
•
•
–4.9976V
–5.0000V
LTC1290 AI05a
Bipolar Transfer Curve (UNI = 0)
011111111111
011111111110
1LSB
–VREF + 1LSB
–VREF
•
•
•
000000000001
000000000000
VIN
100000000001
VREF
–1LSB
–2LSB
•
•
•
VREF – 1LSB
111111111110
VREF – 2LSB
111111111111
LTC1290 AI05b
100000000000
11
LTC1290
U
W
U
UO
APPLICATI
S I FOR ATIO
MSB-First/LSB-First Format (MSBF)
The output data of the LTC1290 is programmed for MSBfirst or LSB-first sequence using the MSBF bit. For MSB
first output data the input word clocked to the LTC1290
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB-first output data the input
word clocked to the LTC1290 should always contain a zero
in the MSBF bit location. The MSBF bit affects only the
order of the output data word. The order of the input word
is unaffected by this bit.
MSBF
OUTPUT FORMAT
0
LSB First
1
MSB First
Word Length (WL1, WL0) and Power Shutdown
resumed once CS goes low or an SCLK is applied, if CS is
already low.
WL1
WL0
OUTPUT WORD LENGTH
0
0
8-Bits
0
1
Power Shutdown
1
0
12-Bits
1
1
16-Bits
Deglitcher
A deglitching circuit has been added to the Chip Select
input of the LTC1290 to minimize the effects of errors
caused by noise on that input. This circuit ignores changes
in state on the CS input that are shorter in duration than
one ACLK cycle. After a change of state on the CS input, the
LTC1290 waits for two falling edge of the ACLK before
recognizing a valid chip select. One indication of CS
recognition is the DOUT line becoming active (leaving the
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
The last two bits of the input word (WL1 and WL0)
program the output data word length and the power
shutdown feature of the LTC1290. Word lengths of 8, 12
or 16 bits can be selected according to the following table.
The WL1 and WL0 bits in a given DIN word control the
length of the present, not the next, DOUT word. WL1 and
WL0 are never “don’t cares” and must be set for the
correct DOUT word length even when a “dummy” DIN word
is sent. On any transfer cycle, the word length should be
made equal to the number of SCLK cycles sent by the
MPU. Power down will occur when WL1 = 0 and WL0 = 1
is selected. The previous conversion result will be clocked
out as a 10 bit word so a “dummy”conversion is required
before powering down the LTC1290. Conversions are
In the normal mode of operation, CS is brought high
during the conversion time. The serial port ignores any
SCLK activity while CS is high. The LTC1290 will also
operate with CS low during the conversion. In this mode,
SCLK must remain low during the conversion as shown in
the following figure. After the conversion is complete, the
DOUT line will become active with the first output bit. Then
the data transfer can begin as normal.
Low CS Recognized Internally
High CS Recognized Internally
CS Low During Conversion
ACLK
ACLK
CS
CS
DOUT
HI-Z
DOUT
VALID OUTPUT
LTC1290 • AI06
12
VALID OUTPUT
HI-Z
LTC1290 • AI07
LTC1290
W
U
U
UO
APPLICATI
S I FOR ATIO
8-Bit Word Length
tSMPL
tCONV
CS
SCLK
1
8
(SB)
DOUT
MSB-FIRST
B11
B10
B9
B8
B7
B6
B5
B4
DOUT
LSB-FIRST
B0
B1
B2
B3
B4
B5
B6
B7
THE LAST FOUR BITS
ARE TRUNCATED
12-Bit Word Length
tSMPL
tCONV
CS
1
SCLK
10
12
(SB)
DOUT
MSB-FIRST
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
DOUT
LSB-FIRST
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B0
(SB)
B11
16-Bit Word Length
tSMPL
tCONV
CS
SCLK
1
12
16
(SB)
DOUT
MSB-FIRST
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
DOUT
LSB-FIRST
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B0
FILL
ZEROS
(SB)
B11
*
* IN UNIPOLAR MODE, THESE BITS ARE FILLED WITH ZEROS.
IN BIPOLAR MODE, THE SIGN BIT IS EXTENDED INTO THESE LOCATIONS.
*
*
LTC1290 F02
Figure 2. Data Output (DOUT) Timing with Different Word Lengths
13
LTC1290
W
U
U
UO
APPLICATI
S I FOR ATIO
SHIFT
MUX ADDRESS
IN
tSMPL
SAMPLE ANALOG
INPUT
48 TO 52
ACLK CYC
SHIFT RESULT OUT
AND NEW ADDRESS IN
CS
SCLK
DON’T CARE
DIN
DOUT
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
LTC1290 F03
Figure 3. CS High During Conversion
SHIFT
MUX ADDRESS
IN
tSMPL
SAMPLE ANALOG
INPUT
48 TO 52
ACLK CYC
SHIFT RESULT OUT
AND NEW ADDRESS IN
CS
SCLK MUST
REMAIN LOW
SCLK
DIN
DOUT
DON’T CARE
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
LTC1290 F04
Figure 4. CS Low During Conversion (CS Must go High to Low Once to Insure Proper Operation in this Mode)
Microprocessor Interfaces
Serial Port Microprocessors
The LTC1290 can interface directly (without external hardware) to most popular microprocessor (MPU) synchronous serial formats (see Table 2). If an MPU without a
serial interface is used, then four of the MPU’s parallel port
lines can be programmed to form the serial link to the
LTC1290. Included here are two serial interface examples
and one example showing a parallel port programmed to
form the serial interface
Most synchronous serial formats contain a shift clock
(SCLK) and two data lines, one for transmitting and one for
receiving. In most cases data bits are transmitted on the
falling edge of the clock (SCLK) and captured on the rising
edge. However, serial port formats vary among MPU
manufactures as to the smallest number of bits that can be
sent in one group (e.g., 4-bit, 8-bit or 16-bit transfers).
They also vary as to the order in which the bits are
transmitted (LSB or MSB first). The following examples
show how the LTC1290 accommodates these differences.
14
LTC1290
W
U
U
UO
APPLICATI
S I FOR ATIO
Table 2. Microprocessors with Hardware Serial Interfaces
Compatible with the LTC1290**
PART NUMBER
TYPE OF INTERFACE
Motorola
MC6805S2, S3
MC68HC11
MC68HC05
SPI
SPI
SPI
CDP68HC05
SPI
RCA
National MICROWIRE (COP402)
The COP402 transfers data MSB first and in 4-bit increments (nibbles). This is easily accommodated by setting
the LTC1290 to MSB-first format and 12-bit word length.
The data output word is then received by the COP402 in
three 4-bit blocks.
COP402 Code
Hitachi
HD6305
HD6301
HD63701
HD6303
HD64180
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
National Semiconductor
MICROWIRETM
MICROWIRE/PLUSTM
MICROWIRE/PLUS
MICROWIRE/PLUS
COP400 Family
COP800 Family
NS8050U
HPC16000 Family
Texas Instruments
TMS7002
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020
TMS370C050
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
SPI
*Requires external hardware
** Contact factory for interface information for processors not on this list
Hardware and Software Interface to COP402 Processor
COP402
LTC1290
ANALOG
INPUTS
•
•
•
•
LOOP
MNEMONIC
COMMENTS
CLRA
LBI
STII
STII
STII
LEI
SC
LDD
OGI
XAS
LDD
NOP
XAS
XIS
LDD
XAS
XIS
RC
CLRA
XAS
OGI
XIS
LBI
Must be First Instruction
BR = 1BD = 0 Initialize B Reg.
First DIN Nibble in $10
Second DIN Nibble in $11
Null Data in $12, B = $13
Set EN to (1100) BIN
Carry Set
Load First DIN Nibble In ACC
Go (CS) Cleared
ACC to Shift Reg. Begin Shift
Load Next DIN Nibble in ACC
Timing
Next Nibble, Shift Continues
First Nibble DOUT to $13
Put Null Data in ACC
Shift Continues, DOUT to ACC
Next Nibble DOUT to $14
Clear Carry
Clear ACC
Third Nibble DOUT to ACC
Go (CS) Set
Third Nibble DOUT to $15
Set B Reg. For Next Loop
1,0
8
E
0
C
1,0
0
1,1
0
1,2
0
1
0
1,3
CS
GO
Motorola SPI (MC68HC05C4)
SCLK
SK
DIN
SO
DOUT
SI
The MC68HC05C4 transfers data MSB first and in 8-bit
increments. Programming the LTC1290 for MSB-first
format and 16-bit word length allows the 12-bit data
output to be received by the MPU as two 8-bit bytes with
the final four unused bits filled with zeros by the LTC1290.
LTC1290 • AI08
DOUT from LTC1290 Stored in COP402 RAM
MSB†
LOCATION $13
B11
B10
B9
B8
FIRST 4 BITS
LOCATION $14
B7
B6
B5
B4
SECOND 4 BITS
LSB
LOCATION $15
†
B3
B2
B1
B0
THIRD 4 BITS
B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR
MICROWIRE and MICROWIRE PLUS are trademarks of National Semiconductor Corp
15
LTC1290
W
U
U
UO
APPLICATI
S I FOR ATIO
Hardware and Software Interface to Motorola
MC68HC05C4 Processor
CO
CS
•
•
•
•
When interfacing the LTC1290 to an MPU which has a
parallel port, the serial signals are created on the port with
software. Three MPU port lines are programmed to create
the CS, SCLK and DIN signals for the LTC1290. A fourth
port line reads the DOUT line. An example is made of the
Intel 8051/8052/80C252 family.
MC68HC05C4
LTC1290
ANALOG
INPUTS
Parallel Port Microprocessors
SCLK
SCK
DIN
MOSI
DOUT
MISO
LTC1290 • AI09
Intel 8051
DOUT from LTC1290 Stored in MC68HC05C4 RAM
MSB*
LOCATION $61
B11
B10
B9
B8
B7
B6
B5
B4
BYTE 1
0
0
0
0
BYTE 2
To interface to the 8051, the LTC1290 is programmed for
MSB-first format and 12-bit word length. The 8051 generates CS, SCLK and DIN on three port lines and reads DOUT
on the fourth.
LSB
LOCATION $62
B3
B2
B1
B0
Hardware and Software Interface to Intel 8051 Processor
8051
LTC1290
*B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR
•
•
•
•
•
•
•
•
MC68HC05C4 Code
MNEMONIC
START
LDA
STA
LDA
STA
LDA
STA
BCLR
LDA
STA
#$50
$0A
#$FF
$06
#$0F
$50
0,$20
$50
$0C
NOP
LDA
LDA
STA
STA
8 NOPs for Timing
$0B
$0C
$61
$0C
NOP
BSET
LDA
LDA
STA
16
COMMENTS
Configuration Data for SPCR
Load Data Into SPCR ($0A)
Config. Data for Port C DDR
Load Data Into Port C DDR
Load LTC1290 DIN Data Into ACC
Load LTC1290 DIN Data Into $50
CO Goes Low (CS Goes Low)
Load DIN Into ACC from $50
Load DIN Into SPI, Start SCK
Check SPI Status Reg
Load LTC1290 MSBs Into ACC
Store MSBs in $61
Start Next SPI Cycle
6 NOPs for Timing
0,$02
$0B
$0C
$62
CO Goes High (CS Goes High)
Check SPI Status Register
Load LTC1290 LSBs Into ACC
Store LSBs in $62
ANALOG
INPUTS
DOUT
P1.1
DIN
P1.2
SCLK
P1.3
CS
P1.4
ACLK
ALE
LTC1290 • AI10
DOUT from LTC1290 Stored in 8051 RAM
MSB*
R2
B11
B10
B9
B8
B7
B6
B5
54
0
0
0
0
LSB
R3
B3
B2
B1
B0
*B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR
LTC1290
W
U
U
UO
APPLICATI
S I FOR ATIO
8051 Code
Sharing the Serial Interface
MNEMONIC
CONT
LOOP
DELAY
MOV
CLR
SETB
MOV
CLR
MOV
NOP
MOV
RLC
MOV
SETB
CLR
DJNZ
MOV
MOV
CLR
RLC
SETB
CLR
MOV
RLC
SETB
CLR
MOV
RLC
SETB
CLR
MOV
RRC
RRC
RRC
RRC
MOV
SETB
CLR
SETB
P1,#02H
P1.3
P1.4
A,#0EH
P1.4
R4,#08H
C,P1.1
A
P1.2,C
P1.3
P1.3
R4,LOOP
R2,A
C,P1.1
A
A
P1.3
P1.3
C,P1.1
A
P1.3
P1.3
C,P1.1
A
P1.3
P1.3
C, P1.1
A
A
A
A
R3,A
P1.3
P1.3
P1.4
MOV R5,#0BH
DJNZ R5,DELAY
COMMENTS
The LTC1290 can share the same 3-wire serial interface
with other perpheral components or other LTC1290s (see
Figure 5). In this case, the CS signals decide which
LTC1290 is being addressed by the MPU.
Bit 1 Port 1 Set as Input
SCLK Goes Low
CS Goes High
DIN Word for LTC1290
CS Goes Low
Load Counter
Delay for Deglitcher
Read Data Bit Into Carry
Rotate Data Bit Into ACC
Output DIN Bit to LTC1290
SCLK Goes High
SCLK Goes Low
Next Bit
Store MSBs in R2
Read Data Bit Into Carry
Clear ACC
Rotate Data Bit Into ACC
SCLK Goes High
SCLK Goes Low
Read Data Bit Into Carry
Rotate Data Bit Into ACC
SCLK Goes High
SCLK Goes Low
Read Data Bit Into Carry
Rotate Data Bit Into ACC
SCLK Goes High
SCLK Goes Low
Read Data Bit Into Carry
Rotate Right Into ACC
Rotate Right Into ACC
Rotate Right Into ACC
Rotate Right Into ACC
Store LSBs in R3
SCLK Goes High
SCLK Goes Low
CS Goes High
ANALOG CONSIDERATIONS
1. Grounding
The LTC1290 should be used with an analog ground plane
and single point grounding techniques.
AGND (Pin 11) should be tied directly to this ground plane.
DGND (Pin 10) can also be tied directly to this ground
plane because minimal digital noise is generated within
the chip itself.
VCC (Pin 20) should be bypassed to the ground plane with
a 22µF tantalum with leads as short as possible. V – (Pin
12) should be bypassed with a 0.1µF ceramic disk. For
single supply applications, V – can be tied to the ground
plane.
It is also recommended that REF – (Pin 13) and COM (Pin
9) be tied directly to the ground plane. All analog inputs
should be referenced directly to the single point ground.
Digital inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
Load Counter
Go to Delay if Not Done
2
1
0
OUTPUT PORT
SERIAL DATA
MPU
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1290s
3
3
3
3
CS
LTC1290
CS
LTC1290
CS
LTC1290
8 CHANNELS
8 CHANNELS
8 CHANNELS
LTC1290 F05
Figure 5. Several LTC1290s Sharing One 3-Wire Serial Interface
17
LTC1290
W
U
U
UO
APPLICATI
S I FOR ATIO
VCC
1
VERTICAL: 0.5mV/DIV
22µF
TANTALUM
20
HORIZONTAL: 10µs/DIV
Figure 7. Poor VCC Bypassing.
Noise and Ripple Can Cause A/D Errors
V–
10
ANALOG
GROUND
PLANE
0.1µF
CERAMIC
DISK
LTC1290 F06
Figure 6 shows an example of an ideal ground plane design
for a two-sided board. Of course, this much ground plane
will not always be possible, but users should strive to get
as close to this ideal as possible.
VERTICAL: 0.5mV/DIV
Figure 6. Example Ground Plane for the LTC1290
CS
VCC
HORIZONTAL: 10µs/DIV
2. Bypassing
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
analog ground during a conversion cycle can induce
errors or noise in the output code. VCC noise and ripple can
be kept below 0.5mV by bypassing the VCC pin directly to
the analog ground plane with a 22µF tantalum capacitor
and leads as short as possible. The lead from the device to
the VCC supply should also be kept to a minimum and the
VCC supply should have a low output impedance such as
that obtained from a voltage regulator (e.g., LT323A).
Figures 7 and 8 show the effects of good and poor VCC
bypassing.
3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1290 have
capacitive switching input current spikes. These current
18
Figure 8. Good VCC Bypassing Keeps
Noise and Ripple on VCC Below 1mV
spikes settle quickly and do not cause a problem. However, if large source resistances are used or if slow settling
op amps drive the inputs, care must be taken to insure that
the transients caused by the current spikes settle completely before the conversion begins.
Source Resistance
The analog inputs of the LTC1290 look like a 100pF
capacitor (CIN) in series with a 500Ω resistor (RON) as
shown in Figure 9. CIN gets switched between the selected
“+” and “–” inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC time
constants be short enough to allow the analog inputs to
completely settle within the allowed time.
LTC1290
W
U
U
UO
APPLICATI
S I FOR ATIO
“–” Input Settling
“+”
INPUT
RSOURCE +
LTC1290
VIN +
RSOURCE –
C1
4TH SCLK
RON = 500Ω
“–”
INPUT
LAST SCLK
CIN =
100pF
VIN –
C2
LTC1290 F09
Figure 9. Analog Input Equivalent Circuit
“+” Input Settling
This input capacitor is switched onto the “+” input during
the sample phase (tSMPL, see Figure 10). The sample
phase starts at the 4th SCLK cycle and lasts until the falling
edge of the last SCLK (the 8th, 12th or 16th SCLK cycle
depending on the selected word length). The voltage on
the “+” input must settle completely within this sample
time. Minimizing RSOURCE+ and C1 will improve the input
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
SCLK frequency or selecting a longer word length. With
the minimum possible sample time of 2µs, RSOURCE+ < 1k
and C1 < 20pF will provide adequate settling.
SAMPLE
MUX ADDRESS
SHIFTED IN
ACLK
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 10). Again, the “+” and “–” input sampling
times can be extended as described above to accommodate slower op amps. Most op amps including the LT1006
and LT1013 single supply op amps can be made to settle
well even with the minimum settling windows of 2µs (“+”
input) and 1µs (“–” input) which occur at the maximum
HOLD
•••
CS
SCLK
“+” INPUT
MUST SETTLE
DURING THIS TIME
tSMPL
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figure 10).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage be free of noise and settle completely during the
first four ACLK cycles of the conversion time. Minimizing
RSOURCE– and C2 will improve settling time. If large “–”
input source resistance must be used, the time allowed for
settling can be extended by using a slower ACLK frequency. At the maximum ACLK rate of 4MHz, RSOURCE– <
250Ω and C2 < 20pF will provide adequate settling.
1
2
3
4
LAST SCLK (8TH, 12TH OR 16TH DEPENDING ON WORD LENGTH)
•••
•••
1
2
3
4
•••
1ST BIT TEST
“–” INPUT MUST SETTLE
DURING THIS TIME
“+” INPUT
“–” INPUT
1290 • F10
Figure 10. “+” and “–” Input Settling Windows
19
LTC1290
U
W
U
UO
APPLICATI
S I FOR ATIO
clock rates (ACLK = 4MHz and SCLK = 2MHz). Figures 11
and 12 show examples of adequate and poor op amp
settling.
RFILTER
IDC
VIN
"+"
CFILTER
LTC1290
"–"
LTC1290 F13
VERTICAL: 5mV/DIV
Figure 13. RC Input Filtering
Input Leakage Current
HORIZONTAL: 500ns/DIV
Figure 11. Adequate Settling of Op Amps Driving Analog Input
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum input
leakage specification of 1µA (at 125°C) flowing through a
source resistance of 1kΩ will cause a voltage drop of 1mV
or 0.8LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see the
typical curve of Input Channel Leakage Current vs Temperature).
VERTICAL: 5mV/DIV
Noise Coupling Into Inputs
HORIZONTAL: 20µs/DIV
Figure 12. Poor Op Amp Settling Can Cause A/D Errors
RC Input Filtering
It is possible to filter the inputs with an RC network as shown
in Figure 13. For large values of CF (e.g., 1µF), the capacitive
input switching currents are averaged into a net DC current.
Therefore, a filter should be chosen with a small resistor and
large capacitor to prevent DC drops across the resistor. The
magnitude of the DC current is approximately IDC =
(100pF)(VIN/tCYC) and is roughly proportional to VIN. When
running at the minimum cycle time of 20µs, the input
current equals 25µA at VIN = 5V. In this case, a filter resistor
of 5Ω will cause 0.1LSB of full-scale error. If a larger filter
resistor must be used, errors can be eliminated by increasing the cycle time as shown in the typical curve of Maximum
Filter Resistor vs Cycle Time.
20
High source resistance input signals (>500Ω) are more
sensitive to coupling from external sources. It is preferable to use channels near the center of the package (i.e.,
CH2 to CH7) for signals which have the highest output
resistance because they are essentially shielded by the
pins on the package ends (DGND and CH0). Grounding
any unused inputs (especially the end pin, CH0) will also
reduce outside coupling into high source resistances.
4. Sample-and-Hold
Single-Ended Inputs
The LTC1290 provides a built-in sample-and-hold (S&H)
function for all signals acquired in the single-ended mode
(COM pin grounded). This sample-and-hold allows the
LTC1290 to convert rapidly varying signals (see the typical
curve of S&H Acquisition Time vs Source Resistance). The
input voltage is sampled during the tSMPL time as shown in
Figure 10. The sampling interval begins after the fourth MUX
address bit is shifted in and continues during the remainder
of the data transfer. On the falling edge of the final SCLK, the
S&H goes into hold mode and the conversion begins. The
voltage will be held on either the 8th, 12th or 16th falling edge
of the SCLK depending on the word length selected.
LTC1290
W
U
U
UO
S I FOR ATIO
With differential inputs or when the COM pin is not tied to
ground, the A/D no longer converts just a single voltage but
rather the difference between two voltages. In these cases,
the voltage on the selected “+” input is still sampled and held
and therefore may be rapidly time varying just as in singleended mode. However, the voltage on the selected “–” input
must remain constant and be free of noise and ripple
throughout the conversion time. Otherwise, the differencing
operation may not be performed accurately. The conversion
time is 52 ACLK cycles. Therefore, a change in the “–” input
voltage during this interval can cause conversion errors.
For a sinusoidal voltage on the “–” input this error would be:
VERROR (MAX) = (VPEAK)(2π)[ f(“–”)](52/fACLK)
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fACLK is the frequency of
the ACLK. In most cases VERROR will not be significant. For
a 60Hz signal on the “–” input to generate a 0.25LSB error
(300µV) with the converter running at ACLK = 4MHz, its
peak value would have to be 61mV.
5. Reference Inputs
The voltage between the reference inputs of the LTC1290
defines the voltage span of the A/D converter. The reference inputs will have transient capacitive switching currents due to the switched capacitor conversion technique
(see Figure 14). During each bit test of the conversion
(every 4 ACLK cycles), a capacitive current spike will be
generated on the reference pins by the A/D. These current
spikes settle quickly and do not cause a problem. However, if slow settling circuitry is used to drive the reference
inputs, care must be taken to insure that transients caused
by these current spikes settle completely during each bit
test of the conversion.
REF+
14
ROUT
VREF
REF–
13
LTC1290
EVERY 4 ACLK CYCLES
RON
When driving the reference inputs, two things should be
kept in mind:
1. Transients on the reference inputs caused by the
capacitive switching currents must settle completely
during each bit test (each 4 ACLK cycles). Figures 15
and 16 show examples of both adequate and poor
settling. Using a slower ACLK will allow more time for
the reference to settle. However, even at the maximum
ACLK rate of 4MHz most references and op amps can
be made to settle within the 1µs bit time. For example
the LT1027 will settle adequately or with a 10µF bypass
capacitor at REF + the LT1021 can also be used.
2. It is recommended that REF – input be tied directly to
the analog ground plane. If REF – is biased at a voltage
other than ground, the voltage must not change during
a conversion cycle. This voltage must also be free of
noise and ripple with respect to analog ground.
VERTICAL: 0.5mV/DIV
Differential Inputs
HORIZONTAL: 1µs/DIV
Figure 15. Adequate Reference Settling
VERTICAL: 0.5mV/DIV
APPLICATI
8pF TO 40pF
LTC 1290 F14
Figure 14. Reference Input Equivalent Circuit
HORIZONTAL: 1µs/DIV
Figure 16. Poor Reference Settling Can Cause A/D Errors
21
LTC1290
U
W
U
UO
APPLICATI
S I FOR ATIO
6. Reduced Reference Operation
The effective resolution of the LTC1290 can be increased
by reducing the input span of the converter. The LTC1290
exhibits good linearity and gain over a wide range of
reference voltages (see the typical curves of Linearity and
Gain Error vs Reference Voltage). However, care must be
taken when operating at low values of VREF because of the
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. The following factors
must be considered when operating at low VREF values:
1. Offset
2. Noise
Offset with Reduced VREF
The offset of the LTC1290 has a larger effect on the output
code when the A/D is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The typical curve of Unadjusted Offset Error vs
Reference Voltage shows how offset in LSBs is related to
reference voltage for a typical value of VOS. For example,
a VOS of 0.1mV which is 0.1LSB with a 5V reference
becomes 0.4LSB with a 1.25V reference. If this offset is
unacceptable, it can be corrected digitally by the receiving
system or by offsetting the “–” input to the LTC1290.
Noise with Reduced VREF
The total input referred noise of the LTC1290 can be
reduced to approximately 200µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
is insignificant with a 5V reference but will become a larger
fraction of an LSB as the size of the LSB is reduced. The
typical curve of Noise Error vs Reference Voltage shows
the LSB contribution of this 200µV of noise.
For operation with a 5V reference, the 200µV noise is only
0.16LSB peak-to-peak. In this case, the LTC1290 noise
will contribute virtually no uncertainty to the output code.
However, for reduced references, the noise may become
a significant fraction of an LSB and cause undesirable jitter
in the output code. For example, with a 1.25V reference,
this same 200µV noise is 0.64LSB peak-to-peak. This will
22
reduce the range of input voltages over which a stable
output code can be achieved by 0.64LSB. In this case
averaging readings may be necessary.
This noise data was taken in a very clean setup. Any setup
induced noise (noise or ripple on VCC, VREF, VIN or V –) will
add to the internal noise. The lower the reference voltage
to be used, the more critical it becomes to have a clean,
noise-free setup.
7. LTC1290 AC Characteristics
Two commonly used figures of merit for specifying the
dynamic performance of the A/D’s in digital signal processing applications are the Signal-to-Noise Ratio (SNR)
and the “effective number of bits (ENOB).” SNR is defined
as the ratio of the RMS magnitude of the fundamental to
the RMS magnitude of all the nonfundamental signals up
to the Nyquist frequency (half the sampling frequency).
The theoretical maximum SNR for a sine wave input is
given by:
SNR = (6.02N + 1.76dB)
where N is the number of bits. Thus the SNR is a function
of the resolution of the A/D. For an ideal 12-bit A/D the SNR
is equal to 74dB. A Fast Fourier Transform(FFT) plot of the
output spectrum of the LTC1290 is shown in Figures 17a
and 17b. The input (fIN) frequencies are 1kHz and 25kHz
with the sampling frequency (fS) at 50.6kHz. The SNR
obtained from the plot are 73.25dB and 72.54dB.
Rewriting the SNR expression it is possible to obtain the
equivalent resolution based on the SNR measurement.
N = (SNR – 1.76dB)/6.02
This is the so-called effective number of bits (ENOB). For
the example shown in Figures 17a and 17b, N = 11.9 bits
and 11.8 bits, respectively. Figure 18 shows a plot of ENOB
as a function of input frequency. The curve shows the
A/D’s ENOB remain in the range of 11.9 to 11.8 for input
frequencies up to fS/2.
Figure 19 shows an FFT plot of the output spectrum for two
tones applied to the input of the A/D. Nonlinearities in the
A/D will cause distortion products at the sum and difference frequencies of the fundamentals and products of the
LTC1290
U
UO
S I FOR ATIO
fIN = 1kHz
fSAMPLE = 50.6kHz
SNR = 73.25dB
0
–20
MAGNITUDE (dB)
W
U
APPLICATI
–20
MAGNITUDE (dB)
–40
–60
–80
–40
–60
–80
–100
–100
–120
–120
–140
0
4
8
12
16
20
FREQUENCY (kHz)
fIN = 25kHz
fSAMPLE = 50.6kHz
SNR = 72.54dB
0
–140
24
0
4
8
12
16
20
FREQUENCY (kHz)
1290 • F17a
1290 • F17b
Figure 17a. LTC1290 FFT Plot
fIN1 = 5.1kHz
fIN2 = 5.6kHz
fSAMPLE = 50.6kHz
0
11.6
–20
11.2
MAGNITUDE (dB)
EFFECTIVE NUMBER OF BITS
Figure 17b. LTC1290 FFT Plot
fSAMPLE = 50.6kHz
12
24
10.8
10.4
10
9.6
–40
–60
–80
–100
9.2
–120
8.8
0
20
60
40
FREQUENCY (kHz)
80
100
0
4
8
12
16
20
FREQUENCY (kHz)
1290 F18
24
1290 • F19
Figure 18. LTC1290 ENOB vs Input Frequency
Figure 19. LTC1290 FFT Plot
fundamentals. This is classically referred to as
intermodulation distortion (IMD).
then the following guidelines can be used. Limit the
current to 7mA per channel and 28mA for all channels.
This means four channels can handle 7mA of input current
each. Reducing the ACLK and SCLK frequencies from the
maximum of 4MHz and 2MHz, respectively, (see Typical
Peformance Characteristics curves Maximum ACLK Frequency vs Source Resistance and Sample-and-Hold
Acquisition Time vs Source Resistance) allows the use of
8. Overvoltage Protection
Applying signals to the analog MUX that exceed the
positive or negative supply of the device will degrade the
accuracy of the A/D and possibly damage the device. For
example this condition would occur if a signal is applied to
the analog MUX before power is applied to the LTC1290.
Another example is the input source is operating from
different supplies of larger value than the LTC1290. These
conditions should be prevented either with proper supply
sequencing or by use of external circuitry to clamp or
current limit the input source. As shown in Figure 20, a 1k
resistor is enough to stand off ±15V (15mA for one only
channel). If more than one channel exceeds the supplies
VIN
1k
VCC
CH0
5V
22µF
LTC1290
DGND
V–
–5V
AGND
0.1µF
1290 F20
Figure 20. Overvoltage Protection for MUX
23
LTC1290
W
U
U
UO
APPLICATI
S I FOR ATIO
larger current limiting resistors. Use 1N4148 diode clamps
from the MUX inputs to VCC and V – if the value of the series
resistor will not allow the maximum clock speeds to be
used or if an unknown source is used to drive the LTC1290
MUX inputs.
How the various power supplies to the LTC1290 are
applied can also lead to overvoltage conditions. For single
supply operation (i.e., unipolar mode), if VCC and REF + are
not tied together, then VCC should be turned on first, then
REF +. If this sequence cannot be met, connecting a diode
from REF + to VCC is recommended (see Figure 21).
For dual supplies (bipolar mode) placing two Schottky
diodes from VCC and V – to ground (Figure 23) will prevent
VCC
20
power supply reversal from occuring when an input source
is applied to the analog MUX before power is applied to the
device. Power supply reversal occurs, for example, if the
input is pulled below V – then VCC will pull a diode drop
below ground which could cause the device not to power
up properly. Likewise, if the input is pulled above VCC then
V – will be pulled a diode drop above ground. If no inputs
are present on the MUX, the Schottky diodes are not
required if V – is applied first, then VCC.
Because a unique input protection structure is used on the
digital input pins, the signal levels on these pins can
exceed the device VCC without damaging the device.
5V
VCC
5V
22µF
LTC1290
1N5817
22µF
1N5817
0.1µF
LTC1290
1N4148
V–
+ 14
REF
DGND
VREF
–5V
AGND
1290 F21
1290 F22
Figure 21
Figure 22. Power Supply Reversal
UO
TYPICAL APPLICATI
S
A “Quick Look” Circuit for the LTC1290
A “Quick Look” Circuit for the LTC1290
Users can get a quick look at the function and timing of the
LTC1290 by using the following simple circuit. REF + and
DIN are tied to VCC selecting a 5V input span, CH7 as a
single-ended input, unipolar mode, MSB-first format and
16-bit word length. ACLK and SCLK are tied together and
driven by an external clock. CS is driven at 1/128 the clock
rate by the CD4520 and DOUT outputs the data. All other
pins are tied to a ground plane. The output data from the
DOUT pin can be viewed on an oscilloscope which is set up
to trigger on the falling edge of CS.
5V
22µF
VIN
LTC1290
f/128
CHO
VCC
CH1
ACLK
CH2
SCLK
CLK
f
VDD
EN
RESET
Q4
CH3
DIN
Q1
CH4
DOUT
Q2
CH5
CS
Q3
Q2
CH6
REF +
Q4
Q1
CH7
REF –
RESET
COM
V–
DGND
CD4520
VSS
Q3
EN
CLK
AGND
{
CLOCK IN
2MHz MAX
TO
OSCILLOSCOPE
24
0.1µF
1290 TA02
LTC1290
UO
TYPICAL APPLICATI
S
Scope Trace of LTC1290 “Quick Look” Circuit
Showing A/D Output of 010101010101 (555HEX)
CS
ACLK/
SCLK
DOUT
DEGLITCHER
TIME
FILLS
ZEROS
LSB
(B0)
MSB
(B11)
VERTICAL: 5V/DIV
HORIZONTAL: 1µs/DIV
SNEAK-A-BITTM
The LTC1290’s unique ability to software select the polarity of the differential inputs and the output word length is
used to achieve one more bit of resolution. Using the
circuit below with two conversions and some software, a
2’s complement 12-bit + sign word is returned to memory
inside the MPU. The MC68HC05C4 was chosen as an
example, however, any processor could be used.
Two 12-bit unipolar conversions are performed: the first
over a 0V to 5V span and the second over a 0V to –5V span
(by reversing the polarity of the inputs). The sign of the
input is determined by which of the two spans contained
it. Then the resulting number (ranging from –4095 to
+4095 decimal) is converted to 2’s complement notation
and stored in RAM.
SNEAK-A-BIT Circuit
SNEAK-A-BIT
VIN
22µF
5V
LT1021-5
9V
VIN
(+) CH6
1ST CONVERSION
4096 STEPS
(–) CH7
2MHz
CLOCK
OTHER CHANNELS
OR SNEAK-A-BIT
INPUTS
CHO
VCC
CH1
ACLK
CH2
SCLK
CH3
DIN
MOSI
CH4
DOUT
MISO
CH5
VIN
–5V TO 5V
1ST CONVERSION
MC68HC05C4
SCLK
LTC1290
REF +
CH7
REF –
COM
DGND
V
0V
SOFTWARE
0V
(–) CH6
0V
8191
STEPS
2ND CONVERSION
4096 STEPS
(+) CH7
–5V
–5V
2ND CONVERSION
1290 TA05
CO
CS
CH6
VIN
5V
1290 TA04
–
AGND
0.1µF
–5V
SNEAK-A-BIT is a trademark of Linear Technology Corp.
25
LTC1290
UO
TYPICAL APPLICATI
S
SNEAK-A-BIT Code
SNEAK-A-BIT Code for the LTC1290 Using the MC68HC05C4
DOUT from LTC1290 in MC68HC05C4 RAM
MNEMONIC
Sign
READ –/+:
LOCATION $77
B12
B11
B10
B9
LOCATION $87
B4
B3
B2
B1
B8
B7
B6
B5
LSB
B0
Filled with 0s
DIN Words for LTC1290
MSBF
MUX Addr.
UNI
Word
Length
(ODD/SIGN)
DIN1
0
0
1
1
1
1
1
1
DIN2
0
1
1
1
1
1
1
1
DIN3
0
0
1
1
1
1
1
1
1290 TA06
SNEAK-A-BIT Code for the LTC1290 Using the MC68HC05C4
MNEMONIC
26
LDA
STA
LDA
STA
BSET
JSR
#$50
$0A
#$FF
$06
0,$02
READ –/+
JSR
JSR
JSR
READ –/+
READ –/+
CHK Sign
DESCRIPTION
Configuration Data for SPCR
Load Configuration Data into $0A
Configuration Data for Port C DDR
Load Configuration Data into Port C DDR
Make Sure CS is High
Dummy Read Configures LTC1290
for next read
Read CH6 with Respect to CH7
Read CH7 with Respect to CH6
Determines which Reading has Valid Data,
Converts to 2’s Complement and
Stores in RAM
LDA
JSR
LDA
STA
LDA
STA
RTS
READ +/–: LDA
JSR
LDA
STA
LDA
STA
RTS
TRANSFER: BCLR
STA
LOOP 1:
TST
BPL
LDA
STA
STA
LOOP 2:
TST
BPL
BSET
LDA
STA
RTS
CHK SIGN: LDA
ORA
BEQ
CLC
ROR
ROR
LDA
STA
LDA
STA
BRA
MINUS:
CLC
ROR
ROR
COM
COM
LDA
ADD
STA
CLRA
ADC
STA
STA
LDA
STA
END:
RTS
#$3F
TRANSFER
$60
$71
$61
$72
#$7F
TRANSFER
$60
$73
$61
$74
0,$02
$0C
$0B
LOOP 1
$0C
$0C
$60
$0B
LOOP 2
0,$02
$0C
$61
$73
$74
MINUS
$73
$74
$73
$77
$74
$87
END
$71
$72
$71
$72
$72
#$01
$72
$71
$71
$77
$72
$87
DESCRIPTION
Load DIN Word for LTC1290 into ACC
Read LTC1290 Routine
Load MSBs from LTC1290 into ACC
Store MSBs in $71
Load LSBs from LTC1290 into ACC
Store LSBs in $72
Return
Load DIN Word for LTC1290 into ACC
Read LTC1290 Routine
Load MSBs from LTC1290 into ACC
Store MSBs in $73
Load LSBs from LTC1290 into ACC
Store LSBs in $74
Return
CS Goes Low
Load DIN into SPI, Start Transfer
Test Status of SPIF
Loop to Previous Instruction if Not Done
Load Contents of SPI Data Reg. into ACC
Start Next Cycle
Store MSBs in $60
Test Status of SPIF
Loop to Previous Instruction if Not Done
CS Goes High
Load Contents of SPI Data Reg. into ACC
Store LSBs in $61
Return
Load MSBs of ± Read into ACC
Or ACC (MSBs) with LSBs of ± Read
If Result is 0 Go to Minus
Clear Carry
Rotate Right $73 Through Carry
Rotate Right $74 Through Carry
Load MSBs of ± Read into ACC
Store MSBs in RAM Location $77
Load LSBs of ± Read into ACC
Store LSBs in RAM Location $87
Go to End of Routine
Clear Carry
Shift MSBs of ± Read Right
Shift LSBs of ± Read Right
1’s Complement of MSBs
1’s Complement of LSBs
Load LSBs into ACC
Add 1 to LSBs
Store ACC in $72
Clear ACC
Add with Carry to MSBs. Result in ACC
Store ACC in $71
Store MSBs in RAM Location $77
Load LSBs in ACC
Store LSBs in RAM Location $87
Return
LTC1290
UO
TYPICAL APPLICATI
S
Power Shutdown
For battery-powered applications it is desirable to keep
power dissipation at a minimum. The LTC1290 can be
powered down when not in use reducing the supply
current from a nominal value of 5mA to typically 5µA (with
ACLK turned off). See the curve for Supply Current (Power
Shutdown) vs ACLK if ACLK cannot be turned off when the
LTC1290 is powered down. In this case the supply current
is proportional to the ACLK frequency and is independent
of temperature until it reaches the magnitude of the supply
current attained with ACLK turned off.
As an example of how to use this feature let’s add this to
the previous application, SNEAK-A-BIT. After the CHK
SIGN subroutine call insert the following:
•
•
JSR CHK SIGN
Determines which reading has valid
data, converts to 2’s complement
and stores in RAM
JSR SHUTDOWN
LTC1290 power shutdown routine
The actual subroutine is:
Load DIN word for
LTC1290 into ACC
JSR TRANSFER Read LTC1290 routine
RTS
Return
SHUTDOWN: LDA #$3D
To place the device in power shutdown the word length
bits are set to WL1 = 0 and WL0 = 1. The LTC1290 is
powered up on the next request for a conversion and it’s
ready to digitize an input signal immediately.
Power Shutdown Timing Considerations
After power shutdown has been requested, the LTC1290
is powered up on the next request for a conversion. This
request can be initiated either by bringing CS low or by
starting the next cycle of SCLKs if CS is kept low (see
Figures 3 and 4). When the SCLK frequency is much
slower than the ACLK frequency a situation can arise
where the LTC1290 could power down and then prematurely power back up. Power shutdown begins at the
negative going edge of the 10th SCLK once it has been
requested. A dummy conversion is executed and the
LTC1290 waits for the next request for conversion. If the
SCLKs have not finished once the LTC1290 has finished its
dummy conversion, it will recognize the next remaining
SCLKs as a request to start a conversion and power up the
LTC1290 (see Figure 23). To prevent this, bring either CS
high at the 10th SCLK (Figure 24) or clock out only 10
SCLKs (Figure 25) when power shutdown is requested.
CS
1
10
SCLK
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
POWER UP
1290 TAF23
Figure 23. Power Shutdown Timing Problem
CS
1
10
POWER UP
SCLK
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
1290 TAF24
Figure 24. Power Shutdown Timing
CS
1
10
POWER UP
SCLK
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
1290 TAF25
Figure 25. Power Shutdown Timing
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
27
LTC1290
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
J Package
20-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
0.300 BSC
(0.762 BSC)
0.008 – 0.018
(0.203 – 0.457)
CORNER LEADS OPTION
(4 PLCS)
0.015 – 0.060
(0.381 – 1.524)
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
0° – 15°
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
1.060
(26.924)
MAX
0.200
(5.080)
MAX
20
11
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
0.220 – 0.310 0.025
(5.588 – 7.874) (0.635)
RAD TYP
1
0.125
(3.175)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.045 – 0.068
(1.143 – 1.727)
0.014 – 0.026
(0.356 – 0.660)
10
0.005
(0.127)
MIN
J20 1197
N Package
20-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
(
+0.035
0.325 –0.015
+0.889
8.255
–0.381
0.045 – 0.065
(1.143 – 1.651)
0.020
(0.508)
MIN
0.009 – 0.015
(0.229 – 0.381)
)
1.040*
(26.416)
MAX
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
9
0.018 ± 0.003
(0.457 ± 0.076)
0.005
(0.127)
MIN
11
0.255 ± 0.015*
(6.477 ± 0.381)
0.065
(1.651)
TYP
0.125
(3.175)
MIN
20
10
N20 1197
0.100 ± 0.010
(2.540 ± 0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
SW Package
20-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.291 – 0.299**
(7.391 – 7.595)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0.093 – 0.104
(2.362 – 2.642)
0.496 – 0.512*
(12.598 – 13.005)
0.037 – 0.045
(0.940 – 1.143)
20 19 18 17 16 15 14 13 12 11
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
0.050
(1.270)
TYP
0.014 – 0.019
(0.356 – 0.482)
TYP
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.004 – 0.012
(0.102 – 0.305)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
1
2
3
4
5
6
7
8
9 10
S20 (WIDE) 0396
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
*
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
**
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1286/LTC1298
12-Bit, Micropower Serial ADC in SO-8
1- or 2-Channel, Autoshutdown
LTC1293/LTC1294/LTC1296
12-Bit, Multiplexed Serial ADC
6-, 8- or 8-Channel with Shutdown Output
LTC1594/LTC1598
12-Bit, Micropower Serial ADC
4- or 8-Channel, 3V Versions Available
28
Linear Technology Corporation
1290fcs, sn1290 LT/GP 1098 2K REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1991