CD74FCT651, CD74FCT652 Data sheet acquired from Harris Semiconductor SCHS262 D ENDE M M O S EC IGN NOT R NEW DES ology n Tech FOR January 1997 Features MOS Use C • CD74FCT652 - Noninverting • Family Features - SCR Latchup Resistant BiCMOS Process and Circuit Design - Speed of Bipolar FAST™/AS/S - 64mA Output Sink Current - Output Voltage Swing Limited to 3.7V at VCC = 5V - Controlled Output Edge Rates - Input/Output Isolation to VCC - BiCMOS Technology with Low Quiescent Power Ordering Information TEMP. RANGE (oC) PACKAGE Description The CD74FCT651 and CD74FCT652 three-state, octal bus transceivers/registers use a small geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output HIGH level to two diode drops below VCC. This resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 milliamperes. • Buffered Inputs • Typical Propagation Delay: 6.8ns at VCC = 5V, TA = 25oC, CL = 50pF • CD75FCT651 - Inverting PART NUMBER BiCMOS FCT Interface Logic, Octal Bus Transceivers/Registers, Three-State PKG. NO. CD74FCT651EN 0 to 70 24 Ld PDIP E24.3 CD74FCT652EN 0 to 70 24 Ld PDIP E24.3 CD74FCT651M 0 to 70 24 Ld SOIC M24.3 CD74FCT652M 0 to 70 24 Ld SOIC M24.3 NOTE: When ordering the suffix M packages, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. These devices consist of bus transceiver circuits, D-Type flipflops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output Enables OEAB and OEBA are provided to control the transceiver functions. SAB and SBA control pins are provided to select whether real-time or stored data is transferred. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A LOW input level selects real-time data and a HIGH selects stored data. The following examples demonstrate the four fundamental bus management functions that can be performed with the octal bus transceivers and registers. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low to high transitions at the appropriate clock pins (CAB or CBA) regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-Type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. Pinouts CD74FCT651 (PDIP, SOIC) TOP VIEW CD74FCT652 (PDIP, SOIC) TOP VIEW CAB 1 24 VCC CAB 1 24 VCC SAB 2 23 CBA SAB 2 23 CBA OEAB 3 22 SBA OEAB 3 22 SBA A0 4 21 OEBA A0 4 21 OEBA A1 5 20 B0 A1 5 20 B0 A2 6 19 B1 A2 6 19 B1 A3 7 18 B2 A3 7 18 B2 A4 8 17 B3 A4 8 17 B3 A5 9 16 B4 A5 9 16 B4 A6 10 15 B5 A6 10 15 B5 A7 11 14 B6 A7 11 14 B6 GND 12 13 B7 GND 12 13 B7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a trademark of Fairchild Semiconductor. Copyright © Harris Corporation 1997 8-1 File Number 2394.2 CD74FCT651, CD74FCT652 Functional Diagram A0 A1 A2 A3 A DATA PORT A4 A5 A6 A7 FLIP-FLOP CLOCKS 4 20 5 19 6 18 7 17 8 16 9 15 10 14 11 13 OEBA OEAB CAB CLOCK CBA CLOCK 21 3 1 23 2 22 B0 B1 B2 B3 B DATA PORT B4 B5 B6 B7 SAB SOURCE SBA SOURCE DATA SOURCE SELECTION INPUTS GND = PIN 12 VCC = PIN 24 TRUTH TABLE INPUTS OEAB OEBA CAB CBA H or L H or L ↑ ↑ DATA I/O SBA X X X X Input Input Input Input Input Input Unspecified (2) Store A, Hold B Output Store A in both registers L L H H X H H H ↑ ↑ H or L ↑ X X (3) X X L L X L H or L ↑ ↑ ↑ X X X X (3) L L L L X X X H or L X X H H H H X H or L X X H L H or L H or L A0 THRU A7 B0 THRU B7 OPERATION OR FUNCTION SAB CD74FCT651 Isolation (Note 1) Store A and B Data CD74FCT652 Isolation (Note 1) Store A and B Data Store A, Hold B Store A in both registers Unspecified (2) Input Output Input Hold A, Store B Store B in both registers Hold A, Store B Store B in both registers L H Output Output Input Input Real-Time B Data to A Bus Real-Time B Data to A Bus Stored B Data to A Bus Stored B Data to A Bus L H X X Input Input Output Output Real-Time A Data to B Bus Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus H H Output Output Stored A Data to B Bus Stored B Data to A Bus Stored A Data to B Bus Stored B Data to A Bus NOTES: 1. To prevent excess currents in the High-Z (isolation) modes, all I/O terminals should be terminated with 10kΩ to 1MΩ resistors. 2. The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. 3. Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered in order to load both registers. 8-2 CD74FCT651, CD74FCT652 IEC Logic Symbol CD74FCT651 21 3 22 2 23 1 3EN1 3EN2 G6 G7 >C4 >C5 1 ≥1 6 6 4 CD74FCT652 5D 21 3 22 2 23 1 1 ≥1 6 6 4D 7 ≥1 2 7 3EN1 3EN2 G6 G7 >C4 >C5 20 4 5D 4D 7 ≥1 2 7 20 5 19 5 19 6 18 6 7 8 9 10 18 17 16 15 14 7 17 8 16 9 15 10 14 11 13 11 13 8-3 CD74FCT651, CD74FCT652 Absolute Maximum Ratings Thermal Information DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . -20mA DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . . 70mA DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140mA DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . . 528mA Thermal Resistance (Typical, Note 4) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC-Lead Tips Only) Operating Conditions Operating Temperature Range (TA) . . . . . . . . . . . . . . . .0oC to 70oC Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ VCC Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Commercial Temperature Range 0oC to 70oC, VCC Max = 5.25V, VCC Min = 4.75V AMBIENT TEMPERATURE (TA) 25oC TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) 0oC TO 70oC VCC (V) MIN MAX MIN MAX UNITS High Level Input Voltage VIH 4.75 to 5.25 2 - 2 - V Low Level Input Voltage VIL 4.75 to 5.25 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -15 Min 2.4 - 2.4 - V Low Level Output Voltage VOL VIH or VIL 64 Min - 0.55 - 0.55 V High Level Input Current IIH VCC Max - 0.1 - 1 µA Low Level Input Current IIL GND Max - -0.1 - -1 µA IOZH VCC Max - 0.5 - 10 µA IOZL GND Max - -0.5 - -10 µA Input Clamp Voltage VIK VCC or GND Min - -1.2 - -1.2 V Short Circuit Output Current (Note 5) IOS VO = 0 VCC or GND Max -60 - -60 - mA Quiescent Supply Current, MSI ICC VCC or GND Max - 8 - 80 µA ∆ICC 3.4V (Note 6) Max - 1.6 - 1.6 mA Three-State Leakage Current Additional Quiescent Supply Current per Input Pin TTL Inputs High, 1 Unit Load -18 0 NOTES: 5. Not more than one output should be shorted at one time. Test duration should not exceed 100ms. 6. Inputs that are not measured are at VCC or GND. 7. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Electrical Specifications table, e.g., 1.6mA Max. at 70oC. 8-4 CD74FCT651, CD74FCT652 Switching Specifications Over Operating Range FCT Series tr, tf = 2.5ns, CL = 50pF, RL (Figure 4) PARAMETER 25oC 0oC TO 70oC SYMBOL VCC (V) TYP MIN MAX UNITS Propagation Delays Stored An → Bn CD74FCT651 tPLH, tPHL 5 6.8 2 9 ns Stored An → Bn CD74FCT652 tPLH, tPHL 5 6.8 2 9 ns Stored Bn → An CD74FCT651 tPLH, tPHL 5 6.8 2 9 ns Stored Bn → An CD74FCT652 tPLH, tPHL 5 6.8 2 9 ns An → Bn CD74FCT651 tPLH, tPHL 5 6.8 2 9 ns An → Bn CD74FCT652 tPLH, tPHL 5 6.8 2 9 ns Bn → An CD74FCT651 tPLH, tPHL 5 6.8 2 9 ns Bn → An CD74FCT652 tPLH, tPHL 5 6.8 2 9 ns Select to Data CD74FCT651, CD74FCT652 tPLH, tPHL 5 8.3 2 11 ns Three-State Enabling Time, Bus to Output or Register to Output CD74FCT651, CD74FCT652 tPZL, tPZH 5 7.5 2 10 ns Three-State Disabling Time, Bus to Output or Register to Output CD74FCT651, CD74FCT652 tPLZ, tPHZ 5 7.5 2 10 ns CPD (Note 8) − Minimum (Valley) VOHV During Switching of Other Outputs (Output Under Test Not Switching) VOHV 5 0.5 Typical at 25oC V Maximum (Peak) VOLP During Switching of Other Outputs (Output Under Test Not Switching) VOLP 5 1 Typical at 25oC V CI - - - 10 pF CI/O - - - 15 pF Power Dissipation Capacitance Input Capacitance Input/Output Capacitance pF NOTE: 8. CPD, measured per flip-flop, is used to determine the dynamic power consumption. PD (per package) = VCC ICC + Σ(VCC2 fI CPD + VO2 fO CL + VCC ∆ICC D) where: VCC = supply voltage ∆ICC = flow through current x unit load CL = output load capacitance D = duty cycle of input high fO = output frequency fI = input frequency Prerequisite for Switching 25oC PARAMETER 0oC TO 70oC SYMBOL VCC (V) TYP MIN MAX UNITS fMAX 5 (Note 9) - 85 - MHz tSU 5 - 4 - ns Data to Clock Hold Time tH 5 - 2 - ns Clock Pulse Width tW 5 - 6 - ns Maximum Frequency Data to Clock Setup Time NOTE: 9. 5V: Minimum is at 4.75V for 0oC to 70oC, Typical is at 5V. 8-5 Test Circuits and Waveforms VCC tr, tf = 2.5ns (NOTE 10) VI 3V 0 PULSE ZO GEN SWITCH POSITION 7V 500Ω RL V0 DUT CL 50pF RT RT = ZO 500Ω RL 10. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZOUT ≤ 50Ω; tf, tr ≤ 2.5ns. FIGURE 1. TEST CIRCUIT tPLZ, tPZL, Open Drain Closed tPHZ, tPZH, tPLH, tPHL Open 3V 1.5V 0V DATA INPUT tH 3V 1.5V 0V TIMING INPUT tREM ASYNCHRONOUS CONTROL SWITCH DEFINITIONS: CL = Load capacitance, includes jig and probe capacitance. RT = Termination resistance, should be equal to ZOUT of the Pulse Generator. VIN = 0V to 3V. Input: tr = tf = 2.5ns (10% to 90%), unless otherwise specified NOTE: tSH TEST 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 3V 1.5V 0V tH tSH HIGH-LOW-HIGH PULSE FIGURE 2. SETUP, HOLD, AND RELEASE TIMING ENABLE 1.5V FIGURE 3. PULSE WIDTH DISABLE 3V 3V SAME PHASE INPUT TRANSITION 1.5V CONTROL INPUT 0V 3.5V OUTPUT NORMALLY LOW SWITCH CLOSED SWITCH OPEN tPHL 3.5V VOH 1.5V 1.5V VOL OUTPUT 0.3V tPZH OUTPUT NORMALLY HIGH tPLH tPLZ tPZL 1.5V tPHZ 0.3V VOL tPLH tPHL VOH 3V OPPOSITE PHASE INPUT TRANSITION 1.5V 0V 0V 0V 1.5V 0V FIGURE 4. ENABLE AND DISABLE TIMING FIGURE 5. PROPAGATION DELAY 8-6 Test Circuits and Waveforms (Continued) VOH OTHER OUTPUTS VOL VOH OUTPUT UNDER TEST VOHV VOLP VOL NOTES: 11. VOLP is measured with respect to a ground reference near the output under test. VOHV is measured with respect to VOH. 12. Input pulses have the following characteristics: PRR ≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns. 13. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and probes require 700MHz bandwidth. FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS 8-7 PACKAGE OPTION ADDENDUM www.ti.com 7-Jun-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CD74FCT651EN OBSOLETE PDIP NT 24 TBD Call TI Call TI Samples Not Available CD74FCT651M OBSOLETE SOIC DW 24 TBD Call TI Call TI Samples Not Available CD74FCT652EN OBSOLETE PDIP NT 24 TBD Call TI Call TI Samples Not Available CD74FCT652M OBSOLETE SOIC DW 24 TBD Call TI Call TI Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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