PD - 9.1096B
IRF7104
HEXFET® Power MOSFET
Adavanced Process Technology
Ultra Low On-Resistance
l Dual P-Channel MOSFET
l Surface Mount
l Available in Tape & Reel
l Dynamic dv/dt Rating
l Fast Switching
Description
l
l
1
8
D1
G1
2
7
D1
S2
3
6
D2
G2
4
5
D2
S1
VDSS = -20V
RDS(on) = 0.250Ω
ID = -2.3A
Top View
Fourth Generation HEXFETs from International
Rectifier utilize advanced processing techniques to
achieve the lowest possible on-resistance per silicon
area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET
Power MOSFETs are well known for, provides the
designer with an extremely efficient device for use in
a wide variety of applications.
The SO-8 has been modified through a customized
leadframe for enhanced thermal characteristics and
dual-die capability making it ideal in a variety of power
applications. With these improvements, multiple
devices can be used in an application with dramatically
reduced board space. The package is designed for
vapor phase, infra red, or wave soldering techniques.
Power dissipation of greater than 0.8W is possible in
a typical PCB mount application.
S O -8
Absolute Maximum Ratings
Parameter
ID @ TA = 25°C
ID @ TA = 70°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ, TSTG
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Junction and Storage Temperature Range
Units
-2.3
-1.8
-10
2.0
0.016
± 12
-3.0
-55 to + 150
A
W
W/°C
V
V/nS
°C
Thermal Resistance Ratings
Parameter
RθJA
Maximum Junction-to-Ambient
Min.
Typ.
Max.
Units
–––
–––
62.5
°C/W
8/25/97
IRF7104
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
RDS(ON)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
V(BR)DSS
Qg
Q gs
Q gd
t d(on)
tr
t d(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
LD
Internal Drain Inductance
IGSS
Min.
-20
–––
–––
–––
-1.0
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ. Max. Units
Conditions
––– –––
V
VGS = 0V, ID = -250µA
-0.015 ––– V/°C Reference to 25°C, ID = -1mA
0.19 0.25
VGS = -10V, I D = -1.0A
Ω
0.30 0.40
VGS = -4.5V, ID = -0.50A
––– -3.0
V
VDS = VGS, I D = -250µA
2.5 –––
S
V DS = -15V, ID = -2.3A
––– -2.0
VDS = -16V, VGS = 0V
µA
––– -25
VDS = -16V, VGS = 0V, TJ = 55 °C
––– -100
VGS = -12V
nA
––– 100
VGS = 12V
9.3
25
I D = -2.3A
1.6 –––
nC VDS = -10V
3.0 –––
VGS = -10V
12
40
VDD = -10V
16
40
I D = -1.0A
ns
42
90
R G = 6.0Ω
30
50
RD = 10Ω
D
–––
4.0
–––
nH
LS
Internal Source Inductance
–––
6.0
–––
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
290
210
67
–––
–––
–––
pF
Between lead,6mm(0.25in.)
from package and center
of die contact
VGS = 0V
VDS = -15V
ƒ = 1.0MHz
G
Source-Drain Ratings and Characteristics
IS
ISM
V SD
t rr
Q rr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– -2.0
showing the
A
G
integral reverse
––– ––– -9.2
p-n junction diode.
S
––– ––– -1.2
V
TJ = 25°C, IS = -1.25A, VGS = 0V
––– 69 100
ns
TJ = 25°C, IF = -1.25A
––– 90 140
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
ISD ≤ -2.3A, di/dt ≤ 100A/µs, VDD ≤ V (BR)DSS,
TJ ≤ 150°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Surface mounted on FR-4 board, t ≤ 10sec.
S
-ID , Drain-to-Source Current ( A )
-ID , Drain-to-Source Current ( A )
IRF7104
-VDS , Drain-to-Source Voltage ( V )
-VDS , Drain-to-Source Voltage ( V )
Fig 2. Typical Output Characteristics
-ID , Drain-to-Source Current ( A )
RDS (on) , Drain-to-Source On Resistance
( Normalized)
Fig 1. Typical Output Characteristics
-VGS , Gate-to-Source Voltage ( V )
Fig 3. Typical Transfer Characteristics
TJ , Junction Temperature ( °C )
Fig 4. Normalized On-Resistance
Vs. Temperature
C , Capacitance ( pF )
-V GS , Gate-to-Source Voltage ( V )
IRF7104
SEE FIGURE 12
QG , Total Gate Charge ( nC )
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
-ID , Drain Current ( A )
-ISD , Reverse Drain Current ( A )
-VDS , Drain-to-Source Voltage ( V )
-VSD , Source-to-Drain Voltage ( V )
Fig 7. Typical Source-Drain Diode
Forward Voltage
-VDS , Drain-to-Source Voltage ( V )
Fig 8. Maximum Safe Operating Area
IRF7104
V DS
VGS
RD
D.U.T.
-ID , Drain Current ( A )
RG
+
VDD
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
td(on)
tr
t d(off)
tf
VGS
10%
TA , Ambient Temperature ( °C )
90%
VDS
Fig 9. Maximum Drain Current Vs.
Ambient Temperature
Fig 10b. Switching Time Waveforms
(Z thJA )
100
D = 0.50
0.20
10
Thermal Response
0.10
0.05
0.02
1
PDM
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
0.1
0.0001
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJA + TA
0.001
0.01
0.1
1
10
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
100
IRF7104
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
-10V
QGS
QGD
D.U.T.
+VDS
VGS
VG
-3mA
Charge
Fig 12a. Basic Gate Charge Waveform
IG
ID
Current Sampling Resistors
Fig 12b. Gate Charge Test Circuit
IRF7104
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
RG
VGS
*
+
-
V DD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 13.For P-Channel HEXFETS
[ ISD ]
IRF7104
Package Outline
SO8 Outline
INCHES
DIM
D
-B-
5
8
7
6
5
1
2
3
4
e
6X
0.25 (.010)
M
A M
MIN
A
.0532
.0688
1.35
1.75
A1
.0040
.0098
0.10
0.25
B
.014
.018
0.36
0.46
C
.0075
.0098
0.19
0.25
D
.189
.196
4.80
4.98
E
.150
.157
3.81
3.99
e
K x 45°
e1
e1
θ
A
-C-
0.10 (.004)
L
8X
A1
B 8X
0.25 (.010)
MAX
5
H
E
-A-
6
C
8X
.050 BASIC
1.27 BASIC
.025 BASIC
0.635 BASIC
.2284
.2440
5.80
K
.011
.019
0.28
0.48
L
0.16
.050
0.41
1.27
8°
0°
8°
0°
6.20
RECOMMENDED FOOTPRINT
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M-1982.
2. CONTROLLING DIMENSION : INCH.
3. DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES).
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS
6
MAX
H
θ
M C A S B S
MILLIMETERS
MIN
0.72 (.028 )
8X
6.46 ( .255 )
1.78 (.070)
8X
MOLD PROTRUSIONS NOT TO EXCEED 0.25 (.006).
DIMENSIONS IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE..
1.27 ( .050 )
3X
Part Marking Information
SO8
E X A M P LE : TH IS IS A N IR F 7 101
3 12
IN T E R N A TI ON A L
R E C T IF IE R
LO G O
D A T E C O D E (Y W W )
Y = LA S T D IG IT O F T H E YE A R
W W = W EEK
XX X X
F 7 101
T OP
PART NUMBER
W AFER
LO T C O D E
(LA S T 4 D IG IT S )
B O T TO M
IRF7104
Tape & Reel Information
SO8
Dimensions are shown in millimeters (inches)
T ER M IN A L N U M B E R 1
12 .3 ( .48 4 )
11 .7 ( .46 1 )
8 .1 ( .3 18 )
7 .9 ( .3 12 )
F E ED D IR E C T IO N
N O TE S:
1 . CO N TRO LL IN G D IM E N SIO N : M ILLIM E TE R.
2 . A LL DIM E NS IO NS A R E S HO W N IN M ILL IM E TER S (INC HE S ).
3 . O UTL IN E C O NFO RM S TO E IA - 48 1 & E IA -5 41 .
33 0. 00
(12 .99 2)
M A X.
1 4. 40 ( .5 66 )
1 2. 40 ( .4 88 )
N O T ES :
1. C O N T R O LL IN G D IM E N S IO N : M IL LIM E T ER .
2. O U T L IN E C O N F O R M S T O E IA -48 1 & E IA -54 1.
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http://www.irf.com/
Data and specifications subject to change without notice.
8/97