ETC1 NX29F010-70TI 1m-bit (128k x 8-bit) cmos, 5.0v only ultra-fast sectored flash memory Datasheet

NX29F010
1M-BIT (128K x 8-bit)
CMOS, 5.0V Only
ULTRA-FAST SECTORED FLASH MEMORY
JUNE 2000
FEATURES
• Ultra-fast Performance
– 35, 45, 55, 70, and 90 ns max. access times
• Temperature Ranges
– Commercial 0oc-70oc
– Industrial -40oc-85oc
• Single 5V-only Power Supply
– 5V ± 10% for Read, Program, and Erase
• CMOS Low Power Consumption
– 20 mA (typical) active read current
– 30 mA (typical) Program/Erase current
• Compatible with JEDEC-Standard Pinouts
– 32-pin DIP, PLCC, TSOP
• Program/function Compatible with AM29F010
– No system firmware changes
– Uses same PROM programer algorithm
DESCRIPTION
The NexFlash NX29F010 is a 1 Megabit (131,072 bytes)
single 5.0V-only Sectored Flash Memory. The NX29F010
provides in-system programming with the standard system
5.0V-only Vcc supply and can be programmed or erased in
standard PROM programmers.
The NX29F010 offers access times of 35, 45, 55, 70, and
90 ns allowing high-speed controller and DSPs' to operate
without wait states. Byte-wide data appears on DQ0-DQ7.
Separate chip enable (CE), write enable (WE), and output
enable (OE) controls eliminates bus contention.
Power consumption is greatly reduced when the system
places the device into the Standby Mode.
The device is offered in 32-pin PLCC, TSOP, and PDIP
packages.
• Flexible sector architecture
– Erase any of eight uniform sectors or full chip erase
– Sector protection/unprotection using PROM
programming equipment
• 100,000 Program/Erase cycles
• Embedded algorithms
– Automatically programs and verifies data at
specified address
– Auto-programs and erases the chip or any
designated sector
• Data/Polling and Toggle Bits
– Detect program or erase cycle completion
Principles of Operation
Only a single 5.0V power supply is required for both read and
write functions. Program or erase operations do not require
12.0V VPP. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with the
JEDEC single power supply Flash standard. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as input to
an internal state machine that controls the erase and
programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and
erase operations. Reading data out of the device is similar
to reading from other Flash or EPROM devices.
Executing the Program Command Sequence invokes the
Embedded Program Algorithm, an internal algorithm that
automatically times the program pulse widths and verifies
proper cell margin.
This document contains PRELIMINARY data. NexFlash reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We
assume no responsibility for any errors which may appear in this publication. © Copyright 1998, NexFlash Technologies, Inc..
NexFlash Technologies, Inc.
NXPF001F-0600
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NX29F010
Executing the Erase Command Sequence invokes the
Embedded Erase Algorithm, an internal algorithm that
automatically pre-programs the array to all zeros (if it is not
already programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin during erase.
By reading the DQ7 (Data Polling) and DQ6 (toggle) status
bits, the host system can detect whether a program or erase
operation is complete. After completion, the device is ready
to read array data or accept another command.
The sector erase architecture is designed to allow memory
sectors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is erased
before it is shipped to customers.
The hardware data protection includes a low Vcc detector
that automatically inhibits write operations during power
transitions. The hardware sector protection feature will
disable both program and erase operations in any combination of the sectors of memory, and is implemented using
standard EPROM programming algorithm.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. Data are
programmed one byte at a time using the EPROM programming algorithm of hot electron injection.
DQ7-DQ0
8
VCC
GND
WE
ERASE VOLTAGE
GENERATOR
INPUT/OUTPUT
BUFFERS
STATE
CONTROL
8
COMMAND
REGISTER
8
PGM VOLTAGE
GENERATOR
STB
CHIP ENABLE/
OUTPUT ENABLE
LOGIC
CE
OE
8
ADDRESS LATCH
TIMER
8
A0-A16
8
STB
VCC
DETECTOR
DATA
LATCH
Y-DECODER
Y-GATING
X-DECODER
CELL
MATRIX
Figure 1. NX29F010 Block Diagram
2
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NX29F010
PIN CONFIGURATIONS
Table 1. Pin Descriptions
NC
1
32
VCC
A0-A16
Address Inputs
A16
2
31
WE
DQ0-DQ7
Data Inputs/Outputs
A15
3
30
NC
CE
Chip Enable Input
A12
4
29
A14
A7
5
28
A13
OE
Output Enable Input
A6
6
27
A8
WE
Write Enable Input
A5
7
26
A9
Vcc
Power Supply Voltage
A4
8
25
A11
GND
Ground
A3
9
24
OE
NC
No Internal Connection
A2
10
23
A10
A1
11
22
CE
A0
12
21
DQ7
DQ0
13
20
DQ6
DQ1
14
19
DQ5
DQ2
15
18
DQ4
GND
16
17
DQ3
A15
A16
NC
VCC
WE
NC
INDEX
A12
Figure 2. NX29F010 32-pin Plastic DIP
4
3
2
1
32
31
30
A13
A5
7
27
A8
A4
8
26
A9
A3
9
25
A11
A2
10
24
OE
A1
11
23
A10
A0
12
22
CE
DQ0
13
21
DQ7
14
15
16
17
18
19
20
DQ6
28
DQ5
6
DQ4
A6
DQ3
A14
GND
29
DQ2
5
DQ1
A7
Figure 3. NX29F010 32-pin PLCC
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A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
Figure 4. NX29F010 32-pin TSOP
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NX29F010
BUS OPERATIONS
Table 2. Device Bus Operations(1, 2)
Operation
Read
Write
Standby
Output Disable
CE
OE
WE
Address (A16-A0)
DQ0-DQ7
L
L
VCC ± 0.5V
L
L
H
X
H
H
L
X
H
AIN
AIN
X
X
Data Out
Data In
High-Z
High-Z
Notes:
1. L = VIL , H = VIH , X = Don't care, AIN = Address In.
2. The sector protect and sector unprotect functions must be implemented via programming equipment.
See the Sector Protection/Unprotection section.
Requirements for Reading Array Data
Upon device power-up, or after a hardware reset, the internal
state machine is set for reading array data. This ensures
that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device
address inputs produce valid data on the device data
outputs. The device remains enabled for read access until
the command register contents are altered.
The system must drive the CE and OE pins to VIL to read
array data from the outputs. CE is the power control and
selects the device. OE is the output control that passes
array data to the output pins. During a READ operation, WE
must remain at VIH.
Write Commands/Command Sequences
The system must drive WE and CE to VIL, and OE to VIH to
write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory).
An erase operation can erase one sector, multiple sectors,
or the entire device. The Sector Address Table (see Table 3)
indicate the address space that each sector occupies. A
"sector address" consists of the address bits required to
uniquely select a sector. See the "Command Definitions"
section for details on erasing a sector or the entire chip.
4
Table 3. Sector Addresses Table
Sector
Sector A0
Sector A1
Sector A2
Sector A3
Sector A4
Sector A5
Sector A6
Sector A7
A16
0
0
0
0
1
1
1
1
A15
0
0
1
1
0
0
1
1
A14
0
1
0
1
0
1
0
1
Address Range
00000H-03FFFH
04000H-07FFFH
08000H-0BFFFH
0C000H-0FFFFH
10000H-13FFFH
14000H-17FFFH
18000H-1BFFFH
1C000H-1FFFFH
After the system writes the auto-select command
sequence, the device enters the auto-select mode. The
system can then read auto-select codes from the internal
register (which is separate from the memory array) on
DQ7-DQ0. Standard read cycle timings apply in this mode.
Refer to the "Auto-select Mode and Auto-select Command
Sequence" sections for more information.
Program and Erase Operation Status
By reading the status bits on DQ7-DQ0, the system may
check the status of the operation during an erase or program
operation.
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NX29F010
Standby Mode
In the Standby Mode, current consumption is greatly
reduced, and the outputs are placed in the high impedance
state, independent of the OE input. The system can place
the device in the standby mode when it is not reading or
writing to the device.
The device enters the CMOS standby mode when the CE
pin is held at VCC ± 0.5V. The device enters the TTL standby
mode when CE is held at VIH. The device requires the
standard access time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
sector protection, the sector address must appear on the
appropriate highest order address bits. Refer to the corresponding Sector Address Table (Table 3). The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on DQ7-DQ0.
To access the auto-select codes in-system, the host
system can issue the auto-select command via the
command register, as shown in the Command Definitions
table. This method does not require VID. See "Command
Definitions" for details on using the auto-select mode.
Sector Protection/Unprotection
Output Disable Mode
When the OE = VIH, the output from the device is disabled
and the output pins are placed in the high-impedance state.
Auto-select Mode
The auto-select mode provides access to the manufacturer
and device equivalent codes, as well as sector protection
verification codes, via the DQ7-DQ0 pins. This mode is
primarily intended for programming equipment to automatically
match a device to be programmed with its corresponding
programming algorithm. However, the auto-select codes
can also be accessed in-system through the command
register.
When using programming equipment, the auto-select mode
requires VID (11.5V to 12.5V) on address pin A9. Address
pins A1 and A0 must be as shown in Auto-select Codes
(High Voltage Method), Table 4. In addition, when verifying
The hardware sector protection feature disables both program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
Sector protection/unprotection procedure requires a high
voltage (VID) on address pin A9 and the control pins. Details
on this method are provided in a supplement. Contact an
NexFlash representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected. NexFlash
offers the option of programming and protecting sectors at
its factory prior to shipping the device. Contact a NexFlash
representative for details.
It is possible to determine whether a sector is protected or
unprotected. See "Auto-select Mode" for details.
Table 4. Auto-select Codes (High Voltage Method)
Description
Manufacturer
Equivalent ID
CE
L
OE
L
WE
H
A16-A14
X
A13-A10
X
A9
VID
A8-A2
X
A1
L
A0
L
DQ7-DQ0
01 (Hex)
Device
Equivalent ID
L
L
H
X
X
VID
X
L
H
20 (Hex)
Sector Protection
Verification
L
L
H
SA
X
VID
X
H
L
01H
(protected)
00H
(unprotected)
Note:
1. L = VIL , H = VIH , VID = 11.5 TO 12.5V , SA = ADDRESS SECTOR , X = Don't care.
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NX29F010
Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures prevent accidental erasure or programming, which
might otherwise be caused by spurious system level
signals during VCC power-up and power-down transitions, or
from system noise.
The system must issue the reset command to re-enable the
device for reading array data if the error status bit, DQ5, is set
high after an erase or program operation, or while in the
auto-select mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operation's table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
Reset Command
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL,
CE = VIH, or WE = VIH. To initiate a write cycle, CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power-up, the device
does not accept commands on the rising edge of WE. The
internal state machine is automatically reset to reading
array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions Table 5 defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
All addresses are latched on the falling edge of WE or CE,
whichever happens later. All data is latched on the rising
edge of WE or CE, whichever happens first. Refer to the
appropriate timing diagrams in the "AC Characteristics"
section.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm.
6
The reset command may be written between the sequence
cycles in an erase command sequence before erasing
begins. This resets the device for reading array data. Once
erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming begins. This resets the device to reading array data.
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an auto-select command sequence.
Once in the auto-select mode, the reset command must be
written to return to reading array data.
If the error status bit, DQ5, goes high during a program or
erase operation, writing the reset command returns the
device to reading array data.
Auto-select Command Sequence
The auto-select command sequence allows the host system to access the manufacturer and device equivalent
codes, and determines whether or not a sector is protected.
The Command Definitions Table 5 shows the address and
data requirements. This method is an alternative to that
shown in the Auto-select Codes (High Voltage Method)
Table 4, which is intended for PROM programmers and
requires VID on address bit A9.
The auto-select command sequence is initiated by writing
two unlock cycles, followed by the auto-select command.
The device then enters the auto-select mode, and the
system may read at any address any number of times,
without initiating another command sequence.
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NX29F010
Table 5. Command Definitions
Command(1)
1st
Sequence
Cycles Addr Data
Read(3,4)
1
RA
RD
(5)
Reset
1
XXXX F0
Auto-select(6)
Manufacturer Equiv. ID 4
5555 AA
Device Equiv. ID
4
5555 AA
Sector Protect
4
5555 AA
Verify(7,8)
Program(9)
4
5555 AA
Chip Erase
6
5555 AA
2nd
Addr Data
Bus Cycles (2)
(Hexadecimal)
3rd
4th
Addr Data
Addr Data
2AAA 55
2AAA 55
2AAA 55
5555
5555
5555
90
90
90
2AAA 55
2AAA 55
5555
5555
Sector Erase
2AAA 55
5555
6
5555
AA
5th
Addr Data
6th
Addr Data
A0
80
XX00
XX01
(SA)
X02
PA
5555
01
20
00
01
PD
AA
2AAA 55
5555
10
80
5555 AA
2AAA 55
SA
30
Notes:
1. Bus Operations are described in Table 2.
2. All command bus cycles are write operations, except when reading array or auto-select data.
3. No unlock or command cycles are required when reading array data.
4. RA = Address of the memory location to be read; RD = Data read from location RA during read operation
5. The Reset command is required to return to reading array data when device is in the auto-select mode, or if DQ5 goes high
(while the device is providing status data).
6. The fourth cycle of the "Auto-select Command Sequence" is a read operation.
7. The data is 00H for an unprotected sector and 01h for a protected sector. See "Auto-select Command Sequence" for more
information.
8. SA = Address of the sector to be verified (in auto-select mode) or erased. Address bits A16-A14 uniquely select any sector
9. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,
whichever happens later; PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse,
whichever happens first.
10. Address bit A16 and A15 =x (don't care) for all address commands except for Program Address (PA), Read Address (RA) and
Sector Address (SA).
11. X = Don't Care.
A read cycle at address XX00H or retrieves the manufacturer code. A read cycle at address XX01H returns the
device code. A read cycle containing a sector address (SA)
and the address 02H in returns 01H if that sector is
protected, or 00H if it is unprotected. Refer to the Sector
Address tables for valid sector addresses.
The system must write the reset command to exit the
auto-select mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program setup command. The pro-
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gram address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is not required
to provide further controls or timings. The device automatically provides internally generated program pulses and verify
the programmed cell margin. The Command Definitions Table
(Table 5) shows the address and data requirements for the
byte program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using DQ7 or DQ6.
See "Write Operation Status" for information on these
status bits.
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NX29F010
Commands written to the device while the Embedded
Program Algorithm is in progress are ignored.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a '0' back
to a '1'. Attempting to do so may halt the operation and set
the error status bit, DQ5, to '1', or cause the Data Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is still
'0'. Only erase operations can convert a '0' to a '1'.
Note: See Command Definitions (Table 5) for program
command sequence.
The system can determine the status of the erase operation
by using DQ7 or DQ6. See "Write Operation Status" for
information on these status bits. When the Embedded
Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.
WRITE PROGRAM
COMMAND
SEQUENCE
Sector Erase Command Sequence
YES
NO
Figure 6 illustrates the algorithm for the erase operation.
See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip/Sector Erase
Operation Timings for timing waveforms.
DATA POLL
FROM
SYSTEM
VERIFY
DATA?
INCREMENT
ADDRESS
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a setup command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory
for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings
during these operations. The Command Definitions table
shows the address and data requirements for the chip erase
command sequence.
Commands written to the chip while the Embedded Erase
Algorithm is in progress are ignored.
START
EMBEDDED
PROGRAM
ALGORITHM
IN PROGRESS
Chip Erase Command Sequence
LAST
ADDRESS?
YES
PROGRAMMING
COMPLETE
NO
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a setup command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions Table (Table 5) shows the address and data
requirements for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The embedded erase algorithm
automatically programs and verifies the sector for an all
zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
Figure 5. Program Operation
8
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NX29F010
START
WRITE ERASE
COMMAND
SEQUENCE
EMBEDDED
ERASE
ALGORITHM
IN PROGRESS
DATA POLL
FROM
SYSTEM
NO
DATA = FFH?
YES
ERASURE
COMPLETE
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may
be written. Loading the sector erase buffer may be done in
any sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional
cycles must be less than 50 µs, otherwise the last address
and command might not be accepted, and erasure may
begin. It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be
less than 50 µs, the system need not monitor DQ3. Any
command during the time-out period resets the device to
reading array data. The system must rewrite the command
sequence and any additional sector addresses and
commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the "DQ3: Sector Erase
Timer" section.) The time-out begins from the rising edge of
the final WE pulse in the command sequence.
Once the sector erase operation has begun, all other
commands are ignored.
Figure 6. Erase Operation
Notes:
1. For Erase Command Sequence. See Command Definitions
table.
2. See "DQ3: Sector Erase Timer" for more information.
When the embedded erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched. The system can determine the status of the
erase operation by using DQ7 or DQ6. Refer to
"Write Operation Status" for information on these status bits.
Figure 6 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
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NX29F010
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a write operation: DQ3, DQ5, DQ6, and DQ7. DQ7 and DQ6
each offer a method for determining whether a program or
erase operation is complete or in progress. Table 6 and the
following subsections describe the functions of these bits.
START
READ
DQ7-DQ0
ADDR = VA
DQ7: Data Polling
The Data Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or completed. Data Polling is valid after the rising edge of the final
WE pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed
to DQ7. When the Embedded Program algorithm is complete, the device outputs the true datum programmed to
DQ7. The system must provide the program address to read
valid status information on DQ7. If a program address falls
within a protected sector, Data Polling on DQ7 is active for
approximately 2 µs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data Polling produces a "0" on DQ7. When the Embedded Erase algorithm
is complete, Data Polling produces a "1" on DQ7. This is
analogous to the complement/true datum output described
for the Embedded Program algorithm: the erase function
changes all the bits in a sector to "1"; prior to this, the device
outputs the "complement," or "0". The system must provide
an address within any of the sectors selected for erasure to
read valid status information on DQ7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on DQ7 is
active for approximately 100 µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7-DQ0
on the following read cycles. This is because DQ7 may
change asynchronously with DQ0-DQ6 while Output Enable
(OE) is asserted low. The Data Polling Timings (During
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this.
10
YES
DQ7 = DATA?
NO
NO
DQ5 = 1?
YES
READ
DQ7-DQ0
ADDR = VA
DQ7 = DATA?
YES
NO
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within
any sector selected for erasure. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 ="1" because
DQ7 may change simultaneously with DQ5.
Figure 7. Data Polling Algorithm
Table 6 shows the outputs for Data Polling on DQ7.
Figure 7 shows the Data Polling algorithm.
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
NX29F010
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the final WE pulse in the command
sequence (prior to the program or erase operation), and
during the sector erase time-out.
START
ADDR = VA
READ DQ7-DQ0(1)
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause DQ6 to
toggle. (The system may use either OE or CE to control the
read cycles.) When the operation is complete, DQ6 stops
toggling.
OLD_DQ6 < DQ6
ADDR = VA
READ DQ7-DQ0
NEW_DQ6 < DQ6
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
If a program address falls within a protected sector, DQ6
toggles for approximately 2 µs after the program command
sequence is written, then returns to reading array data.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 8 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram.
Reading Toggle Bit DQ6
Refer to Figure 8 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
DQ7-DQ0 at least twice in a row to determine whether a
toggle bit is toggling.
Typically, a system would note and store the value of the
toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on DQ7-DQ0 on the following read cycle.
NEW_DQ6 =
OLD_DQ6?
YES
NO
NO
DQ5 = 1?
YES
OLD_DQ6 < DQ6
ADDR = VA
READ DQ7-DQ0
NEW_DQ6 < DQ6
NEW_DQ6 =
OLD_DQ6?
YES
NO
FAIL
PASS
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as
DQ5 changes to '1'. See text.
3. VA = Valid Address.
Figure 8. Toggle Bit Algorithm
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
11
NX29F010
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the
section on DQ5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as DQ5 went high. If the
toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still
toggling, the device did not complete the operation successfully, and the system must write the reset command to
return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone
high. The system may continue to monitor the toggle bit and
DQ5 through successive read cycles, determining the
status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this
case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation (top of Figure 8).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a "1." This is a failure condition
that indicates the program or erase cycle as not successfully completed.
The DQ5 failure condition may appear if the system tries to
program a "1" to a location that is previously programmed
to "0." Only an erase operation can change a "0" back to a
"1." Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, DQ5
produces a "1."
Under both these conditions, the system must issue the
reset command to return the device to reading array data.
12
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out
is complete, DQ3 switches from "0" to "1." The system may
ignore DQ3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50 µs. See also the "Sector Erase Command
Sequence" section.
After the sector erase command sequence is written, the
system should read the status on DQ7 (Data Polling) or
DQ6 (Toggle Bit I) to ensure the device has accepted the
command sequence, and then read DQ3. If DQ3 is "1", the
internally controlled erase cycle has begun; all further
commands are ignored until the erase operation is complete. If DQ3 is "0", the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase
command. If DQ3 is high on the second status check, the
last command might not have been accepted. Table 6
shows the outputs for DQ3.
Table 6. Write Operation Status
Operation
DQ7(1)
DQ6
DQ5(2)
DQ3
Embedded
Program Algorithm
DQ7#
Toggle
0
N/A
0
Toggle
0
1
Embedded
Erase Algorithm
Notes:
1. DQ7 requires a valid address when reading status
information.
2. DQ5 switches to '1' when an Embedded Program or
Embedded Erase operation has exceeded the maximum
timing limits. See "DQ5: Exceeded Timing Limits" for more
information.
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
NX29F010
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
ISC
TA
TA
TSTG
Parameter
Terminal Voltage with Respect to GND
Any Pin Except A9
A9
VCC
Output Short Circuit Current (Max. Limit)
Commercial Operating Temperature
Industrial Operating Temperature
Storage Temperature
Value
Unit
–2.0 to +7.0(2)
–2.0 to +12.5(2)
–2.0 to +7.0(2)
200
0 to +70
–40 to +85
–65 to +125
V
V
V
mA
°C
°C
°C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Minimum DC inputs, I/O, and A9 pins voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for
periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V, which may overshoot to Vcc + 2.0V
for periods less than 20 ns. Maximum DC voltage on A9 is +12.5V that may overshoot to +12.5V for periods less
than 20 ns.
3. No more than one output shorted at one time. Duration of short shall not exceed one second.
20 ns
20 ns
20 ns
Vcc + 2.0V
Vcc + 0.5V
+0.8V
—0.5V
—2.0V
+2.0V
20 ns
20 ns
Figure 9. Maximum Negative Overshoot Waveform
20 ns
Figure 10. Maximum Positive Overshoot Waveform
OPERATING RANGE
Range
Commercial
Industrial(1)
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
5V ± 10%
5V ± 10%
Note:
1. Operating ranges define those limits between which the
functionally of the device is guaranteed.
CAPACITANCE
Symbol
Parameter
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
3
6
pF
COC/C
Output and Control
Capacitance
VOUT = 0V
7
12
pF
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
13
NX29F010
DC CHARACTERISTICS: TTL/NMOS COMPATIBLE
Symbol
ILI
ILI2
ILO
ICCS
ICC1
ICC2
VIL
VIH
VID
VOL
VOH
Parameter Description
Test Conditions
Min.
Max.
Unit
Input Leakage Current
A9 Input Current
Output Leakage Current
VCC Standby Current
VCC Active Current(1)
VCC Active Current(2,3)
Input Low Voltage
Input High Voltage
Voltage For Auto-select and
Temporary Sector Unprotect
Output Low Voltage
Output High Voltage
VCC = VCC Max., VIN = VCC to GND
VCC = VCC Max., A9 = 12.5V
VCC = VCC Max., VOUT = GND to VCC
VCC = VCC Max., CE and OE = VIH
VCC = VCC Max., CE = VIL, OE = VIH
VCC = VCC Max., CE = VIL, OE = VIH
VCC = 5.0V
—
—
—
—
—
—
–0.5
2.0
11.5
±1.0
50
±1.0
1.0
30
50
0.8
VCC + 0.5
12.5
µA
µA
µA
mA
mA
mA
V
V
V
IOL = 12 mA, VCC = VCC Min.
IOH = –2.5 mA, VCC = VCC Min.
—
2.4
0.45
—
V
V
Min.
Max.
Unit
—
—
—
—
±1.0
50
±1.0
100
µA
µA
µA
µA
—
—
–0.5
0.7 X VCC
11.5
30
50
0.8
VCC + 0.5
12.5
mA
mA
V
V
V
—
0.85 x VCC
VCC – 0.4
0.45
—
—
V
V
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz with OE at VIH.
2. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.
3. Not 100% tested.
DC CHARACTERISTICS: CMOS COMPATIBLE
Symbol
Parameter Description
Test Conditions
ILI
ILI2
ILO
ICCS
Input Leakage Current
A9 Input Current
Output Leakage Current
VCC Standby Current
ICC1
ICC2
VIL
VIH
VID
VCC Active Current(1)
VCC Active Current(2,3)
Input Low Voltage
Input High Voltage
Voltage For Auto-select and
Temporary Sector Unprotect
Output Low Voltage
Output High Voltage
Output High Voltage
VCC = VCC Max., VIN = VCC or GND
VCC = VCC Max., A9 = 12.5V
VCC = VCC Max., VOUT = GND to VCC
VCC = VCC Max., CE = Vcc ± 0.5V,
OE = VIH
VCC = VCC Max., CE = VIL, OE = VIH
VCC = VCC Max., CE = VIL, OE = VIH
VOL
VOH1
VOH2
VCC = 5.0V
IOL = 12 mA, VCC = VCC Min.
IOH = –2.5 mA, VCC = VCC Min.
IOH = –100 µA, VCC = VCC Min.
Notes:
1. The ICC current listed is typically less than 2 mA/MHz with OE at VIH.
2. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.
3. Not 100% tested.
14
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
NX29F010
AC CHARACTERISTICS: READ ONLY (Over Operating Range)
Std.
Symbol
tRC
tCE
tACC
tOE
tDF
tDF
tOEH
tOH
-35
Parameter
Min. Max.
Read Cycle Time(1)
35 —
(2)
Chip Enable Access Time
— 35
Address Access Time(3)
— 35
Output Enable Access Time
— 25
Chip Enable to Output High Z(1,4) — 10
Output Enable to Output High Z(1,4) — 10
Output Enable Hold Time(1)Read
0
—
Toggle & Data Polling 10 —
Output Hold from First of
0
—
Address, CE or OE
Whichever Occurs First
-45
Min. Max.
45 —
— 45
— 45
— 25
— 10
— 10
0
—
10 —
0
—
-55
Min. Max.
55 —
— 55
— 55
— 30
— 15
— 15
0
—
10 —
0
—
-70
Min. Max.
70 —
— 70
— 70
— 30
— 20
— 20
0
—
10 —
0
—
-90
Min. Max.
90 —
— 90
— 90
— 35
— 20
— 20
0
—
10 —
0
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Not 100% tested.
2. OE = VIL.
3. CE and OE = VIL.
4. Output Driver Disable Time.
5. See Figure 12 and Table 6 for test specifications.
tRC
ADDRESS
ADDRESS STABLE
tACC
tCE
CE
tDF
tOE
OE
tOEH
WE
tOH
OUTPUTS
HIGH-Z
HIGH-Z
OUTPUT VALID
Figure 11. AC Waveform: READ Only
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
15
NX29F010
TEST CONDITIONS
Table 6. AC Test Specifications
Vcc = 5.0V
Test Conditions
35 ns
All Others
Output Load
Unit
1 TTL Gate
2.7KΩ
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
20
ns
0 to 3.0
0.45 to 2.4
V
Input Timing Measurement
Reference Levels
1.5
0.8
V
Output Timing Measurement
Reference Levels
1.5
2.0
V
Input Pulse Levels
DEVICE
UNDER
TEST
6.2KΩ
CL
Figure 12. Test Setup
AC CHARACTERISTICS: ERASE AND PROGRAM
Std.
Symbol Parameter
tWC
Write Cycle Time(1)
-35
Min. Max.
35 —
-45
Min. Max.
45 —
-55
Min. Max.
45 —
-70
Min. Max.
45 —
-90
Min. Max.
90 —
Unit
ns
tAS
Address Setup Time
0
—
0
—
0
—
0
—
0
—
ns
tAH
Address Hold Time
30
—
35
—
45
—
45
—
45
—
ns
tDS
Data Setup Time
15
—
20
—
20
—
30
—
45
—
ns
tDH
Data Hold Time
0
—
0
—
0
—
0
—
0
—
ns
Read Recovery Time before Write 0
(OE HIGH to WE LOW)
—
0
—
0
—
0
—
0
—
ns
tCS
CE Setup Time
0
—
0
—
0
—
0
—
0
—
ns
tCH
CE Hold Time
0
—
0
—
0
—
0
—
0
—
ns
tWP
Write Pulse Width
20
—
25
—
30
—
35
—
45
—
ns
tWPH
Write Pulse Width HIGH
20
—
20
—
20
—
20
—
20
—
ns
20
—
20
—
20
—
20
—
20
—
µs
1.0
—
1.0
—
1.0
—
1.0
—
1.0
—
sec
50
—
50
—
1.0
—
1.0
—
1.0
—
µs
tGHWL
tWHWH1
tWHWH2
tVCS
(2)
Byte Programming Operation
(2)
Sector Erase Operation
(1)
VCC Setup Time
Note:
1. Not 100% tested.
16
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
NX29F010
PROGRAM COMMAND SEQUENCE (Last Two Cycles)
tWC
ADDRESS
READ STATUS DATA (Last Two Cycles)
tAS
555H
PA
PA
PA
tAH
CE
tCH
tGHWL
OE
tWPH
tWP
tWHWH1
WE
tCS
tDH
tDS
A0H
DATA
PD
STATUS
DOUT
tVCS
Vcc
Figure 13. AC Waveform: Program Operation
Note:
1. PA = Program Address, PD = Program Data, DOUT is the true data at the Program Address.
ERASE COMMAND SEQUENCE (Last Two Cycles)
tWC
ADDRESS
READ STATUS DATA
tAS
SA
2AAH
(555H FOR CHIP ERASE)
VA
VA
tAH
CE
tCH
tGHWL
OE
tWPH
tWP
tWHWH2
WE
tCS
tDH
tDS
55H
DATA
tVCS
30H
IN
PROGRESS
COMPLETE
10H FOR
CHIP ERASE
Vcc
Figure 14. AC Waveform: Erase Operation
Note:
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status").
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
17
NX29F010
tRC
ADDRESS
VA
VA
VA
tACC
tCE
CE
tCH
tOE
OE
tOEH
tDF
WE
tOH
DQ7
COMPLEMENT
COMPLEMENT
TRUE
VALID DATA
DQ0-DQ6
STATUS DATA
STATUS DATA
TRUE
VALID DATA
Figure 15. AC Waveform:
Note:
1. VA = Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
tRC
ADDRESS
VA
VA
VA
VA
VALID STATUS
STATUS
STATUS
(FIRST READ)
(SECOND READ)
(STOPS TOGGLING)
tACC
tCE
CE
tCH
tOE
OE
tOEH
WE
DQ6
tDF
tOH
VALID DATA
Figure 16. AC Waveform: Erase and Program Operations, Alternate CE Controlled Writes
Note:
1. VA = Valid Address, not required for DQ6. Illustration shows first two status cycles after command sequence, last status read cycle,
and array data read cycle.
18
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
NX29F010
AC ELECTRICAL CHARACTERISTICS
Std.
Symbol Parameter
tWC
Write Cycle Time (1)
-35
Min. Max.
35
—
-45
Min. Max.
45
—
-55
Min. Max.
55
—
-70
Min. Max.
70
—
-90
Min. Max.
90
—
Unit
ns
tAS
Addess Setup Time
0
—
0
—
0
—
0
—
0
—
ns
t AH
Address Hold Time
30
—
35
—
45
—
45
—
45
—
ns
t DS
Data Setup Time
20
—
20
—
20
—
30
—
45
—
ns
t DH
Data Hold Time
0
—
0
—
0
—
0
—
0
—
ns
0
—
0
—
0
—
0
—
0
—
ns
(1)
t OES
Output Enable Setup Time
t GHWL
Read Recovery Time Before Write
0
—
0
—
0
—
0
—
0
—
ns
t WS
Write Enable Setup Time
0
—
0
—
0
—
0
—
0
—
ns
tWH
Write Enable Hold Time
0
—
0
—
0
—
0
—
0
—
ns
t CP
Chip Enable Pulse Width
20
—
25
—
30
—
35
—
45
—
ns
t CPH
Chip Enable Pulse Width HIGH
20
—
20
—
20
—
20
—
20
—
ns
20
—
20
—
20
—
20
—
20
—
µs
1.0
—
1.0
—
1.0
—
1.0
—
1.0
—
sec
t WHWH1
t WHWH2
Byte Programming Operation
Sector Erase Operation
(2)
(2)
Note:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
555H FOR PROGRAM
2AAH FOR ERASE
PA FOR PROGRAM
SA FOR SECTOR ERASE
555H FOR CHIP ERASE
DATA# POLLING
ADDRESS
VA
tWC
tAS
tAH
WE
tWH
tGHEL
OE
tCPH
tCP
tWHWH1 OR 2
CE
tWS
tDH
tDS
DQ7#
DATA
A0H FOR PROGRAM
55H FOR ERASE
DOUT
PD FOR PROGRAM
30H FOR ERASE
10H FOR CHIP ERASE
Figure 17. AC Waveform:
Note:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
19
NX29F010
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ.(1) Max.(2)
Unit
Comments
Chip/Sector Erase Time
1.0
15
sec
Excludes 00H Programming Prior to Erase(4)
Byte Programming Time
27
300/1000
µs
Commercial / Industrial Temperature
Excludes System Level Overhead(5)
Chip Programming Time(3)
3.5
12.5
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0V Vcc, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions for Commercial and Industrial temperature ranges, Vcc = 4.5V (4.75V for –35),
100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since
most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is
exceeded, only then does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming.
See Table 2 for further information on command definitions.
6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed.
LATCHUP CHARACTERISTIC
Parameter
Min.
Max.(2)
Input Voltage with Respect to GND on I/O Pins
–1.0V
VCC + 1.0V
–100 mA
+100 mA
Vcc Current
Note:
1. Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
DATA RETENTION
Parameter
20
Test Conditions
Min.
Unit
Minimum Pattern Data Retention Time
150°C
10
Years
Vcc Current
125°C
20
Years
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
NX29F010
PACKAGING INFORMATION
600-mil Plastic DIP
Package Code: W
N
E1
1
D
S
SEATING PLANE
B1
E
A
L
C
α
A1
e
B
600-mil Plastic DIP (W)
Inches
Symbol Min Max
Min Max
Min Max
Ref. Std.
N
28
32
40
A
0.160 0.185 0.165 0.180 0.165 0.200
A1 0.020 0.030 0.010 —
0.020 0.045
B
0.015 0.020
0.018
0.015 0.022
B1 0.050 0.065
0.050
0.045 0.067
C 0.008 0.012
0.010
0.008 0.015
D 1.420 1.460 1.645 1.655 2.045 2.055
E
0.600 0.620 0.590 0.610 0.600 0.620
E1 0.530 0.555 0.540 0.555 0.530 0.560
eA 0.610 0.660 0.620 0.680 0.600 0.680
e
0.100 BSC
0.100 BSC 0.100 BSC
L
0.120 0.150 0.120 0.140 0.120 0.138
S
0.055 0.080 0.065 0.085 0.055 0.085
a
0°
15°
2°
8°
—
—
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
eA
Notes:
1. Controlling dimension: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusions and should be measured from the
bottom of the package.
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
21
NX29F010
PACKAGING INFORMATION
Plastic TSOP - 32-pins
Package Code: T (Type I)
1
E
H
N
D
SEATING PLANE
A
S
B
e
L
A1
α
C
Plastic TSOP (T—Type I)
Symbol
Ref. Std.
No. Leads
A
A1
B
C
D
E
H
e
L
a
22
Millimeters
Min
Max
Inches
Min
Max
32
–
1.20
0.05
0.15
0.17
0.27
0.10
0.21
7.90
8.10
18.30 18.50
19.80 20.20
0.50 BSC
0.50
0.70
0°
5°
–
0.047
0.002 0.005
0.007 0.009
0.004 0.008
0.308 0.316
0.714 0.722
0.772 0.788
0.020 BSC
0.016 0.024
0°
5°
Notes:
1. Controlling dimension: millimeters, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect to
one another within 0.004 inches at the
seating plane.
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
NX29F010
PACKAGING INFORMATION
PLCC (Plastic Leaded Chip Carrier)
Package Code: PL
C
PIN 1
e
b
b1
D2
D1 D
A
E
A3
E1
A1
A2
SEATING
PLANE
E2
Plastic Leaded Chip Carrier (PL)
Millimeters
Inches
Symbol Min Max
Min
Max
Ref. Std.
No. Leads
32
A
3.33 3.56 0.131 0.140
A1
0.50
–
0.020
–
A2
2.67 2.93 0.105 0.115
A3
1.91 0.81 0.026 0.032
b
0.66 8.10 0.311 0.319
b1
0.33 0.54 0.013 0.021
C
0.20 0.35 0.008 0.014
D
13.89 14.05 0.547 0.553
D1
14.86 15.10 0.585 0.595
D2
–
7.62
–
0.400
E
11.35 11.51 0.447 0.453
E1
12.32 12.57 0.485 0.495
E2
–
7.62
–
0.300
e
1.27 BSC
0.050 BSC
0o
10o
0o
10o
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash
protrusions.
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
5. ND and NE represent the number of leads in D and
E directions, respectively.
6. D1 and E1 should be measured from the bottom of
the package.
23
NX29F010
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
35
NX29F010-35W
NX29F010-45PL
NX29F010-35T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
45
NX29F010-45W
NX29F010-45PL
NX29F010-45T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
55
NX29F010-55W
NX29F010-55PL
NX29F010-45T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
70
NX29F010-70W
NX29F010-70PL
NX29F010-70T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
90
NX29F010-90W
NX29F010-90PL
NX29F010-90T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
Note: Contact NexFlash Marketing for availability of DIP packages
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
24
Order Part No.
Package
45
NX29F010-45PLI
NX29F010-45TI
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
55
NX29F010-55PLI
NX29F010-55TI
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
70
NX29F010-70PLI
NX29F010-70TI
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
90
NX29F010-90PLI
NX29F010-90TI
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
NX29F010
PRELIMINARY DESIGNATION
LIFE SUPPORT POLICY
The “Preliminary” designation on an NexFlash data sheet
indicates that the product is not fully characterized. The
specifications are subject to change and are not guaranteed. NexFlash or an authorized sales representative should
be consulted for current information before using this
product.
NexFlash does not recommend the use of any of it's
products in life support applications where the failure or
malfunction of the product can reasonably be expected to
cause failure in the life support system or to significantly
affect its safety or effectiveness. Products are not
authorized for use in such applications unless NexFlash
receives written assurances, to it’s satisfaction, that:
IMPORTANT NOTICE
(a) the risk of injury or damage has been minimized;
NexFlash reserves the right to make changes to the
products contained in this publication in order to improve
design, performance or reliability. NexFlash assumes no
responsibility for the use of any circuits described herein,
conveys no license under any patent or other right, and
makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary
depending upon a user’s specific application. While the
information in this publication has been carefully checked,
NexFlash shall not be liable for any damages arising as a
result of any error or omission.
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
(b) the user assumes all such risks; and
(c) potential liability of NexFlash is adequately protected
under the circumstances.
Trademarks:
NexFlash is a trademark of NexFlash Technologies, Inc. All
other marks are the property of their respective owner.
25